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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1545 1 T2 2 T3 3 T4 6
auto[1] 1907 1 T2 1 T3 3 T4 1


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 119 1 T77 1 T34 1 T188 1
auto[134217728:268435455] 99 1 T3 1 T14 1 T5 2
auto[268435456:402653183] 126 1 T14 1 T5 5 T46 1
auto[402653184:536870911] 91 1 T5 3 T6 1 T92 2
auto[536870912:671088639] 104 1 T5 2 T34 1 T46 3
auto[671088640:805306367] 105 1 T3 2 T4 1 T14 1
auto[805306368:939524095] 98 1 T2 1 T4 2 T46 3
auto[939524096:1073741823] 94 1 T46 1 T305 1 T44 1
auto[1073741824:1207959551] 123 1 T4 1 T13 1 T5 1
auto[1207959552:1342177279] 106 1 T2 1 T14 1 T5 1
auto[1342177280:1476395007] 118 1 T46 1 T182 1 T189 1
auto[1476395008:1610612735] 101 1 T5 1 T46 2 T92 1
auto[1610612736:1744830463] 98 1 T5 1 T24 1 T46 4
auto[1744830464:1879048191] 125 1 T3 1 T5 2 T24 1
auto[1879048192:2013265919] 116 1 T6 1 T46 1 T44 3
auto[2013265920:2147483647] 103 1 T5 1 T78 1 T46 2
auto[2147483648:2281701375] 123 1 T14 1 T5 1 T6 2
auto[2281701376:2415919103] 94 1 T13 1 T5 1 T46 4
auto[2415919104:2550136831] 114 1 T4 1 T5 1 T46 1
auto[2550136832:2684354559] 98 1 T46 2 T189 1 T21 1
auto[2684354560:2818572287] 108 1 T14 1 T5 2 T46 3
auto[2818572288:2952790015] 105 1 T3 1 T4 1 T13 1
auto[2952790016:3087007743] 112 1 T5 1 T21 1 T120 1
auto[3087007744:3221225471] 115 1 T2 1 T13 2 T5 2
auto[3221225472:3355443199] 97 1 T14 1 T34 2 T46 3
auto[3355443200:3489660927] 117 1 T13 1 T5 2 T6 1
auto[3489660928:3623878655] 96 1 T6 1 T46 2 T92 2
auto[3623878656:3758096383] 105 1 T3 1 T4 1 T6 1
auto[3758096384:3892314111] 94 1 T6 1 T44 3 T120 1
auto[3892314112:4026531839] 120 1 T14 2 T116 1 T46 1
auto[4026531840:4160749567] 126 1 T5 1 T34 1 T7 1
auto[4160749568:4294967295] 102 1 T46 1 T189 1 T44 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 55 1 T77 1 T34 1 T21 1
auto[0:134217727] auto[1] 64 1 T188 1 T305 1 T48 1
auto[134217728:268435455] auto[0] 50 1 T14 1 T5 1 T6 1
auto[134217728:268435455] auto[1] 49 1 T3 1 T5 1 T92 1
auto[268435456:402653183] auto[0] 57 1 T14 1 T5 5 T46 1
auto[268435456:402653183] auto[1] 69 1 T47 1 T63 1 T363 2
auto[402653184:536870911] auto[0] 40 1 T5 1 T92 1 T44 2
auto[402653184:536870911] auto[1] 51 1 T5 2 T6 1 T92 1
auto[536870912:671088639] auto[0] 46 1 T34 1 T46 1 T21 1
auto[536870912:671088639] auto[1] 58 1 T5 2 T46 2 T48 1
auto[671088640:805306367] auto[0] 54 1 T3 2 T34 1 T46 1
auto[671088640:805306367] auto[1] 51 1 T4 1 T14 1 T6 1
auto[805306368:939524095] auto[0] 47 1 T2 1 T4 2 T46 1
auto[805306368:939524095] auto[1] 51 1 T46 2 T7 1 T48 1
auto[939524096:1073741823] auto[0] 43 1 T46 1 T305 1 T44 1
auto[939524096:1073741823] auto[1] 51 1 T67 1 T68 1 T410 1
auto[1073741824:1207959551] auto[0] 50 1 T4 1 T5 1 T46 1
auto[1073741824:1207959551] auto[1] 73 1 T13 1 T6 1 T62 1
auto[1207959552:1342177279] auto[0] 51 1 T5 1 T116 1 T46 1
auto[1207959552:1342177279] auto[1] 55 1 T2 1 T14 1 T63 1
auto[1342177280:1476395007] auto[0] 47 1 T44 3 T260 1 T225 1
auto[1342177280:1476395007] auto[1] 71 1 T46 1 T182 1 T189 1
auto[1476395008:1610612735] auto[0] 43 1 T5 1 T7 1 T44 1
auto[1476395008:1610612735] auto[1] 58 1 T46 2 T92 1 T62 1
auto[1610612736:1744830463] auto[0] 44 1 T5 1 T24 1 T46 3
auto[1610612736:1744830463] auto[1] 54 1 T46 1 T305 1 T7 1
auto[1744830464:1879048191] auto[0] 59 1 T24 1 T46 3 T49 2
auto[1744830464:1879048191] auto[1] 66 1 T3 1 T5 2 T92 1
auto[1879048192:2013265919] auto[0] 47 1 T121 1 T124 1 T250 1
auto[1879048192:2013265919] auto[1] 69 1 T6 1 T46 1 T44 3
auto[2013265920:2147483647] auto[0] 41 1 T46 1 T7 1 T55 1
auto[2013265920:2147483647] auto[1] 62 1 T5 1 T78 1 T46 1
auto[2147483648:2281701375] auto[0] 56 1 T14 1 T5 1 T6 1
auto[2147483648:2281701375] auto[1] 67 1 T6 1 T46 1 T182 1
auto[2281701376:2415919103] auto[0] 36 1 T5 1 T46 1 T305 1
auto[2281701376:2415919103] auto[1] 58 1 T13 1 T46 3 T186 1
auto[2415919104:2550136831] auto[0] 52 1 T4 1 T5 1 T250 1
auto[2415919104:2550136831] auto[1] 62 1 T46 1 T182 1 T189 1
auto[2550136832:2684354559] auto[0] 46 1 T46 2 T59 1 T178 1
auto[2550136832:2684354559] auto[1] 52 1 T189 1 T21 1 T48 1
auto[2684354560:2818572287] auto[0] 54 1 T5 1 T46 3 T189 1
auto[2684354560:2818572287] auto[1] 54 1 T14 1 T5 1 T62 1
auto[2818572288:2952790015] auto[0] 44 1 T3 1 T4 1 T5 2
auto[2818572288:2952790015] auto[1] 61 1 T13 1 T78 1 T46 1
auto[2952790016:3087007743] auto[0] 55 1 T5 1 T225 1 T63 2
auto[2952790016:3087007743] auto[1] 57 1 T21 1 T120 1 T121 1
auto[3087007744:3221225471] auto[0] 51 1 T2 1 T5 1 T46 1
auto[3087007744:3221225471] auto[1] 64 1 T13 2 T5 1 T46 1
auto[3221225472:3355443199] auto[0] 40 1 T14 1 T34 1 T46 1
auto[3221225472:3355443199] auto[1] 57 1 T34 1 T46 2 T191 1
auto[3355443200:3489660927] auto[0] 52 1 T13 1 T5 1 T124 1
auto[3355443200:3489660927] auto[1] 65 1 T5 1 T6 1 T46 1
auto[3489660928:3623878655] auto[0] 37 1 T92 1 T195 1 T250 1
auto[3489660928:3623878655] auto[1] 59 1 T6 1 T46 2 T92 1
auto[3623878656:3758096383] auto[0] 50 1 T4 1 T6 1 T49 1
auto[3623878656:3758096383] auto[1] 55 1 T3 1 T46 2 T7 1
auto[3758096384:3892314111] auto[0] 42 1 T44 2 T105 2 T60 1
auto[3758096384:3892314111] auto[1] 52 1 T6 1 T44 1 T120 1
auto[3892314112:4026531839] auto[0] 51 1 T14 1 T191 1 T192 1
auto[3892314112:4026531839] auto[1] 69 1 T14 1 T116 1 T46 1
auto[4026531840:4160749567] auto[0] 63 1 T5 1 T49 2 T59 1
auto[4026531840:4160749567] auto[1] 63 1 T34 1 T7 1 T44 2
auto[4160749568:4294967295] auto[0] 42 1 T46 1 T189 1 T260 1
auto[4160749568:4294967295] auto[1] 60 1 T44 1 T22 1 T68 1

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