Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.37 99.00 97.99 98.38 97.67 98.93 98.41 91.22


Total test records in report: 1089
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1008 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4071309922 Jun 10 05:29:15 PM PDT 24 Jun 10 05:29:16 PM PDT 24 16435679 ps
T1009 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.575750959 Jun 10 05:29:07 PM PDT 24 Jun 10 05:29:09 PM PDT 24 27055837 ps
T1010 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.328071231 Jun 10 05:29:46 PM PDT 24 Jun 10 05:29:48 PM PDT 24 14996284 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3665901351 Jun 10 05:29:51 PM PDT 24 Jun 10 05:29:53 PM PDT 24 64519427 ps
T1012 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1957826824 Jun 10 05:29:09 PM PDT 24 Jun 10 05:29:20 PM PDT 24 413909880 ps
T1013 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3194211598 Jun 10 05:29:11 PM PDT 24 Jun 10 05:29:13 PM PDT 24 43613018 ps
T1014 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1928984683 Jun 10 05:29:12 PM PDT 24 Jun 10 05:29:13 PM PDT 24 10211084 ps
T1015 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2298799804 Jun 10 05:29:13 PM PDT 24 Jun 10 05:29:18 PM PDT 24 227614136 ps
T153 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4018231671 Jun 10 05:28:57 PM PDT 24 Jun 10 05:29:00 PM PDT 24 417905783 ps
T1016 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3796611204 Jun 10 05:28:56 PM PDT 24 Jun 10 05:29:02 PM PDT 24 1434723406 ps
T1017 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.319245890 Jun 10 05:29:18 PM PDT 24 Jun 10 05:29:27 PM PDT 24 237868619 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2364065846 Jun 10 05:29:04 PM PDT 24 Jun 10 05:29:07 PM PDT 24 34218031 ps
T1019 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1856264982 Jun 10 05:29:19 PM PDT 24 Jun 10 05:29:20 PM PDT 24 62218533 ps
T1020 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3674470731 Jun 10 05:29:19 PM PDT 24 Jun 10 05:29:20 PM PDT 24 8174501 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3660808863 Jun 10 05:29:21 PM PDT 24 Jun 10 05:29:22 PM PDT 24 12212658 ps
T1022 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.718256583 Jun 10 05:29:08 PM PDT 24 Jun 10 05:29:12 PM PDT 24 185761244 ps
T1023 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1388619544 Jun 10 05:28:58 PM PDT 24 Jun 10 05:29:10 PM PDT 24 457348956 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2400248050 Jun 10 05:29:51 PM PDT 24 Jun 10 05:29:52 PM PDT 24 8654784 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3018915764 Jun 10 05:29:27 PM PDT 24 Jun 10 05:29:39 PM PDT 24 34484180 ps
T1026 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.900528011 Jun 10 05:29:26 PM PDT 24 Jun 10 05:29:28 PM PDT 24 84564971 ps
T1027 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2345983684 Jun 10 05:29:43 PM PDT 24 Jun 10 05:29:47 PM PDT 24 283884670 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.523163361 Jun 10 05:29:08 PM PDT 24 Jun 10 05:29:10 PM PDT 24 182684349 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.999291068 Jun 10 05:29:45 PM PDT 24 Jun 10 05:29:51 PM PDT 24 425012048 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.283950669 Jun 10 05:29:13 PM PDT 24 Jun 10 05:29:18 PM PDT 24 584637522 ps
T1031 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1184312156 Jun 10 05:29:56 PM PDT 24 Jun 10 05:29:57 PM PDT 24 223720548 ps
T1032 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3364022345 Jun 10 05:29:03 PM PDT 24 Jun 10 05:29:12 PM PDT 24 240422240 ps
T148 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1781391 Jun 10 05:28:54 PM PDT 24 Jun 10 05:29:04 PM PDT 24 245301890 ps
T156 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2635674518 Jun 10 05:29:07 PM PDT 24 Jun 10 05:29:15 PM PDT 24 1921033306 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2641931268 Jun 10 05:29:14 PM PDT 24 Jun 10 05:29:16 PM PDT 24 22603948 ps
T1034 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.300304441 Jun 10 05:29:13 PM PDT 24 Jun 10 05:29:15 PM PDT 24 75879856 ps
T1035 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3068789216 Jun 10 05:29:18 PM PDT 24 Jun 10 05:29:19 PM PDT 24 10613754 ps
T1036 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3155202182 Jun 10 05:29:08 PM PDT 24 Jun 10 05:29:17 PM PDT 24 343037767 ps
T1037 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2261020968 Jun 10 05:28:58 PM PDT 24 Jun 10 05:29:01 PM PDT 24 230893993 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3383503755 Jun 10 05:29:45 PM PDT 24 Jun 10 05:29:47 PM PDT 24 50427337 ps
T1039 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1620156483 Jun 10 05:29:24 PM PDT 24 Jun 10 05:29:25 PM PDT 24 106013335 ps
T161 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3562940501 Jun 10 05:29:30 PM PDT 24 Jun 10 05:29:37 PM PDT 24 269462778 ps
T1040 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2585870900 Jun 10 05:29:08 PM PDT 24 Jun 10 05:29:11 PM PDT 24 60740111 ps
T1041 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.69127679 Jun 10 05:29:15 PM PDT 24 Jun 10 05:29:23 PM PDT 24 139022029 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1598307651 Jun 10 05:29:29 PM PDT 24 Jun 10 05:29:32 PM PDT 24 190416626 ps
T1043 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2806118876 Jun 10 05:29:18 PM PDT 24 Jun 10 05:29:29 PM PDT 24 3229538129 ps
T1044 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1037173558 Jun 10 05:29:50 PM PDT 24 Jun 10 05:29:53 PM PDT 24 323458049 ps
T1045 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2900449750 Jun 10 05:29:47 PM PDT 24 Jun 10 05:29:51 PM PDT 24 497441878 ps
T1046 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.679125664 Jun 10 05:29:47 PM PDT 24 Jun 10 05:29:49 PM PDT 24 65635633 ps
T1047 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.107573538 Jun 10 05:29:23 PM PDT 24 Jun 10 05:29:24 PM PDT 24 38379452 ps
T1048 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2324900239 Jun 10 05:29:03 PM PDT 24 Jun 10 05:29:15 PM PDT 24 734772510 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3644489697 Jun 10 05:29:27 PM PDT 24 Jun 10 05:29:33 PM PDT 24 234729164 ps
T1050 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1206759945 Jun 10 05:29:00 PM PDT 24 Jun 10 05:29:11 PM PDT 24 822551094 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2607103747 Jun 10 05:29:07 PM PDT 24 Jun 10 05:29:09 PM PDT 24 61099495 ps
T375 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3635686171 Jun 10 05:29:16 PM PDT 24 Jun 10 05:29:22 PM PDT 24 484655434 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2442411259 Jun 10 05:29:13 PM PDT 24 Jun 10 05:29:16 PM PDT 24 183213817 ps
T157 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1248727721 Jun 10 05:29:03 PM PDT 24 Jun 10 05:29:07 PM PDT 24 80847757 ps
T1053 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2915310194 Jun 10 05:29:14 PM PDT 24 Jun 10 05:29:16 PM PDT 24 110562575 ps
T1054 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2265560405 Jun 10 05:29:46 PM PDT 24 Jun 10 05:29:51 PM PDT 24 135730033 ps
T1055 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4187045490 Jun 10 05:29:12 PM PDT 24 Jun 10 05:29:13 PM PDT 24 16719797 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1697317422 Jun 10 05:29:47 PM PDT 24 Jun 10 05:29:49 PM PDT 24 126121170 ps
T1057 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2215938307 Jun 10 05:29:05 PM PDT 24 Jun 10 05:29:19 PM PDT 24 430879984 ps
T1058 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2377247015 Jun 10 05:29:57 PM PDT 24 Jun 10 05:29:58 PM PDT 24 57608093 ps
T1059 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3993062062 Jun 10 05:29:18 PM PDT 24 Jun 10 05:29:20 PM PDT 24 121114349 ps
T1060 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2309279064 Jun 10 05:29:05 PM PDT 24 Jun 10 05:29:07 PM PDT 24 40388266 ps
T1061 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3637027052 Jun 10 05:29:48 PM PDT 24 Jun 10 05:29:50 PM PDT 24 131711017 ps
T164 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3309185763 Jun 10 05:28:56 PM PDT 24 Jun 10 05:29:00 PM PDT 24 216417380 ps
T1062 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3569390958 Jun 10 05:29:53 PM PDT 24 Jun 10 05:29:54 PM PDT 24 9342104 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.504273137 Jun 10 05:29:34 PM PDT 24 Jun 10 05:29:37 PM PDT 24 241584849 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1747577384 Jun 10 05:29:15 PM PDT 24 Jun 10 05:29:16 PM PDT 24 27171544 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3801676506 Jun 10 05:28:59 PM PDT 24 Jun 10 05:29:00 PM PDT 24 37046692 ps
T1066 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3393003672 Jun 10 05:29:16 PM PDT 24 Jun 10 05:29:17 PM PDT 24 76854045 ps
T1067 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.56359454 Jun 10 05:29:04 PM PDT 24 Jun 10 05:29:06 PM PDT 24 28771107 ps
T1068 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4000256551 Jun 10 05:29:18 PM PDT 24 Jun 10 05:29:19 PM PDT 24 14898757 ps
T1069 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1498644939 Jun 10 05:29:17 PM PDT 24 Jun 10 05:29:19 PM PDT 24 10069529 ps
T1070 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.544070225 Jun 10 05:29:38 PM PDT 24 Jun 10 05:29:43 PM PDT 24 204543560 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3869009252 Jun 10 05:29:01 PM PDT 24 Jun 10 05:29:04 PM PDT 24 35078345 ps
T1072 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.300343229 Jun 10 05:29:41 PM PDT 24 Jun 10 05:29:42 PM PDT 24 25045948 ps
T1073 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.36643648 Jun 10 05:29:51 PM PDT 24 Jun 10 05:29:53 PM PDT 24 41151738 ps
T1074 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2472333315 Jun 10 05:29:14 PM PDT 24 Jun 10 05:29:22 PM PDT 24 439262537 ps
T1075 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4267886550 Jun 10 05:29:02 PM PDT 24 Jun 10 05:29:07 PM PDT 24 69024463 ps
T1076 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.764974022 Jun 10 05:29:14 PM PDT 24 Jun 10 05:29:17 PM PDT 24 339932999 ps
T1077 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2913820902 Jun 10 05:29:07 PM PDT 24 Jun 10 05:29:09 PM PDT 24 12039174 ps
T1078 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1220996948 Jun 10 05:29:09 PM PDT 24 Jun 10 05:29:17 PM PDT 24 770333859 ps
T1079 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2867972075 Jun 10 05:29:04 PM PDT 24 Jun 10 05:29:13 PM PDT 24 433441122 ps
T1080 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4130924357 Jun 10 05:28:57 PM PDT 24 Jun 10 05:29:03 PM PDT 24 132502514 ps
T1081 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4166032498 Jun 10 05:29:38 PM PDT 24 Jun 10 05:29:46 PM PDT 24 222390206 ps
T1082 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1208602679 Jun 10 05:29:23 PM PDT 24 Jun 10 05:29:27 PM PDT 24 126904421 ps
T1083 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2964974914 Jun 10 05:29:03 PM PDT 24 Jun 10 05:29:04 PM PDT 24 116201632 ps
T1084 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2738287009 Jun 10 05:29:01 PM PDT 24 Jun 10 05:29:03 PM PDT 24 146855406 ps
T1085 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2239099595 Jun 10 05:29:08 PM PDT 24 Jun 10 05:29:10 PM PDT 24 21894280 ps
T1086 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1443297722 Jun 10 05:29:35 PM PDT 24 Jun 10 05:29:36 PM PDT 24 37403863 ps
T1087 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2007546277 Jun 10 05:29:28 PM PDT 24 Jun 10 05:29:42 PM PDT 24 1383720272 ps
T1088 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1082029666 Jun 10 05:29:53 PM PDT 24 Jun 10 05:29:54 PM PDT 24 16293569 ps
T1089 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3310170500 Jun 10 05:29:49 PM PDT 24 Jun 10 05:29:51 PM PDT 24 24336738 ps

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1846075566
Short name T3
Test name
Test status
Simulation time 166887823 ps
CPU time 4.2 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 210380 kb
Host smart-cfd69dd6-be04-4994-8585-31c803a1a423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846075566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1846075566
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4199607509
Short name T5
Test name
Test status
Simulation time 112359985904 ps
CPU time 354.89 seconds
Started Jun 10 05:36:32 PM PDT 24
Finished Jun 10 05:42:27 PM PDT 24
Peak memory 222644 kb
Host smart-cc23d821-47af-4411-b9e3-ca1b9a9c3b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199607509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4199607509
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2209679184
Short name T46
Test name
Test status
Simulation time 1219390802 ps
CPU time 47.7 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 221076 kb
Host smart-37ffd02a-f5ba-4b8f-9ac6-b3c8f215649d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209679184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2209679184
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3551474222
Short name T50
Test name
Test status
Simulation time 1092882930 ps
CPU time 20.25 seconds
Started Jun 10 05:37:27 PM PDT 24
Finished Jun 10 05:37:47 PM PDT 24
Peak memory 222476 kb
Host smart-8ca95ab5-6314-4655-bff8-bb418b198b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551474222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3551474222
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1431451223
Short name T42
Test name
Test status
Simulation time 2524377511 ps
CPU time 14.43 seconds
Started Jun 10 05:34:48 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 231964 kb
Host smart-4f810ffb-9b4b-4924-a2c4-81572bcb5d5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431451223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1431451223
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.162691373
Short name T7
Test name
Test status
Simulation time 349349050 ps
CPU time 20.62 seconds
Started Jun 10 05:35:56 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 222640 kb
Host smart-2731be92-1713-45cb-87dd-57676214c821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162691373 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.162691373
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4094935017
Short name T110
Test name
Test status
Simulation time 173622124 ps
CPU time 2.89 seconds
Started Jun 10 05:29:41 PM PDT 24
Finished Jun 10 05:29:45 PM PDT 24
Peak memory 213992 kb
Host smart-157c0465-f605-4ffe-8de5-cbe9300d5b8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094935017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4094935017
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2863715412
Short name T127
Test name
Test status
Simulation time 2812857411 ps
CPU time 71.06 seconds
Started Jun 10 05:35:38 PM PDT 24
Finished Jun 10 05:36:49 PM PDT 24
Peak memory 215668 kb
Host smart-3b64b0e4-1974-4a16-9c0f-1a372dbbb77c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863715412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2863715412
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.643157737
Short name T63
Test name
Test status
Simulation time 1818551271 ps
CPU time 25.15 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:37 PM PDT 24
Peak memory 215116 kb
Host smart-ec95dbce-b4bc-4859-ab15-64883db8e56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643157737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.643157737
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.258397183
Short name T33
Test name
Test status
Simulation time 127637444 ps
CPU time 1.87 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 210736 kb
Host smart-6dbcff9b-f185-4354-8927-ecb582c59ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258397183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.258397183
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2048858515
Short name T102
Test name
Test status
Simulation time 501201667 ps
CPU time 3.84 seconds
Started Jun 10 05:29:41 PM PDT 24
Finished Jun 10 05:29:45 PM PDT 24
Peak memory 214240 kb
Host smart-e051fcdb-1c52-435f-85a9-099aba992cfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048858515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2048858515
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.382575198
Short name T122
Test name
Test status
Simulation time 2931572456 ps
CPU time 15.73 seconds
Started Jun 10 05:35:54 PM PDT 24
Finished Jun 10 05:36:10 PM PDT 24
Peak memory 214720 kb
Host smart-d69fc40a-43b3-4c8c-b476-d38d72e6ae0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382575198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.382575198
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1363961939
Short name T178
Test name
Test status
Simulation time 6022215456 ps
CPU time 54.4 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:52 PM PDT 24
Peak memory 222636 kb
Host smart-ff815023-1550-4945-aac9-4aa2280e2ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363961939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1363961939
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2928299063
Short name T231
Test name
Test status
Simulation time 147250473 ps
CPU time 8.2 seconds
Started Jun 10 05:35:23 PM PDT 24
Finished Jun 10 05:35:32 PM PDT 24
Peak memory 222692 kb
Host smart-9f0de625-9264-49d9-9c75-06f2579f63a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928299063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2928299063
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1357987562
Short name T17
Test name
Test status
Simulation time 76683544 ps
CPU time 3.52 seconds
Started Jun 10 05:36:51 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 209680 kb
Host smart-20e628e7-50d6-4de9-b29f-ecf1a37666b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357987562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1357987562
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3635200260
Short name T22
Test name
Test status
Simulation time 235152848 ps
CPU time 5.46 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 218424 kb
Host smart-cd1c9b72-4244-4064-8773-9f019817f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635200260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3635200260
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.662813693
Short name T170
Test name
Test status
Simulation time 199936416 ps
CPU time 10.32 seconds
Started Jun 10 05:36:55 PM PDT 24
Finished Jun 10 05:37:06 PM PDT 24
Peak memory 215416 kb
Host smart-c03d8779-dc91-434d-93bc-79a243a5db46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662813693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.662813693
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3210222508
Short name T406
Test name
Test status
Simulation time 622094553 ps
CPU time 9.51 seconds
Started Jun 10 05:37:28 PM PDT 24
Finished Jun 10 05:37:38 PM PDT 24
Peak memory 222412 kb
Host smart-34dcf42d-44ea-42bd-8084-ed18fa59fa38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3210222508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3210222508
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1777030499
Short name T13
Test name
Test status
Simulation time 136997502 ps
CPU time 2.81 seconds
Started Jun 10 05:35:37 PM PDT 24
Finished Jun 10 05:35:41 PM PDT 24
Peak memory 214404 kb
Host smart-e7d71c6c-4374-4c47-9416-f35bd3d77889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777030499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1777030499
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2080460185
Short name T241
Test name
Test status
Simulation time 189377649 ps
CPU time 6.96 seconds
Started Jun 10 05:36:48 PM PDT 24
Finished Jun 10 05:36:56 PM PDT 24
Peak memory 215152 kb
Host smart-d1b4a811-c0cc-4b4c-ba75-7bf58c40016d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080460185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2080460185
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3508111114
Short name T885
Test name
Test status
Simulation time 93920291 ps
CPU time 3.26 seconds
Started Jun 10 05:37:22 PM PDT 24
Finished Jun 10 05:37:26 PM PDT 24
Peak memory 209720 kb
Host smart-a5d91b46-111f-4202-bf31-409af8c136c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508111114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3508111114
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.846817625
Short name T60
Test name
Test status
Simulation time 23590168328 ps
CPU time 91.49 seconds
Started Jun 10 05:35:54 PM PDT 24
Finished Jun 10 05:37:26 PM PDT 24
Peak memory 217104 kb
Host smart-5c22a6ec-0ef5-42ba-8a53-fe7980cba0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846817625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.846817625
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3913977125
Short name T405
Test name
Test status
Simulation time 304047040 ps
CPU time 8.12 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:39 PM PDT 24
Peak memory 215028 kb
Host smart-2f3c13f0-87b4-4a39-92ba-5b569ccb7b80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913977125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3913977125
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1980197439
Short name T140
Test name
Test status
Simulation time 369092793 ps
CPU time 3.13 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:06 PM PDT 24
Peak memory 217864 kb
Host smart-3daed914-31bd-4f20-9ec9-eb33829acd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980197439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1980197439
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2260932589
Short name T109
Test name
Test status
Simulation time 212976945 ps
CPU time 1.44 seconds
Started Jun 10 05:29:49 PM PDT 24
Finished Jun 10 05:29:51 PM PDT 24
Peak memory 214016 kb
Host smart-bb27a2c8-d90d-4cb9-82d1-1337ea5e55d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260932589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2260932589
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3841128240
Short name T26
Test name
Test status
Simulation time 162305657 ps
CPU time 1.92 seconds
Started Jun 10 05:36:57 PM PDT 24
Finished Jun 10 05:36:59 PM PDT 24
Peak memory 208072 kb
Host smart-50d61ad6-f640-479d-b136-adcf279cbbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841128240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3841128240
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3656415281
Short name T23
Test name
Test status
Simulation time 641308740 ps
CPU time 7.61 seconds
Started Jun 10 05:35:54 PM PDT 24
Finished Jun 10 05:36:02 PM PDT 24
Peak memory 208500 kb
Host smart-81c413ed-4040-4e2a-aaf7-1234b969a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656415281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3656415281
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3267060299
Short name T199
Test name
Test status
Simulation time 2647667449 ps
CPU time 35.94 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 222444 kb
Host smart-e8689d5c-0588-47bc-8dea-1fe58a87637f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267060299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3267060299
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3901106676
Short name T24
Test name
Test status
Simulation time 66588812 ps
CPU time 3.27 seconds
Started Jun 10 05:37:47 PM PDT 24
Finished Jun 10 05:37:50 PM PDT 24
Peak memory 210200 kb
Host smart-21f63bb2-a048-4cd4-9040-ca4dfa8c07b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901106676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3901106676
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1694294937
Short name T229
Test name
Test status
Simulation time 1151053840 ps
CPU time 57.95 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 222444 kb
Host smart-d68ee553-c88a-43e0-8540-1849ee87425d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694294937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1694294937
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3579687337
Short name T80
Test name
Test status
Simulation time 697372689 ps
CPU time 7.66 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:24 PM PDT 24
Peak memory 209340 kb
Host smart-b107a436-af01-4931-a996-bae620871ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579687337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3579687337
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2229881989
Short name T250
Test name
Test status
Simulation time 201676631 ps
CPU time 2.67 seconds
Started Jun 10 05:35:24 PM PDT 24
Finished Jun 10 05:35:28 PM PDT 24
Peak memory 222440 kb
Host smart-f19cb81f-c61c-4efb-8ca3-baa7e9c2c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229881989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2229881989
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.4165317116
Short name T432
Test name
Test status
Simulation time 24873001 ps
CPU time 0.77 seconds
Started Jun 10 05:35:26 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 205948 kb
Host smart-7d55bb80-5106-4c4b-9985-8776fd49c64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165317116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4165317116
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3085350890
Short name T160
Test name
Test status
Simulation time 142660865 ps
CPU time 5.07 seconds
Started Jun 10 05:29:37 PM PDT 24
Finished Jun 10 05:29:43 PM PDT 24
Peak memory 214984 kb
Host smart-6c681069-ecac-46f2-b94e-4d776ba87c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085350890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3085350890
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3281969228
Short name T128
Test name
Test status
Simulation time 67396160 ps
CPU time 4.21 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:46 PM PDT 24
Peak memory 214340 kb
Host smart-672bd59a-95c4-4eb6-b365-5d25f1c56b47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281969228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3281969228
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.242112863
Short name T247
Test name
Test status
Simulation time 2418512429 ps
CPU time 24.45 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:31 PM PDT 24
Peak memory 215964 kb
Host smart-6111eb48-af19-430a-b033-dcb39c46999c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242112863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.242112863
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4124395456
Short name T242
Test name
Test status
Simulation time 93345980 ps
CPU time 4.46 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 222480 kb
Host smart-37680493-bb44-4948-b5ae-995b5867764b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124395456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4124395456
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1298655425
Short name T590
Test name
Test status
Simulation time 187378963 ps
CPU time 4.11 seconds
Started Jun 10 05:36:43 PM PDT 24
Finished Jun 10 05:36:48 PM PDT 24
Peak memory 214244 kb
Host smart-58fdea9a-381e-4a38-9df0-77669a63cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298655425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1298655425
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2995979259
Short name T39
Test name
Test status
Simulation time 84238214 ps
CPU time 1.94 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:00 PM PDT 24
Peak memory 210092 kb
Host smart-d49f5073-d0a8-4f86-bb19-428e7e6db10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995979259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2995979259
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2526311503
Short name T217
Test name
Test status
Simulation time 2990052339 ps
CPU time 35.93 seconds
Started Jun 10 05:37:20 PM PDT 24
Finished Jun 10 05:37:56 PM PDT 24
Peak memory 214384 kb
Host smart-da270e96-c115-44d8-ab06-a79d2f3cea90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526311503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2526311503
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.793399039
Short name T151
Test name
Test status
Simulation time 107645843 ps
CPU time 4.22 seconds
Started Jun 10 05:29:34 PM PDT 24
Finished Jun 10 05:29:38 PM PDT 24
Peak memory 205624 kb
Host smart-51e1ef84-597e-43b0-8b36-d7b667c89ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793399039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
793399039
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2528042000
Short name T238
Test name
Test status
Simulation time 930982572 ps
CPU time 24.41 seconds
Started Jun 10 05:34:48 PM PDT 24
Finished Jun 10 05:35:13 PM PDT 24
Peak memory 214240 kb
Host smart-9250b83d-e071-4993-91d2-d853d19a77a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528042000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2528042000
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2567101203
Short name T124
Test name
Test status
Simulation time 48442385 ps
CPU time 1.96 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 214256 kb
Host smart-a4f119d8-1362-44c9-ba74-7caeea0f8b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567101203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2567101203
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.668168575
Short name T399
Test name
Test status
Simulation time 2026874486 ps
CPU time 20.4 seconds
Started Jun 10 05:35:23 PM PDT 24
Finished Jun 10 05:35:44 PM PDT 24
Peak memory 216152 kb
Host smart-5f4325da-f060-4d5d-9207-f8b7d500c9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668168575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.668168575
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.256069900
Short name T103
Test name
Test status
Simulation time 180742993 ps
CPU time 2.38 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 214172 kb
Host smart-592582d9-f2b0-4ec5-b687-a968756b54e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256069900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.256069900
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1955374029
Short name T54
Test name
Test status
Simulation time 235161209 ps
CPU time 1.53 seconds
Started Jun 10 05:35:17 PM PDT 24
Finished Jun 10 05:35:19 PM PDT 24
Peak memory 209468 kb
Host smart-03bb1ef3-e8f6-454f-b19c-c0d065a86b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955374029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1955374029
Directory /workspace/9.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3967822113
Short name T143
Test name
Test status
Simulation time 178081249 ps
CPU time 5.47 seconds
Started Jun 10 05:36:35 PM PDT 24
Finished Jun 10 05:36:41 PM PDT 24
Peak memory 222592 kb
Host smart-41dd15a1-28ed-4cfc-933e-ef9f21bed83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967822113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3967822113
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3706268590
Short name T142
Test name
Test status
Simulation time 404677374 ps
CPU time 5.56 seconds
Started Jun 10 05:35:08 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 218464 kb
Host smart-a49e660e-d58b-4128-b4f7-32442707c280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706268590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3706268590
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2735711343
Short name T179
Test name
Test status
Simulation time 1043712046 ps
CPU time 35.95 seconds
Started Jun 10 05:35:54 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 216880 kb
Host smart-5dba2e65-64fd-491f-bb06-a8bc62fceafe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735711343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2735711343
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4282793911
Short name T416
Test name
Test status
Simulation time 352193673 ps
CPU time 11.3 seconds
Started Jun 10 05:34:55 PM PDT 24
Finished Jun 10 05:35:07 PM PDT 24
Peak memory 214348 kb
Host smart-570b7051-ce10-40b8-8932-d00eb7777e05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282793911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4282793911
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3096733150
Short name T6
Test name
Test status
Simulation time 1044085226 ps
CPU time 18 seconds
Started Jun 10 05:36:54 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 222648 kb
Host smart-896e31a5-6044-41f1-a163-3b25e4183fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096733150 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3096733150
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1709882961
Short name T263
Test name
Test status
Simulation time 241808973 ps
CPU time 4.53 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 222432 kb
Host smart-b63c88b5-75ac-4b61-bdd4-43f05ea4e20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709882961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1709882961
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.486842467
Short name T144
Test name
Test status
Simulation time 667541374 ps
CPU time 4.71 seconds
Started Jun 10 05:35:54 PM PDT 24
Finished Jun 10 05:35:59 PM PDT 24
Peak memory 217400 kb
Host smart-62783230-debb-442f-a870-4564554a6aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486842467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.486842467
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3848251930
Short name T243
Test name
Test status
Simulation time 7996317518 ps
CPU time 29.88 seconds
Started Jun 10 05:36:00 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 222956 kb
Host smart-349241d8-86f8-4fd5-9c9b-309cb781b995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848251930 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3848251930
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2635674518
Short name T156
Test name
Test status
Simulation time 1921033306 ps
CPU time 7.87 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 213796 kb
Host smart-f5120aee-55f8-49b9-9f82-3be6394d11b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635674518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2635674518
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3600638779
Short name T158
Test name
Test status
Simulation time 114178582 ps
CPU time 3.98 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:18 PM PDT 24
Peak memory 205632 kb
Host smart-3b572de9-fd18-495a-8522-929c5ccb23f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600638779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3600638779
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3415648233
Short name T31
Test name
Test status
Simulation time 374956315 ps
CPU time 3.7 seconds
Started Jun 10 05:37:18 PM PDT 24
Finished Jun 10 05:37:22 PM PDT 24
Peak memory 209676 kb
Host smart-305b7996-6047-4e56-9066-d69a467b810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415648233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3415648233
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1901887285
Short name T281
Test name
Test status
Simulation time 132243881 ps
CPU time 3.99 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:35:54 PM PDT 24
Peak memory 214324 kb
Host smart-2c633455-ce09-4522-b3a7-60d591f3db92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901887285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1901887285
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2445611668
Short name T202
Test name
Test status
Simulation time 5575128294 ps
CPU time 54.17 seconds
Started Jun 10 05:35:59 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 217516 kb
Host smart-71bcd44f-0017-4a6e-9e64-aa18e3990f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445611668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2445611668
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.382652061
Short name T212
Test name
Test status
Simulation time 5191378206 ps
CPU time 58.09 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 215724 kb
Host smart-f8e67a46-9ea4-4c2e-9f69-31c397c689d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382652061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.382652061
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.872371003
Short name T418
Test name
Test status
Simulation time 65463566 ps
CPU time 4.73 seconds
Started Jun 10 05:35:03 PM PDT 24
Finished Jun 10 05:35:08 PM PDT 24
Peak memory 215828 kb
Host smart-1f62d31d-478a-47a5-9818-3838b4491e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872371003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.872371003
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3562940501
Short name T161
Test name
Test status
Simulation time 269462778 ps
CPU time 6.88 seconds
Started Jun 10 05:29:30 PM PDT 24
Finished Jun 10 05:29:37 PM PDT 24
Peak memory 205492 kb
Host smart-78d4c33a-5e75-41de-8724-83f9bd518a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562940501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3562940501
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4223935041
Short name T139
Test name
Test status
Simulation time 516455167 ps
CPU time 5.31 seconds
Started Jun 10 05:35:36 PM PDT 24
Finished Jun 10 05:35:41 PM PDT 24
Peak memory 217936 kb
Host smart-b9bbc432-03e9-4a05-914c-2d9568377b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223935041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4223935041
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1403144687
Short name T619
Test name
Test status
Simulation time 118815903 ps
CPU time 4.4 seconds
Started Jun 10 05:34:47 PM PDT 24
Finished Jun 10 05:34:52 PM PDT 24
Peak memory 222432 kb
Host smart-1a48cbcf-32d8-404a-8bb9-eea04071f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403144687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1403144687
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.560520172
Short name T306
Test name
Test status
Simulation time 185232687 ps
CPU time 2.23 seconds
Started Jun 10 05:35:47 PM PDT 24
Finished Jun 10 05:35:50 PM PDT 24
Peak memory 218440 kb
Host smart-a4edcc17-d4c1-4477-8f8e-9ec10544a600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560520172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.560520172
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1134938883
Short name T368
Test name
Test status
Simulation time 45269507 ps
CPU time 2.63 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:48 PM PDT 24
Peak memory 209816 kb
Host smart-ce062a7c-325d-4f75-bd18-fc6f5d2f4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134938883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1134938883
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.847215823
Short name T34
Test name
Test status
Simulation time 167132774 ps
CPU time 6.79 seconds
Started Jun 10 05:34:50 PM PDT 24
Finished Jun 10 05:34:57 PM PDT 24
Peak memory 214260 kb
Host smart-d1d68080-42f4-4fc1-89c9-0c474404a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847215823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.847215823
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1375177512
Short name T341
Test name
Test status
Simulation time 3623880882 ps
CPU time 25.03 seconds
Started Jun 10 05:36:09 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 216380 kb
Host smart-f2c5bac0-7023-4367-9f07-46bba4d96b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375177512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1375177512
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.882176608
Short name T325
Test name
Test status
Simulation time 137693725 ps
CPU time 1.99 seconds
Started Jun 10 05:37:35 PM PDT 24
Finished Jun 10 05:37:38 PM PDT 24
Peak memory 214284 kb
Host smart-0c1cb303-c09f-4f1b-87fb-f0320f709d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882176608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.882176608
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3731106828
Short name T44
Test name
Test status
Simulation time 3127737852 ps
CPU time 56.44 seconds
Started Jun 10 05:37:27 PM PDT 24
Finished Jun 10 05:38:23 PM PDT 24
Peak memory 222468 kb
Host smart-cf6d1f6c-02c3-4ea3-a9a9-3b8d5336904b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731106828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3731106828
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3016783908
Short name T198
Test name
Test status
Simulation time 3186555371 ps
CPU time 32.12 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 208796 kb
Host smart-854dabfb-d3d1-4c8a-aec2-92eae7fa3520
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016783908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3016783908
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4018231671
Short name T153
Test name
Test status
Simulation time 417905783 ps
CPU time 2.69 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 213812 kb
Host smart-76dbf0d5-5fea-4722-ad60-5ee82877d38d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018231671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4018231671
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3309185763
Short name T164
Test name
Test status
Simulation time 216417380 ps
CPU time 3.5 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 215096 kb
Host smart-9c2f7a5d-86f0-4350-a5b3-ac16a670ee72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309185763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3309185763
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.90558761
Short name T155
Test name
Test status
Simulation time 110498338 ps
CPU time 4.16 seconds
Started Jun 10 05:29:57 PM PDT 24
Finished Jun 10 05:30:01 PM PDT 24
Peak memory 215116 kb
Host smart-b18a21f7-d877-45f7-8a98-3c44b7e45877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90558761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.90558761
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.715977546
Short name T43
Test name
Test status
Simulation time 507182621 ps
CPU time 12.94 seconds
Started Jun 10 05:34:44 PM PDT 24
Finished Jun 10 05:34:57 PM PDT 24
Peak memory 238164 kb
Host smart-589f5189-4115-4a9d-87bb-e1441dc3cca4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715977546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.715977546
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2316482733
Short name T61
Test name
Test status
Simulation time 74800601 ps
CPU time 4.25 seconds
Started Jun 10 05:35:52 PM PDT 24
Finished Jun 10 05:35:57 PM PDT 24
Peak memory 217992 kb
Host smart-ab9a04f0-0246-41a7-a814-1d9a2ba0d8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316482733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2316482733
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3328484163
Short name T141
Test name
Test status
Simulation time 185693481 ps
CPU time 4.38 seconds
Started Jun 10 05:34:57 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 222736 kb
Host smart-bfafd835-4a94-475b-a161-5f9f9babe1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328484163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3328484163
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2500630349
Short name T297
Test name
Test status
Simulation time 128011458 ps
CPU time 6.9 seconds
Started Jun 10 05:34:37 PM PDT 24
Finished Jun 10 05:34:44 PM PDT 24
Peak memory 214364 kb
Host smart-4d562f23-8389-41bc-82a6-e1e2e29a2a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500630349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2500630349
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1530790656
Short name T56
Test name
Test status
Simulation time 160619937 ps
CPU time 4.56 seconds
Started Jun 10 05:34:43 PM PDT 24
Finished Jun 10 05:34:48 PM PDT 24
Peak memory 210516 kb
Host smart-b6e9fcbf-e8f6-42fb-8ee2-b09b9fb191a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530790656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1530790656
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4109028035
Short name T291
Test name
Test status
Simulation time 283721065 ps
CPU time 4.41 seconds
Started Jun 10 05:34:48 PM PDT 24
Finished Jun 10 05:34:53 PM PDT 24
Peak memory 214320 kb
Host smart-ce1137f3-1ba7-472e-ab91-c4931ed63a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109028035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4109028035
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3605236849
Short name T337
Test name
Test status
Simulation time 192874715 ps
CPU time 2.89 seconds
Started Jun 10 05:34:46 PM PDT 24
Finished Jun 10 05:34:49 PM PDT 24
Peak memory 206912 kb
Host smart-326f101e-b171-4c48-a901-c7590c113302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605236849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3605236849
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.382205488
Short name T287
Test name
Test status
Simulation time 387706837 ps
CPU time 7.6 seconds
Started Jun 10 05:35:24 PM PDT 24
Finished Jun 10 05:35:31 PM PDT 24
Peak memory 209388 kb
Host smart-c93f7f01-1025-4e64-bb40-4aae11c7f93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382205488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.382205488
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1059008804
Short name T45
Test name
Test status
Simulation time 330361774 ps
CPU time 5.16 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 220180 kb
Host smart-c217a269-439b-44d7-8d9e-a86b3ec81e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059008804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1059008804
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.804609223
Short name T111
Test name
Test status
Simulation time 1802041430 ps
CPU time 20.37 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 222548 kb
Host smart-a013d000-8f98-4b2f-94b8-3a50a7fc3af3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804609223 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.804609223
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.51901203
Short name T908
Test name
Test status
Simulation time 52237042 ps
CPU time 2.69 seconds
Started Jun 10 05:35:39 PM PDT 24
Finished Jun 10 05:35:42 PM PDT 24
Peak memory 214508 kb
Host smart-117f39f9-2414-44d2-be7e-706281a2d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51901203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.51901203
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.3249201389
Short name T354
Test name
Test status
Simulation time 66815381 ps
CPU time 3.1 seconds
Started Jun 10 05:34:51 PM PDT 24
Finished Jun 10 05:34:55 PM PDT 24
Peak memory 207464 kb
Host smart-2a548429-c71a-4639-bdbe-68f045160e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249201389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3249201389
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3325214676
Short name T208
Test name
Test status
Simulation time 621649502 ps
CPU time 3.08 seconds
Started Jun 10 05:36:10 PM PDT 24
Finished Jun 10 05:36:14 PM PDT 24
Peak memory 210248 kb
Host smart-1e15bdda-d441-4c65-9cec-08168bff3873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325214676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3325214676
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.130882615
Short name T867
Test name
Test status
Simulation time 293471944 ps
CPU time 3.89 seconds
Started Jun 10 05:36:08 PM PDT 24
Finished Jun 10 05:36:13 PM PDT 24
Peak memory 208984 kb
Host smart-4b5063d5-2d5f-4544-9e85-6680f274d035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130882615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.130882615
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.860441526
Short name T367
Test name
Test status
Simulation time 695215807 ps
CPU time 18.4 seconds
Started Jun 10 05:36:12 PM PDT 24
Finished Jun 10 05:36:31 PM PDT 24
Peak memory 222540 kb
Host smart-ef56b38f-8d26-4a39-a313-10a0eb655a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860441526 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.860441526
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1492142105
Short name T320
Test name
Test status
Simulation time 70530179 ps
CPU time 2.51 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 214280 kb
Host smart-0915b2fe-fcbf-4767-8e17-ca0e402e8916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492142105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1492142105
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2284226019
Short name T214
Test name
Test status
Simulation time 2364421509 ps
CPU time 15.77 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:36 PM PDT 24
Peak memory 217116 kb
Host smart-05a6100c-8cc6-4bdb-92df-b6a73a8fa588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284226019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2284226019
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.225145445
Short name T216
Test name
Test status
Simulation time 459649019 ps
CPU time 3.96 seconds
Started Jun 10 05:34:58 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 209444 kb
Host smart-f2cb8bb8-7d27-4575-ab15-306ec9b2e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225145445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.225145445
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3657431732
Short name T213
Test name
Test status
Simulation time 41291532 ps
CPU time 2.8 seconds
Started Jun 10 05:36:33 PM PDT 24
Finished Jun 10 05:36:36 PM PDT 24
Peak memory 209488 kb
Host smart-240dfcfa-7adf-4409-9053-fdc07f76d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657431732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3657431732
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3137842826
Short name T303
Test name
Test status
Simulation time 141378429 ps
CPU time 2.35 seconds
Started Jun 10 05:36:44 PM PDT 24
Finished Jun 10 05:36:47 PM PDT 24
Peak memory 214300 kb
Host smart-af821f23-4288-47cf-8a2e-d1b94ca35445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137842826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3137842826
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.434012730
Short name T81
Test name
Test status
Simulation time 44810316 ps
CPU time 3.16 seconds
Started Jun 10 05:36:46 PM PDT 24
Finished Jun 10 05:36:49 PM PDT 24
Peak memory 214416 kb
Host smart-5339cc48-8475-4947-aae0-150d66775b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434012730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.434012730
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2547603178
Short name T342
Test name
Test status
Simulation time 471624331 ps
CPU time 4.07 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:09 PM PDT 24
Peak memory 214448 kb
Host smart-8e111cbe-f3de-421e-9ef2-0b19f6f902e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547603178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2547603178
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3796611204
Short name T1016
Test name
Test status
Simulation time 1434723406 ps
CPU time 5.83 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205668 kb
Host smart-bb731788-6ade-46b8-811c-a416309e1f66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796611204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
796611204
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1388619544
Short name T1023
Test name
Test status
Simulation time 457348956 ps
CPU time 12.2 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 205568 kb
Host smart-c7bfccda-f126-4c36-9d03-7c4213d80a31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388619544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
388619544
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3069391821
Short name T975
Test name
Test status
Simulation time 99380866 ps
CPU time 1.44 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205612 kb
Host smart-1859838a-4d29-40e2-9981-9c1d48202e26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069391821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
069391821
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2838550778
Short name T985
Test name
Test status
Simulation time 184478613 ps
CPU time 2.26 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 213816 kb
Host smart-3e259140-ce91-4aae-a658-bd1827dc4bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838550778 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2838550778
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2738287009
Short name T1084
Test name
Test status
Simulation time 146855406 ps
CPU time 0.92 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:03 PM PDT 24
Peak memory 205372 kb
Host smart-ac21f9d5-e307-48bb-8ad5-cdc90df60875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738287009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2738287009
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.940384791
Short name T951
Test name
Test status
Simulation time 12181830 ps
CPU time 0.86 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 205256 kb
Host smart-d5c2f26f-1f7f-4d66-97fc-8b87b59737e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940384791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.940384791
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3425028704
Short name T969
Test name
Test status
Simulation time 271684615 ps
CPU time 1.53 seconds
Started Jun 10 05:29:37 PM PDT 24
Finished Jun 10 05:29:39 PM PDT 24
Peak memory 205628 kb
Host smart-efd82cfe-4658-4f0e-9d81-961fc10b9076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425028704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3425028704
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1393805092
Short name T972
Test name
Test status
Simulation time 603950849 ps
CPU time 3.17 seconds
Started Jun 10 05:29:22 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 214180 kb
Host smart-c7fe266c-2c6e-4b2c-bccc-41cc06e4f660
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393805092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1393805092
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1690796777
Short name T947
Test name
Test status
Simulation time 808271476 ps
CPU time 14.62 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 214288 kb
Host smart-9d638d88-3f4c-4101-a0a7-f3252a789320
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690796777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1690796777
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3987029330
Short name T946
Test name
Test status
Simulation time 191350619 ps
CPU time 3.54 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 216352 kb
Host smart-1d97156f-c598-480b-ae41-e9a4ce553362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987029330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3987029330
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1781391
Short name T148
Test name
Test status
Simulation time 245301890 ps
CPU time 9.05 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 215204 kb
Host smart-fa2fc787-2b92-4066-99a9-4e3af4a76238
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.1781391
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2324900239
Short name T1048
Test name
Test status
Simulation time 734772510 ps
CPU time 10.64 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 205592 kb
Host smart-41f1c057-334e-4092-a50f-61f51e22c828
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324900239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
324900239
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4130924357
Short name T1080
Test name
Test status
Simulation time 132502514 ps
CPU time 6.32 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:29:03 PM PDT 24
Peak memory 205652 kb
Host smart-42c15be8-1f0d-4d08-9d69-7ddafd393a20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130924357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
130924357
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2904853496
Short name T939
Test name
Test status
Simulation time 19888552 ps
CPU time 1.19 seconds
Started Jun 10 05:29:47 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 205624 kb
Host smart-36d90380-8785-4aa1-8095-b3d3d35da2e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904853496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
904853496
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3960095214
Short name T999
Test name
Test status
Simulation time 108295054 ps
CPU time 1.42 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205692 kb
Host smart-0ad016e4-28f6-42ca-9f4c-26db54c0eaab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960095214 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3960095214
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2209691399
Short name T992
Test name
Test status
Simulation time 231265526 ps
CPU time 1.22 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 205612 kb
Host smart-da283b57-9dd8-4c0f-9767-5b6564dc66c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209691399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2209691399
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.964328032
Short name T964
Test name
Test status
Simulation time 45742560 ps
CPU time 0.71 seconds
Started Jun 10 05:29:30 PM PDT 24
Finished Jun 10 05:29:31 PM PDT 24
Peak memory 205312 kb
Host smart-41322885-36f6-40de-b7bf-2fbda2785e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964328032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.964328032
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3763116827
Short name T986
Test name
Test status
Simulation time 124822825 ps
CPU time 4.66 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205628 kb
Host smart-3dafb0ba-f81d-4fb3-b1ab-5416fc1fe64e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763116827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3763116827
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4217373806
Short name T982
Test name
Test status
Simulation time 364607058 ps
CPU time 3.16 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 214152 kb
Host smart-e735595d-5c48-4713-8360-d24b2f811620
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217373806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4217373806
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2007546277
Short name T1087
Test name
Test status
Simulation time 1383720272 ps
CPU time 13.6 seconds
Started Jun 10 05:29:28 PM PDT 24
Finished Jun 10 05:29:42 PM PDT 24
Peak memory 214116 kb
Host smart-589b0caf-637d-4b74-bd7d-958d85d3786a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007546277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2007546277
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1208602679
Short name T1082
Test name
Test status
Simulation time 126904421 ps
CPU time 4.43 seconds
Started Jun 10 05:29:23 PM PDT 24
Finished Jun 10 05:29:27 PM PDT 24
Peak memory 213876 kb
Host smart-f7c0f7f9-6d67-4cae-b6b0-7cf4bad28e28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208602679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1208602679
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.155056148
Short name T987
Test name
Test status
Simulation time 98549412 ps
CPU time 1.45 seconds
Started Jun 10 05:29:48 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 213880 kb
Host smart-1e1c7e20-5b3d-4abd-905e-ed9bc4864756
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155056148 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.155056148
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2607103747
Short name T1051
Test name
Test status
Simulation time 61099495 ps
CPU time 1.03 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 205660 kb
Host smart-e844fd49-90e8-4e5d-9037-180519a51493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607103747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2607103747
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2676044673
Short name T968
Test name
Test status
Simulation time 46775106 ps
CPU time 0.75 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 205456 kb
Host smart-c60340c2-f45f-47b7-8357-0e599106bd60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676044673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2676044673
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2265560405
Short name T1054
Test name
Test status
Simulation time 135730033 ps
CPU time 3.95 seconds
Started Jun 10 05:29:46 PM PDT 24
Finished Jun 10 05:29:51 PM PDT 24
Peak memory 205544 kb
Host smart-05f26338-2fa2-47a6-9c00-f0c05ddfc1ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265560405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2265560405
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.319245890
Short name T1017
Test name
Test status
Simulation time 237868619 ps
CPU time 3.77 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:27 PM PDT 24
Peak memory 214192 kb
Host smart-9528e5e7-df0f-4b5d-b5bb-bad5a32057ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319245890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.319245890
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1957826824
Short name T1012
Test name
Test status
Simulation time 413909880 ps
CPU time 10.43 seconds
Started Jun 10 05:29:09 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 214116 kb
Host smart-29cb0a05-e715-4bf6-b93b-7eab3d803a25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957826824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1957826824
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2585870900
Short name T1040
Test name
Test status
Simulation time 60740111 ps
CPU time 2.29 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 205688 kb
Host smart-68f87a8c-d3d3-4c7e-be38-7601ed9597f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585870900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2585870900
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.56359454
Short name T1067
Test name
Test status
Simulation time 28771107 ps
CPU time 1.2 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 205712 kb
Host smart-4877abfe-81f5-491b-9da1-64193d862959
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56359454 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.56359454
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2239099595
Short name T1085
Test name
Test status
Simulation time 21894280 ps
CPU time 1.03 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 205328 kb
Host smart-ace4cb81-151a-4ff6-9467-ec0aa92009bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239099595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2239099595
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3458933475
Short name T1007
Test name
Test status
Simulation time 21529679 ps
CPU time 0.71 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 205304 kb
Host smart-14512ab4-b520-4b4d-a0cd-e285cd5e96a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458933475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3458933475
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.982860360
Short name T133
Test name
Test status
Simulation time 119711311 ps
CPU time 2.33 seconds
Started Jun 10 05:29:45 PM PDT 24
Finished Jun 10 05:29:47 PM PDT 24
Peak memory 205604 kb
Host smart-8f6f7d00-1d84-4645-a795-89b1b6dfde1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982860360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.982860360
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.227832024
Short name T107
Test name
Test status
Simulation time 261147131 ps
CPU time 2.46 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 214180 kb
Host smart-bea04fbd-7c86-4331-b149-6b770505b197
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227832024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.227832024
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3644489697
Short name T1049
Test name
Test status
Simulation time 234729164 ps
CPU time 5.68 seconds
Started Jun 10 05:29:27 PM PDT 24
Finished Jun 10 05:29:33 PM PDT 24
Peak memory 214276 kb
Host smart-295d4fa6-4867-4581-bd6b-dfb4ec6d7114
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644489697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3644489697
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2721831632
Short name T973
Test name
Test status
Simulation time 428974882 ps
CPU time 4.29 seconds
Started Jun 10 05:29:09 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 213816 kb
Host smart-4446b6e5-f24c-4d9a-8bab-0e0f975b263e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721831632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2721831632
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2309279064
Short name T1060
Test name
Test status
Simulation time 40388266 ps
CPU time 1.29 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205632 kb
Host smart-5e5cf24b-fc1d-4da9-b8fc-f2d3298e12cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309279064 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2309279064
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1071864545
Short name T131
Test name
Test status
Simulation time 45212075 ps
CPU time 1.04 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205520 kb
Host smart-17c1079d-d338-4c2f-b2e1-74d028490c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071864545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1071864545
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2913820902
Short name T1077
Test name
Test status
Simulation time 12039174 ps
CPU time 0.82 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 205324 kb
Host smart-838a55e2-06e9-451e-9f13-1fb4a4e37f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913820902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2913820902
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3191070589
Short name T970
Test name
Test status
Simulation time 48091172 ps
CPU time 2.17 seconds
Started Jun 10 05:29:17 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205580 kb
Host smart-84d16878-b901-4efd-af68-e31870ece084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191070589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3191070589
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.408273010
Short name T1001
Test name
Test status
Simulation time 450349730 ps
CPU time 2.38 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:21 PM PDT 24
Peak memory 214184 kb
Host smart-cca170f0-cc4a-4172-8e67-fa3cff3b2e96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408273010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.408273010
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2215938307
Short name T1057
Test name
Test status
Simulation time 430879984 ps
CPU time 14.15 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 214360 kb
Host smart-529b57df-c836-48f4-bbc1-7c329ae23756
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215938307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2215938307
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2285508543
Short name T957
Test name
Test status
Simulation time 79146168 ps
CPU time 2.45 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:08 PM PDT 24
Peak memory 213724 kb
Host smart-c991a33b-3fb0-4034-bc8d-880cbed0aa4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285508543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2285508543
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1468156840
Short name T983
Test name
Test status
Simulation time 54257280 ps
CPU time 3.18 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 213844 kb
Host smart-c3f1b154-7525-49c7-8e8c-3b2a05268e81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468156840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1468156840
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3393003672
Short name T1066
Test name
Test status
Simulation time 76854045 ps
CPU time 1.36 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 213840 kb
Host smart-27c14494-3ef5-4aa1-82bb-b85bed69155a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393003672 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3393003672
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1983677292
Short name T978
Test name
Test status
Simulation time 40596946 ps
CPU time 1 seconds
Started Jun 10 05:29:42 PM PDT 24
Finished Jun 10 05:29:43 PM PDT 24
Peak memory 205616 kb
Host smart-2f77b7cc-e58e-45bd-8173-fd2a7067935b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983677292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1983677292
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4187045490
Short name T1055
Test name
Test status
Simulation time 16719797 ps
CPU time 0.75 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205324 kb
Host smart-80d6120e-1347-44ad-9ca9-a728c65efe0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187045490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4187045490
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4166032498
Short name T1081
Test name
Test status
Simulation time 222390206 ps
CPU time 2.43 seconds
Started Jun 10 05:29:38 PM PDT 24
Finished Jun 10 05:29:46 PM PDT 24
Peak memory 205564 kb
Host smart-7f195fc9-dc3f-467d-9668-ab71c9a6e95d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166032498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4166032498
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1220996948
Short name T1078
Test name
Test status
Simulation time 770333859 ps
CPU time 7.52 seconds
Started Jun 10 05:29:09 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 220308 kb
Host smart-b582fa25-083f-4cca-9cc1-8d8e817b1e65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220996948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1220996948
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1281952771
Short name T922
Test name
Test status
Simulation time 121650554 ps
CPU time 3.2 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 213836 kb
Host smart-99d744dd-34ba-4076-97f7-43e7ac08189b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281952771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1281952771
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1700036300
Short name T380
Test name
Test status
Simulation time 31772556 ps
CPU time 1.41 seconds
Started Jun 10 05:29:29 PM PDT 24
Finished Jun 10 05:29:34 PM PDT 24
Peak memory 213916 kb
Host smart-55a21030-93d0-479a-9f58-928c2e01a056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700036300 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1700036300
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2873397100
Short name T138
Test name
Test status
Simulation time 17452998 ps
CPU time 0.9 seconds
Started Jun 10 05:29:39 PM PDT 24
Finished Jun 10 05:29:40 PM PDT 24
Peak memory 205448 kb
Host smart-913bfb53-58fb-4efb-8ea1-d5ce168e69ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873397100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2873397100
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1818435531
Short name T923
Test name
Test status
Simulation time 18072217 ps
CPU time 0.79 seconds
Started Jun 10 05:29:57 PM PDT 24
Finished Jun 10 05:29:58 PM PDT 24
Peak memory 205296 kb
Host smart-522f5f99-ade8-4b7f-938e-9af3fb1445d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818435531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1818435531
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.334036353
Short name T132
Test name
Test status
Simulation time 93738965 ps
CPU time 2.48 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 205732 kb
Host smart-cb5e4fe0-4459-492d-bee2-61d35bb574d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334036353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.334036353
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3908803026
Short name T940
Test name
Test status
Simulation time 42504120 ps
CPU time 1.4 seconds
Started Jun 10 05:29:10 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 214180 kb
Host smart-c86fe12a-8840-4d1a-a7d5-178ee02b2fdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908803026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3908803026
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1332732325
Short name T941
Test name
Test status
Simulation time 566349420 ps
CPU time 7.74 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 214192 kb
Host smart-8c0b56ee-34bb-47f1-9d83-d6964c4513a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332732325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1332732325
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.54024508
Short name T933
Test name
Test status
Simulation time 511447437 ps
CPU time 5.33 seconds
Started Jun 10 05:29:10 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 213768 kb
Host smart-6ea1aca4-ac15-472e-8ebb-6ea318e3938c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54024508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.54024508
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2762544003
Short name T147
Test name
Test status
Simulation time 1815609763 ps
CPU time 6.61 seconds
Started Jun 10 05:29:40 PM PDT 24
Finished Jun 10 05:29:47 PM PDT 24
Peak memory 213808 kb
Host smart-d05aae8c-1e75-439a-93ff-fdb7a5179ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762544003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2762544003
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3997737206
Short name T149
Test name
Test status
Simulation time 166717227 ps
CPU time 1.99 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 214052 kb
Host smart-b153e54b-4768-478d-9465-1fa9ce9d94d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997737206 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3997737206
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.328071231
Short name T1010
Test name
Test status
Simulation time 14996284 ps
CPU time 1.15 seconds
Started Jun 10 05:29:46 PM PDT 24
Finished Jun 10 05:29:48 PM PDT 24
Peak memory 205656 kb
Host smart-095b29c7-63f8-40b0-a77f-13a7b8749324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328071231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.328071231
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2712126115
Short name T926
Test name
Test status
Simulation time 36940863 ps
CPU time 0.71 seconds
Started Jun 10 05:29:35 PM PDT 24
Finished Jun 10 05:29:36 PM PDT 24
Peak memory 205316 kb
Host smart-43e2ffba-8b20-4b95-8322-64efe8d54294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712126115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2712126115
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3310170500
Short name T1089
Test name
Test status
Simulation time 24336738 ps
CPU time 1.46 seconds
Started Jun 10 05:29:49 PM PDT 24
Finished Jun 10 05:29:51 PM PDT 24
Peak memory 205560 kb
Host smart-0793713f-c0d0-4627-b99d-60c607e938c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310170500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3310170500
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.300304441
Short name T1034
Test name
Test status
Simulation time 75879856 ps
CPU time 1.64 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 214096 kb
Host smart-2178cfbc-d63d-48d7-b8f9-10c0ba61f958
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300304441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.300304441
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.31258061
Short name T104
Test name
Test status
Simulation time 792173733 ps
CPU time 10.15 seconds
Started Jun 10 05:29:17 PM PDT 24
Finished Jun 10 05:29:28 PM PDT 24
Peak memory 214240 kb
Host smart-d71a6cd0-ad1c-42ed-a987-c4bd4fe686c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31258061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_shadow_reg_errors_with_csr_rw.31258061
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4228460874
Short name T925
Test name
Test status
Simulation time 127132280 ps
CPU time 3.65 seconds
Started Jun 10 05:29:31 PM PDT 24
Finished Jun 10 05:29:35 PM PDT 24
Peak memory 213812 kb
Host smart-0a338e1b-9226-4715-a704-20776988ec2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228460874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4228460874
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1198069521
Short name T994
Test name
Test status
Simulation time 172610677 ps
CPU time 1.53 seconds
Started Jun 10 05:29:27 PM PDT 24
Finished Jun 10 05:29:34 PM PDT 24
Peak memory 213940 kb
Host smart-484a266e-6ced-4d65-a8e4-583a277196c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198069521 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1198069521
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.780161624
Short name T962
Test name
Test status
Simulation time 27630297 ps
CPU time 1.48 seconds
Started Jun 10 05:29:47 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 205512 kb
Host smart-018c8e4d-2e0f-4425-9f77-19996fa48a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780161624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.780161624
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2400248050
Short name T1024
Test name
Test status
Simulation time 8654784 ps
CPU time 0.78 seconds
Started Jun 10 05:29:51 PM PDT 24
Finished Jun 10 05:29:52 PM PDT 24
Peak memory 205300 kb
Host smart-af9b5c69-b4d2-4b4a-912e-09b14b250160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400248050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2400248050
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.764974022
Short name T1076
Test name
Test status
Simulation time 339932999 ps
CPU time 2.96 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 205612 kb
Host smart-441ee2a7-f992-4b00-9fc0-aed4c0ccd143
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764974022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.764974022
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.504273137
Short name T1063
Test name
Test status
Simulation time 241584849 ps
CPU time 2.44 seconds
Started Jun 10 05:29:34 PM PDT 24
Finished Jun 10 05:29:37 PM PDT 24
Peak memory 214152 kb
Host smart-b5a958b5-6d65-4667-9d49-d5cd8a05af0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504273137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.504273137
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3503606184
Short name T950
Test name
Test status
Simulation time 138629084 ps
CPU time 7.52 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:21 PM PDT 24
Peak memory 220356 kb
Host smart-1555f7ad-6fd1-41f4-8e76-ebcc52dea51f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503606184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3503606184
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3637027052
Short name T1061
Test name
Test status
Simulation time 131711017 ps
CPU time 1.57 seconds
Started Jun 10 05:29:48 PM PDT 24
Finished Jun 10 05:29:50 PM PDT 24
Peak memory 213800 kb
Host smart-593bdb84-642f-479c-aa95-a31137aeadb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637027052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3637027052
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4230791536
Short name T152
Test name
Test status
Simulation time 371602048 ps
CPU time 4.23 seconds
Started Jun 10 05:29:44 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 213772 kb
Host smart-220e036d-160a-4aa3-b6b8-e1a2a9df7f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230791536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.4230791536
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2786592522
Short name T961
Test name
Test status
Simulation time 60829053 ps
CPU time 1.44 seconds
Started Jun 10 05:29:44 PM PDT 24
Finished Jun 10 05:29:46 PM PDT 24
Peak memory 213988 kb
Host smart-6d040eaf-d3c9-47a4-a341-c2123a88af85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786592522 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2786592522
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1747577384
Short name T1064
Test name
Test status
Simulation time 27171544 ps
CPU time 1.23 seconds
Started Jun 10 05:29:15 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 205620 kb
Host smart-d530cbe7-f0cd-47ae-a41e-974841e03a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747577384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1747577384
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2296471381
Short name T1002
Test name
Test status
Simulation time 34329835 ps
CPU time 0.79 seconds
Started Jun 10 05:29:34 PM PDT 24
Finished Jun 10 05:29:35 PM PDT 24
Peak memory 205300 kb
Host smart-d068c41c-e4ae-4e10-943e-bb7c97129651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296471381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2296471381
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1262904023
Short name T136
Test name
Test status
Simulation time 157666324 ps
CPU time 2.53 seconds
Started Jun 10 05:29:41 PM PDT 24
Finished Jun 10 05:29:44 PM PDT 24
Peak memory 205600 kb
Host smart-4be24473-0164-42d3-96f0-aedf4b79a437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262904023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1262904023
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1697317422
Short name T1056
Test name
Test status
Simulation time 126121170 ps
CPU time 1.85 seconds
Started Jun 10 05:29:47 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 214244 kb
Host smart-6cc5a49f-c1fd-4866-aed8-aad249bbb8f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697317422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1697317422
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2841521278
Short name T990
Test name
Test status
Simulation time 173866366 ps
CPU time 3.08 seconds
Started Jun 10 05:29:45 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 221900 kb
Host smart-e2e9c2b3-5569-4998-87e8-0a2cb9061931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841521278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2841521278
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1223705231
Short name T993
Test name
Test status
Simulation time 185018491 ps
CPU time 4.31 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:18 PM PDT 24
Peak memory 205548 kb
Host smart-7845eab6-7cd5-470a-92e2-ba231636f48c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223705231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1223705231
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2902354099
Short name T931
Test name
Test status
Simulation time 17697923 ps
CPU time 1.19 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205540 kb
Host smart-8acb5bb8-d0ac-4e45-ad10-84b8705edf9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902354099 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2902354099
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3665901351
Short name T1011
Test name
Test status
Simulation time 64519427 ps
CPU time 0.88 seconds
Started Jun 10 05:29:51 PM PDT 24
Finished Jun 10 05:29:53 PM PDT 24
Peak memory 205268 kb
Host smart-6438fa4d-67ca-4421-a9a8-969c27297fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665901351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3665901351
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1518623447
Short name T927
Test name
Test status
Simulation time 10864138 ps
CPU time 0.73 seconds
Started Jun 10 05:29:15 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 205184 kb
Host smart-c9e5690c-12df-4b6b-877c-907088c986c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518623447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1518623447
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3194211598
Short name T1013
Test name
Test status
Simulation time 43613018 ps
CPU time 1.44 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205644 kb
Host smart-b3861871-8064-40b1-9b19-959e2cbe4883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194211598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3194211598
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1037173558
Short name T1044
Test name
Test status
Simulation time 323458049 ps
CPU time 2.92 seconds
Started Jun 10 05:29:50 PM PDT 24
Finished Jun 10 05:29:53 PM PDT 24
Peak memory 214084 kb
Host smart-d57d0ab5-a9b9-49f7-bd19-939471070134
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037173558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1037173558
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2472333315
Short name T1074
Test name
Test status
Simulation time 439262537 ps
CPU time 7.68 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:22 PM PDT 24
Peak memory 214036 kb
Host smart-cca8384a-1ea6-47bc-83c4-af6500de858c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472333315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2472333315
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2345983684
Short name T1027
Test name
Test status
Simulation time 283884670 ps
CPU time 3.86 seconds
Started Jun 10 05:29:43 PM PDT 24
Finished Jun 10 05:29:47 PM PDT 24
Peak memory 217132 kb
Host smart-b1b470a1-f6e8-4a47-a4ac-618f34243b84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345983684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2345983684
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2806118876
Short name T1043
Test name
Test status
Simulation time 3229538129 ps
CPU time 10.87 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:29 PM PDT 24
Peak memory 213904 kb
Host smart-5f2f696a-cccc-4e13-9387-e7cbf0596761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806118876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2806118876
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.530174314
Short name T145
Test name
Test status
Simulation time 182265499 ps
CPU time 1.73 seconds
Started Jun 10 05:29:43 PM PDT 24
Finished Jun 10 05:29:45 PM PDT 24
Peak memory 213832 kb
Host smart-f161c303-35f9-49f5-b45f-8d7395086339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530174314 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.530174314
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2547471604
Short name T135
Test name
Test status
Simulation time 76600964 ps
CPU time 1.06 seconds
Started Jun 10 05:29:48 PM PDT 24
Finished Jun 10 05:29:59 PM PDT 24
Peak memory 205536 kb
Host smart-95212e50-bd1c-4f1f-b266-0733fc4350c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547471604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2547471604
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.36643648
Short name T1073
Test name
Test status
Simulation time 41151738 ps
CPU time 0.82 seconds
Started Jun 10 05:29:51 PM PDT 24
Finished Jun 10 05:29:53 PM PDT 24
Peak memory 204656 kb
Host smart-d332a33a-2758-47a0-ae23-62e9278822c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.36643648
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2317811449
Short name T952
Test name
Test status
Simulation time 94519666 ps
CPU time 2.21 seconds
Started Jun 10 05:30:00 PM PDT 24
Finished Jun 10 05:30:03 PM PDT 24
Peak memory 205608 kb
Host smart-0f2a5cbd-a55f-4e98-b089-edd32a0a0763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317811449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2317811449
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2915310194
Short name T1053
Test name
Test status
Simulation time 110562575 ps
CPU time 1.82 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 214120 kb
Host smart-1fabc877-fd47-4863-baae-30827101f1b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915310194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2915310194
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4236300407
Short name T956
Test name
Test status
Simulation time 665660006 ps
CPU time 13.01 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:31 PM PDT 24
Peak memory 214272 kb
Host smart-d608f8d4-8764-4b17-8102-c6f3b8e2a90a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236300407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4236300407
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2298799804
Short name T1015
Test name
Test status
Simulation time 227614136 ps
CPU time 4.65 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:18 PM PDT 24
Peak memory 216152 kb
Host smart-dd6f0b29-ff91-4ce4-bb97-aa5df8d39054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298799804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2298799804
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2900449750
Short name T1045
Test name
Test status
Simulation time 497441878 ps
CPU time 3.87 seconds
Started Jun 10 05:29:47 PM PDT 24
Finished Jun 10 05:29:51 PM PDT 24
Peak memory 213812 kb
Host smart-4fc6d0c1-a800-4895-b430-d2c8ebf2e3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900449750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2900449750
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4267886550
Short name T1075
Test name
Test status
Simulation time 69024463 ps
CPU time 4.61 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205644 kb
Host smart-ceccd70f-bbfb-4f5a-8507-5a5560ca018c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267886550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
267886550
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.609274076
Short name T988
Test name
Test status
Simulation time 847316133 ps
CPU time 12.68 seconds
Started Jun 10 05:29:31 PM PDT 24
Finished Jun 10 05:29:44 PM PDT 24
Peak memory 205620 kb
Host smart-341c85c7-b291-4981-98fc-192dd00fab45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609274076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.609274076
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.128028559
Short name T976
Test name
Test status
Simulation time 25400341 ps
CPU time 1.18 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 205520 kb
Host smart-5dc78651-8f7d-4050-b85f-749638191847
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128028559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.128028559
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2716678276
Short name T948
Test name
Test status
Simulation time 80389730 ps
CPU time 1.65 seconds
Started Jun 10 05:29:21 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 213920 kb
Host smart-4047ec98-dec4-44b9-a154-532a2c53bf15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716678276 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2716678276
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3801676506
Short name T1065
Test name
Test status
Simulation time 37046692 ps
CPU time 1.18 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205652 kb
Host smart-dc844106-9100-4db4-bd93-b90a01e03f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801676506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3801676506
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1844984641
Short name T979
Test name
Test status
Simulation time 22116063 ps
CPU time 0.68 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:03 PM PDT 24
Peak memory 205268 kb
Host smart-e2720878-c574-4c24-8b2c-a22614b730ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844984641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1844984641
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1598307651
Short name T1042
Test name
Test status
Simulation time 190416626 ps
CPU time 2.74 seconds
Started Jun 10 05:29:29 PM PDT 24
Finished Jun 10 05:29:32 PM PDT 24
Peak memory 205616 kb
Host smart-e2cca06a-bde2-49ce-8a0a-6e57b68f880d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598307651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1598307651
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.283950669
Short name T1030
Test name
Test status
Simulation time 584637522 ps
CPU time 4.6 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:18 PM PDT 24
Peak memory 214112 kb
Host smart-5ebd05d0-1513-4522-9528-3d16b3a9214d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283950669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.283950669
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.695307138
Short name T960
Test name
Test status
Simulation time 395059989 ps
CPU time 14.5 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:35 PM PDT 24
Peak memory 214224 kb
Host smart-08cc12b1-90f6-4626-85d7-479bb283ad47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695307138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.695307138
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2832274814
Short name T169
Test name
Test status
Simulation time 326416434 ps
CPU time 3.37 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 216948 kb
Host smart-bec03f65-bf66-4419-9045-0d431d695953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832274814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2832274814
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2987493948
Short name T996
Test name
Test status
Simulation time 18684994 ps
CPU time 0.84 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205260 kb
Host smart-cbe3cd25-0849-4baa-ad3e-5cdb8e918650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987493948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2987493948
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1498644939
Short name T1069
Test name
Test status
Simulation time 10069529 ps
CPU time 0.83 seconds
Started Jun 10 05:29:17 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205488 kb
Host smart-0d6998f1-9adb-417b-81ee-ea75545ee7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498644939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1498644939
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2339422171
Short name T930
Test name
Test status
Simulation time 10231029 ps
CPU time 0.69 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205224 kb
Host smart-92522768-4eac-436a-b21a-e2fe819a4207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339422171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2339422171
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2137662218
Short name T1004
Test name
Test status
Simulation time 9336114 ps
CPU time 0.78 seconds
Started Jun 10 05:30:04 PM PDT 24
Finished Jun 10 05:30:06 PM PDT 24
Peak memory 205180 kb
Host smart-69f902a8-2125-485a-81be-e14c8987da2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137662218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2137662218
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2662896535
Short name T1005
Test name
Test status
Simulation time 14534283 ps
CPU time 0.89 seconds
Started Jun 10 05:29:34 PM PDT 24
Finished Jun 10 05:29:36 PM PDT 24
Peak memory 205412 kb
Host smart-00de6d0a-4c9f-4400-b757-d1c952f6c040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662896535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2662896535
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3848640810
Short name T958
Test name
Test status
Simulation time 11770462 ps
CPU time 0.77 seconds
Started Jun 10 05:29:51 PM PDT 24
Finished Jun 10 05:29:52 PM PDT 24
Peak memory 205228 kb
Host smart-1c597bd7-1890-4307-b27a-0dddea2f6629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848640810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3848640810
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4071309922
Short name T1008
Test name
Test status
Simulation time 16435679 ps
CPU time 0.89 seconds
Started Jun 10 05:29:15 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 205472 kb
Host smart-0f7e32b3-c9e6-4a67-8912-343930cf9200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071309922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4071309922
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3503993904
Short name T980
Test name
Test status
Simulation time 17896517 ps
CPU time 0.91 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205508 kb
Host smart-83da2b0e-d38d-44d8-8f06-df17beed3aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503993904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3503993904
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3068789216
Short name T1035
Test name
Test status
Simulation time 10613754 ps
CPU time 0.74 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205216 kb
Host smart-dae6a062-4c34-435f-af8f-ae824d6d56b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068789216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3068789216
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3593402664
Short name T981
Test name
Test status
Simulation time 11923947 ps
CPU time 0.72 seconds
Started Jun 10 05:29:42 PM PDT 24
Finished Jun 10 05:29:43 PM PDT 24
Peak memory 205336 kb
Host smart-615befb0-a3e7-4c7c-9dd4-1888bcac6977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593402664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3593402664
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1206759945
Short name T1050
Test name
Test status
Simulation time 822551094 ps
CPU time 10.37 seconds
Started Jun 10 05:29:00 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 205580 kb
Host smart-46cbd1f5-b398-49bf-981b-4a481459c345
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206759945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
206759945
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1802702010
Short name T937
Test name
Test status
Simulation time 257389827 ps
CPU time 14.95 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205620 kb
Host smart-2aeff640-cf39-431e-9a98-7cb4d8c7ada8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802702010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
802702010
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.258685154
Short name T944
Test name
Test status
Simulation time 208530282 ps
CPU time 1.14 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 205584 kb
Host smart-4fc78268-55ff-4edc-ad44-e51b62f9fe5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258685154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.258685154
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2964974914
Short name T1083
Test name
Test status
Simulation time 116201632 ps
CPU time 1.2 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 205688 kb
Host smart-674666fb-767e-4de1-a2c3-925883db9f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964974914 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2964974914
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2362908322
Short name T942
Test name
Test status
Simulation time 119928694 ps
CPU time 1.05 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 205440 kb
Host smart-64b68710-5fb1-4f70-995d-8b105dca1781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362908322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2362908322
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.107573538
Short name T1047
Test name
Test status
Simulation time 38379452 ps
CPU time 0.78 seconds
Started Jun 10 05:29:23 PM PDT 24
Finished Jun 10 05:29:24 PM PDT 24
Peak memory 205340 kb
Host smart-0ff73eab-2296-47e6-af0a-dd11fea77eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107573538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.107573538
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2418345606
Short name T954
Test name
Test status
Simulation time 51541919 ps
CPU time 1.66 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205528 kb
Host smart-b99e0ace-7c2c-4eb9-af39-3666a25f4192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418345606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2418345606
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.999291068
Short name T1029
Test name
Test status
Simulation time 425012048 ps
CPU time 6.29 seconds
Started Jun 10 05:29:45 PM PDT 24
Finished Jun 10 05:29:51 PM PDT 24
Peak memory 214124 kb
Host smart-1c113fa5-4eb6-453f-bbbf-d869b7f6e662
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999291068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.999291068
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2261020968
Short name T1037
Test name
Test status
Simulation time 230893993 ps
CPU time 2.11 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 213832 kb
Host smart-0167df9f-9112-4058-bd9c-f4d78e7a5282
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261020968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2261020968
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.300343229
Short name T1072
Test name
Test status
Simulation time 25045948 ps
CPU time 0.71 seconds
Started Jun 10 05:29:41 PM PDT 24
Finished Jun 10 05:29:42 PM PDT 24
Peak memory 205244 kb
Host smart-5c9cba77-d499-4712-9af1-d0b287bde9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300343229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.300343229
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1184312156
Short name T1031
Test name
Test status
Simulation time 223720548 ps
CPU time 0.79 seconds
Started Jun 10 05:29:56 PM PDT 24
Finished Jun 10 05:29:57 PM PDT 24
Peak memory 205264 kb
Host smart-7c92032b-9833-4235-bf76-28c856e1a1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184312156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1184312156
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4266808203
Short name T936
Test name
Test status
Simulation time 32478966 ps
CPU time 0.87 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205232 kb
Host smart-dec97067-bbae-46f7-83d5-73dd4d8fbee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266808203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4266808203
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2292087932
Short name T938
Test name
Test status
Simulation time 32123200 ps
CPU time 0.68 seconds
Started Jun 10 05:29:38 PM PDT 24
Finished Jun 10 05:29:39 PM PDT 24
Peak memory 205300 kb
Host smart-076bdd22-49b2-41f0-bc18-2b8739cae707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292087932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2292087932
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2377247015
Short name T1058
Test name
Test status
Simulation time 57608093 ps
CPU time 0.82 seconds
Started Jun 10 05:29:57 PM PDT 24
Finished Jun 10 05:29:58 PM PDT 24
Peak memory 205300 kb
Host smart-1e49ac75-0fd9-4313-ba04-6073a0e43457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377247015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2377247015
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2320677516
Short name T965
Test name
Test status
Simulation time 8728492 ps
CPU time 0.82 seconds
Started Jun 10 05:29:51 PM PDT 24
Finished Jun 10 05:29:52 PM PDT 24
Peak memory 205180 kb
Host smart-7509ca09-774e-45c3-b4e9-0b0b09875243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320677516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2320677516
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.390928144
Short name T932
Test name
Test status
Simulation time 10090722 ps
CPU time 0.68 seconds
Started Jun 10 05:29:41 PM PDT 24
Finished Jun 10 05:29:42 PM PDT 24
Peak memory 205200 kb
Host smart-de4c0cde-cf74-4694-bc5d-13f196b4d21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390928144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.390928144
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1443297722
Short name T1086
Test name
Test status
Simulation time 37403863 ps
CPU time 0.71 seconds
Started Jun 10 05:29:35 PM PDT 24
Finished Jun 10 05:29:36 PM PDT 24
Peak memory 205300 kb
Host smart-e9712c33-adeb-4746-ad82-c71ffb0b2ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443297722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1443297722
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1968219600
Short name T929
Test name
Test status
Simulation time 84401532 ps
CPU time 0.79 seconds
Started Jun 10 05:29:21 PM PDT 24
Finished Jun 10 05:29:22 PM PDT 24
Peak memory 205308 kb
Host smart-a436fd64-ea15-4bde-b26d-f49db23123da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968219600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1968219600
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3674470731
Short name T1020
Test name
Test status
Simulation time 8174501 ps
CPU time 0.72 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205476 kb
Host smart-8c763d7d-382c-4371-a3af-89a375e4ab89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674470731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3674470731
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2867972075
Short name T1079
Test name
Test status
Simulation time 433441122 ps
CPU time 8.15 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205596 kb
Host smart-68484d2a-01d3-49c5-aa32-607ce6f68464
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867972075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
867972075
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1435161166
Short name T974
Test name
Test status
Simulation time 556687769 ps
CPU time 6.07 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205608 kb
Host smart-1b57b40b-3a61-4bd5-a206-73d788b7b61c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435161166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
435161166
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3018915764
Short name T1025
Test name
Test status
Simulation time 34484180 ps
CPU time 1.2 seconds
Started Jun 10 05:29:27 PM PDT 24
Finished Jun 10 05:29:39 PM PDT 24
Peak memory 205624 kb
Host smart-55299254-a3cf-4fe3-9143-c84c29d65d75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018915764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
018915764
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2364065846
Short name T1018
Test name
Test status
Simulation time 34218031 ps
CPU time 2.13 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 213836 kb
Host smart-96528b0a-7c01-4d07-b804-02619b1c9487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364065846 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2364065846
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1344011335
Short name T998
Test name
Test status
Simulation time 46051733 ps
CPU time 1.03 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205616 kb
Host smart-61380022-5841-49f2-a5fd-edd020f27ee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344011335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1344011335
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3660808863
Short name T1021
Test name
Test status
Simulation time 12212658 ps
CPU time 0.74 seconds
Started Jun 10 05:29:21 PM PDT 24
Finished Jun 10 05:29:22 PM PDT 24
Peak memory 205200 kb
Host smart-49abbdbe-cc52-40d6-90ed-e22561487b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660808863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3660808863
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2641931268
Short name T1033
Test name
Test status
Simulation time 22603948 ps
CPU time 1.6 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 205624 kb
Host smart-127ae18f-3d57-4259-b272-6d66cc1416ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641931268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2641931268
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3142811111
Short name T991
Test name
Test status
Simulation time 115601886 ps
CPU time 3.18 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 218500 kb
Host smart-adb39f7d-881b-4250-a5d9-1f5f42f1a79d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142811111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3142811111
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2165709661
Short name T949
Test name
Test status
Simulation time 224595164 ps
CPU time 7.87 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 214124 kb
Host smart-dfc5945e-148e-49ef-99ed-46a92e8a22ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165709661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2165709661
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3178935871
Short name T977
Test name
Test status
Simulation time 56316340 ps
CPU time 3.22 seconds
Started Jun 10 05:29:33 PM PDT 24
Finished Jun 10 05:29:36 PM PDT 24
Peak memory 216948 kb
Host smart-f04eb836-c681-4cf4-83b6-8efe4102c703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178935871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3178935871
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3799087913
Short name T163
Test name
Test status
Simulation time 328660188 ps
CPU time 7 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 216304 kb
Host smart-8eba9557-f8f3-4b1d-b505-a4a6dba96783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799087913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3799087913
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3569390958
Short name T1062
Test name
Test status
Simulation time 9342104 ps
CPU time 0.68 seconds
Started Jun 10 05:29:53 PM PDT 24
Finished Jun 10 05:29:54 PM PDT 24
Peak memory 205344 kb
Host smart-d000131e-b2a9-482b-acd4-869b2425ca59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569390958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3569390958
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1219282634
Short name T984
Test name
Test status
Simulation time 11690333 ps
CPU time 0.82 seconds
Started Jun 10 05:29:38 PM PDT 24
Finished Jun 10 05:29:39 PM PDT 24
Peak memory 205300 kb
Host smart-5ebaa5d5-6146-4598-bde0-a4161505fd47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219282634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1219282634
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1723090380
Short name T934
Test name
Test status
Simulation time 14384058 ps
CPU time 0.92 seconds
Started Jun 10 05:29:17 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205396 kb
Host smart-d6852cb9-cec2-4fa8-a3df-f6c7ac566474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723090380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1723090380
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.543259090
Short name T928
Test name
Test status
Simulation time 17235663 ps
CPU time 0.79 seconds
Started Jun 10 05:29:42 PM PDT 24
Finished Jun 10 05:29:43 PM PDT 24
Peak memory 205320 kb
Host smart-cd587dfd-2797-4ae7-ae3e-01ef4ff397dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543259090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.543259090
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4000256551
Short name T1068
Test name
Test status
Simulation time 14898757 ps
CPU time 0.93 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205408 kb
Host smart-177dde1d-17cc-46f7-b5ff-fcf951fff19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000256551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4000256551
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1097520629
Short name T959
Test name
Test status
Simulation time 10716080 ps
CPU time 0.73 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205240 kb
Host smart-a9f015de-ecfd-4d78-8822-f7207c57e3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097520629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1097520629
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1323503326
Short name T1000
Test name
Test status
Simulation time 8366235 ps
CPU time 0.81 seconds
Started Jun 10 05:29:59 PM PDT 24
Finished Jun 10 05:30:00 PM PDT 24
Peak memory 205240 kb
Host smart-f9f75cc2-06be-41cf-a0c3-a90669a5597d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323503326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1323503326
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3256983006
Short name T945
Test name
Test status
Simulation time 42238523 ps
CPU time 0.72 seconds
Started Jun 10 05:29:56 PM PDT 24
Finished Jun 10 05:29:57 PM PDT 24
Peak memory 205300 kb
Host smart-642c717d-0c65-4a90-a3cd-467fb24d3ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256983006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3256983006
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1620156483
Short name T1039
Test name
Test status
Simulation time 106013335 ps
CPU time 0.74 seconds
Started Jun 10 05:29:24 PM PDT 24
Finished Jun 10 05:29:25 PM PDT 24
Peak memory 205308 kb
Host smart-b7c7487a-f708-46cc-861a-aba83030280c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620156483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1620156483
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1082029666
Short name T1088
Test name
Test status
Simulation time 16293569 ps
CPU time 0.91 seconds
Started Jun 10 05:29:53 PM PDT 24
Finished Jun 10 05:29:54 PM PDT 24
Peak memory 205488 kb
Host smart-c2c2257d-b88f-4999-93aa-8d9494f1635a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082029666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1082029666
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3993062062
Short name T1059
Test name
Test status
Simulation time 121114349 ps
CPU time 1.29 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205848 kb
Host smart-46e0296f-e68c-48bb-a598-e7571a8b5575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993062062 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3993062062
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.4212561534
Short name T137
Test name
Test status
Simulation time 91919972 ps
CPU time 1.15 seconds
Started Jun 10 05:29:44 PM PDT 24
Finished Jun 10 05:29:46 PM PDT 24
Peak memory 205568 kb
Host smart-3f89213a-9074-4b35-8d57-e4729db10fc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212561534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.4212561534
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.56823859
Short name T997
Test name
Test status
Simulation time 34213108 ps
CPU time 0.79 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205320 kb
Host smart-8e2f8e89-c88d-49a4-86b7-23d7015de01c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56823859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.56823859
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.69127679
Short name T1041
Test name
Test status
Simulation time 139022029 ps
CPU time 1.84 seconds
Started Jun 10 05:29:15 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 205684 kb
Host smart-5879bc95-7225-4947-9a6b-a3bf623354df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69127679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same
_csr_outstanding.69127679
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.207277396
Short name T995
Test name
Test status
Simulation time 320982310 ps
CPU time 4.12 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 214136 kb
Host smart-86a59a71-dc71-4a3c-86f6-2255a1830e31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207277396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.207277396
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.544070225
Short name T1070
Test name
Test status
Simulation time 204543560 ps
CPU time 4.84 seconds
Started Jun 10 05:29:38 PM PDT 24
Finished Jun 10 05:29:43 PM PDT 24
Peak memory 220092 kb
Host smart-64a9714b-97b1-4c23-a0c7-b9025cf6625a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544070225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.544070225
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.276976702
Short name T921
Test name
Test status
Simulation time 50576652 ps
CPU time 3.21 seconds
Started Jun 10 05:29:37 PM PDT 24
Finished Jun 10 05:29:41 PM PDT 24
Peak memory 213916 kb
Host smart-6cfd00ab-bbfd-455a-8b01-ab9a1d806888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276976702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.276976702
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3635686171
Short name T375
Test name
Test status
Simulation time 484655434 ps
CPU time 5.11 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:29:22 PM PDT 24
Peak memory 213812 kb
Host smart-114afbf3-9bf6-4991-bca2-b3eb9df0469c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635686171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3635686171
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3564302973
Short name T1006
Test name
Test status
Simulation time 48678338 ps
CPU time 1.21 seconds
Started Jun 10 05:29:26 PM PDT 24
Finished Jun 10 05:29:27 PM PDT 24
Peak memory 205520 kb
Host smart-9ae2300d-4908-4453-8731-643634645c00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564302973 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3564302973
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1928984683
Short name T1014
Test name
Test status
Simulation time 10211084 ps
CPU time 0.88 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205528 kb
Host smart-9644c21d-bfe0-48ce-871e-720c1fc29449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928984683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1928984683
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1693050054
Short name T943
Test name
Test status
Simulation time 7400626 ps
CPU time 0.7 seconds
Started Jun 10 05:29:27 PM PDT 24
Finished Jun 10 05:29:28 PM PDT 24
Peak memory 205228 kb
Host smart-1a977c84-4f2d-4fb5-9c34-e4e95a9516cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693050054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1693050054
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1051097067
Short name T971
Test name
Test status
Simulation time 244747134 ps
CPU time 1.75 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205628 kb
Host smart-c6970b27-b2bc-442d-b584-9dd5abf8261b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051097067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1051097067
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3383503755
Short name T1038
Test name
Test status
Simulation time 50427337 ps
CPU time 1.85 seconds
Started Jun 10 05:29:45 PM PDT 24
Finished Jun 10 05:29:47 PM PDT 24
Peak memory 214160 kb
Host smart-75f621e8-ac39-48ea-b2b3-a385abab2f5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383503755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3383503755
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3364022345
Short name T1032
Test name
Test status
Simulation time 240422240 ps
CPU time 8.68 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 214084 kb
Host smart-456e9ab5-4753-481d-ab2a-da3e6392e3a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364022345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3364022345
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.719480460
Short name T955
Test name
Test status
Simulation time 196572300 ps
CPU time 3.92 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 217172 kb
Host smart-2d1bc7c9-d1ed-4108-a6b2-067f0413fd9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719480460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.719480460
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2442411259
Short name T1052
Test name
Test status
Simulation time 183213817 ps
CPU time 2.94 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:16 PM PDT 24
Peak memory 215028 kb
Host smart-ceae75be-8e8a-4df6-b763-1239eb6b8974
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442411259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2442411259
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2141854324
Short name T967
Test name
Test status
Simulation time 96728862 ps
CPU time 1.43 seconds
Started Jun 10 05:29:41 PM PDT 24
Finished Jun 10 05:29:43 PM PDT 24
Peak memory 213908 kb
Host smart-9ce9a30b-dbc4-41b5-9849-8a42e22e0ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141854324 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2141854324
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1856264982
Short name T1019
Test name
Test status
Simulation time 62218533 ps
CPU time 0.94 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205512 kb
Host smart-03fb4e7d-c695-4b4f-a0b0-62044c40d9a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856264982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1856264982
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2480083102
Short name T935
Test name
Test status
Simulation time 13279456 ps
CPU time 0.7 seconds
Started Jun 10 05:29:25 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 205200 kb
Host smart-bf697152-2d22-4653-8192-167182ac7371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480083102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2480083102
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.718256583
Short name T1022
Test name
Test status
Simulation time 185761244 ps
CPU time 3.95 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205620 kb
Host smart-8e4102a8-1077-4671-a78c-cc82b4a5ee89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718256583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.718256583
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2911848996
Short name T106
Test name
Test status
Simulation time 259759473 ps
CPU time 2.83 seconds
Started Jun 10 05:29:43 PM PDT 24
Finished Jun 10 05:29:46 PM PDT 24
Peak memory 214328 kb
Host smart-05368f4d-550a-4258-92a3-f726baf29d8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911848996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2911848996
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.801806136
Short name T1003
Test name
Test status
Simulation time 268146542 ps
CPU time 6.21 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:14 PM PDT 24
Peak memory 214180 kb
Host smart-33adb82a-6a25-428c-832e-dc36ad59b505
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801806136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.801806136
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3869009252
Short name T1071
Test name
Test status
Simulation time 35078345 ps
CPU time 1.64 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 216408 kb
Host smart-4ff00c65-8611-4908-bfa4-10441d73ccb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869009252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3869009252
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3469745318
Short name T162
Test name
Test status
Simulation time 202860231 ps
CPU time 6.13 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:27 PM PDT 24
Peak memory 213888 kb
Host smart-68a99594-0ebe-4a31-bbc6-8335ddf3065b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469745318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3469745318
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4041510720
Short name T953
Test name
Test status
Simulation time 93123246 ps
CPU time 1.62 seconds
Started Jun 10 05:29:24 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 213840 kb
Host smart-8d54bee4-3405-4871-acf5-3a5bee397b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041510720 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4041510720
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3891954323
Short name T150
Test name
Test status
Simulation time 54489699 ps
CPU time 1.07 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205724 kb
Host smart-8eeb9291-e5cf-4997-b977-9821b93bacde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891954323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3891954323
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.821197009
Short name T989
Test name
Test status
Simulation time 13506347 ps
CPU time 0.9 seconds
Started Jun 10 05:29:09 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 205528 kb
Host smart-9afd8f9c-1b20-4182-9cbf-3962e440c001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821197009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.821197009
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2582233860
Short name T134
Test name
Test status
Simulation time 163041712 ps
CPU time 2.55 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205584 kb
Host smart-72aa823b-54ab-4b6f-b8d2-466dd8e6d62d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582233860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2582233860
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2672469348
Short name T108
Test name
Test status
Simulation time 172179025 ps
CPU time 5.73 seconds
Started Jun 10 05:29:20 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 220392 kb
Host smart-3a4a113d-badc-4ba2-b4fd-fac6d6a256ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672469348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2672469348
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3709534631
Short name T924
Test name
Test status
Simulation time 37408215 ps
CPU time 1.79 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 214544 kb
Host smart-97e90b84-ad44-482d-a42e-2dfffdd8590e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709534631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3709534631
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1248727721
Short name T157
Test name
Test status
Simulation time 80847757 ps
CPU time 3.58 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 213896 kb
Host smart-d5e5ed69-38b2-451f-91d6-4738b3eaafdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248727721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1248727721
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4043246126
Short name T966
Test name
Test status
Simulation time 105739794 ps
CPU time 1.43 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 213852 kb
Host smart-9cc8a066-4058-4b4d-8bbd-a9b54b9e5611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043246126 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4043246126
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2497210486
Short name T963
Test name
Test status
Simulation time 44360769 ps
CPU time 1.07 seconds
Started Jun 10 05:29:53 PM PDT 24
Finished Jun 10 05:29:54 PM PDT 24
Peak memory 205484 kb
Host smart-449745cc-4dec-4b55-b9d5-60ff5392cbef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497210486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2497210486
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.575750959
Short name T1009
Test name
Test status
Simulation time 27055837 ps
CPU time 0.74 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 205312 kb
Host smart-0fe2b13f-4cb6-4256-a53b-d7801305359f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575750959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.575750959
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.679125664
Short name T1046
Test name
Test status
Simulation time 65635633 ps
CPU time 1.34 seconds
Started Jun 10 05:29:47 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 205648 kb
Host smart-065ef386-15bd-4238-9326-33ac8040547c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679125664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.679125664
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.523163361
Short name T1028
Test name
Test status
Simulation time 182684349 ps
CPU time 1.82 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 214208 kb
Host smart-9c65c4e6-641d-402c-86f2-6e9046e44d0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523163361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.523163361
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3155202182
Short name T1036
Test name
Test status
Simulation time 343037767 ps
CPU time 9.05 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 220420 kb
Host smart-b9fc71c7-f18a-49f0-b528-b4a458d6a477
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155202182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3155202182
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.900528011
Short name T1026
Test name
Test status
Simulation time 84564971 ps
CPU time 1.65 seconds
Started Jun 10 05:29:26 PM PDT 24
Finished Jun 10 05:29:28 PM PDT 24
Peak memory 214100 kb
Host smart-b1e56521-e17d-4828-a5e3-70da413aaf04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900528011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.900528011
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1341252036
Short name T808
Test name
Test status
Simulation time 18310364 ps
CPU time 0.78 seconds
Started Jun 10 05:34:43 PM PDT 24
Finished Jun 10 05:34:44 PM PDT 24
Peak memory 205920 kb
Host smart-5f1b89b2-38e6-467f-9623-4c0e392d7aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341252036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1341252036
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.718136911
Short name T25
Test name
Test status
Simulation time 48928916 ps
CPU time 1.54 seconds
Started Jun 10 05:34:46 PM PDT 24
Finished Jun 10 05:34:47 PM PDT 24
Peak memory 208720 kb
Host smart-9ebbad85-5060-469f-9554-b1a752f4a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718136911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.718136911
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1465977567
Short name T101
Test name
Test status
Simulation time 279719093 ps
CPU time 4.01 seconds
Started Jun 10 05:34:37 PM PDT 24
Finished Jun 10 05:34:41 PM PDT 24
Peak memory 208032 kb
Host smart-80c32037-bfdb-4610-a901-7e3947d70435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465977567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1465977567
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1389513004
Short name T491
Test name
Test status
Simulation time 57193466 ps
CPU time 3.43 seconds
Started Jun 10 05:34:45 PM PDT 24
Finished Jun 10 05:34:49 PM PDT 24
Peak memory 209272 kb
Host smart-8013a792-7456-472c-b157-3dbcd56de3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389513004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1389513004
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3038594506
Short name T249
Test name
Test status
Simulation time 45607531 ps
CPU time 2.02 seconds
Started Jun 10 05:34:42 PM PDT 24
Finished Jun 10 05:34:44 PM PDT 24
Peak memory 214280 kb
Host smart-8f3071da-0528-4768-87a7-861ed5f88828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038594506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3038594506
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3459324402
Short name T284
Test name
Test status
Simulation time 1059151128 ps
CPU time 3.28 seconds
Started Jun 10 05:34:43 PM PDT 24
Finished Jun 10 05:34:46 PM PDT 24
Peak memory 219996 kb
Host smart-41255250-97c4-4343-a375-d7f4c03383b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459324402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3459324402
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3869943009
Short name T468
Test name
Test status
Simulation time 337899692 ps
CPU time 11.4 seconds
Started Jun 10 05:34:39 PM PDT 24
Finished Jun 10 05:34:51 PM PDT 24
Peak memory 208348 kb
Host smart-c0d60e03-8100-47ac-8e8b-3b61b15ed327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869943009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3869943009
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.369027411
Short name T196
Test name
Test status
Simulation time 44278675 ps
CPU time 2.64 seconds
Started Jun 10 05:34:37 PM PDT 24
Finished Jun 10 05:34:40 PM PDT 24
Peak memory 208596 kb
Host smart-c895af63-f1b1-4640-8298-e11ed6060560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369027411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.369027411
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3106604680
Short name T782
Test name
Test status
Simulation time 53274954 ps
CPU time 2.85 seconds
Started Jun 10 05:34:40 PM PDT 24
Finished Jun 10 05:34:43 PM PDT 24
Peak memory 206876 kb
Host smart-bb19f0ad-bd7c-4768-a59f-40474a47cc2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106604680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3106604680
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2849608853
Short name T476
Test name
Test status
Simulation time 158162888 ps
CPU time 4.92 seconds
Started Jun 10 05:34:39 PM PDT 24
Finished Jun 10 05:34:44 PM PDT 24
Peak memory 208564 kb
Host smart-8e31fcfe-0d7d-4ee1-9da1-d10286beb8b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849608853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2849608853
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2135146529
Short name T721
Test name
Test status
Simulation time 217606411 ps
CPU time 6.39 seconds
Started Jun 10 05:34:40 PM PDT 24
Finished Jun 10 05:34:47 PM PDT 24
Peak memory 208092 kb
Host smart-7fdf5fb5-e541-496f-910f-f5326272d416
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135146529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2135146529
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3252098301
Short name T603
Test name
Test status
Simulation time 1568189744 ps
CPU time 10.68 seconds
Started Jun 10 05:34:42 PM PDT 24
Finished Jun 10 05:34:53 PM PDT 24
Peak memory 214244 kb
Host smart-bc17c379-7f5e-44ca-9479-22d49c41c9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252098301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3252098301
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.537929510
Short name T849
Test name
Test status
Simulation time 167653963 ps
CPU time 3.6 seconds
Started Jun 10 05:34:40 PM PDT 24
Finished Jun 10 05:34:44 PM PDT 24
Peak memory 208588 kb
Host smart-8c2a342c-def6-4d28-a7fd-fa2ae207bb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537929510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.537929510
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2671606782
Short name T265
Test name
Test status
Simulation time 926317615 ps
CPU time 23.38 seconds
Started Jun 10 05:34:49 PM PDT 24
Finished Jun 10 05:35:13 PM PDT 24
Peak memory 215636 kb
Host smart-b3e07dca-df67-46a0-a465-b6b7a3bdef0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671606782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2671606782
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1639450331
Short name T52
Test name
Test status
Simulation time 197986204 ps
CPU time 8.11 seconds
Started Jun 10 05:34:43 PM PDT 24
Finished Jun 10 05:34:51 PM PDT 24
Peak memory 222092 kb
Host smart-5ae127dd-5b80-4368-a292-64bba4bbac3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639450331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1639450331
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1900585050
Short name T720
Test name
Test status
Simulation time 900329816 ps
CPU time 10.69 seconds
Started Jun 10 05:34:42 PM PDT 24
Finished Jun 10 05:34:53 PM PDT 24
Peak memory 214388 kb
Host smart-db00e379-ef4b-434b-895c-e6b1425e9f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900585050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1900585050
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3821662097
Short name T499
Test name
Test status
Simulation time 18761594 ps
CPU time 0.76 seconds
Started Jun 10 05:34:53 PM PDT 24
Finished Jun 10 05:34:55 PM PDT 24
Peak memory 205848 kb
Host smart-c9f5705b-3e5a-4ecd-91b1-928656aa4142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821662097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3821662097
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.538757639
Short name T411
Test name
Test status
Simulation time 1679166757 ps
CPU time 91.59 seconds
Started Jun 10 05:34:45 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 215704 kb
Host smart-0b02735a-a089-426f-84fb-93a9da8cdc30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538757639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.538757639
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.5256335
Short name T625
Test name
Test status
Simulation time 156191470 ps
CPU time 6.01 seconds
Started Jun 10 05:34:46 PM PDT 24
Finished Jun 10 05:34:53 PM PDT 24
Peak memory 214276 kb
Host smart-a67ab6fe-ad46-4bf6-affe-04d4f6d206ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5256335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.5256335
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2963409802
Short name T715
Test name
Test status
Simulation time 143319781 ps
CPU time 2.53 seconds
Started Jun 10 05:34:46 PM PDT 24
Finished Jun 10 05:34:49 PM PDT 24
Peak memory 209840 kb
Host smart-1d63e2a5-416f-4ced-9797-74fa6b4c5779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963409802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2963409802
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3192938206
Short name T823
Test name
Test status
Simulation time 249887596 ps
CPU time 2.7 seconds
Started Jun 10 05:34:49 PM PDT 24
Finished Jun 10 05:34:52 PM PDT 24
Peak memory 214316 kb
Host smart-e21e152c-65d3-4200-913e-87dabe3d2181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192938206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3192938206
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_random.1131591943
Short name T773
Test name
Test status
Simulation time 841530109 ps
CPU time 4.95 seconds
Started Jun 10 05:34:43 PM PDT 24
Finished Jun 10 05:34:48 PM PDT 24
Peak memory 209384 kb
Host smart-2201d437-3932-47f9-8fcc-18fe74f9576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131591943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1131591943
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3928175627
Short name T893
Test name
Test status
Simulation time 604259060 ps
CPU time 5.19 seconds
Started Jun 10 05:34:44 PM PDT 24
Finished Jun 10 05:34:49 PM PDT 24
Peak memory 208576 kb
Host smart-20139d0c-00f2-4b90-a6cb-36c9a4aa42e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928175627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3928175627
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1740517658
Short name T482
Test name
Test status
Simulation time 208306637 ps
CPU time 2.83 seconds
Started Jun 10 05:34:46 PM PDT 24
Finished Jun 10 05:34:50 PM PDT 24
Peak memory 206936 kb
Host smart-e05f920b-5912-4265-9279-4bd958e02604
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740517658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1740517658
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4288219204
Short name T469
Test name
Test status
Simulation time 320520777 ps
CPU time 4.06 seconds
Started Jun 10 05:34:42 PM PDT 24
Finished Jun 10 05:34:47 PM PDT 24
Peak memory 209232 kb
Host smart-87b806b2-ee6c-4a88-af7f-2128c809b247
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288219204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4288219204
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3666138263
Short name T789
Test name
Test status
Simulation time 202869146 ps
CPU time 2.89 seconds
Started Jun 10 05:34:47 PM PDT 24
Finished Jun 10 05:34:50 PM PDT 24
Peak memory 209696 kb
Host smart-ba938298-d84b-418b-9b06-4a02a0e77171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666138263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3666138263
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3188040205
Short name T601
Test name
Test status
Simulation time 624227483 ps
CPU time 4.44 seconds
Started Jun 10 05:34:43 PM PDT 24
Finished Jun 10 05:34:48 PM PDT 24
Peak memory 208308 kb
Host smart-dd746713-334a-4704-87fb-32bcacd09cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188040205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3188040205
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.4103508213
Short name T113
Test name
Test status
Simulation time 471318334 ps
CPU time 8.92 seconds
Started Jun 10 05:34:49 PM PDT 24
Finished Jun 10 05:34:58 PM PDT 24
Peak memory 219744 kb
Host smart-9b1da92a-7669-4bee-8b16-b24db033bc0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103508213 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.4103508213
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.85042376
Short name T234
Test name
Test status
Simulation time 405263438 ps
CPU time 6.8 seconds
Started Jun 10 05:34:49 PM PDT 24
Finished Jun 10 05:34:57 PM PDT 24
Peak memory 214300 kb
Host smart-35920ed7-6846-4f12-8ec8-b5af15642ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85042376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.85042376
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3957711245
Short name T57
Test name
Test status
Simulation time 506863769 ps
CPU time 2.87 seconds
Started Jun 10 05:34:47 PM PDT 24
Finished Jun 10 05:34:51 PM PDT 24
Peak memory 210492 kb
Host smart-90dbc9e5-b993-440e-854c-586f0ea6dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957711245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3957711245
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1197656369
Short name T910
Test name
Test status
Simulation time 64419615 ps
CPU time 0.98 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:22 PM PDT 24
Peak memory 206052 kb
Host smart-3a6c9a37-9566-405e-bca2-2b8a4131a3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197656369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1197656369
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1831828486
Short name T27
Test name
Test status
Simulation time 80784071 ps
CPU time 3.6 seconds
Started Jun 10 05:35:25 PM PDT 24
Finished Jun 10 05:35:29 PM PDT 24
Peak memory 208948 kb
Host smart-82315580-099b-40a7-ac12-b3ab125182b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831828486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1831828486
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3333956023
Short name T758
Test name
Test status
Simulation time 385220360 ps
CPU time 5.27 seconds
Started Jun 10 05:35:23 PM PDT 24
Finished Jun 10 05:35:28 PM PDT 24
Peak memory 209868 kb
Host smart-5504a771-e42c-4201-978d-ba6029e95e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333956023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3333956023
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2587643096
Short name T93
Test name
Test status
Simulation time 125322205 ps
CPU time 2.42 seconds
Started Jun 10 05:35:24 PM PDT 24
Finished Jun 10 05:35:26 PM PDT 24
Peak memory 214312 kb
Host smart-7b2e82df-aa32-4095-9ddc-fb91c89f40fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587643096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2587643096
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.811008522
Short name T764
Test name
Test status
Simulation time 84695513 ps
CPU time 4.09 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:26 PM PDT 24
Peak memory 209668 kb
Host smart-66964130-14bb-4a14-ac13-4e7a060557e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811008522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.811008522
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2933824672
Short name T120
Test name
Test status
Simulation time 168579328 ps
CPU time 5.21 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 214328 kb
Host smart-be52fb43-5722-4c9e-8eef-d9f297f090d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933824672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2933824672
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.455688205
Short name T909
Test name
Test status
Simulation time 48608507 ps
CPU time 2.22 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:24 PM PDT 24
Peak memory 208552 kb
Host smart-db2e4365-f0e0-49ca-a106-c230c093d63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455688205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.455688205
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.123254477
Short name T16
Test name
Test status
Simulation time 93279841 ps
CPU time 2.54 seconds
Started Jun 10 05:35:22 PM PDT 24
Finished Jun 10 05:35:25 PM PDT 24
Peak memory 207652 kb
Host smart-75951e87-53ae-4e5b-b190-6fe576a1459e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123254477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.123254477
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2741843665
Short name T550
Test name
Test status
Simulation time 304672296 ps
CPU time 4.72 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:24 PM PDT 24
Peak memory 207000 kb
Host smart-cdafa37d-a8ad-416b-8815-d0c3024cdb27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741843665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2741843665
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.840247616
Short name T819
Test name
Test status
Simulation time 263503777 ps
CPU time 3.16 seconds
Started Jun 10 05:35:22 PM PDT 24
Finished Jun 10 05:35:25 PM PDT 24
Peak memory 209812 kb
Host smart-8dc78833-c5c0-462d-92c8-8440f11af667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840247616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.840247616
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3112629422
Short name T426
Test name
Test status
Simulation time 230281289 ps
CPU time 3.01 seconds
Started Jun 10 05:35:18 PM PDT 24
Finished Jun 10 05:35:22 PM PDT 24
Peak memory 206768 kb
Host smart-d8a6a0f5-8aa8-4201-bbc8-482ba3180b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112629422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3112629422
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3160730594
Short name T762
Test name
Test status
Simulation time 17291405 ps
CPU time 0.85 seconds
Started Jun 10 05:35:26 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 205704 kb
Host smart-f7976f97-8766-4640-ac93-e3a3f70bc493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160730594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3160730594
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2827801018
Short name T121
Test name
Test status
Simulation time 238405333 ps
CPU time 3.31 seconds
Started Jun 10 05:35:24 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 207620 kb
Host smart-bbc53049-b0c9-450d-a148-ba162eca95f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827801018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2827801018
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1029205391
Short name T862
Test name
Test status
Simulation time 197156785 ps
CPU time 1.98 seconds
Started Jun 10 05:35:25 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 210012 kb
Host smart-b3d56124-516e-403c-822b-4674448f7188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029205391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1029205391
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1254337666
Short name T786
Test name
Test status
Simulation time 58324649 ps
CPU time 2.45 seconds
Started Jun 10 05:35:28 PM PDT 24
Finished Jun 10 05:35:30 PM PDT 24
Peak memory 214376 kb
Host smart-9aea4e56-207c-4af7-bec5-ae268c134983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254337666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1254337666
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1327802491
Short name T537
Test name
Test status
Simulation time 9337175003 ps
CPU time 74.39 seconds
Started Jun 10 05:35:27 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 222420 kb
Host smart-5722306c-2435-4097-be66-e79b462fef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327802491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1327802491
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.386564580
Short name T69
Test name
Test status
Simulation time 15281514 ps
CPU time 1.48 seconds
Started Jun 10 05:35:27 PM PDT 24
Finished Jun 10 05:35:29 PM PDT 24
Peak memory 207940 kb
Host smart-7ac5ef62-40ff-4c85-b625-5fdc3bc4c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386564580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.386564580
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.730973294
Short name T87
Test name
Test status
Simulation time 961463669 ps
CPU time 25.15 seconds
Started Jun 10 05:35:27 PM PDT 24
Finished Jun 10 05:35:53 PM PDT 24
Peak memory 214336 kb
Host smart-fa46e5ca-d2ca-40fa-96e1-ca18909bfbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730973294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.730973294
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1965389430
Short name T710
Test name
Test status
Simulation time 46983003 ps
CPU time 2.08 seconds
Started Jun 10 05:35:27 PM PDT 24
Finished Jun 10 05:35:30 PM PDT 24
Peak memory 221136 kb
Host smart-7eb18111-5123-44e6-8d12-c2c9e24e060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965389430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1965389430
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2372317540
Short name T420
Test name
Test status
Simulation time 55211479 ps
CPU time 2.92 seconds
Started Jun 10 05:35:27 PM PDT 24
Finished Jun 10 05:35:30 PM PDT 24
Peak memory 222492 kb
Host smart-e94e7abf-d325-48f8-9b20-5a8e7cccf194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372317540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2372317540
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4228057867
Short name T856
Test name
Test status
Simulation time 252259047 ps
CPU time 3.41 seconds
Started Jun 10 05:35:25 PM PDT 24
Finished Jun 10 05:35:29 PM PDT 24
Peak memory 210212 kb
Host smart-cb49d9ca-c853-4c64-bb86-5338aa5ed200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228057867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4228057867
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1759273175
Short name T744
Test name
Test status
Simulation time 88034616 ps
CPU time 3.44 seconds
Started Jun 10 05:35:27 PM PDT 24
Finished Jun 10 05:35:31 PM PDT 24
Peak memory 208688 kb
Host smart-05b434a3-238e-4dec-bf72-53633e16df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759273175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1759273175
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.157882381
Short name T821
Test name
Test status
Simulation time 56840100 ps
CPU time 2.87 seconds
Started Jun 10 05:35:26 PM PDT 24
Finished Jun 10 05:35:29 PM PDT 24
Peak memory 206620 kb
Host smart-d2fb80b0-883b-4794-8ef6-c452c40c9b67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157882381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.157882381
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1636570721
Short name T224
Test name
Test status
Simulation time 303082395 ps
CPU time 3.16 seconds
Started Jun 10 05:35:34 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 206972 kb
Host smart-587ef729-8c92-4923-8f69-6c534aec866e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636570721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1636570721
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3171397918
Short name T582
Test name
Test status
Simulation time 36751795 ps
CPU time 2.42 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:35:35 PM PDT 24
Peak memory 206828 kb
Host smart-1a63b366-fab4-4795-8c2d-987007a009b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171397918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3171397918
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2024811452
Short name T515
Test name
Test status
Simulation time 78084943 ps
CPU time 2.04 seconds
Started Jun 10 05:35:26 PM PDT 24
Finished Jun 10 05:35:28 PM PDT 24
Peak memory 207464 kb
Host smart-6369ad22-0081-4f12-9ced-d82f3b9e33f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024811452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2024811452
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2016163374
Short name T494
Test name
Test status
Simulation time 1576442061 ps
CPU time 50.45 seconds
Started Jun 10 05:35:26 PM PDT 24
Finished Jun 10 05:36:16 PM PDT 24
Peak memory 208192 kb
Host smart-3758d733-fd50-4a22-aa54-d34711b3059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016163374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2016163374
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2394031346
Short name T165
Test name
Test status
Simulation time 1492460310 ps
CPU time 38.93 seconds
Started Jun 10 05:35:26 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 215672 kb
Host smart-cae45d32-faff-4239-81bb-07966ce0bd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394031346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2394031346
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3013835626
Short name T628
Test name
Test status
Simulation time 3602751565 ps
CPU time 28.56 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 223452 kb
Host smart-c81e2d0a-f319-4a49-8725-1127380d009b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013835626 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3013835626
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4159404112
Short name T376
Test name
Test status
Simulation time 878810389 ps
CPU time 9.55 seconds
Started Jun 10 05:35:29 PM PDT 24
Finished Jun 10 05:35:39 PM PDT 24
Peak memory 211200 kb
Host smart-9497604a-747e-4816-b071-a3a76c58601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159404112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4159404112
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3804964936
Short name T433
Test name
Test status
Simulation time 192065005 ps
CPU time 0.75 seconds
Started Jun 10 05:35:33 PM PDT 24
Finished Jun 10 05:35:34 PM PDT 24
Peak memory 205984 kb
Host smart-5f07961b-fba5-4c0f-929d-09a1c7abb7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804964936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3804964936
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4099159146
Short name T886
Test name
Test status
Simulation time 53734500 ps
CPU time 3.6 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:36 PM PDT 24
Peak memory 215236 kb
Host smart-6af3413a-d86a-47e6-bd5c-dedea33dc8ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4099159146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4099159146
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.600906379
Short name T65
Test name
Test status
Simulation time 89858128 ps
CPU time 2.88 seconds
Started Jun 10 05:35:34 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 217948 kb
Host smart-350b5971-7310-4254-a038-c99ab911ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600906379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.600906379
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3779986902
Short name T280
Test name
Test status
Simulation time 10831767711 ps
CPU time 53.43 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:36:26 PM PDT 24
Peak memory 214524 kb
Host smart-32f50a3c-cc57-44dc-9244-7f73369849bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779986902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3779986902
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2759883769
Short name T761
Test name
Test status
Simulation time 214153111 ps
CPU time 6.18 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 208052 kb
Host smart-329e96ce-9554-40f3-b70d-4f652d80658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759883769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2759883769
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3525720546
Short name T227
Test name
Test status
Simulation time 223083829 ps
CPU time 3.54 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:36 PM PDT 24
Peak memory 222376 kb
Host smart-bc2d927f-df52-40c2-b36c-e8b2b40833cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525720546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3525720546
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.3900339624
Short name T394
Test name
Test status
Simulation time 110105322 ps
CPU time 3.68 seconds
Started Jun 10 05:35:30 PM PDT 24
Finished Jun 10 05:35:34 PM PDT 24
Peak memory 209368 kb
Host smart-f0fa2670-afa2-4167-b6d9-8b63a89b38f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900339624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3900339624
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1896974374
Short name T479
Test name
Test status
Simulation time 35250777 ps
CPU time 1.93 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:34 PM PDT 24
Peak memory 208008 kb
Host smart-b33a8e26-d5da-4e4c-9143-fca2b8a7e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896974374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1896974374
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.884269691
Short name T235
Test name
Test status
Simulation time 164238342 ps
CPU time 3.51 seconds
Started Jun 10 05:35:33 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 208784 kb
Host smart-e411807b-c435-4dda-9212-42d97daa94f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884269691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.884269691
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.729585240
Short name T602
Test name
Test status
Simulation time 56600726 ps
CPU time 3.04 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 206936 kb
Host smart-4e070768-e7e6-4df6-9e7d-db2954a5c157
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729585240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.729585240
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.22636862
Short name T617
Test name
Test status
Simulation time 64973866 ps
CPU time 3.22 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:35:36 PM PDT 24
Peak memory 208920 kb
Host smart-f8af7d05-bcbb-40cf-b878-5af4a62aa421
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.22636862
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3133598939
Short name T330
Test name
Test status
Simulation time 142654590 ps
CPU time 2.86 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 208916 kb
Host smart-f72b5499-7b51-43f0-95a2-dac444aab5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133598939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3133598939
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3641141926
Short name T183
Test name
Test status
Simulation time 412800215 ps
CPU time 4.61 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:40 PM PDT 24
Peak memory 206836 kb
Host smart-290428cf-4732-4506-8cbb-b6bd5404e809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641141926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3641141926
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.206513534
Short name T661
Test name
Test status
Simulation time 950667520 ps
CPU time 13.58 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:35:46 PM PDT 24
Peak memory 215852 kb
Host smart-9a6e8c3e-1ebc-4d32-9b8d-e347d3650c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206513534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.206513534
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1181471780
Short name T561
Test name
Test status
Simulation time 71619282 ps
CPU time 4.65 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:40 PM PDT 24
Peak memory 218556 kb
Host smart-66d96d9a-551d-4c01-99ac-5d315737adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181471780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1181471780
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2795732640
Short name T172
Test name
Test status
Simulation time 458472871 ps
CPU time 2.27 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:35:35 PM PDT 24
Peak memory 209828 kb
Host smart-4497e289-0afc-422f-bcf9-779579894871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795732640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2795732640
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1293696414
Short name T555
Test name
Test status
Simulation time 43690905 ps
CPU time 0.8 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:36 PM PDT 24
Peak memory 205960 kb
Host smart-f7d3acd6-2284-4895-8ac8-8f4c908a3e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293696414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1293696414
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3761727552
Short name T560
Test name
Test status
Simulation time 975872747 ps
CPU time 6.59 seconds
Started Jun 10 05:35:43 PM PDT 24
Finished Jun 10 05:35:50 PM PDT 24
Peak memory 208988 kb
Host smart-d914f50d-4da5-4758-935a-b6f3e0dee347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761727552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3761727552
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2717324988
Short name T502
Test name
Test status
Simulation time 190063569 ps
CPU time 4.26 seconds
Started Jun 10 05:35:37 PM PDT 24
Finished Jun 10 05:35:41 PM PDT 24
Peak memory 215240 kb
Host smart-ba496dfb-c004-4c2e-907e-b520ec02064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717324988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2717324988
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1841596387
Short name T517
Test name
Test status
Simulation time 2192608942 ps
CPU time 5.08 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:41 PM PDT 24
Peak memory 222508 kb
Host smart-d123f3ec-7009-468e-9386-838d6047c9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841596387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1841596387
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1620456868
Short name T647
Test name
Test status
Simulation time 901685942 ps
CPU time 23.81 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:59 PM PDT 24
Peak memory 214352 kb
Host smart-5254e78a-3113-458e-876e-b7d20a0b3770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620456868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1620456868
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3431434446
Short name T458
Test name
Test status
Simulation time 71203070 ps
CPU time 2.74 seconds
Started Jun 10 05:35:33 PM PDT 24
Finished Jun 10 05:35:36 PM PDT 24
Peak memory 208668 kb
Host smart-3957e302-6b1c-41c9-88ff-a3cf212b1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431434446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3431434446
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1822743363
Short name T663
Test name
Test status
Simulation time 3036957557 ps
CPU time 29.07 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:36:02 PM PDT 24
Peak memory 208568 kb
Host smart-5c0a1d47-2676-4e12-9813-02d0090c7826
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822743363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1822743363
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3161131061
Short name T646
Test name
Test status
Simulation time 112452279 ps
CPU time 2.42 seconds
Started Jun 10 05:35:31 PM PDT 24
Finished Jun 10 05:35:33 PM PDT 24
Peak memory 206860 kb
Host smart-d42e82b0-aca3-4e08-8c8f-02c1d1450d99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161131061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3161131061
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3942792598
Short name T670
Test name
Test status
Simulation time 347200876 ps
CPU time 5.13 seconds
Started Jun 10 05:35:37 PM PDT 24
Finished Jun 10 05:35:43 PM PDT 24
Peak memory 207780 kb
Host smart-91b465f5-143b-419b-b984-12b6df60e68a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942792598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3942792598
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2818500284
Short name T639
Test name
Test status
Simulation time 1041660460 ps
CPU time 19.05 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 214336 kb
Host smart-71312c49-cdcf-4a1f-a9db-caf4f084ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818500284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2818500284
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2328625647
Short name T718
Test name
Test status
Simulation time 718594952 ps
CPU time 4.61 seconds
Started Jun 10 05:35:32 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 206888 kb
Host smart-fea7b054-b7e6-4f62-add3-a2bf4929747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328625647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2328625647
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.972290393
Short name T629
Test name
Test status
Simulation time 314883395 ps
CPU time 3.89 seconds
Started Jun 10 05:35:33 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 209112 kb
Host smart-da5aaa1f-4d93-49ce-a9a1-51e4fbc056dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972290393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.972290393
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3980866833
Short name T167
Test name
Test status
Simulation time 1011373222 ps
CPU time 10.2 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:46 PM PDT 24
Peak memory 221792 kb
Host smart-febdc5e8-8794-49e1-856c-3c47ebf45a4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980866833 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3980866833
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2931212593
Short name T363
Test name
Test status
Simulation time 8642780345 ps
CPU time 46.85 seconds
Started Jun 10 05:35:43 PM PDT 24
Finished Jun 10 05:36:31 PM PDT 24
Peak memory 209864 kb
Host smart-6af5df5e-ff04-4463-bb8f-58e4f14e4ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931212593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2931212593
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3935269630
Short name T464
Test name
Test status
Simulation time 208468351 ps
CPU time 0.78 seconds
Started Jun 10 05:35:41 PM PDT 24
Finished Jun 10 05:35:42 PM PDT 24
Peak memory 205876 kb
Host smart-f77ee4fb-d44f-4884-ba63-fa21a335a303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935269630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3935269630
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3364297777
Short name T308
Test name
Test status
Simulation time 50216511 ps
CPU time 3.55 seconds
Started Jun 10 05:35:37 PM PDT 24
Finished Jun 10 05:35:41 PM PDT 24
Peak memory 214804 kb
Host smart-56c6bc32-c58d-437c-95b8-ffea670379b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364297777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3364297777
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2259840352
Short name T864
Test name
Test status
Simulation time 91127972 ps
CPU time 3.17 seconds
Started Jun 10 05:35:42 PM PDT 24
Finished Jun 10 05:35:45 PM PDT 24
Peak memory 222632 kb
Host smart-3291ba6f-1f27-4a8d-9791-dd3cae57a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259840352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2259840352
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1612390553
Short name T733
Test name
Test status
Simulation time 974575260 ps
CPU time 10.51 seconds
Started Jun 10 05:35:40 PM PDT 24
Finished Jun 10 05:35:51 PM PDT 24
Peak memory 208940 kb
Host smart-e4bdfcf6-1735-4436-954b-fd539648f930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612390553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1612390553
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.921248643
Short name T580
Test name
Test status
Simulation time 73485418 ps
CPU time 4.11 seconds
Started Jun 10 05:35:41 PM PDT 24
Finished Jun 10 05:35:46 PM PDT 24
Peak memory 222504 kb
Host smart-14518bfc-05f6-4f38-a147-9f41084300af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921248643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.921248643
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2325222569
Short name T559
Test name
Test status
Simulation time 70910062 ps
CPU time 2.58 seconds
Started Jun 10 05:35:40 PM PDT 24
Finished Jun 10 05:35:43 PM PDT 24
Peak memory 220192 kb
Host smart-3e96eb50-c4b3-4cff-9438-91be9af06244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325222569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2325222569
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2958607741
Short name T771
Test name
Test status
Simulation time 275726364 ps
CPU time 4.3 seconds
Started Jun 10 05:35:43 PM PDT 24
Finished Jun 10 05:35:47 PM PDT 24
Peak memory 218540 kb
Host smart-9b4a9f13-63d2-4247-b8d7-55ef0cd311b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958607741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2958607741
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2698241598
Short name T802
Test name
Test status
Simulation time 108041818 ps
CPU time 3.46 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 206748 kb
Host smart-330fc912-3e83-406b-aedd-4f031b8ae670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698241598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2698241598
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2877193124
Short name T586
Test name
Test status
Simulation time 191071493 ps
CPU time 4.13 seconds
Started Jun 10 05:35:36 PM PDT 24
Finished Jun 10 05:35:40 PM PDT 24
Peak memory 208580 kb
Host smart-bcb831cf-d9dc-40e2-8695-5ec7592b5bb4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877193124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2877193124
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3539474494
Short name T671
Test name
Test status
Simulation time 726851913 ps
CPU time 8.86 seconds
Started Jun 10 05:35:35 PM PDT 24
Finished Jun 10 05:35:44 PM PDT 24
Peak memory 208668 kb
Host smart-5daefd1e-dcd0-46a2-8ec8-a91f3133e3e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539474494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3539474494
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3327510221
Short name T492
Test name
Test status
Simulation time 97841867 ps
CPU time 1.94 seconds
Started Jun 10 05:35:38 PM PDT 24
Finished Jun 10 05:35:40 PM PDT 24
Peak memory 206888 kb
Host smart-79243a83-6039-4f9f-8eaa-695b2739c30c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327510221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3327510221
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4235291742
Short name T186
Test name
Test status
Simulation time 77990036 ps
CPU time 2.63 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:35:47 PM PDT 24
Peak memory 214340 kb
Host smart-8a7f3324-3a50-4491-af3b-222ca191b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235291742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4235291742
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2036425045
Short name T832
Test name
Test status
Simulation time 151396269 ps
CPU time 2.81 seconds
Started Jun 10 05:35:34 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 208056 kb
Host smart-239a04e3-8028-403e-85a9-d039d035a6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036425045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2036425045
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.672421769
Short name T711
Test name
Test status
Simulation time 349882403 ps
CPU time 1 seconds
Started Jun 10 05:35:40 PM PDT 24
Finished Jun 10 05:35:42 PM PDT 24
Peak memory 206012 kb
Host smart-519a9cc4-51a9-489e-838e-6e89da3fa56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672421769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.672421769
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2422519138
Short name T166
Test name
Test status
Simulation time 762663669 ps
CPU time 7.08 seconds
Started Jun 10 05:35:41 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 222524 kb
Host smart-8f622f14-617a-4d59-9804-ca8ae3ddccf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422519138 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2422519138
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2742538088
Short name T260
Test name
Test status
Simulation time 2983787037 ps
CPU time 22.33 seconds
Started Jun 10 05:35:41 PM PDT 24
Finished Jun 10 05:36:04 PM PDT 24
Peak memory 209680 kb
Host smart-ab58533d-ed1e-4fd5-8450-ca275cbd9592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742538088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2742538088
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2850558
Short name T624
Test name
Test status
Simulation time 743833027 ps
CPU time 2.22 seconds
Started Jun 10 05:35:41 PM PDT 24
Finished Jun 10 05:35:44 PM PDT 24
Peak memory 210068 kb
Host smart-56a28046-ebe0-40d0-a8fe-105f1e8688bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2850558
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4021293282
Short name T425
Test name
Test status
Simulation time 11547578 ps
CPU time 0.75 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:46 PM PDT 24
Peak memory 205972 kb
Host smart-42e04fc3-f088-4728-8efd-2728e9122af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021293282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4021293282
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2384166814
Short name T364
Test name
Test status
Simulation time 113756115 ps
CPU time 3.61 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 214376 kb
Host smart-5fda548a-7d6e-473f-aaf3-b5037142c1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384166814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2384166814
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2049129529
Short name T903
Test name
Test status
Simulation time 589688067 ps
CPU time 4.09 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 209604 kb
Host smart-7503760d-be5f-4ba0-b073-8ec9f1bf91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049129529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2049129529
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.469392007
Short name T510
Test name
Test status
Simulation time 298405427 ps
CPU time 2.81 seconds
Started Jun 10 05:35:48 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 207416 kb
Host smart-7c08166f-61d2-4df7-9163-1a0f605deb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469392007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.469392007
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.669129436
Short name T21
Test name
Test status
Simulation time 722548972 ps
CPU time 9.25 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 214196 kb
Host smart-ae4a6f50-fc52-4857-b007-da25812a747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669129436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.669129436
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.677722053
Short name T798
Test name
Test status
Simulation time 50538640 ps
CPU time 1.88 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 214256 kb
Host smart-803f862c-4821-4800-ab8d-2aea3cecf7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677722053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.677722053
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4019122934
Short name T664
Test name
Test status
Simulation time 514087702 ps
CPU time 5.46 seconds
Started Jun 10 05:35:47 PM PDT 24
Finished Jun 10 05:35:53 PM PDT 24
Peak memory 220068 kb
Host smart-debce3fd-9189-4954-a40e-81bdc25af3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019122934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4019122934
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3314759421
Short name T700
Test name
Test status
Simulation time 890601187 ps
CPU time 5.28 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 209132 kb
Host smart-2f346a6a-9aba-447a-808e-e48b91bca49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314759421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3314759421
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4253673359
Short name T246
Test name
Test status
Simulation time 129221845 ps
CPU time 2.62 seconds
Started Jun 10 05:35:42 PM PDT 24
Finished Jun 10 05:35:45 PM PDT 24
Peak memory 207428 kb
Host smart-66533099-6e59-4392-8c09-8980a5531a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253673359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4253673359
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4062296389
Short name T709
Test name
Test status
Simulation time 53652843 ps
CPU time 3.03 seconds
Started Jun 10 05:35:43 PM PDT 24
Finished Jun 10 05:35:47 PM PDT 24
Peak memory 208764 kb
Host smart-5865d47a-5ccb-49a0-83a6-4fb100d64c72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062296389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4062296389
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2474928267
Short name T901
Test name
Test status
Simulation time 353394559 ps
CPU time 2.43 seconds
Started Jun 10 05:35:40 PM PDT 24
Finished Jun 10 05:35:43 PM PDT 24
Peak memory 206896 kb
Host smart-97330fac-9f54-468a-8956-7d6ddddf22d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474928267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2474928267
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.441329419
Short name T614
Test name
Test status
Simulation time 53730437 ps
CPU time 1.98 seconds
Started Jun 10 05:35:47 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 209056 kb
Host smart-4eb27882-dc38-4823-8f06-ddfafbff8805
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441329419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.441329419
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3169891514
Short name T579
Test name
Test status
Simulation time 248277459 ps
CPU time 2.62 seconds
Started Jun 10 05:35:41 PM PDT 24
Finished Jun 10 05:35:44 PM PDT 24
Peak memory 206852 kb
Host smart-1d5384c5-4435-4d71-b3a9-f9fcc1dd1543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169891514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3169891514
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3091413191
Short name T331
Test name
Test status
Simulation time 382518150 ps
CPU time 6.14 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:53 PM PDT 24
Peak memory 219748 kb
Host smart-31c4bb38-ec11-4ff4-b078-c368842c467b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091413191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3091413191
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.379097536
Short name T194
Test name
Test status
Simulation time 261606700 ps
CPU time 8.43 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 208656 kb
Host smart-348c6c00-3d7a-4733-92d9-c15ccc0c38da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379097536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.379097536
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1851956586
Short name T809
Test name
Test status
Simulation time 46881239 ps
CPU time 1.95 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:48 PM PDT 24
Peak memory 209916 kb
Host smart-bebc2c52-e090-48ee-a7db-2db14a4423e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851956586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1851956586
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1576978037
Short name T860
Test name
Test status
Simulation time 31528028 ps
CPU time 0.91 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:35:50 PM PDT 24
Peak memory 205936 kb
Host smart-9c95b703-537d-421c-917e-1a3d3cb3fa48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576978037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1576978037
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3023160114
Short name T748
Test name
Test status
Simulation time 113482301 ps
CPU time 2.64 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:48 PM PDT 24
Peak memory 221564 kb
Host smart-7e7a8b56-4ba4-4591-8c27-8fbbfd77c2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023160114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3023160114
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.952551472
Short name T318
Test name
Test status
Simulation time 64129740 ps
CPU time 3.3 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 209268 kb
Host smart-879aba3a-08f8-4428-a26a-f23c45749908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952551472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.952551472
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1887793707
Short name T277
Test name
Test status
Simulation time 99175858 ps
CPU time 2.12 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:35:47 PM PDT 24
Peak memory 214192 kb
Host smart-ea069da4-cda8-43a9-b902-27397b5dd7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887793707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1887793707
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1119423101
Short name T206
Test name
Test status
Simulation time 63648168 ps
CPU time 2.62 seconds
Started Jun 10 05:35:48 PM PDT 24
Finished Jun 10 05:35:51 PM PDT 24
Peak memory 220456 kb
Host smart-1b7d60e2-620a-4577-9f96-70c691b357e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119423101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1119423101
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1537834196
Short name T797
Test name
Test status
Simulation time 4849257634 ps
CPU time 8.1 seconds
Started Jun 10 05:35:51 PM PDT 24
Finished Jun 10 05:36:00 PM PDT 24
Peak memory 210564 kb
Host smart-86b84f97-a00e-4614-9bd9-98ffd576eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537834196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1537834196
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1955830603
Short name T724
Test name
Test status
Simulation time 795284327 ps
CPU time 3.81 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:50 PM PDT 24
Peak memory 206844 kb
Host smart-dae1ae0c-54d2-4ebd-970d-0faea13de78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955830603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1955830603
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.292616196
Short name T259
Test name
Test status
Simulation time 902290445 ps
CPU time 5.98 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:35:51 PM PDT 24
Peak memory 207860 kb
Host smart-3d7a7214-c61d-48cb-bcdd-eaeaef20d029
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292616196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.292616196
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3602233460
Short name T429
Test name
Test status
Simulation time 141381554 ps
CPU time 4.31 seconds
Started Jun 10 05:35:45 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 206992 kb
Host smart-48d26ae4-6d24-4b06-a50c-c435a0ff2747
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602233460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3602233460
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4127484491
Short name T578
Test name
Test status
Simulation time 3610736782 ps
CPU time 27.63 seconds
Started Jun 10 05:35:43 PM PDT 24
Finished Jun 10 05:36:11 PM PDT 24
Peak memory 208840 kb
Host smart-33c9d345-8254-4992-b395-88210db4cf48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127484491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4127484491
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1852178373
Short name T268
Test name
Test status
Simulation time 39277529 ps
CPU time 2.25 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 208360 kb
Host smart-c587948d-d28b-4eda-b44a-df09f7747062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852178373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1852178373
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3436969678
Short name T508
Test name
Test status
Simulation time 133644113 ps
CPU time 2.18 seconds
Started Jun 10 05:35:44 PM PDT 24
Finished Jun 10 05:35:46 PM PDT 24
Peak memory 207148 kb
Host smart-fa292a5d-03de-4c40-96d0-9bd49c428ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436969678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3436969678
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1470195712
Short name T467
Test name
Test status
Simulation time 98567943 ps
CPU time 4.75 seconds
Started Jun 10 05:35:46 PM PDT 24
Finished Jun 10 05:35:51 PM PDT 24
Peak memory 222564 kb
Host smart-a692bf3d-4e76-449e-a9ff-493fe9775b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470195712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1470195712
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3304649635
Short name T571
Test name
Test status
Simulation time 326864684 ps
CPU time 6.41 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 210360 kb
Host smart-e8ff57da-3671-4e9e-860e-1af837cac68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304649635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3304649635
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.849809095
Short name T803
Test name
Test status
Simulation time 30101815 ps
CPU time 0.78 seconds
Started Jun 10 05:35:51 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 205964 kb
Host smart-e124b4c0-0e62-498b-9092-da4ebf5d7acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849809095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.849809095
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3770634409
Short name T752
Test name
Test status
Simulation time 48441557 ps
CPU time 2.6 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 209772 kb
Host smart-fe2f0b39-d0d7-4f85-b497-f687ccf738f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770634409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3770634409
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2968863283
Short name T83
Test name
Test status
Simulation time 47639272 ps
CPU time 3.35 seconds
Started Jun 10 05:35:48 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 214848 kb
Host smart-a48c472d-2b05-4e41-9131-63192742333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968863283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2968863283
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3032183367
Short name T48
Test name
Test status
Simulation time 101264590 ps
CPU time 3.45 seconds
Started Jun 10 05:35:51 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 215208 kb
Host smart-729982f3-d4bd-4d5d-a867-e3a62176e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032183367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3032183367
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3011493078
Short name T875
Test name
Test status
Simulation time 96663019 ps
CPU time 2.33 seconds
Started Jun 10 05:35:53 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 209692 kb
Host smart-1d5f89da-3062-4af2-a0c4-22e3e9f04b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011493078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3011493078
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2185278338
Short name T336
Test name
Test status
Simulation time 1513842500 ps
CPU time 27.6 seconds
Started Jun 10 05:35:51 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 209988 kb
Host smart-2d520864-4672-4d4c-a874-f5ea7180befb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185278338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2185278338
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2411442355
Short name T454
Test name
Test status
Simulation time 501804042 ps
CPU time 4.48 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:35:54 PM PDT 24
Peak memory 206808 kb
Host smart-71adfacb-15fc-4acc-9e4e-f1b3d81ebd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411442355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2411442355
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2652215418
Short name T585
Test name
Test status
Simulation time 728072201 ps
CPU time 5.72 seconds
Started Jun 10 05:35:48 PM PDT 24
Finished Jun 10 05:35:54 PM PDT 24
Peak memory 208936 kb
Host smart-2b95f0bd-e7d3-4d67-a355-44638090f1f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652215418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2652215418
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4140618328
Short name T593
Test name
Test status
Simulation time 142628664 ps
CPU time 2.33 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:35:53 PM PDT 24
Peak memory 206872 kb
Host smart-931376b6-718a-4f03-8016-ca9f1fd2672f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140618328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4140618328
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2934613265
Short name T722
Test name
Test status
Simulation time 2100444302 ps
CPU time 4.12 seconds
Started Jun 10 05:35:51 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 207640 kb
Host smart-a8191c72-7ff9-4360-90f9-56faab074412
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934613265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2934613265
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3096425649
Short name T685
Test name
Test status
Simulation time 500184655 ps
CPU time 3.3 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:35:53 PM PDT 24
Peak memory 209676 kb
Host smart-6cfdb031-3327-4461-8575-fd1ab6f83860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096425649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3096425649
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2104590836
Short name T727
Test name
Test status
Simulation time 79079094 ps
CPU time 3.09 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:06 PM PDT 24
Peak memory 208396 kb
Host smart-aaf5b9a6-978f-460e-9098-f21b526844c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104590836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2104590836
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3085537926
Short name T778
Test name
Test status
Simulation time 1143343504 ps
CPU time 16.99 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:36:07 PM PDT 24
Peak memory 215992 kb
Host smart-7c3246bf-7812-478a-bf8c-b4a078dd9575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085537926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3085537926
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2591318063
Short name T562
Test name
Test status
Simulation time 364045276 ps
CPU time 4.57 seconds
Started Jun 10 05:35:51 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 208728 kb
Host smart-51dafab1-3fc5-439e-9f0c-9b3c2b8e5e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591318063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2591318063
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3345647663
Short name T481
Test name
Test status
Simulation time 145270884 ps
CPU time 2.07 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 210436 kb
Host smart-34ef179b-6df8-4f62-87bb-d4e22cce8103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345647663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3345647663
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1636649820
Short name T525
Test name
Test status
Simulation time 32279106 ps
CPU time 0.97 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:35:57 PM PDT 24
Peak memory 206100 kb
Host smart-d2ea4e29-cdfb-4169-8257-6068e3d286b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636649820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1636649820
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.198691112
Short name T384
Test name
Test status
Simulation time 1160743830 ps
CPU time 6.06 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 215464 kb
Host smart-f692c6bf-5c74-46ee-8c9c-3d4ae445bcf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198691112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.198691112
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1582653125
Short name T298
Test name
Test status
Simulation time 63393974 ps
CPU time 3.08 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:35:53 PM PDT 24
Peak memory 214436 kb
Host smart-1be99ad5-4a11-4d14-bedb-96580870790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582653125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1582653125
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2881652959
Short name T278
Test name
Test status
Simulation time 236260116 ps
CPU time 2.17 seconds
Started Jun 10 05:35:53 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 214356 kb
Host smart-c9108c18-86fa-48b8-bf7c-5bd4496e06c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881652959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2881652959
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.187315020
Short name T345
Test name
Test status
Simulation time 137334429 ps
CPU time 3.46 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:35:54 PM PDT 24
Peak memory 214264 kb
Host smart-38c44840-2c1d-4d5d-bfac-13aea88133a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187315020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.187315020
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.951320167
Short name T911
Test name
Test status
Simulation time 58658645 ps
CPU time 4.2 seconds
Started Jun 10 05:35:52 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 210972 kb
Host smart-4485f9a1-514c-428d-9651-24ed17e4243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951320167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.951320167
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2831107908
Short name T632
Test name
Test status
Simulation time 2649487577 ps
CPU time 27.32 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 214420 kb
Host smart-c0689b9b-ff6c-48a5-a9ef-f7084e271aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831107908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2831107908
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2510137769
Short name T576
Test name
Test status
Simulation time 286425878 ps
CPU time 3.9 seconds
Started Jun 10 05:35:48 PM PDT 24
Finished Jun 10 05:35:52 PM PDT 24
Peak memory 207888 kb
Host smart-6ec4a813-3fbd-464e-8f0c-dd4c4b9cc7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510137769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2510137769
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2153776800
Short name T610
Test name
Test status
Simulation time 6253231443 ps
CPU time 39.16 seconds
Started Jun 10 05:35:49 PM PDT 24
Finished Jun 10 05:36:29 PM PDT 24
Peak memory 209276 kb
Host smart-ef8ad410-3991-4488-998e-63afe7072959
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153776800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2153776800
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.89636728
Short name T293
Test name
Test status
Simulation time 302286851 ps
CPU time 4.93 seconds
Started Jun 10 05:35:50 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 208556 kb
Host smart-12c9c748-7c08-4282-9770-8d89a2c0b5f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89636728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.89636728
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3675991602
Short name T572
Test name
Test status
Simulation time 48195402 ps
CPU time 2.74 seconds
Started Jun 10 05:35:53 PM PDT 24
Finished Jun 10 05:35:57 PM PDT 24
Peak memory 207028 kb
Host smart-ce21cae1-f0ee-4bd4-9fed-3ca556d693fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675991602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3675991602
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1838392441
Short name T397
Test name
Test status
Simulation time 291649398 ps
CPU time 2.49 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 215308 kb
Host smart-1f23924f-57b9-4def-9dcf-c2458122689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838392441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1838392441
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2294810508
Short name T455
Test name
Test status
Simulation time 28940235 ps
CPU time 2.15 seconds
Started Jun 10 05:35:52 PM PDT 24
Finished Jun 10 05:35:54 PM PDT 24
Peak memory 206936 kb
Host smart-00d92d7d-201e-49da-a26f-fa90a0b1042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294810508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2294810508
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2494446501
Short name T230
Test name
Test status
Simulation time 426896031 ps
CPU time 6.27 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:09 PM PDT 24
Peak memory 218148 kb
Host smart-bc7e376d-2251-4765-a42c-5fdf5f4db858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494446501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2494446501
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1889734120
Short name T776
Test name
Test status
Simulation time 325397197 ps
CPU time 3.08 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:35:58 PM PDT 24
Peak memory 210652 kb
Host smart-b8f97266-f3c3-45e9-9fbb-41b6a7b08a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889734120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1889734120
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3816818154
Short name T423
Test name
Test status
Simulation time 23688612 ps
CPU time 0.76 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:04 PM PDT 24
Peak memory 205892 kb
Host smart-59458e9b-51cd-4f23-979e-c0d190a4dbfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816818154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3816818154
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2878910274
Short name T359
Test name
Test status
Simulation time 205064041 ps
CPU time 3.27 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:35:58 PM PDT 24
Peak memory 218344 kb
Host smart-d3b5574c-bdeb-4d50-9836-67e09eab75f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878910274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2878910274
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1125967457
Short name T228
Test name
Test status
Simulation time 137959733 ps
CPU time 3.45 seconds
Started Jun 10 05:35:53 PM PDT 24
Finished Jun 10 05:35:57 PM PDT 24
Peak memory 222440 kb
Host smart-5a6d4696-30b8-4182-973d-602255101ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125967457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1125967457
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2456216724
Short name T594
Test name
Test status
Simulation time 64782483 ps
CPU time 2.18 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 207092 kb
Host smart-3f3a14fa-a2bc-405a-9fc3-ad553a5ec10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456216724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2456216724
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3040613940
Short name T836
Test name
Test status
Simulation time 75699559 ps
CPU time 3.2 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:35:59 PM PDT 24
Peak memory 208196 kb
Host smart-1a157047-50b6-4191-8828-4e3a47ddda05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040613940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3040613940
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1684916978
Short name T436
Test name
Test status
Simulation time 34514015 ps
CPU time 2.3 seconds
Started Jun 10 05:35:56 PM PDT 24
Finished Jun 10 05:35:59 PM PDT 24
Peak memory 206892 kb
Host smart-d4501d51-7e75-4e4d-b485-1a97300647aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684916978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1684916978
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.103708986
Short name T487
Test name
Test status
Simulation time 240410971 ps
CPU time 3.13 seconds
Started Jun 10 05:35:56 PM PDT 24
Finished Jun 10 05:36:00 PM PDT 24
Peak memory 206860 kb
Host smart-703c4653-82d2-43c2-a9a2-9746c7354252
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103708986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.103708986
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2019514488
Short name T460
Test name
Test status
Simulation time 107352653 ps
CPU time 4.11 seconds
Started Jun 10 05:35:56 PM PDT 24
Finished Jun 10 05:36:00 PM PDT 24
Peak memory 206992 kb
Host smart-41a413ac-e9e2-42f2-9e57-ee315cca93da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019514488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2019514488
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2224251874
Short name T524
Test name
Test status
Simulation time 8116128432 ps
CPU time 11.7 seconds
Started Jun 10 05:35:56 PM PDT 24
Finished Jun 10 05:36:08 PM PDT 24
Peak memory 208760 kb
Host smart-0c97faea-3b6d-41ef-8933-1b082ce31d9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224251874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2224251874
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.433300941
Short name T77
Test name
Test status
Simulation time 82311047 ps
CPU time 2.23 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 209588 kb
Host smart-b418e1ea-1d2c-456c-b6df-280803b7851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433300941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.433300941
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1697407894
Short name T854
Test name
Test status
Simulation time 865059673 ps
CPU time 5.38 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 207940 kb
Host smart-b7cdb37d-ce10-4fa0-bb67-ee275c008786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697407894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1697407894
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.42760614
Short name T898
Test name
Test status
Simulation time 296999392 ps
CPU time 3.72 seconds
Started Jun 10 05:35:52 PM PDT 24
Finished Jun 10 05:35:56 PM PDT 24
Peak memory 207672 kb
Host smart-10eac090-c7a9-4882-a30b-61b3a5005247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42760614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.42760614
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2462909497
Short name T852
Test name
Test status
Simulation time 811111846 ps
CPU time 2.4 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:35:58 PM PDT 24
Peak memory 210828 kb
Host smart-eedfd8c6-5010-4e68-9a84-b55a1b503b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462909497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2462909497
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1353126596
Short name T650
Test name
Test status
Simulation time 22841554 ps
CPU time 1.1 seconds
Started Jun 10 05:34:50 PM PDT 24
Finished Jun 10 05:34:51 PM PDT 24
Peak memory 206028 kb
Host smart-03821330-67d9-4fec-9852-a39eac066261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353126596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1353126596
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1020143493
Short name T99
Test name
Test status
Simulation time 25827772 ps
CPU time 2.11 seconds
Started Jun 10 05:34:52 PM PDT 24
Finished Jun 10 05:34:54 PM PDT 24
Peak memory 214328 kb
Host smart-bb0e5e53-fdc0-4abc-9bf2-6dc48aa760f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020143493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1020143493
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2915527236
Short name T512
Test name
Test status
Simulation time 135665574 ps
CPU time 2.67 seconds
Started Jun 10 05:34:53 PM PDT 24
Finished Jun 10 05:34:56 PM PDT 24
Peak memory 222736 kb
Host smart-7d62b9ee-4091-4251-a0bc-cbcd587a24c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915527236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2915527236
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.651460648
Short name T497
Test name
Test status
Simulation time 3847959078 ps
CPU time 24.16 seconds
Started Jun 10 05:34:51 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 218552 kb
Host smart-3e3b67e7-99c3-41c8-83fc-80ee9c19e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651460648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.651460648
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3868438513
Short name T884
Test name
Test status
Simulation time 83531661 ps
CPU time 2.75 seconds
Started Jun 10 05:34:50 PM PDT 24
Finished Jun 10 05:34:54 PM PDT 24
Peak memory 221848 kb
Host smart-7567afa9-d773-40b0-ba15-6ede61020334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868438513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3868438513
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.676119448
Short name T398
Test name
Test status
Simulation time 100029342 ps
CPU time 3.67 seconds
Started Jun 10 05:34:51 PM PDT 24
Finished Jun 10 05:34:55 PM PDT 24
Peak memory 209884 kb
Host smart-3b7467ac-babd-4f5b-9937-2155dd1a20c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676119448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.676119448
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2985511332
Short name T9
Test name
Test status
Simulation time 431851279 ps
CPU time 6.54 seconds
Started Jun 10 05:34:51 PM PDT 24
Finished Jun 10 05:34:57 PM PDT 24
Peak memory 237344 kb
Host smart-a0716f46-58b5-4d10-9e27-a2d1defd4d51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985511332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2985511332
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1533960324
Short name T295
Test name
Test status
Simulation time 885120065 ps
CPU time 4.29 seconds
Started Jun 10 05:34:50 PM PDT 24
Finished Jun 10 05:34:54 PM PDT 24
Peak memory 206952 kb
Host smart-5f3e644f-d788-49f7-856f-8db788414855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533960324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1533960324
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3257420671
Short name T643
Test name
Test status
Simulation time 1035269388 ps
CPU time 28.89 seconds
Started Jun 10 05:34:51 PM PDT 24
Finished Jun 10 05:35:20 PM PDT 24
Peak memory 207904 kb
Host smart-28bb39d7-fcc8-48b5-b59d-bf498095c914
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257420671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3257420671
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2287000231
Short name T573
Test name
Test status
Simulation time 1924786566 ps
CPU time 24 seconds
Started Jun 10 05:34:50 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 208484 kb
Host smart-c08f0f8f-fa89-45a4-8933-4fa29a23fd97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287000231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2287000231
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2706885695
Short name T503
Test name
Test status
Simulation time 210814339 ps
CPU time 2.82 seconds
Started Jun 10 05:34:54 PM PDT 24
Finished Jun 10 05:34:57 PM PDT 24
Peak memory 208748 kb
Host smart-2ec32abb-88a3-439d-90f8-1c53261d61f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706885695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2706885695
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3645624353
Short name T869
Test name
Test status
Simulation time 2885567446 ps
CPU time 9.63 seconds
Started Jun 10 05:34:56 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 209032 kb
Host smart-f874af33-71e3-4923-bf61-c152a52f502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645624353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3645624353
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.406171990
Short name T612
Test name
Test status
Simulation time 464045368 ps
CPU time 4.83 seconds
Started Jun 10 05:34:47 PM PDT 24
Finished Jun 10 05:34:52 PM PDT 24
Peak memory 207880 kb
Host smart-6cf12e49-6c78-4413-ac5a-19d818151314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406171990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.406171990
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2865678086
Short name T842
Test name
Test status
Simulation time 1289213973 ps
CPU time 13.67 seconds
Started Jun 10 05:34:56 PM PDT 24
Finished Jun 10 05:35:10 PM PDT 24
Peak memory 220828 kb
Host smart-f9a98867-f3a1-4d42-9ddf-746ee510e4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865678086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2865678086
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.669188148
Short name T204
Test name
Test status
Simulation time 235676231 ps
CPU time 6.29 seconds
Started Jun 10 05:34:49 PM PDT 24
Finished Jun 10 05:34:56 PM PDT 24
Peak memory 220336 kb
Host smart-381be51d-39f7-430f-bf2b-85090ff6f1c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669188148 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.669188148
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.385035087
Short name T872
Test name
Test status
Simulation time 104229349 ps
CPU time 3.51 seconds
Started Jun 10 05:34:52 PM PDT 24
Finished Jun 10 05:34:56 PM PDT 24
Peak memory 208192 kb
Host smart-4ebeb454-960a-4741-a61c-e4c52b3be0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385035087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.385035087
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.938674472
Short name T630
Test name
Test status
Simulation time 122716900 ps
CPU time 4.3 seconds
Started Jun 10 05:34:54 PM PDT 24
Finished Jun 10 05:34:59 PM PDT 24
Peak memory 210136 kb
Host smart-6cca0300-18e3-4399-862b-7fe44f8f099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938674472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.938674472
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2040166061
Short name T504
Test name
Test status
Simulation time 68801842 ps
CPU time 0.77 seconds
Started Jun 10 05:36:00 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 205940 kb
Host smart-e819b008-3f71-4b04-8235-dbb3ca064ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040166061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2040166061
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1944229108
Short name T419
Test name
Test status
Simulation time 55928764 ps
CPU time 2.63 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 214384 kb
Host smart-ca3a663f-84b1-4481-a3d3-93235c324c42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944229108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1944229108
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1687638585
Short name T445
Test name
Test status
Simulation time 79155840 ps
CPU time 2.97 seconds
Started Jun 10 05:36:00 PM PDT 24
Finished Jun 10 05:36:04 PM PDT 24
Peak memory 219008 kb
Host smart-432706ab-8c4f-4041-ad4c-a87d771b49ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687638585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1687638585
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3790201513
Short name T74
Test name
Test status
Simulation time 59760849 ps
CPU time 2.81 seconds
Started Jun 10 05:35:59 PM PDT 24
Finished Jun 10 05:36:02 PM PDT 24
Peak memory 208708 kb
Host smart-09ad29c3-752b-478b-b6b8-3fc46e5d7ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790201513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3790201513
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3133400302
Short name T84
Test name
Test status
Simulation time 1360334967 ps
CPU time 6.4 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 221800 kb
Host smart-deb534ab-7f85-457c-93ba-03ccb6e5700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133400302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3133400302
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.424924409
Short name T346
Test name
Test status
Simulation time 35125760 ps
CPU time 2.05 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 214276 kb
Host smart-d908f3ea-25cd-4365-b2cf-62fb5eed1fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424924409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.424924409
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2404617721
Short name T684
Test name
Test status
Simulation time 114391189 ps
CPU time 2.52 seconds
Started Jun 10 05:35:59 PM PDT 24
Finished Jun 10 05:36:02 PM PDT 24
Peak memory 214336 kb
Host smart-9cd4154f-d971-4142-9a69-2d2f827192b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404617721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2404617721
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.872448268
Short name T195
Test name
Test status
Simulation time 380167474 ps
CPU time 4.6 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:03 PM PDT 24
Peak memory 207816 kb
Host smart-a666273f-3959-4971-aaea-f9d896f08bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872448268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.872448268
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3668428041
Short name T427
Test name
Test status
Simulation time 195370596 ps
CPU time 4.83 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:36:00 PM PDT 24
Peak memory 208876 kb
Host smart-20a35ded-73c4-42ae-9494-de2f12c29523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668428041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3668428041
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.842295282
Short name T818
Test name
Test status
Simulation time 101153117 ps
CPU time 4.15 seconds
Started Jun 10 05:36:00 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 208644 kb
Host smart-955be4e4-89ab-4960-a643-fd21cd1399fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842295282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.842295282
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1421810328
Short name T703
Test name
Test status
Simulation time 329643152 ps
CPU time 5.34 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:04 PM PDT 24
Peak memory 208016 kb
Host smart-106c3b13-c6d7-49e9-a0e4-6f101cce148a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421810328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1421810328
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2491852716
Short name T919
Test name
Test status
Simulation time 1461772431 ps
CPU time 44.17 seconds
Started Jun 10 05:35:59 PM PDT 24
Finished Jun 10 05:36:44 PM PDT 24
Peak memory 208468 kb
Host smart-a2954489-d99c-4fa1-8fa8-6c31d0c18c5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491852716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2491852716
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.224422374
Short name T395
Test name
Test status
Simulation time 82330014 ps
CPU time 2.01 seconds
Started Jun 10 05:35:59 PM PDT 24
Finished Jun 10 05:36:02 PM PDT 24
Peak memory 215496 kb
Host smart-d7ac0604-4ad4-482e-b235-ab09c6b1f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224422374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.224422374
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3332780123
Short name T541
Test name
Test status
Simulation time 394641574 ps
CPU time 9.4 seconds
Started Jun 10 05:35:55 PM PDT 24
Finished Jun 10 05:36:04 PM PDT 24
Peak memory 208464 kb
Host smart-128c277f-fb0b-4e88-b1dd-231b02695616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332780123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3332780123
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1504689911
Short name T658
Test name
Test status
Simulation time 98980467 ps
CPU time 2.17 seconds
Started Jun 10 05:36:04 PM PDT 24
Finished Jun 10 05:36:06 PM PDT 24
Peak memory 207508 kb
Host smart-5ff2b732-57c5-4f1c-b3ec-2daa3975230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504689911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1504689911
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1253213320
Short name T90
Test name
Test status
Simulation time 22642453 ps
CPU time 0.76 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:04 PM PDT 24
Peak memory 205952 kb
Host smart-970c7aeb-95e4-4e5d-9593-0395f7feb1d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253213320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1253213320
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3237921081
Short name T412
Test name
Test status
Simulation time 209326751 ps
CPU time 9.86 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:12 PM PDT 24
Peak memory 215136 kb
Host smart-0bdb6495-118e-4e2f-890d-c97b3faa5d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237921081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3237921081
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1201110185
Short name T551
Test name
Test status
Simulation time 264809199 ps
CPU time 7.56 seconds
Started Jun 10 05:36:00 PM PDT 24
Finished Jun 10 05:36:09 PM PDT 24
Peak memory 210432 kb
Host smart-f3ce74d8-c1e6-42a4-8685-706fa9ed221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201110185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1201110185
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3226244751
Short name T745
Test name
Test status
Simulation time 923575029 ps
CPU time 20.8 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:24 PM PDT 24
Peak memory 214356 kb
Host smart-729d420e-30e8-403d-906b-764c8e5c372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226244751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3226244751
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2852260103
Short name T858
Test name
Test status
Simulation time 126284567 ps
CPU time 4.66 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 208844 kb
Host smart-05f55bc0-df94-4187-889f-61390a4d1197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852260103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2852260103
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2950290197
Short name T2
Test name
Test status
Simulation time 62595133 ps
CPU time 3.46 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:06 PM PDT 24
Peak memory 218320 kb
Host smart-0424c6d0-8fb4-47e6-9b8b-fe9df762a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950290197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2950290197
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1582522868
Short name T768
Test name
Test status
Simulation time 4595496310 ps
CPU time 31.04 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:34 PM PDT 24
Peak memory 209852 kb
Host smart-d0ba9610-e155-4ae4-a6cd-a172cb054f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582522868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1582522868
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1638061775
Short name T388
Test name
Test status
Simulation time 176440373 ps
CPU time 5.4 seconds
Started Jun 10 05:35:56 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 208020 kb
Host smart-f1c77b97-9c1f-4b1e-b4ab-e03679f360be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638061775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1638061775
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1838632522
Short name T615
Test name
Test status
Simulation time 91824699 ps
CPU time 3.36 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:07 PM PDT 24
Peak memory 207008 kb
Host smart-9d2db270-b821-4929-916a-eff0c0118089
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838632522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1838632522
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2107315067
Short name T791
Test name
Test status
Simulation time 601984063 ps
CPU time 2.66 seconds
Started Jun 10 05:35:59 PM PDT 24
Finished Jun 10 05:36:03 PM PDT 24
Peak memory 206828 kb
Host smart-ed731eed-9a73-49fc-9c7c-3a2e0b12f183
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107315067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2107315067
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.606026504
Short name T272
Test name
Test status
Simulation time 32729849 ps
CPU time 2.52 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 206972 kb
Host smart-4713449a-6564-4ef0-84d3-c75d1342e7ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606026504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.606026504
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1440216276
Short name T498
Test name
Test status
Simulation time 366281061 ps
CPU time 3.09 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 218244 kb
Host smart-181db1ab-174c-4948-8bfe-41531d4cba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440216276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1440216276
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3756974444
Short name T829
Test name
Test status
Simulation time 79749408 ps
CPU time 2.92 seconds
Started Jun 10 05:35:58 PM PDT 24
Finished Jun 10 05:36:01 PM PDT 24
Peak memory 207436 kb
Host smart-78fa4d3e-72d4-490c-b98e-320529f91657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756974444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3756974444
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3662703235
Short name T899
Test name
Test status
Simulation time 528699290 ps
CPU time 21.46 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:25 PM PDT 24
Peak memory 215144 kb
Host smart-226cf04d-09ce-434d-8a75-a599380f83e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662703235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3662703235
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1894329622
Short name T92
Test name
Test status
Simulation time 1261053945 ps
CPU time 8.67 seconds
Started Jun 10 05:36:01 PM PDT 24
Finished Jun 10 05:36:10 PM PDT 24
Peak memory 222608 kb
Host smart-94d278b7-ff2d-4a53-a7ca-f96cb2a2178a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894329622 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1894329622
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2582132594
Short name T674
Test name
Test status
Simulation time 186030634 ps
CPU time 3.36 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:06 PM PDT 24
Peak memory 206656 kb
Host smart-bd368e7e-fd82-4980-8841-4489aeb7c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582132594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2582132594
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.814655363
Short name T154
Test name
Test status
Simulation time 89879567 ps
CPU time 2.33 seconds
Started Jun 10 05:36:05 PM PDT 24
Finished Jun 10 05:36:08 PM PDT 24
Peak memory 210740 kb
Host smart-f05b0e95-0d65-4028-a1e6-13c96d668e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814655363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.814655363
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.278269337
Short name T509
Test name
Test status
Simulation time 9447820 ps
CPU time 0.81 seconds
Started Jun 10 05:36:10 PM PDT 24
Finished Jun 10 05:36:11 PM PDT 24
Peak memory 205968 kb
Host smart-6f1d3059-b867-41de-baf1-482d094a8345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278269337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.278269337
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.682531530
Short name T365
Test name
Test status
Simulation time 449997764 ps
CPU time 6.9 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:10 PM PDT 24
Peak memory 214324 kb
Host smart-2b028b21-e63e-4ece-bef5-689a79316647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682531530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.682531530
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2614877655
Short name T36
Test name
Test status
Simulation time 669548326 ps
CPU time 5.99 seconds
Started Jun 10 05:36:09 PM PDT 24
Finished Jun 10 05:36:15 PM PDT 24
Peak memory 209428 kb
Host smart-df36f9b7-c96c-43b5-85b1-e57994aa468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614877655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2614877655
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.748011990
Short name T47
Test name
Test status
Simulation time 159605989 ps
CPU time 5.86 seconds
Started Jun 10 05:36:04 PM PDT 24
Finished Jun 10 05:36:10 PM PDT 24
Peak memory 214436 kb
Host smart-a147e880-c42d-491e-a627-20ae79fd463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748011990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.748011990
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2187769346
Short name T726
Test name
Test status
Simulation time 8256980103 ps
CPU time 58.58 seconds
Started Jun 10 05:36:09 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 222724 kb
Host smart-748d92c0-044d-432f-b1ea-d4ce31077f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187769346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2187769346
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1432585895
Short name T801
Test name
Test status
Simulation time 350092578 ps
CPU time 3.93 seconds
Started Jun 10 05:36:08 PM PDT 24
Finished Jun 10 05:36:12 PM PDT 24
Peak memory 220792 kb
Host smart-1dc90291-4bed-4221-b4c3-2062ae8ae4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432585895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1432585895
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2771600885
Short name T14
Test name
Test status
Simulation time 112076690 ps
CPU time 2.83 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:06 PM PDT 24
Peak memory 215520 kb
Host smart-a2f293ca-7170-448c-b94b-25035b57f8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771600885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2771600885
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1962884174
Short name T282
Test name
Test status
Simulation time 44500354 ps
CPU time 3.15 seconds
Started Jun 10 05:36:03 PM PDT 24
Finished Jun 10 05:36:07 PM PDT 24
Peak memory 210200 kb
Host smart-40d0388c-5812-4132-a700-7992e456c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962884174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1962884174
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2747573531
Short name T549
Test name
Test status
Simulation time 748816617 ps
CPU time 8.22 seconds
Started Jun 10 05:36:08 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 206952 kb
Host smart-c2850ede-82a1-4413-b370-d5e0261fc8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747573531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2747573531
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.290891073
Short name T176
Test name
Test status
Simulation time 1992445489 ps
CPU time 19.64 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 208108 kb
Host smart-d9211a31-8e2a-4356-9a8b-49ac278f0704
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290891073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.290891073
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1142376048
Short name T529
Test name
Test status
Simulation time 55567662 ps
CPU time 2.82 seconds
Started Jun 10 05:36:07 PM PDT 24
Finished Jun 10 05:36:10 PM PDT 24
Peak memory 206928 kb
Host smart-f1d9a20a-b9d3-449d-a501-4af3537b5997
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142376048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1142376048
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2748369498
Short name T714
Test name
Test status
Simulation time 148122098 ps
CPU time 4.77 seconds
Started Jun 10 05:36:05 PM PDT 24
Finished Jun 10 05:36:10 PM PDT 24
Peak memory 208768 kb
Host smart-86b592cc-1a9a-4f1f-9f8a-50c3d1556840
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748369498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2748369498
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.118481113
Short name T698
Test name
Test status
Simulation time 137118158 ps
CPU time 3.38 seconds
Started Jun 10 05:36:10 PM PDT 24
Finished Jun 10 05:36:14 PM PDT 24
Peak memory 208260 kb
Host smart-b32e6a68-2ff6-407d-a3da-718b7e4f71fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118481113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.118481113
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1352237750
Short name T536
Test name
Test status
Simulation time 132787715 ps
CPU time 1.74 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:05 PM PDT 24
Peak memory 206848 kb
Host smart-0ad94470-26aa-4828-a0a5-89adf52e5301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352237750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1352237750
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2759534042
Short name T547
Test name
Test status
Simulation time 2502273670 ps
CPU time 9.21 seconds
Started Jun 10 05:36:02 PM PDT 24
Finished Jun 10 05:36:11 PM PDT 24
Peak memory 209796 kb
Host smart-4c7e1f7b-055f-4849-be89-6f3a9a4a32bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759534042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2759534042
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2260262686
Short name T177
Test name
Test status
Simulation time 245227489 ps
CPU time 3.02 seconds
Started Jun 10 05:36:11 PM PDT 24
Finished Jun 10 05:36:15 PM PDT 24
Peak memory 209796 kb
Host smart-9fa35ea8-62c0-4eb1-bcb6-7ddddb0f84e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260262686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2260262686
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.401165405
Short name T814
Test name
Test status
Simulation time 37456871 ps
CPU time 0.98 seconds
Started Jun 10 05:36:12 PM PDT 24
Finished Jun 10 05:36:13 PM PDT 24
Peak memory 206256 kb
Host smart-d23b9d5d-e332-44f9-b77c-f2ed458c2151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401165405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.401165405
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2265286494
Short name T353
Test name
Test status
Simulation time 57778697 ps
CPU time 4.23 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 214676 kb
Host smart-7d3791fe-e420-4e00-8b01-942bf890ee01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265286494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2265286494
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.255538105
Short name T18
Test name
Test status
Simulation time 298979101 ps
CPU time 2.32 seconds
Started Jun 10 05:36:14 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 219320 kb
Host smart-2ec21970-0370-4354-8451-8baf8e8d25a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255538105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.255538105
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1725588386
Short name T838
Test name
Test status
Simulation time 36120106 ps
CPU time 1.87 seconds
Started Jun 10 05:36:11 PM PDT 24
Finished Jun 10 05:36:13 PM PDT 24
Peak memory 209824 kb
Host smart-e18b01e2-64db-4777-a1af-2a11e71703c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725588386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1725588386
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1055996327
Short name T371
Test name
Test status
Simulation time 102069991 ps
CPU time 5.18 seconds
Started Jun 10 05:36:14 PM PDT 24
Finished Jun 10 05:36:19 PM PDT 24
Peak memory 222296 kb
Host smart-297bfd1b-29d7-4a23-bfd8-e154c656a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055996327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1055996327
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3179210578
Short name T225
Test name
Test status
Simulation time 259075203 ps
CPU time 3.58 seconds
Started Jun 10 05:36:12 PM PDT 24
Finished Jun 10 05:36:15 PM PDT 24
Peak memory 214540 kb
Host smart-331d0178-378b-418d-a5db-f2fc94b909a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179210578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3179210578
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3157272190
Short name T581
Test name
Test status
Simulation time 106200562 ps
CPU time 2.84 seconds
Started Jun 10 05:36:09 PM PDT 24
Finished Jun 10 05:36:12 PM PDT 24
Peak memory 208084 kb
Host smart-5ab650cf-5177-4c46-bca2-4e902bb748af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157272190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3157272190
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2653598049
Short name T236
Test name
Test status
Simulation time 58593021 ps
CPU time 3.26 seconds
Started Jun 10 05:36:07 PM PDT 24
Finished Jun 10 05:36:11 PM PDT 24
Peak memory 208760 kb
Host smart-69f01e22-86f9-4b78-b926-d65e3024da6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653598049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2653598049
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3128411176
Short name T456
Test name
Test status
Simulation time 336301436 ps
CPU time 2.64 seconds
Started Jun 10 05:36:12 PM PDT 24
Finished Jun 10 05:36:15 PM PDT 24
Peak memory 207328 kb
Host smart-d4676da0-4783-45b3-9bdd-f77ca45188cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128411176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3128411176
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2760283455
Short name T644
Test name
Test status
Simulation time 56225917 ps
CPU time 3.1 seconds
Started Jun 10 05:36:09 PM PDT 24
Finished Jun 10 05:36:12 PM PDT 24
Peak memory 206996 kb
Host smart-3d56ae94-49e0-4c75-8252-32878d7c92a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760283455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2760283455
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.457251438
Short name T669
Test name
Test status
Simulation time 292916425 ps
CPU time 3.64 seconds
Started Jun 10 05:36:12 PM PDT 24
Finished Jun 10 05:36:16 PM PDT 24
Peak memory 209456 kb
Host smart-32ef83c7-e896-4108-b90a-f7a61aecf110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457251438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.457251438
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.172081278
Short name T680
Test name
Test status
Simulation time 97345311 ps
CPU time 3.78 seconds
Started Jun 10 05:36:08 PM PDT 24
Finished Jun 10 05:36:12 PM PDT 24
Peak memory 208596 kb
Host smart-9bf7847a-681f-437b-8606-767a09e1c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172081278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.172081278
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.882621656
Short name T484
Test name
Test status
Simulation time 122549098 ps
CPU time 5.42 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 215912 kb
Host smart-85d56c4b-0a74-4aa7-b289-0cf1263c006d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882621656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.882621656
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4009935686
Short name T501
Test name
Test status
Simulation time 1261192866 ps
CPU time 5.15 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 207996 kb
Host smart-4b2db694-e2c6-4687-8ba6-5d470e58cdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009935686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4009935686
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2005238935
Short name T159
Test name
Test status
Simulation time 122227106 ps
CPU time 2.57 seconds
Started Jun 10 05:36:11 PM PDT 24
Finished Jun 10 05:36:14 PM PDT 24
Peak memory 210388 kb
Host smart-562565a3-5407-4224-b052-72ed969387c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005238935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2005238935
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.419209426
Short name T596
Test name
Test status
Simulation time 195918929 ps
CPU time 1.16 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 206144 kb
Host smart-802f33a1-ffeb-4ee7-bdff-9ab7fde6474a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419209426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.419209426
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3710805931
Short name T609
Test name
Test status
Simulation time 69469800 ps
CPU time 3.12 seconds
Started Jun 10 05:36:49 PM PDT 24
Finished Jun 10 05:36:52 PM PDT 24
Peak memory 209380 kb
Host smart-25f5e19a-0109-4ad0-b459-a3329f9fc7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710805931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3710805931
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.412936659
Short name T788
Test name
Test status
Simulation time 53382289 ps
CPU time 2.78 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:16 PM PDT 24
Peak memory 208872 kb
Host smart-f860997d-36f7-4547-8126-fdbf3356b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412936659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.412936659
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1728238642
Short name T264
Test name
Test status
Simulation time 152765532 ps
CPU time 2.71 seconds
Started Jun 10 05:36:14 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 214320 kb
Host smart-9396fd39-22fd-438b-ae58-c7c668e3c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728238642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1728238642
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2335155405
Short name T207
Test name
Test status
Simulation time 115233401 ps
CPU time 3.21 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:19 PM PDT 24
Peak memory 220212 kb
Host smart-9b27a165-8df5-4c90-b5ec-d1eeb2bc0a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335155405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2335155405
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1989114030
Short name T730
Test name
Test status
Simulation time 506004335 ps
CPU time 4.59 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 207444 kb
Host smart-fc2bda17-d986-4187-be84-21c390bc9559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989114030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1989114030
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1146858756
Short name T256
Test name
Test status
Simulation time 50588592 ps
CPU time 2.82 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:19 PM PDT 24
Peak memory 208736 kb
Host smart-26761fd3-b9b2-48b1-90ba-2862312ef2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146858756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1146858756
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.232423246
Short name T754
Test name
Test status
Simulation time 180971395 ps
CPU time 5.4 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:21 PM PDT 24
Peak memory 208764 kb
Host smart-83849481-0983-451b-8299-5bc9fd378a4d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232423246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.232423246
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3061513755
Short name T705
Test name
Test status
Simulation time 59421662 ps
CPU time 3.18 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 208780 kb
Host smart-602f851b-2a56-42ef-8168-8949c9879c15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061513755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3061513755
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1212158115
Short name T667
Test name
Test status
Simulation time 69113422 ps
CPU time 3.15 seconds
Started Jun 10 05:36:14 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 206928 kb
Host smart-1443da1b-a939-4f3d-9729-db44057cd478
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212158115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1212158115
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.960886335
Short name T488
Test name
Test status
Simulation time 45347712 ps
CPU time 3.1 seconds
Started Jun 10 05:36:17 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 214364 kb
Host smart-c1d61084-ef24-4316-8490-ac5e38cef9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960886335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.960886335
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2039398752
Short name T431
Test name
Test status
Simulation time 643726375 ps
CPU time 4.67 seconds
Started Jun 10 05:36:12 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 208076 kb
Host smart-de03a001-71f5-4586-a4a6-5629d33f4368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039398752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2039398752
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3486267734
Short name T339
Test name
Test status
Simulation time 8185407337 ps
CPU time 62.01 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 222668 kb
Host smart-cd3553a1-082c-4b92-bb66-b3760fa714ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486267734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3486267734
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3066588694
Short name T393
Test name
Test status
Simulation time 737977825 ps
CPU time 3.15 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 210508 kb
Host smart-3dad0168-93a6-4d1e-bcbb-3968b15289d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066588694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3066588694
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3751744154
Short name T91
Test name
Test status
Simulation time 42572503 ps
CPU time 0.88 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 206052 kb
Host smart-b4899c92-35ad-4bfc-8072-cf2d6a5c0b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751744154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3751744154
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4060483423
Short name T386
Test name
Test status
Simulation time 175421501 ps
CPU time 2.52 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:19 PM PDT 24
Peak memory 215180 kb
Host smart-168f0da6-d4cc-4c99-beaf-6be25fe61cb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060483423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4060483423
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2716184810
Short name T895
Test name
Test status
Simulation time 752948456 ps
CPU time 5.1 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:22 PM PDT 24
Peak memory 220168 kb
Host smart-b66d5cd7-54a2-4501-a4ae-1eb3fa31f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716184810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2716184810
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1717114267
Short name T913
Test name
Test status
Simulation time 345990751 ps
CPU time 3.16 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 207572 kb
Host smart-6bd1dfb0-e2bf-42f6-9ed2-e32047bc1eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717114267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1717114267
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3061226584
Short name T275
Test name
Test status
Simulation time 76068909 ps
CPU time 2.72 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:19 PM PDT 24
Peak memory 214396 kb
Host smart-f4886571-9733-432c-b82b-8e4ebe93e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061226584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3061226584
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3781794333
Short name T305
Test name
Test status
Simulation time 150789938 ps
CPU time 5.17 seconds
Started Jun 10 05:36:14 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 207296 kb
Host smart-bee1f300-f702-4300-b0e7-7a29b77312ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781794333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3781794333
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1562024209
Short name T626
Test name
Test status
Simulation time 56811403 ps
CPU time 3.5 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 218312 kb
Host smart-d47a8c1a-4101-4dc1-9178-1c30b5852131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562024209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1562024209
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4119701858
Short name T522
Test name
Test status
Simulation time 37967617 ps
CPU time 2.54 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 207452 kb
Host smart-81889ca1-e4e5-41eb-bbb2-67a39184b65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119701858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4119701858
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3036695116
Short name T461
Test name
Test status
Simulation time 638710215 ps
CPU time 8.42 seconds
Started Jun 10 05:36:17 PM PDT 24
Finished Jun 10 05:36:26 PM PDT 24
Peak memory 208848 kb
Host smart-8e21b8a9-ba0b-4d7f-8881-2ac0a0bc6cf4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036695116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3036695116
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2308247713
Short name T459
Test name
Test status
Simulation time 202140946 ps
CPU time 2.96 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:22 PM PDT 24
Peak memory 206968 kb
Host smart-4c0e2d19-069c-4053-85ae-dabfc0534298
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308247713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2308247713
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1435280791
Short name T520
Test name
Test status
Simulation time 102533119 ps
CPU time 4.23 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 208560 kb
Host smart-8f6f179c-19d6-4501-b1c0-735678177042
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435280791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1435280791
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2974061210
Short name T753
Test name
Test status
Simulation time 108330403 ps
CPU time 2.77 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 218180 kb
Host smart-f9d896e6-8cb8-43b1-b216-7ccf192842dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974061210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2974061210
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.88700055
Short name T606
Test name
Test status
Simulation time 71772963 ps
CPU time 1.75 seconds
Started Jun 10 05:36:15 PM PDT 24
Finished Jun 10 05:36:17 PM PDT 24
Peak memory 207144 kb
Host smart-0cd615b1-bfda-49ff-af09-6f72ec2aed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88700055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.88700055
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3352277272
Short name T267
Test name
Test status
Simulation time 239826838 ps
CPU time 15.72 seconds
Started Jun 10 05:36:14 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 222716 kb
Host smart-638a3c79-c57b-42f9-b9a6-a5e63261379a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352277272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3352277272
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3355351226
Short name T627
Test name
Test status
Simulation time 60509855 ps
CPU time 3.25 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:22 PM PDT 24
Peak memory 208908 kb
Host smart-511984bf-b997-4f6c-aba1-4f01a68baca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355351226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3355351226
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1362395163
Short name T859
Test name
Test status
Simulation time 297996954 ps
CPU time 9.28 seconds
Started Jun 10 05:36:13 PM PDT 24
Finished Jun 10 05:36:23 PM PDT 24
Peak memory 210876 kb
Host smart-bbb30d80-7578-4871-bd3a-555f2ac7f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362395163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1362395163
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.28720643
Short name T493
Test name
Test status
Simulation time 42369810 ps
CPU time 0.85 seconds
Started Jun 10 05:36:20 PM PDT 24
Finished Jun 10 05:36:21 PM PDT 24
Peak memory 206016 kb
Host smart-1c2c8270-9425-4d79-93ba-989d6f7220d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28720643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.28720643
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.425829045
Short name T404
Test name
Test status
Simulation time 69752858 ps
CPU time 3.94 seconds
Started Jun 10 05:36:21 PM PDT 24
Finished Jun 10 05:36:25 PM PDT 24
Peak memory 214384 kb
Host smart-8ce3479e-4bc8-4127-b575-51d27ab60948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425829045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.425829045
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2673132011
Short name T64
Test name
Test status
Simulation time 4723315303 ps
CPU time 30.3 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:50 PM PDT 24
Peak memory 210980 kb
Host smart-b972acf9-84ee-4a78-adce-eedf8a10927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673132011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2673132011
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1471652740
Short name T75
Test name
Test status
Simulation time 258567438 ps
CPU time 2.54 seconds
Started Jun 10 05:36:22 PM PDT 24
Finished Jun 10 05:36:25 PM PDT 24
Peak memory 218180 kb
Host smart-75a970b6-0f97-4a70-bb80-290d3f9632d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471652740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1471652740
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4231625168
Short name T321
Test name
Test status
Simulation time 53129020 ps
CPU time 2.31 seconds
Started Jun 10 05:36:20 PM PDT 24
Finished Jun 10 05:36:22 PM PDT 24
Peak memory 214300 kb
Host smart-3bf17cc2-9dd5-4b61-8337-3d7b2be645eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231625168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4231625168
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1802610316
Short name T55
Test name
Test status
Simulation time 45135318 ps
CPU time 2.8 seconds
Started Jun 10 05:36:20 PM PDT 24
Finished Jun 10 05:36:23 PM PDT 24
Peak memory 222368 kb
Host smart-f14951c9-9f41-47ec-9d62-dc0c2a3e3daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802610316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1802610316
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.881366567
Short name T620
Test name
Test status
Simulation time 376405244 ps
CPU time 2.59 seconds
Started Jun 10 05:36:18 PM PDT 24
Finished Jun 10 05:36:21 PM PDT 24
Peak memory 214320 kb
Host smart-c2981557-be3b-4e5c-9473-92c85973e2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881366567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.881366567
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1746400901
Short name T310
Test name
Test status
Simulation time 1203876943 ps
CPU time 9.44 seconds
Started Jun 10 05:36:17 PM PDT 24
Finished Jun 10 05:36:27 PM PDT 24
Peak memory 218480 kb
Host smart-35902732-4ea8-4048-ae9e-d230f5c7b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746400901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1746400901
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1713294444
Short name T97
Test name
Test status
Simulation time 79675131 ps
CPU time 2.6 seconds
Started Jun 10 05:36:23 PM PDT 24
Finished Jun 10 05:36:26 PM PDT 24
Peak memory 208424 kb
Host smart-191050d6-be37-4d49-b24b-ac031e2f4f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713294444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1713294444
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3628389182
Short name T790
Test name
Test status
Simulation time 239526884 ps
CPU time 6.97 seconds
Started Jun 10 05:36:21 PM PDT 24
Finished Jun 10 05:36:28 PM PDT 24
Peak memory 208428 kb
Host smart-34d7a8d8-97ac-4b6c-b254-cc7d92159d2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628389182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3628389182
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.67221110
Short name T641
Test name
Test status
Simulation time 20439064 ps
CPU time 1.83 seconds
Started Jun 10 05:36:16 PM PDT 24
Finished Jun 10 05:36:18 PM PDT 24
Peak memory 207508 kb
Host smart-bb8aaf6c-453a-4db0-9c4a-3d9e0a920d49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67221110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.67221110
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.490562308
Short name T812
Test name
Test status
Simulation time 251087209 ps
CPU time 3.06 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:23 PM PDT 24
Peak memory 208116 kb
Host smart-dffff4f5-95f1-42f1-8340-797c200729e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490562308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.490562308
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3376251167
Short name T735
Test name
Test status
Simulation time 68370243 ps
CPU time 2.48 seconds
Started Jun 10 05:36:18 PM PDT 24
Finished Jun 10 05:36:21 PM PDT 24
Peak memory 209340 kb
Host smart-434a9ea3-0403-40da-8999-b8c7622fb62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376251167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3376251167
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2745609587
Short name T701
Test name
Test status
Simulation time 266136493 ps
CPU time 2.85 seconds
Started Jun 10 05:36:17 PM PDT 24
Finished Jun 10 05:36:20 PM PDT 24
Peak memory 206716 kb
Host smart-af225dab-8d21-4af0-8faf-7e9eb2547511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745609587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2745609587
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2291753490
Short name T182
Test name
Test status
Simulation time 1703941478 ps
CPU time 9.9 seconds
Started Jun 10 05:36:18 PM PDT 24
Finished Jun 10 05:36:28 PM PDT 24
Peak memory 207648 kb
Host smart-a00956ce-fbc9-4694-884e-3c2e40bfa59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291753490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2291753490
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.138521631
Short name T566
Test name
Test status
Simulation time 145786876 ps
CPU time 3.95 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:23 PM PDT 24
Peak memory 210812 kb
Host smart-3e5e825a-0eca-4379-806a-ed6053e158a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138521631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.138521631
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.4238262322
Short name T882
Test name
Test status
Simulation time 9389420 ps
CPU time 0.81 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:36:26 PM PDT 24
Peak memory 205952 kb
Host smart-a3456e78-66d6-4a77-bf78-80e3da9cb0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238262322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.4238262322
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1233848501
Short name T381
Test name
Test status
Simulation time 252929274 ps
CPU time 3.1 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:27 PM PDT 24
Peak memory 215484 kb
Host smart-2edd81de-8331-4f38-959e-492d44c312e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233848501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1233848501
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2014965222
Short name T873
Test name
Test status
Simulation time 112576031 ps
CPU time 3.33 seconds
Started Jun 10 05:36:26 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 218340 kb
Host smart-ba0d3923-89a1-4dff-9e04-0f9974b7a163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014965222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2014965222
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.245022200
Short name T565
Test name
Test status
Simulation time 163557163 ps
CPU time 2.88 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:27 PM PDT 24
Peak memory 209756 kb
Host smart-525ab35e-bb3c-4ac9-9ca5-d303d4217f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245022200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.245022200
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2967731089
Short name T372
Test name
Test status
Simulation time 702162123 ps
CPU time 4.03 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:28 PM PDT 24
Peak memory 222372 kb
Host smart-e6c33034-b0fb-4488-b673-d2dd73b7301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967731089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2967731089
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3186877728
Short name T279
Test name
Test status
Simulation time 114462939 ps
CPU time 4.61 seconds
Started Jun 10 05:36:27 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 206156 kb
Host smart-6af3a27f-a5cc-4091-9f98-8f45dc108c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186877728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3186877728
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1734755305
Short name T4
Test name
Test status
Simulation time 141860935 ps
CPU time 3.36 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:36:29 PM PDT 24
Peak memory 209404 kb
Host smart-3b6b1ec6-a896-41e5-9b4f-8fde02e00006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734755305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1734755305
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1975887631
Short name T717
Test name
Test status
Simulation time 988591239 ps
CPU time 5.14 seconds
Started Jun 10 05:36:20 PM PDT 24
Finished Jun 10 05:36:25 PM PDT 24
Peak memory 208024 kb
Host smart-dc251645-d54b-4b6d-af7e-39853fe14689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975887631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1975887631
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3837302055
Short name T699
Test name
Test status
Simulation time 20287894281 ps
CPU time 48.3 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 209156 kb
Host smart-6e8b8e6e-85c9-45d0-830c-01f167da6a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837302055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3837302055
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2339675467
Short name T659
Test name
Test status
Simulation time 121938440 ps
CPU time 3.07 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:36:22 PM PDT 24
Peak memory 206740 kb
Host smart-871f174d-3b98-4f2f-a679-45a5761a2804
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339675467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2339675467
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3501068381
Short name T434
Test name
Test status
Simulation time 46494648 ps
CPU time 2.67 seconds
Started Jun 10 05:36:20 PM PDT 24
Finished Jun 10 05:36:23 PM PDT 24
Peak memory 207052 kb
Host smart-e283a856-9e66-46f5-83bd-0dbda90979f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501068381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3501068381
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2232198445
Short name T505
Test name
Test status
Simulation time 6762552655 ps
CPU time 49.34 seconds
Started Jun 10 05:36:19 PM PDT 24
Finished Jun 10 05:37:09 PM PDT 24
Peak memory 209220 kb
Host smart-40a64579-3077-45d1-8091-4d9a9f0d8c4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232198445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2232198445
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2249613368
Short name T237
Test name
Test status
Simulation time 2190268102 ps
CPU time 13.12 seconds
Started Jun 10 05:36:26 PM PDT 24
Finished Jun 10 05:36:40 PM PDT 24
Peak memory 208752 kb
Host smart-7f0c3998-56f4-46cc-bca4-dccf59576211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249613368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2249613368
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3968843735
Short name T861
Test name
Test status
Simulation time 57317606 ps
CPU time 2.37 seconds
Started Jun 10 05:36:20 PM PDT 24
Finished Jun 10 05:36:22 PM PDT 24
Peak memory 206840 kb
Host smart-7d92fd5f-ede3-44bc-a4e1-cf65ea97cc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968843735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3968843735
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3405232964
Short name T112
Test name
Test status
Simulation time 132088315 ps
CPU time 7.81 seconds
Started Jun 10 05:36:22 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 220812 kb
Host smart-3ab02495-45c5-45bf-9359-a3a850b09349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405232964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3405232964
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.908122851
Short name T595
Test name
Test status
Simulation time 114579708 ps
CPU time 5.74 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 207708 kb
Host smart-57014a4c-6a40-4816-bfe4-548fdf099779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908122851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.908122851
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3274378668
Short name T616
Test name
Test status
Simulation time 2132299492 ps
CPU time 10.67 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 210336 kb
Host smart-52a2c57e-3153-4392-984b-bdcca8c2f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274378668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3274378668
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.329545899
Short name T453
Test name
Test status
Simulation time 49929555 ps
CPU time 0.82 seconds
Started Jun 10 05:36:27 PM PDT 24
Finished Jun 10 05:36:28 PM PDT 24
Peak memory 205944 kb
Host smart-41bf0db2-ba48-4cd8-8443-f7bc3a4ccf05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329545899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.329545899
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.397899774
Short name T414
Test name
Test status
Simulation time 570273691 ps
CPU time 8.28 seconds
Started Jun 10 05:36:23 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 214340 kb
Host smart-b96727c8-ce0b-468b-a667-701ed1bd05dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397899774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.397899774
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1413733304
Short name T38
Test name
Test status
Simulation time 214431139 ps
CPU time 2.01 seconds
Started Jun 10 05:36:32 PM PDT 24
Finished Jun 10 05:36:34 PM PDT 24
Peak memory 214204 kb
Host smart-52ed6ebd-2266-478f-8cd7-c28fae2d0415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413733304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1413733304
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2847126352
Short name T539
Test name
Test status
Simulation time 401567473 ps
CPU time 12.31 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:36 PM PDT 24
Peak memory 219580 kb
Host smart-9c67b02a-23e9-4ed8-bd91-3aaf027f1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847126352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2847126352
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3082861913
Short name T362
Test name
Test status
Simulation time 396609848 ps
CPU time 4.89 seconds
Started Jun 10 05:36:26 PM PDT 24
Finished Jun 10 05:36:31 PM PDT 24
Peak memory 214260 kb
Host smart-3b635de9-2bf3-42f4-8152-106b9c711a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082861913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3082861913
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3908338589
Short name T248
Test name
Test status
Simulation time 392395591 ps
CPU time 4.11 seconds
Started Jun 10 05:36:28 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 214260 kb
Host smart-829a1688-ff36-462b-84e7-320dc0b08315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908338589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3908338589
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.453586207
Short name T807
Test name
Test status
Simulation time 179317683 ps
CPU time 2.73 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:36:28 PM PDT 24
Peak memory 209128 kb
Host smart-85841558-3a9e-48e6-885b-7f342374564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453586207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.453586207
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.986994867
Short name T533
Test name
Test status
Simulation time 85968960 ps
CPU time 3.85 seconds
Started Jun 10 05:36:26 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 207132 kb
Host smart-e4590d0f-dcd4-40e3-8453-5e74dc8c9c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986994867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.986994867
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1958586380
Short name T740
Test name
Test status
Simulation time 76936959 ps
CPU time 1.75 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:26 PM PDT 24
Peak memory 206864 kb
Host smart-9f067fc2-047b-4b07-9f21-1c471df0e2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958586380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1958586380
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.685991252
Short name T356
Test name
Test status
Simulation time 82616964 ps
CPU time 1.88 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:36:27 PM PDT 24
Peak memory 208504 kb
Host smart-0df976e2-f92c-42f4-8958-3a84eb8dcf00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685991252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.685991252
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2647725116
Short name T896
Test name
Test status
Simulation time 23187583 ps
CPU time 2.02 seconds
Started Jun 10 05:36:32 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 208780 kb
Host smart-4b71b17b-b046-4d89-92c2-7653da345a2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647725116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2647725116
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1095533510
Short name T868
Test name
Test status
Simulation time 312100820 ps
CPU time 11.89 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:41 PM PDT 24
Peak memory 209076 kb
Host smart-b2eb716a-2735-4a4c-a53a-af0ce62f13f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095533510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1095533510
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3303657962
Short name T332
Test name
Test status
Simulation time 298671930 ps
CPU time 3.96 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 218356 kb
Host smart-cf92438a-78d1-4f3e-b584-60cbc4f2b016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303657962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3303657962
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2531680154
Short name T666
Test name
Test status
Simulation time 328204857 ps
CPU time 3.1 seconds
Started Jun 10 05:36:24 PM PDT 24
Finished Jun 10 05:36:27 PM PDT 24
Peak memory 207120 kb
Host smart-555af8c9-2f0d-49fe-a1f6-fa8b719f33e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531680154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2531680154
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3133260927
Short name T334
Test name
Test status
Simulation time 176121010 ps
CPU time 7.57 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 218000 kb
Host smart-137bcd49-70cd-4efd-81b6-6c1f9411e35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133260927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3133260927
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.4241507767
Short name T892
Test name
Test status
Simulation time 1408336115 ps
CPU time 39.07 seconds
Started Jun 10 05:36:26 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 210328 kb
Host smart-11a3a294-e9ad-410e-88a5-341fab0df825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241507767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.4241507767
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.593612995
Short name T880
Test name
Test status
Simulation time 392568771 ps
CPU time 2.68 seconds
Started Jun 10 05:36:28 PM PDT 24
Finished Jun 10 05:36:31 PM PDT 24
Peak memory 210212 kb
Host smart-7aa79d3c-ed52-4425-a804-2c135e3fabec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593612995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.593612995
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.749192853
Short name T894
Test name
Test status
Simulation time 34614329 ps
CPU time 0.78 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 205976 kb
Host smart-e4e65d87-3e8e-4220-a73f-26d86d5d2a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749192853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.749192853
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2462291770
Short name T29
Test name
Test status
Simulation time 4004720901 ps
CPU time 25.24 seconds
Started Jun 10 05:36:34 PM PDT 24
Finished Jun 10 05:36:59 PM PDT 24
Peak memory 209856 kb
Host smart-e3a6c60c-a9a7-48d6-b153-dc3e7899dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462291770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2462291770
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1325288068
Short name T340
Test name
Test status
Simulation time 506367541 ps
CPU time 12.21 seconds
Started Jun 10 05:36:27 PM PDT 24
Finished Jun 10 05:36:40 PM PDT 24
Peak memory 208236 kb
Host smart-d1af6b63-fb34-4e15-8d8f-638187481ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325288068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1325288068
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3079806985
Short name T348
Test name
Test status
Simulation time 412821186 ps
CPU time 4.81 seconds
Started Jun 10 05:36:27 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 214408 kb
Host smart-29bfd42f-81e0-4dc9-947f-6945c6c66259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079806985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3079806985
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.108114972
Short name T360
Test name
Test status
Simulation time 161015131 ps
CPU time 2.6 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:33 PM PDT 24
Peak memory 214192 kb
Host smart-6baa9be9-a61e-487a-965f-dc91c5f33043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108114972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.108114972
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4041116034
Short name T130
Test name
Test status
Simulation time 451325810 ps
CPU time 5.06 seconds
Started Jun 10 05:36:34 PM PDT 24
Finished Jun 10 05:36:39 PM PDT 24
Peak memory 220288 kb
Host smart-ebb925ef-ca1e-43f2-af06-6482c823dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041116034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4041116034
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1115763146
Short name T466
Test name
Test status
Simulation time 158453440 ps
CPU time 4.76 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:34 PM PDT 24
Peak memory 209516 kb
Host smart-fc258d45-d34d-4610-9e60-2d5293a4d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115763146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1115763146
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.38153182
Short name T554
Test name
Test status
Simulation time 255751843 ps
CPU time 3.21 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:34 PM PDT 24
Peak memory 208356 kb
Host smart-d296e333-b35e-47a9-901b-390ad19c3851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38153182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.38153182
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1389498844
Short name T799
Test name
Test status
Simulation time 220606288 ps
CPU time 3.08 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:33 PM PDT 24
Peak memory 208780 kb
Host smart-e15430ae-92e1-44cf-947c-3589bdd783f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389498844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1389498844
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3761156978
Short name T780
Test name
Test status
Simulation time 920035885 ps
CPU time 24.14 seconds
Started Jun 10 05:36:28 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 209060 kb
Host smart-1c711f43-66a1-4861-ade6-42ee253ee758
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761156978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3761156978
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1050860431
Short name T866
Test name
Test status
Simulation time 373576272 ps
CPU time 7.65 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 208816 kb
Host smart-e1c750c3-d55c-4c09-8db0-b3678b8af6fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050860431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1050860431
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1230524027
Short name T905
Test name
Test status
Simulation time 247192416 ps
CPU time 3.29 seconds
Started Jun 10 05:36:28 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 210112 kb
Host smart-b67e1861-d678-4517-b5a8-7e9d5341d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230524027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1230524027
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1351261408
Short name T185
Test name
Test status
Simulation time 810628304 ps
CPU time 2.84 seconds
Started Jun 10 05:36:28 PM PDT 24
Finished Jun 10 05:36:31 PM PDT 24
Peak memory 208208 kb
Host smart-e3fbde7e-1dda-4a9d-b57f-b5d309f838ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351261408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1351261408
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.399826361
Short name T883
Test name
Test status
Simulation time 91545790 ps
CPU time 4.37 seconds
Started Jun 10 05:36:25 PM PDT 24
Finished Jun 10 05:36:30 PM PDT 24
Peak memory 209728 kb
Host smart-eb930718-b700-4df5-8261-16e0e61bcfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399826361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.399826361
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1820624827
Short name T379
Test name
Test status
Simulation time 72133307 ps
CPU time 1.96 seconds
Started Jun 10 05:36:29 PM PDT 24
Finished Jun 10 05:36:32 PM PDT 24
Peak memory 209988 kb
Host smart-2ba3555c-ef59-4292-b72b-54405a2585df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820624827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1820624827
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2717043230
Short name T676
Test name
Test status
Simulation time 16825227 ps
CPU time 0.99 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:13 PM PDT 24
Peak memory 206016 kb
Host smart-67863cbc-f740-4f53-826c-7435a1784259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717043230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2717043230
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3449976260
Short name T477
Test name
Test status
Simulation time 738686649 ps
CPU time 2.87 seconds
Started Jun 10 05:34:54 PM PDT 24
Finished Jun 10 05:34:58 PM PDT 24
Peak memory 208132 kb
Host smart-a87b7749-dacf-4e91-ad31-9974e0f56778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449976260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3449976260
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.863495083
Short name T584
Test name
Test status
Simulation time 303850504 ps
CPU time 4.35 seconds
Started Jun 10 05:34:54 PM PDT 24
Finished Jun 10 05:34:58 PM PDT 24
Peak memory 222536 kb
Host smart-49d5593f-2147-4602-80e3-7f18292d12fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863495083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.863495083
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3790540171
Short name T678
Test name
Test status
Simulation time 202729395 ps
CPU time 3.15 seconds
Started Jun 10 05:34:57 PM PDT 24
Finished Jun 10 05:35:00 PM PDT 24
Peak memory 215328 kb
Host smart-2515a51a-4142-4566-83f4-be2e50ba2c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790540171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3790540171
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.2993907734
Short name T904
Test name
Test status
Simulation time 1452657682 ps
CPU time 4.88 seconds
Started Jun 10 05:34:56 PM PDT 24
Finished Jun 10 05:35:01 PM PDT 24
Peak memory 207352 kb
Host smart-a8f89c25-3a32-4bd0-bf37-207b9e9cad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993907734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2993907734
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1758088312
Short name T8
Test name
Test status
Simulation time 476317142 ps
CPU time 7.68 seconds
Started Jun 10 05:35:17 PM PDT 24
Finished Jun 10 05:35:26 PM PDT 24
Peak memory 230756 kb
Host smart-48c07dae-b067-45bf-9277-bb57adef6ef6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758088312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1758088312
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3181080654
Short name T223
Test name
Test status
Simulation time 1755768824 ps
CPU time 5.19 seconds
Started Jun 10 05:34:57 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 208084 kb
Host smart-0cdd2dc5-42d8-4e25-ab3b-1f81b511d013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181080654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3181080654
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2330755517
Short name T519
Test name
Test status
Simulation time 33144191 ps
CPU time 2.52 seconds
Started Jun 10 05:34:57 PM PDT 24
Finished Jun 10 05:35:00 PM PDT 24
Peak memory 207612 kb
Host smart-c57c9fae-8259-4461-af46-0c70c247a547
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330755517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2330755517
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3431054675
Short name T608
Test name
Test status
Simulation time 595489127 ps
CPU time 5.06 seconds
Started Jun 10 05:34:56 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 208196 kb
Host smart-2114ec27-0668-479f-98ec-8ffae4c59d6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431054675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3431054675
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2122202981
Short name T845
Test name
Test status
Simulation time 47472869 ps
CPU time 2.1 seconds
Started Jun 10 05:34:57 PM PDT 24
Finished Jun 10 05:35:00 PM PDT 24
Peak memory 208956 kb
Host smart-2421c18b-f6fc-4f7a-8ddd-6ffe4058b5de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122202981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2122202981
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1775284469
Short name T577
Test name
Test status
Simulation time 2199584209 ps
CPU time 17.94 seconds
Started Jun 10 05:34:59 PM PDT 24
Finished Jun 10 05:35:17 PM PDT 24
Peak memory 214384 kb
Host smart-15d82fcb-679c-4887-82bb-942b6728cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775284469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1775284469
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.983913267
Short name T737
Test name
Test status
Simulation time 55358845 ps
CPU time 2.64 seconds
Started Jun 10 05:34:59 PM PDT 24
Finished Jun 10 05:35:01 PM PDT 24
Peak memory 207168 kb
Host smart-be8cb47f-d04c-4e4a-aa29-79993459d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983913267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.983913267
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1106695972
Short name T329
Test name
Test status
Simulation time 6546589911 ps
CPU time 63.3 seconds
Started Jun 10 05:35:03 PM PDT 24
Finished Jun 10 05:36:07 PM PDT 24
Peak memory 222636 kb
Host smart-e9875665-60dc-4a4c-a2fd-c6c0017ccad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106695972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1106695972
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.181122845
Short name T233
Test name
Test status
Simulation time 1277299679 ps
CPU time 19.37 seconds
Started Jun 10 05:35:18 PM PDT 24
Finished Jun 10 05:35:38 PM PDT 24
Peak memory 222568 kb
Host smart-f487f539-ae86-4d68-904f-7198e2931d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181122845 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.181122845
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.983722668
Short name T317
Test name
Test status
Simulation time 230224673 ps
CPU time 3.58 seconds
Started Jun 10 05:34:57 PM PDT 24
Finished Jun 10 05:35:01 PM PDT 24
Peak memory 208228 kb
Host smart-694bd707-4521-4b15-b9c6-b59baab30cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983722668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.983722668
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1606264895
Short name T378
Test name
Test status
Simulation time 67048291 ps
CPU time 2.56 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 210024 kb
Host smart-4863b4d1-1d80-4b4b-ac3d-0d7f596d41e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606264895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1606264895
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2692938564
Short name T766
Test name
Test status
Simulation time 69244875 ps
CPU time 0.89 seconds
Started Jun 10 05:36:33 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 205944 kb
Host smart-d9f6469b-69be-47f3-b4c1-f93ba9660298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692938564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2692938564
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1125886180
Short name T382
Test name
Test status
Simulation time 196485976 ps
CPU time 3.92 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:34 PM PDT 24
Peak memory 215176 kb
Host smart-1191d32a-f5bf-4710-8e47-5e57faf4a89b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125886180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1125886180
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2417181752
Short name T465
Test name
Test status
Simulation time 117411408 ps
CPU time 2.04 seconds
Started Jun 10 05:36:34 PM PDT 24
Finished Jun 10 05:36:36 PM PDT 24
Peak memory 208900 kb
Host smart-c796e631-db70-4a11-996f-b26ccb675e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417181752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2417181752
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1609624006
Short name T673
Test name
Test status
Simulation time 44397776 ps
CPU time 1.83 seconds
Started Jun 10 05:36:33 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 207904 kb
Host smart-f63f88a1-6267-4b53-b9a5-6950df1a4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609624006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1609624006
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3148074747
Short name T88
Test name
Test status
Simulation time 431488397 ps
CPU time 12.37 seconds
Started Jun 10 05:36:32 PM PDT 24
Finished Jun 10 05:36:44 PM PDT 24
Peak memory 220776 kb
Host smart-580b179d-59ed-4964-859d-4e4b02d03f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148074747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3148074747
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2189952766
Short name T648
Test name
Test status
Simulation time 85743347 ps
CPU time 1.88 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:36:39 PM PDT 24
Peak memory 214276 kb
Host smart-0d15e1e2-3df4-4c35-aab0-167e2cf3e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189952766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2189952766
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_random.1405495578
Short name T694
Test name
Test status
Simulation time 2403499043 ps
CPU time 22.32 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 208168 kb
Host smart-d65e1c87-03cc-4c4c-a02c-72e6e8ab7f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405495578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1405495578
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.323946394
Short name T534
Test name
Test status
Simulation time 1186952232 ps
CPU time 36.8 seconds
Started Jun 10 05:36:27 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 208484 kb
Host smart-efbea266-0693-4ecc-841b-9f3429b2598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323946394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.323946394
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3171653416
Short name T558
Test name
Test status
Simulation time 118658128 ps
CPU time 4.07 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:34 PM PDT 24
Peak memory 208940 kb
Host smart-f3422547-ad69-4782-99ff-8971c1c98178
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171653416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3171653416
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.769815337
Short name T449
Test name
Test status
Simulation time 11539277360 ps
CPU time 67.7 seconds
Started Jun 10 05:36:32 PM PDT 24
Finished Jun 10 05:37:41 PM PDT 24
Peak memory 208188 kb
Host smart-ec45b7b6-e3ba-4403-998d-9ff4b565b4dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769815337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.769815337
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2719232263
Short name T76
Test name
Test status
Simulation time 136647506 ps
CPU time 2.38 seconds
Started Jun 10 05:36:34 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 206800 kb
Host smart-7632d44b-a738-473f-bd6d-598bcda121ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719232263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2719232263
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1229639070
Short name T890
Test name
Test status
Simulation time 69341044 ps
CPU time 3.19 seconds
Started Jun 10 05:36:33 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 210260 kb
Host smart-d556f813-41e4-4832-86d6-06083ee42569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229639070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1229639070
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3672545791
Short name T640
Test name
Test status
Simulation time 94191075 ps
CPU time 2.53 seconds
Started Jun 10 05:36:28 PM PDT 24
Finished Jun 10 05:36:31 PM PDT 24
Peak memory 206852 kb
Host smart-44e415d7-13f7-4448-8ebd-61f4205101b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672545791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3672545791
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2546277406
Short name T168
Test name
Test status
Simulation time 1371232473 ps
CPU time 12.19 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:43 PM PDT 24
Peak memory 222640 kb
Host smart-073ade88-d0b7-451c-90d2-ad3467b22944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546277406 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2546277406
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1944912819
Short name T257
Test name
Test status
Simulation time 2619356560 ps
CPU time 27.71 seconds
Started Jun 10 05:36:34 PM PDT 24
Finished Jun 10 05:37:02 PM PDT 24
Peak memory 208460 kb
Host smart-1763ce36-e318-4be7-ac3c-09de06c64e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944912819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1944912819
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2199644698
Short name T729
Test name
Test status
Simulation time 237619580 ps
CPU time 2.24 seconds
Started Jun 10 05:36:35 PM PDT 24
Finished Jun 10 05:36:38 PM PDT 24
Peak memory 210820 kb
Host smart-956e8c1a-1054-4e19-b1d5-b12175212060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199644698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2199644698
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.869451539
Short name T618
Test name
Test status
Simulation time 47196689 ps
CPU time 0.72 seconds
Started Jun 10 05:36:36 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 205976 kb
Host smart-42c87108-31e4-4500-8320-a4bd6cb11e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869451539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.869451539
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3728517055
Short name T338
Test name
Test status
Simulation time 373576573 ps
CPU time 10.77 seconds
Started Jun 10 05:36:36 PM PDT 24
Finished Jun 10 05:36:47 PM PDT 24
Peak memory 214284 kb
Host smart-fda51153-d3dd-4d0f-99c2-d705a7d2d5f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728517055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3728517055
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3266242283
Short name T774
Test name
Test status
Simulation time 95215671 ps
CPU time 4.12 seconds
Started Jun 10 05:36:31 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 210420 kb
Host smart-b850921a-8fe7-43e5-a844-544c02f02437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266242283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3266242283
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2325672544
Short name T79
Test name
Test status
Simulation time 171492512 ps
CPU time 1.94 seconds
Started Jun 10 05:36:36 PM PDT 24
Finished Jun 10 05:36:38 PM PDT 24
Peak memory 214320 kb
Host smart-82eb44e0-cd48-4885-b5fd-c38591f5f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325672544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2325672544
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.930796
Short name T656
Test name
Test status
Simulation time 484620926 ps
CPU time 4.57 seconds
Started Jun 10 05:36:43 PM PDT 24
Finished Jun 10 05:36:47 PM PDT 24
Peak memory 222436 kb
Host smart-ea1a8bff-87c5-4a27-8f1d-df86344f5867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.930796
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.165750641
Short name T441
Test name
Test status
Simulation time 241202042 ps
CPU time 6.15 seconds
Started Jun 10 05:36:31 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 209768 kb
Host smart-f4f0066e-6672-4990-a0c9-68e9f8835ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165750641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.165750641
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3539856307
Short name T826
Test name
Test status
Simulation time 670314530 ps
CPU time 5.13 seconds
Started Jun 10 05:36:36 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 208976 kb
Host smart-542c8a98-cb92-492b-8fbe-eb3c84997d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539856307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3539856307
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.384492600
Short name T665
Test name
Test status
Simulation time 133381883 ps
CPU time 3.35 seconds
Started Jun 10 05:36:34 PM PDT 24
Finished Jun 10 05:36:37 PM PDT 24
Peak memory 208476 kb
Host smart-6be35eee-32a2-4e7c-9de3-45fb5cdf20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384492600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.384492600
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2172950863
Short name T828
Test name
Test status
Simulation time 146000264 ps
CPU time 2.21 seconds
Started Jun 10 05:36:31 PM PDT 24
Finished Jun 10 05:36:33 PM PDT 24
Peak memory 206992 kb
Host smart-8f2408ad-a06e-4d48-9560-7d6509372504
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172950863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2172950863
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1458838924
Short name T589
Test name
Test status
Simulation time 170269196 ps
CPU time 5.17 seconds
Started Jun 10 05:36:32 PM PDT 24
Finished Jun 10 05:36:38 PM PDT 24
Peak memory 209152 kb
Host smart-bcb16c84-befe-4193-87f1-7d7fdeb8a8fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458838924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1458838924
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3782965288
Short name T784
Test name
Test status
Simulation time 27677155 ps
CPU time 2.02 seconds
Started Jun 10 05:36:38 PM PDT 24
Finished Jun 10 05:36:41 PM PDT 24
Peak memory 208544 kb
Host smart-50a08c64-e402-4a59-97dc-1879b7c2fcdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782965288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3782965288
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3024624601
Short name T839
Test name
Test status
Simulation time 188238662 ps
CPU time 5.06 seconds
Started Jun 10 05:36:30 PM PDT 24
Finished Jun 10 05:36:35 PM PDT 24
Peak memory 214372 kb
Host smart-2647b5fb-2e2e-4390-bce3-03e7742575b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024624601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3024624601
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3589492757
Short name T794
Test name
Test status
Simulation time 238950943 ps
CPU time 2.63 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:36:40 PM PDT 24
Peak memory 206764 kb
Host smart-ceda493e-3192-4bb1-b817-b0204fff1791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589492757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3589492757
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2982965721
Short name T309
Test name
Test status
Simulation time 963061162 ps
CPU time 11.17 seconds
Started Jun 10 05:36:31 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 209720 kb
Host smart-784fd24d-6333-4acb-87ba-bfc1f4804771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982965721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2982965721
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3862186147
Short name T652
Test name
Test status
Simulation time 203581119 ps
CPU time 12.75 seconds
Started Jun 10 05:36:38 PM PDT 24
Finished Jun 10 05:36:51 PM PDT 24
Peak memory 221284 kb
Host smart-a600d98a-af4c-44f2-ac45-2271bdbe86a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862186147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3862186147
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2210106366
Short name T679
Test name
Test status
Simulation time 109801281 ps
CPU time 5.02 seconds
Started Jun 10 05:36:33 PM PDT 24
Finished Jun 10 05:36:38 PM PDT 24
Peak memory 208740 kb
Host smart-f81dd2be-d1c7-471b-8282-a0b7e8288abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210106366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2210106366
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4096848289
Short name T870
Test name
Test status
Simulation time 148078242 ps
CPU time 2.07 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:36:39 PM PDT 24
Peak memory 209988 kb
Host smart-dcbe1704-8a74-4016-bc26-f4a2842aa306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096848289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4096848289
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2054587069
Short name T428
Test name
Test status
Simulation time 15451145 ps
CPU time 0.72 seconds
Started Jun 10 05:36:44 PM PDT 24
Finished Jun 10 05:36:45 PM PDT 24
Peak memory 205916 kb
Host smart-05185a36-f5f0-4a21-83e0-d5fb2533a0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054587069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2054587069
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1721548922
Short name T37
Test name
Test status
Simulation time 318538339 ps
CPU time 4.39 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:47 PM PDT 24
Peak memory 220528 kb
Host smart-93fba6df-75f2-49be-9172-cc88f4ede77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721548922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1721548922
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1865418279
Short name T299
Test name
Test status
Simulation time 105283559 ps
CPU time 4.13 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:47 PM PDT 24
Peak memory 208508 kb
Host smart-baeec756-856f-4a46-b822-759a7a2c38b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865418279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1865418279
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2493236347
Short name T86
Test name
Test status
Simulation time 458886255 ps
CPU time 5.1 seconds
Started Jun 10 05:36:35 PM PDT 24
Finished Jun 10 05:36:41 PM PDT 24
Peak memory 220596 kb
Host smart-78899d9c-b7a9-458d-b225-ed15a9bcdd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493236347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2493236347
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2315322473
Short name T209
Test name
Test status
Simulation time 136463639 ps
CPU time 2.81 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:36:41 PM PDT 24
Peak memory 207492 kb
Host smart-07a6a498-9440-42d5-96bd-9a7adcabc5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315322473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2315322473
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3814854333
Short name T474
Test name
Test status
Simulation time 220075154 ps
CPU time 3.85 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:37:00 PM PDT 24
Peak memory 219948 kb
Host smart-877e7b9c-31e7-4474-ac4a-796bb32c1fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814854333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3814854333
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1151440658
Short name T912
Test name
Test status
Simulation time 147266829 ps
CPU time 2.65 seconds
Started Jun 10 05:36:39 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 208492 kb
Host smart-9603d6ce-2b14-43b9-a881-8e74bc04f768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151440658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1151440658
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.891794410
Short name T296
Test name
Test status
Simulation time 35562910 ps
CPU time 2.45 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:36:40 PM PDT 24
Peak memory 207052 kb
Host smart-9bde4ba8-ac24-42b4-8755-cb0680b54723
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891794410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.891794410
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3269113927
Short name T335
Test name
Test status
Simulation time 52164361 ps
CPU time 2.92 seconds
Started Jun 10 05:36:38 PM PDT 24
Finished Jun 10 05:36:41 PM PDT 24
Peak memory 207068 kb
Host smart-c0e90fc2-56c8-4f45-b306-f3d11420f469
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269113927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3269113927
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2397422871
Short name T915
Test name
Test status
Simulation time 2741201855 ps
CPU time 19.81 seconds
Started Jun 10 05:36:43 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 209008 kb
Host smart-3ff0366f-816a-4c47-a697-13cb4ff6a401
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397422871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2397422871
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1839183608
Short name T917
Test name
Test status
Simulation time 928611343 ps
CPU time 7.02 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:49 PM PDT 24
Peak memory 218416 kb
Host smart-bd359131-a7b9-4858-9cb8-3e541ee4adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839183608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1839183608
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2632495470
Short name T848
Test name
Test status
Simulation time 205930623 ps
CPU time 2.92 seconds
Started Jun 10 05:36:43 PM PDT 24
Finished Jun 10 05:36:46 PM PDT 24
Peak memory 208316 kb
Host smart-92b533f9-a5a9-4d23-adda-036016b10217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632495470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2632495470
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2856535754
Short name T100
Test name
Test status
Simulation time 1687803358 ps
CPU time 36.13 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 215308 kb
Host smart-64a2b639-5f5c-4894-a52d-7a93142b27f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856535754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2856535754
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3364513752
Short name T820
Test name
Test status
Simulation time 245860735 ps
CPU time 16.55 seconds
Started Jun 10 05:36:37 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 221080 kb
Host smart-5c3e4250-a52d-4cc5-8ef9-666dd48459f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364513752 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3364513752
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1772181304
Short name T770
Test name
Test status
Simulation time 177249363 ps
CPU time 2.85 seconds
Started Jun 10 05:36:39 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 207700 kb
Host smart-ee6b4abf-cfef-4193-9f92-05f8f9f49d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772181304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1772181304
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2516240754
Short name T58
Test name
Test status
Simulation time 393273893 ps
CPU time 2.9 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 209808 kb
Host smart-0d05ba1f-8954-4987-ae27-a5a0c6f125f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516240754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2516240754
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3255693096
Short name T811
Test name
Test status
Simulation time 9103729 ps
CPU time 0.84 seconds
Started Jun 10 05:36:41 PM PDT 24
Finished Jun 10 05:36:42 PM PDT 24
Peak memory 205980 kb
Host smart-40d5bd3e-5e75-4e56-a3b4-d7028667d665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255693096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3255693096
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.225828422
Short name T830
Test name
Test status
Simulation time 558552025 ps
CPU time 4.66 seconds
Started Jun 10 05:36:40 PM PDT 24
Finished Jun 10 05:36:45 PM PDT 24
Peak memory 214576 kb
Host smart-dff893a9-8c15-4df0-ae75-d17f12e98641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225828422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.225828422
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1373040585
Short name T556
Test name
Test status
Simulation time 348768900 ps
CPU time 7.35 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:49 PM PDT 24
Peak memory 214212 kb
Host smart-56a4f164-1c93-48a9-8932-e3fcdb368bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373040585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1373040585
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3195825263
Short name T756
Test name
Test status
Simulation time 100351641 ps
CPU time 1.84 seconds
Started Jun 10 05:36:47 PM PDT 24
Finished Jun 10 05:36:49 PM PDT 24
Peak memory 214212 kb
Host smart-28ad2758-4ec7-4861-b577-7952cc36d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195825263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3195825263
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2661903797
Short name T475
Test name
Test status
Simulation time 121713975 ps
CPU time 3.12 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:45 PM PDT 24
Peak memory 219384 kb
Host smart-8fa393f0-d844-47af-97d5-6693dd7016a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661903797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2661903797
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2460472813
Short name T570
Test name
Test status
Simulation time 49570247 ps
CPU time 2.85 seconds
Started Jun 10 05:36:43 PM PDT 24
Finished Jun 10 05:36:46 PM PDT 24
Peak memory 208504 kb
Host smart-e213b874-51a9-4d3b-9cb1-5d3bdcc71df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460472813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2460472813
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2371157427
Short name T190
Test name
Test status
Simulation time 132126057 ps
CPU time 3.73 seconds
Started Jun 10 05:36:39 PM PDT 24
Finished Jun 10 05:36:43 PM PDT 24
Peak memory 207972 kb
Host smart-472b2eb0-20de-495f-889d-112d20ad321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371157427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2371157427
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2051834336
Short name T804
Test name
Test status
Simulation time 128165579 ps
CPU time 2.11 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 208748 kb
Host smart-9dbf9814-bb00-4397-b37e-ae7dbf2db7cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051834336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2051834336
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2214351639
Short name T349
Test name
Test status
Simulation time 20243855613 ps
CPU time 50.69 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:37:33 PM PDT 24
Peak memory 208908 kb
Host smart-896b1754-3d56-47d0-95a7-6213283923bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214351639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2214351639
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2959313968
Short name T294
Test name
Test status
Simulation time 539669527 ps
CPU time 5.17 seconds
Started Jun 10 05:36:51 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 208100 kb
Host smart-3b7610c1-479c-40c1-a679-ed7f635b25f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959313968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2959313968
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1498874861
Short name T527
Test name
Test status
Simulation time 726896436 ps
CPU time 4.93 seconds
Started Jun 10 05:36:49 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 209660 kb
Host smart-a0bacded-a618-4a0b-9b1e-37ed1325710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498874861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1498874861
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1517211095
Short name T531
Test name
Test status
Simulation time 22935335 ps
CPU time 1.86 seconds
Started Jun 10 05:36:36 PM PDT 24
Finished Jun 10 05:36:39 PM PDT 24
Peak memory 208548 kb
Host smart-b5d65607-55d7-4d46-8368-8f3c4a75bc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517211095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1517211095
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2605537508
Short name T203
Test name
Test status
Simulation time 496938059 ps
CPU time 16.85 seconds
Started Jun 10 05:36:41 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 221084 kb
Host smart-c6d13d08-209f-4a56-afc9-a5a4d4a77ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605537508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2605537508
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.935909407
Short name T707
Test name
Test status
Simulation time 168885023 ps
CPU time 3.73 seconds
Started Jun 10 05:36:40 PM PDT 24
Finished Jun 10 05:36:44 PM PDT 24
Peak memory 208968 kb
Host smart-8a708f41-ab7e-4030-a2af-5d32f3274d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935909407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.935909407
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1341878251
Short name T528
Test name
Test status
Simulation time 54063956 ps
CPU time 1.31 seconds
Started Jun 10 05:36:51 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 209708 kb
Host smart-d9608ac3-b866-4ab8-921e-d698f114f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341878251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1341878251
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3361527827
Short name T495
Test name
Test status
Simulation time 33792545 ps
CPU time 0.79 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 205972 kb
Host smart-8b014b2d-e806-4f94-aad9-f3c1d5f318f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361527827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3361527827
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3634161395
Short name T851
Test name
Test status
Simulation time 217345065 ps
CPU time 2.67 seconds
Started Jun 10 05:36:42 PM PDT 24
Finished Jun 10 05:36:45 PM PDT 24
Peak memory 215468 kb
Host smart-fcb61856-b1ec-4516-8347-dc45c24945d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634161395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3634161395
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3929992592
Short name T71
Test name
Test status
Simulation time 117112635 ps
CPU time 2.26 seconds
Started Jun 10 05:36:54 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 209224 kb
Host smart-6f44729a-bb79-47b4-801b-8f179c9de14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929992592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3929992592
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1981630869
Short name T636
Test name
Test status
Simulation time 205769370 ps
CPU time 1.71 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 214360 kb
Host smart-baa3c179-b840-4350-9575-6d963a23526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981630869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1981630869
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.265335552
Short name T613
Test name
Test status
Simulation time 64598527 ps
CPU time 3.13 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 214356 kb
Host smart-1c25eda4-77fd-497a-99cf-7575d7e0f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265335552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.265335552
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1472256082
Short name T795
Test name
Test status
Simulation time 297355996 ps
CPU time 3.29 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:56 PM PDT 24
Peak memory 218468 kb
Host smart-9126ab9d-01e7-4971-ad59-0598f71f23a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472256082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1472256082
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.416082007
Short name T552
Test name
Test status
Simulation time 1487731842 ps
CPU time 11.83 seconds
Started Jun 10 05:36:54 PM PDT 24
Finished Jun 10 05:37:07 PM PDT 24
Peak memory 208468 kb
Host smart-d9eecdab-1a91-436e-a17e-c40ad6472213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416082007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.416082007
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.722654751
Short name T805
Test name
Test status
Simulation time 133014429 ps
CPU time 2.39 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 206852 kb
Host smart-a6a4c792-91af-43d0-819d-85511edc1de5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722654751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.722654751
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3555313809
Short name T731
Test name
Test status
Simulation time 154622176 ps
CPU time 3.1 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 206956 kb
Host smart-366f3106-a7d7-475f-9cab-d945d4039e3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555313809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3555313809
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3271579913
Short name T490
Test name
Test status
Simulation time 111801143 ps
CPU time 3.71 seconds
Started Jun 10 05:36:44 PM PDT 24
Finished Jun 10 05:36:48 PM PDT 24
Peak memory 206804 kb
Host smart-806790ae-64b6-441e-b230-e0caf64b7fcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271579913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3271579913
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.598360221
Short name T451
Test name
Test status
Simulation time 595179556 ps
CPU time 12.73 seconds
Started Jun 10 05:36:48 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 208824 kb
Host smart-3ec29f05-43fd-4786-9ec0-7ccf6365958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598360221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.598360221
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3440811009
Short name T634
Test name
Test status
Simulation time 2466986510 ps
CPU time 23.97 seconds
Started Jun 10 05:36:41 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 208072 kb
Host smart-9d0a10ab-6f98-4155-a38f-131f10ff3c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440811009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3440811009
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.488677939
Short name T211
Test name
Test status
Simulation time 876091866 ps
CPU time 8.54 seconds
Started Jun 10 05:36:46 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 220120 kb
Host smart-786e353d-ebdd-45fd-92f7-1b672086a8b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488677939 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.488677939
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3368168070
Short name T351
Test name
Test status
Simulation time 164800589 ps
CPU time 5.06 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 207528 kb
Host smart-1002fb9e-3421-4da0-a426-3051179cf792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368168070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3368168070
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2238568833
Short name T35
Test name
Test status
Simulation time 34044391 ps
CPU time 1.38 seconds
Started Jun 10 05:36:48 PM PDT 24
Finished Jun 10 05:36:50 PM PDT 24
Peak memory 209796 kb
Host smart-f0fc4bf5-bab5-493b-90ac-11b02919a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238568833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2238568833
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1519809266
Short name T695
Test name
Test status
Simulation time 53925833 ps
CPU time 0.77 seconds
Started Jun 10 05:36:46 PM PDT 24
Finished Jun 10 05:36:47 PM PDT 24
Peak memory 205956 kb
Host smart-67b852f0-25da-44c4-a288-470bf0c28bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519809266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1519809266
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1284794076
Short name T210
Test name
Test status
Simulation time 207049237 ps
CPU time 2.37 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 208512 kb
Host smart-ed216694-689c-4a53-bd23-0f0a5b7bfb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284794076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1284794076
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.30978167
Short name T358
Test name
Test status
Simulation time 344740059 ps
CPU time 5.01 seconds
Started Jun 10 05:36:57 PM PDT 24
Finished Jun 10 05:37:02 PM PDT 24
Peak memory 209824 kb
Host smart-a9d32a26-c45a-4a96-a6df-8a4553fdc272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30978167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.30978167
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.755353817
Short name T611
Test name
Test status
Simulation time 236177208 ps
CPU time 4.08 seconds
Started Jun 10 05:36:48 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 214224 kb
Host smart-d08246cf-8b75-405f-aad2-df5baf2efbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755353817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.755353817
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1469321687
Short name T741
Test name
Test status
Simulation time 402736062 ps
CPU time 2.51 seconds
Started Jun 10 05:36:45 PM PDT 24
Finished Jun 10 05:36:48 PM PDT 24
Peak memory 215660 kb
Host smart-ae709804-f98e-4c3c-a9b2-86a427bd5f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469321687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1469321687
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2687439106
Short name T273
Test name
Test status
Simulation time 105224509 ps
CPU time 2.35 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 207452 kb
Host smart-c64ee707-ada8-41ca-beae-bd36459db476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687439106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2687439106
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1596056856
Short name T483
Test name
Test status
Simulation time 36628296 ps
CPU time 2.25 seconds
Started Jun 10 05:36:46 PM PDT 24
Finished Jun 10 05:36:49 PM PDT 24
Peak memory 206928 kb
Host smart-a238f7e9-d38d-480f-828e-78400fa7f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596056856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1596056856
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4246882049
Short name T817
Test name
Test status
Simulation time 1277057639 ps
CPU time 40.81 seconds
Started Jun 10 05:36:43 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 208600 kb
Host smart-5bc5c631-ac51-45fd-af97-8b85ce4c0dc4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246882049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4246882049
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1451216798
Short name T850
Test name
Test status
Simulation time 1167915762 ps
CPU time 38.81 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:37:36 PM PDT 24
Peak memory 207908 kb
Host smart-d9f8fcae-f54b-4b2e-beb1-f14e0a7d475b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451216798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1451216798
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1133945827
Short name T763
Test name
Test status
Simulation time 84828283 ps
CPU time 3.29 seconds
Started Jun 10 05:36:46 PM PDT 24
Finished Jun 10 05:36:50 PM PDT 24
Peak memory 208596 kb
Host smart-150404fd-20b7-4abb-af4f-bcc9e1781660
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133945827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1133945827
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3328343685
Short name T438
Test name
Test status
Simulation time 62502776 ps
CPU time 2.73 seconds
Started Jun 10 05:36:45 PM PDT 24
Finished Jun 10 05:36:48 PM PDT 24
Peak memory 215860 kb
Host smart-89539dec-b83c-4737-92c0-6679e9922932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328343685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3328343685
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1835677649
Short name T865
Test name
Test status
Simulation time 226793715 ps
CPU time 3.13 seconds
Started Jun 10 05:36:55 PM PDT 24
Finished Jun 10 05:36:59 PM PDT 24
Peak memory 208508 kb
Host smart-2691824b-da8e-4be3-b1d6-83564f6918b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835677649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1835677649
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3245282144
Short name T421
Test name
Test status
Simulation time 458889773 ps
CPU time 3.37 seconds
Started Jun 10 05:36:47 PM PDT 24
Finished Jun 10 05:36:51 PM PDT 24
Peak memory 206832 kb
Host smart-2ed5dc0d-0186-455d-a348-133d1d1d5993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245282144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3245282144
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2185672842
Short name T316
Test name
Test status
Simulation time 6348100799 ps
CPU time 31.3 seconds
Started Jun 10 05:36:46 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 222716 kb
Host smart-fe4f9c18-107e-444d-a156-cfef6cb58207
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185672842 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2185672842
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2037537539
Short name T261
Test name
Test status
Simulation time 615652802 ps
CPU time 5.41 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 208796 kb
Host smart-425448eb-7d80-46aa-9c0c-b68626664afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037537539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2037537539
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1674178106
Short name T95
Test name
Test status
Simulation time 51904543 ps
CPU time 2.18 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:36:59 PM PDT 24
Peak memory 209944 kb
Host smart-b24fe3e9-5392-47c8-a009-35f1576ab866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674178106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1674178106
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.279130585
Short name T450
Test name
Test status
Simulation time 8935551 ps
CPU time 0.82 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:36:51 PM PDT 24
Peak memory 205944 kb
Host smart-5cc5cb82-bb56-4b10-a038-015162d426b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279130585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.279130585
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2001517591
Short name T129
Test name
Test status
Simulation time 171592988 ps
CPU time 4.89 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 214392 kb
Host smart-1e08dd51-ef8b-46e8-9b5c-c8842dfee652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001517591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2001517591
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2278571323
Short name T739
Test name
Test status
Simulation time 159096260 ps
CPU time 2.99 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 214676 kb
Host smart-63efe7e6-f8b1-49be-acbb-304e3e078b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278571323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2278571323
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2494222462
Short name T889
Test name
Test status
Simulation time 239199007 ps
CPU time 5.13 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 208252 kb
Host smart-4f2ab7a8-dbf1-42ce-9c1f-253e70029ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494222462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2494222462
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3534745453
Short name T344
Test name
Test status
Simulation time 282336386 ps
CPU time 3.88 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 214412 kb
Host smart-9b7daf08-a69e-484c-ba94-ada913c58587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534745453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3534745453
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1664708749
Short name T276
Test name
Test status
Simulation time 72826581 ps
CPU time 2.72 seconds
Started Jun 10 05:36:57 PM PDT 24
Finished Jun 10 05:37:00 PM PDT 24
Peak memory 214276 kb
Host smart-6861110d-0bc9-48ff-abbe-d2a0514a59f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664708749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1664708749
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3770423835
Short name T712
Test name
Test status
Simulation time 504571827 ps
CPU time 2.29 seconds
Started Jun 10 05:36:48 PM PDT 24
Finished Jun 10 05:36:50 PM PDT 24
Peak memory 206156 kb
Host smart-38bb8388-f1a6-4525-9f02-dee012ea9cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770423835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3770423835
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2313666648
Short name T258
Test name
Test status
Simulation time 274655913 ps
CPU time 3.96 seconds
Started Jun 10 05:36:49 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 207344 kb
Host smart-b865691a-9528-4de8-be76-5a7162edc81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313666648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2313666648
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.92769329
Short name T796
Test name
Test status
Simulation time 34749279 ps
CPU time 2.4 seconds
Started Jun 10 05:36:54 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 206844 kb
Host smart-261d7ebe-1d72-4424-aaf0-a26c420c5852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92769329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.92769329
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2877835491
Short name T470
Test name
Test status
Simulation time 96426842 ps
CPU time 2.8 seconds
Started Jun 10 05:36:53 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 208768 kb
Host smart-1c1c7660-51b7-4b7e-9f7d-8913aac8c5fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877835491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2877835491
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1800415576
Short name T478
Test name
Test status
Simulation time 120506383 ps
CPU time 3.41 seconds
Started Jun 10 05:37:02 PM PDT 24
Finished Jun 10 05:37:06 PM PDT 24
Peak memory 208628 kb
Host smart-4c81931f-ca4b-4257-844b-c2494522dfc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800415576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1800415576
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1670368032
Short name T485
Test name
Test status
Simulation time 227126851 ps
CPU time 3.2 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 208332 kb
Host smart-f6219f63-3e07-4ebf-a2e7-b69cfd0069fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670368032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1670368032
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1668209454
Short name T116
Test name
Test status
Simulation time 490430329 ps
CPU time 6.49 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 208928 kb
Host smart-4ba1b0d9-6e60-4946-9811-819501b49c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668209454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1668209454
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.651701170
Short name T649
Test name
Test status
Simulation time 255407443 ps
CPU time 5.23 seconds
Started Jun 10 05:36:48 PM PDT 24
Finished Jun 10 05:36:53 PM PDT 24
Peak memory 208332 kb
Host smart-b90fc97a-5b42-4678-8012-cc208fd58f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651701170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.651701170
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.844095231
Short name T72
Test name
Test status
Simulation time 3414367130 ps
CPU time 60.94 seconds
Started Jun 10 05:36:50 PM PDT 24
Finished Jun 10 05:37:51 PM PDT 24
Peak memory 222596 kb
Host smart-653376a8-c69f-469e-8cc8-481d4a8e5f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844095231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.844095231
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.668677299
Short name T779
Test name
Test status
Simulation time 379629325 ps
CPU time 12.68 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 219636 kb
Host smart-4f75c1f4-7f98-4bc3-b3d1-55e66ee3143f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668677299 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.668677299
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.469334263
Short name T815
Test name
Test status
Simulation time 191848810 ps
CPU time 4.87 seconds
Started Jun 10 05:36:51 PM PDT 24
Finished Jun 10 05:36:56 PM PDT 24
Peak memory 209312 kb
Host smart-f6371800-f8ab-41ee-bdfa-6340eb8054cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469334263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.469334263
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.345703504
Short name T181
Test name
Test status
Simulation time 72797748 ps
CPU time 1.49 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:54 PM PDT 24
Peak memory 208612 kb
Host smart-811d8a1b-9eb9-46d7-9be1-984c8996af59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345703504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.345703504
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3289485473
Short name T631
Test name
Test status
Simulation time 53133305 ps
CPU time 0.7 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:36:59 PM PDT 24
Peak memory 205880 kb
Host smart-39a1ce58-e52d-4251-a179-1d3f4067a4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289485473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3289485473
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1291655359
Short name T220
Test name
Test status
Simulation time 976170846 ps
CPU time 13.59 seconds
Started Jun 10 05:36:49 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 214588 kb
Host smart-e100a018-9298-486e-b0b7-bcbccd716795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291655359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1291655359
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2125561450
Short name T668
Test name
Test status
Simulation time 231403499 ps
CPU time 4.49 seconds
Started Jun 10 05:37:01 PM PDT 24
Finished Jun 10 05:37:06 PM PDT 24
Peak memory 209960 kb
Host smart-d6544a58-ec72-4562-8ca8-52ee129bc605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125561450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2125561450
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3478029116
Short name T765
Test name
Test status
Simulation time 166098952 ps
CPU time 2.84 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 208068 kb
Host smart-99ce9e4a-0f15-44a2-901b-8e99c88a6e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478029116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3478029116
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1421179053
Short name T82
Test name
Test status
Simulation time 151790759 ps
CPU time 4.34 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 214368 kb
Host smart-dc718a7e-dbc4-44fb-97c6-0a7c1d0c89b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421179053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1421179053
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3203285054
Short name T689
Test name
Test status
Simulation time 256482927 ps
CPU time 2.33 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 214280 kb
Host smart-5fb4b754-2f4b-4ca1-8858-d3461b9cccf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203285054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3203285054
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4262555457
Short name T846
Test name
Test status
Simulation time 184569344 ps
CPU time 4.74 seconds
Started Jun 10 05:36:52 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 222444 kb
Host smart-c1e06382-52bf-4e87-8182-31f1c44fbd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262555457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4262555457
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.783911761
Short name T191
Test name
Test status
Simulation time 190982749 ps
CPU time 5.58 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 208020 kb
Host smart-9dde0d79-7856-4237-be20-15ab70418eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783911761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.783911761
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2908020060
Short name T877
Test name
Test status
Simulation time 46522469 ps
CPU time 2.55 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:02 PM PDT 24
Peak memory 208000 kb
Host smart-ad1c8bd3-75f4-4945-824e-14c442942836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908020060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2908020060
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4100000642
Short name T439
Test name
Test status
Simulation time 2971453604 ps
CPU time 5.63 seconds
Started Jun 10 05:36:51 PM PDT 24
Finished Jun 10 05:36:57 PM PDT 24
Peak memory 208292 kb
Host smart-a664994b-8378-466f-85a3-73bad7bb1742
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100000642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4100000642
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.225105323
Short name T633
Test name
Test status
Simulation time 32588235 ps
CPU time 2.44 seconds
Started Jun 10 05:36:55 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 206824 kb
Host smart-3f2fd042-d03d-419d-a415-d1297c5fda0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225105323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.225105323
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4171498586
Short name T816
Test name
Test status
Simulation time 631130840 ps
CPU time 3.91 seconds
Started Jun 10 05:36:51 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 207956 kb
Host smart-c1802fbf-54f6-4e11-91c2-66e14f4f301b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171498586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4171498586
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2564858830
Short name T706
Test name
Test status
Simulation time 47806168 ps
CPU time 1.82 seconds
Started Jun 10 05:36:53 PM PDT 24
Finished Jun 10 05:36:55 PM PDT 24
Peak memory 214336 kb
Host smart-eb9160b9-ec15-49d8-b544-0b54b5a162b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564858830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2564858830
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2146581253
Short name T32
Test name
Test status
Simulation time 67035330 ps
CPU time 1.7 seconds
Started Jun 10 05:36:53 PM PDT 24
Finished Jun 10 05:36:56 PM PDT 24
Peak memory 206928 kb
Host smart-778c1880-c43c-4823-8235-cc50a2b153a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146581253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2146581253
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.368839329
Short name T347
Test name
Test status
Simulation time 1407519052 ps
CPU time 12.34 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 214276 kb
Host smart-aa2ec66b-6733-4c82-bbcc-b2a7d5091f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368839329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.368839329
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.236701671
Short name T827
Test name
Test status
Simulation time 2515546952 ps
CPU time 9.31 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 220136 kb
Host smart-62a3254f-72b2-42e9-9c9a-6bfa92d3a9b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236701671 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.236701671
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.951482333
Short name T221
Test name
Test status
Simulation time 474585279 ps
CPU time 3.93 seconds
Started Jun 10 05:36:54 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 209364 kb
Host smart-4323153a-d33b-4f52-ad6e-1134937e8099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951482333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.951482333
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1280994465
Short name T785
Test name
Test status
Simulation time 47849821 ps
CPU time 1.94 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 210296 kb
Host smart-c6d444cc-cdc4-4a90-a09d-e3c571dc6ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280994465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1280994465
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2734338567
Short name T681
Test name
Test status
Simulation time 88183985 ps
CPU time 0.93 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:00 PM PDT 24
Peak memory 206076 kb
Host smart-a6960670-bf6e-46a8-a447-33baba1bbf42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734338567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2734338567
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3722230508
Short name T328
Test name
Test status
Simulation time 137553178 ps
CPU time 3.37 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 215288 kb
Host smart-3296ee1a-5fae-4c9e-8181-3800a3376f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722230508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3722230508
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2195801202
Short name T447
Test name
Test status
Simulation time 136163230 ps
CPU time 3.52 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 209508 kb
Host smart-0b2cfb56-0e39-4479-8469-c25843222034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195801202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2195801202
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2991706483
Short name T89
Test name
Test status
Simulation time 820633991 ps
CPU time 6.54 seconds
Started Jun 10 05:37:00 PM PDT 24
Finished Jun 10 05:37:07 PM PDT 24
Peak memory 222572 kb
Host smart-abb268ab-ed6d-4d63-a249-f40f46c985e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991706483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2991706483
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3395404112
Short name T226
Test name
Test status
Simulation time 74339664 ps
CPU time 2.87 seconds
Started Jun 10 05:37:05 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 214252 kb
Host smart-6bc4c1e2-b0c7-4e9a-838e-b31a9a1ead0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395404112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3395404112
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.698696476
Short name T677
Test name
Test status
Simulation time 247555889 ps
CPU time 2.55 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:02 PM PDT 24
Peak memory 222412 kb
Host smart-6ca0691d-9913-480d-932f-63b6e1cb7e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698696476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.698696476
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2931875372
Short name T270
Test name
Test status
Simulation time 90220181 ps
CPU time 4.37 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 207492 kb
Host smart-cb019df0-34d2-44ae-863b-02f73a965df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931875372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2931875372
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3926826567
Short name T914
Test name
Test status
Simulation time 114821635 ps
CPU time 3.04 seconds
Started Jun 10 05:37:00 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 206988 kb
Host smart-f8a40ff6-876d-45b9-9588-f1d25ce831a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926826567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3926826567
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1257581298
Short name T787
Test name
Test status
Simulation time 188681289 ps
CPU time 3.06 seconds
Started Jun 10 05:37:03 PM PDT 24
Finished Jun 10 05:37:07 PM PDT 24
Peak memory 207044 kb
Host smart-b2dd79ed-5aed-41a6-a250-3efd641c7ad1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257581298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1257581298
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3503308928
Short name T401
Test name
Test status
Simulation time 133520894 ps
CPU time 3.43 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 208560 kb
Host smart-04a95041-afea-4a84-aa4f-a65f9f3bac77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503308928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3503308928
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2431584588
Short name T446
Test name
Test status
Simulation time 124282757 ps
CPU time 2.45 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 206920 kb
Host smart-0b5f9458-2993-465c-b5e2-f87122751192
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431584588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2431584588
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2166288666
Short name T847
Test name
Test status
Simulation time 30686185 ps
CPU time 1.64 seconds
Started Jun 10 05:37:03 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 208264 kb
Host smart-918c971a-a0fd-4aa3-b313-d9673b1a80c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166288666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2166288666
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3253291743
Short name T810
Test name
Test status
Simulation time 108793906 ps
CPU time 3.13 seconds
Started Jun 10 05:37:02 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 208152 kb
Host smart-8b53c067-15d0-471c-80cd-57baec56cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253291743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3253291743
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2838059480
Short name T357
Test name
Test status
Simulation time 2113982624 ps
CPU time 52.48 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:51 PM PDT 24
Peak memory 208896 kb
Host smart-09d04c4a-8722-48f1-a656-d53bc10afc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838059480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2838059480
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3957164556
Short name T742
Test name
Test status
Simulation time 26426913 ps
CPU time 1.66 seconds
Started Jun 10 05:37:06 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 208740 kb
Host smart-da1c260d-4fbf-4115-b76a-95a0ae28b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957164556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3957164556
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3878153555
Short name T489
Test name
Test status
Simulation time 40410734 ps
CPU time 0.76 seconds
Started Jun 10 05:36:55 PM PDT 24
Finished Jun 10 05:36:56 PM PDT 24
Peak memory 205968 kb
Host smart-2abbf036-57f1-4080-8f72-1eae6906d53a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878153555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3878153555
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1161631075
Short name T417
Test name
Test status
Simulation time 2865410729 ps
CPU time 12.14 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 215404 kb
Host smart-20dd85c0-173c-4133-9c0e-cd2b5e44191d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161631075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1161631075
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1149554633
Short name T19
Test name
Test status
Simulation time 135248030 ps
CPU time 3.91 seconds
Started Jun 10 05:37:00 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 221296 kb
Host smart-6a5c53e4-2c94-4b23-9ef3-58ce8963557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149554633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1149554633
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3253307672
Short name T738
Test name
Test status
Simulation time 142097898 ps
CPU time 5.07 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 210720 kb
Host smart-860701b9-e33a-4eb6-8b56-a62255aad967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253307672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3253307672
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2651619956
Short name T262
Test name
Test status
Simulation time 220562219 ps
CPU time 4.72 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 222320 kb
Host smart-93c9ac22-0612-45bb-8650-ab326fc676fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651619956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2651619956
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3794939779
Short name T62
Test name
Test status
Simulation time 379481750 ps
CPU time 4.65 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 220376 kb
Host smart-9a2b7bc1-dabd-49c9-9231-6bd3d6bcfe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794939779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3794939779
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3234155498
Short name T871
Test name
Test status
Simulation time 3206864701 ps
CPU time 29.23 seconds
Started Jun 10 05:37:03 PM PDT 24
Finished Jun 10 05:37:33 PM PDT 24
Peak memory 222004 kb
Host smart-74c02195-0ac6-43a4-a7bd-828e76dc6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234155498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3234155498
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1787108571
Short name T916
Test name
Test status
Simulation time 569965303 ps
CPU time 14.76 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:14 PM PDT 24
Peak memory 207968 kb
Host smart-05669ae0-b4f3-48a0-931d-89dec198489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787108571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1787108571
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.382299205
Short name T876
Test name
Test status
Simulation time 54120636 ps
CPU time 2.88 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 208920 kb
Host smart-3c6f6c9e-4686-4d63-8429-623c2e5b5afd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382299205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.382299205
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2738754640
Short name T518
Test name
Test status
Simulation time 68357584 ps
CPU time 2.48 seconds
Started Jun 10 05:36:55 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 206880 kb
Host smart-d497c909-5e53-49f5-9e78-c3b4bc137d14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738754640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2738754640
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1001724361
Short name T824
Test name
Test status
Simulation time 786844725 ps
CPU time 3.06 seconds
Started Jun 10 05:36:55 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 206956 kb
Host smart-ff2e2f33-014b-4abc-b074-899db332b21e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001724361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1001724361
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.295571861
Short name T692
Test name
Test status
Simulation time 76113077 ps
CPU time 1.54 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 209348 kb
Host smart-0a933282-0ffc-492f-bfac-2ef937101946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295571861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.295571861
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3352560733
Short name T403
Test name
Test status
Simulation time 35582632 ps
CPU time 1.98 seconds
Started Jun 10 05:36:56 PM PDT 24
Finished Jun 10 05:36:58 PM PDT 24
Peak memory 206904 kb
Host smart-ebd52387-f204-4b05-af76-9f645fbec8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352560733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3352560733
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.770331909
Short name T200
Test name
Test status
Simulation time 1560868956 ps
CPU time 22.93 seconds
Started Jun 10 05:37:02 PM PDT 24
Finished Jun 10 05:37:25 PM PDT 24
Peak memory 222352 kb
Host smart-aa16932d-e496-4d6a-94e2-1d03301780bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770331909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.770331909
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.244587553
Short name T686
Test name
Test status
Simulation time 1063374676 ps
CPU time 17.41 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 222560 kb
Host smart-feee1878-18c1-45fa-85ad-4b1d6bbc13a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244587553 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.244587553
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2657672094
Short name T188
Test name
Test status
Simulation time 267553300 ps
CPU time 6.81 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:06 PM PDT 24
Peak memory 208460 kb
Host smart-89f21a44-cfca-4126-8a3c-ba678ab53abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657672094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2657672094
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2013519633
Short name T840
Test name
Test status
Simulation time 220632996 ps
CPU time 3.25 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 210100 kb
Host smart-e26cffc0-b1ba-4f33-b893-8293180e0a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013519633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2013519633
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.39388009
Short name T12
Test name
Test status
Simulation time 24376971 ps
CPU time 0.78 seconds
Started Jun 10 05:35:01 PM PDT 24
Finished Jun 10 05:35:02 PM PDT 24
Peak memory 205892 kb
Host smart-ba83dbc6-ad4f-4c96-b80c-85b53dc86465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39388009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.39388009
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1904128246
Short name T285
Test name
Test status
Simulation time 71492837 ps
CPU time 4.25 seconds
Started Jun 10 05:35:17 PM PDT 24
Finished Jun 10 05:35:22 PM PDT 24
Peak memory 214268 kb
Host smart-25c27397-ed93-40e3-ab0b-c8c3963d5c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904128246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1904128246
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2618284393
Short name T713
Test name
Test status
Simulation time 99347460 ps
CPU time 2.27 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 208792 kb
Host smart-6f047743-41b1-490f-89ea-c63b70972bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618284393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2618284393
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4118740042
Short name T288
Test name
Test status
Simulation time 72356001 ps
CPU time 3.5 seconds
Started Jun 10 05:35:01 PM PDT 24
Finished Jun 10 05:35:05 PM PDT 24
Peak memory 218252 kb
Host smart-45d2525e-a20f-4dee-902c-fe46564034ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118740042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4118740042
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.369065782
Short name T855
Test name
Test status
Simulation time 154085524 ps
CPU time 3.72 seconds
Started Jun 10 05:34:59 PM PDT 24
Finished Jun 10 05:35:03 PM PDT 24
Peak memory 214328 kb
Host smart-00f0e88b-d441-4462-b4d0-0515ad612ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369065782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.369065782
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.166430727
Short name T897
Test name
Test status
Simulation time 258524409 ps
CPU time 3.41 seconds
Started Jun 10 05:35:02 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 214244 kb
Host smart-970bad7b-c58e-4b11-9e54-614bdf6c6983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166430727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.166430727
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3641561118
Short name T457
Test name
Test status
Simulation time 206659361 ps
CPU time 2.7 seconds
Started Jun 10 05:35:03 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 208108 kb
Host smart-4fa637b4-39ca-4dd6-90cd-25f9aa6c9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641561118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3641561118
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2572143457
Short name T564
Test name
Test status
Simulation time 3583922025 ps
CPU time 61.63 seconds
Started Jun 10 05:35:00 PM PDT 24
Finished Jun 10 05:36:02 PM PDT 24
Peak memory 214420 kb
Host smart-ef25a081-cec5-41ab-bf8d-46aeb0a4c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572143457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2572143457
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2420755829
Short name T10
Test name
Test status
Simulation time 1408325600 ps
CPU time 11.48 seconds
Started Jun 10 05:35:04 PM PDT 24
Finished Jun 10 05:35:16 PM PDT 24
Peak memory 230528 kb
Host smart-46c8b5b9-74ae-4ae8-bc7f-1fa1dcb044fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420755829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2420755829
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1856400246
Short name T424
Test name
Test status
Simulation time 194319876 ps
CPU time 5.11 seconds
Started Jun 10 05:35:01 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 207840 kb
Host smart-3d0406a4-bd0d-4d06-8f61-86d2e28566e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856400246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1856400246
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.112870566
Short name T240
Test name
Test status
Simulation time 440570230 ps
CPU time 3.76 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:10 PM PDT 24
Peak memory 206912 kb
Host smart-287806c6-0b46-42f3-9a5a-214c6e014b9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112870566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.112870566
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1384355799
Short name T197
Test name
Test status
Simulation time 172382403 ps
CPU time 3.13 seconds
Started Jun 10 05:35:02 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 206804 kb
Host smart-c9f5a07f-3874-496a-ab6e-4628c24b130c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384355799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1384355799
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2881698457
Short name T269
Test name
Test status
Simulation time 279189818 ps
CPU time 2.66 seconds
Started Jun 10 05:35:03 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 209228 kb
Host smart-e2e51b83-ef25-4da2-b4e5-60e6dd4a7959
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881698457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2881698457
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3019838515
Short name T587
Test name
Test status
Simulation time 184747846 ps
CPU time 2.95 seconds
Started Jun 10 05:35:03 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 207840 kb
Host smart-a03328db-47ae-40d4-ad14-177988aba012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019838515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3019838515
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.543355735
Short name T435
Test name
Test status
Simulation time 278288742 ps
CPU time 3.45 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:35:09 PM PDT 24
Peak memory 208484 kb
Host smart-245c55b6-c3ce-4145-b430-432e4db37dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543355735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.543355735
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.149090989
Short name T59
Test name
Test status
Simulation time 15222990442 ps
CPU time 30 seconds
Started Jun 10 05:35:01 PM PDT 24
Finished Jun 10 05:35:32 PM PDT 24
Peak memory 216900 kb
Host smart-9879493e-7b26-40a4-94af-bd79a7260626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149090989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.149090989
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1686688400
Short name T750
Test name
Test status
Simulation time 201884082 ps
CPU time 12.44 seconds
Started Jun 10 05:35:01 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 222704 kb
Host smart-b808aeab-ccf1-42b3-ba50-37a22f357cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686688400 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1686688400
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3232556599
Short name T874
Test name
Test status
Simulation time 1150273402 ps
CPU time 13.94 seconds
Started Jun 10 05:35:02 PM PDT 24
Finished Jun 10 05:35:17 PM PDT 24
Peak memory 218108 kb
Host smart-f1b895cb-9e38-4244-a678-aebd92bd705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232556599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3232556599
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.704291063
Short name T40
Test name
Test status
Simulation time 152311892 ps
CPU time 1.97 seconds
Started Jun 10 05:35:11 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 209736 kb
Host smart-9a571edc-5fd5-43a7-a8f8-1163e1611103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704291063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.704291063
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4068569522
Short name T448
Test name
Test status
Simulation time 75594376 ps
CPU time 0.98 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 206200 kb
Host smart-0e6a48da-b176-4763-b5e1-1a3ef205c43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068569522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4068569522
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1970395577
Short name T312
Test name
Test status
Simulation time 198538758 ps
CPU time 3.94 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 222476 kb
Host smart-1015dab1-b800-4fab-b54e-5f0d772c4220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970395577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1970395577
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2064526414
Short name T825
Test name
Test status
Simulation time 289015055 ps
CPU time 4.39 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 222812 kb
Host smart-8daa6779-b062-470f-a344-51772a07a0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064526414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2064526414
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.676205960
Short name T274
Test name
Test status
Simulation time 181341606 ps
CPU time 5.51 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 213972 kb
Host smart-c704e50f-cf18-4b9b-803d-d5c7192867c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676205960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.676205960
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2651064777
Short name T85
Test name
Test status
Simulation time 1537488770 ps
CPU time 5.74 seconds
Started Jun 10 05:37:03 PM PDT 24
Finished Jun 10 05:37:09 PM PDT 24
Peak memory 214248 kb
Host smart-ea9e34e7-92ad-4b38-a681-9a84f69bf638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651064777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2651064777
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3801075323
Short name T343
Test name
Test status
Simulation time 210583723 ps
CPU time 1.78 seconds
Started Jun 10 05:37:02 PM PDT 24
Finished Jun 10 05:37:04 PM PDT 24
Peak memory 214280 kb
Host smart-1138c25f-f1d7-4801-ae85-85ba464d16cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801075323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3801075323
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3163510762
Short name T605
Test name
Test status
Simulation time 39745830 ps
CPU time 2.67 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 209752 kb
Host smart-5758dbae-12c7-43b6-ba2c-fa20acf0a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163510762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3163510762
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3722157993
Short name T408
Test name
Test status
Simulation time 61745011 ps
CPU time 3.36 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:01 PM PDT 24
Peak memory 209268 kb
Host smart-7555ba4a-d2e6-4232-86a2-9c4f6f6431b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722157993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3722157993
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3147121736
Short name T800
Test name
Test status
Simulation time 186608933 ps
CPU time 2.35 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 206928 kb
Host smart-1f587d68-b7a2-49a1-9cf9-b765039ba97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147121736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3147121736
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2032334735
Short name T672
Test name
Test status
Simulation time 34883737 ps
CPU time 2.7 seconds
Started Jun 10 05:37:03 PM PDT 24
Finished Jun 10 05:37:06 PM PDT 24
Peak memory 208980 kb
Host smart-ac4bb8a0-fcee-4fb1-b94b-0e01ccfca9ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032334735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2032334735
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.389426368
Short name T125
Test name
Test status
Simulation time 252426642 ps
CPU time 5.2 seconds
Started Jun 10 05:37:05 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 208080 kb
Host smart-7b41356b-eed7-43fe-9d7c-8bed54e02802
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389426368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.389426368
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.829804051
Short name T313
Test name
Test status
Simulation time 117297870 ps
CPU time 3.1 seconds
Started Jun 10 05:36:59 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 207748 kb
Host smart-36a845a1-1e18-4c6f-be92-d9e667c306f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829804051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.829804051
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2563475498
Short name T94
Test name
Test status
Simulation time 37983894 ps
CPU time 1.81 seconds
Started Jun 10 05:37:01 PM PDT 24
Finished Jun 10 05:37:03 PM PDT 24
Peak memory 214284 kb
Host smart-a9570bdf-df93-4e30-a410-9b172a045fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563475498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2563475498
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3336144312
Short name T511
Test name
Test status
Simulation time 559575039 ps
CPU time 2.4 seconds
Started Jun 10 05:37:02 PM PDT 24
Finished Jun 10 05:37:05 PM PDT 24
Peak memory 206880 kb
Host smart-74f2bf65-c9b5-46a4-952b-fa3e5883f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336144312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3336144312
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.19325430
Short name T853
Test name
Test status
Simulation time 383712513 ps
CPU time 2.6 seconds
Started Jun 10 05:36:57 PM PDT 24
Finished Jun 10 05:37:00 PM PDT 24
Peak memory 208224 kb
Host smart-a456a343-fba3-4c68-aa7d-c6cedd39d4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19325430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.19325430
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1579696263
Short name T708
Test name
Test status
Simulation time 100494877 ps
CPU time 6.52 seconds
Started Jun 10 05:37:05 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 219904 kb
Host smart-9c4f282f-fb98-45ee-b5bb-4848881caf4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579696263 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1579696263
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.951240990
Short name T806
Test name
Test status
Simulation time 155995709 ps
CPU time 3.1 seconds
Started Jun 10 05:36:58 PM PDT 24
Finished Jun 10 05:37:02 PM PDT 24
Peak memory 207696 kb
Host smart-6d2b60c5-5b94-4cdc-a03c-054716168464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951240990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.951240990
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3643277202
Short name T697
Test name
Test status
Simulation time 271140942 ps
CPU time 5.85 seconds
Started Jun 10 05:37:01 PM PDT 24
Finished Jun 10 05:37:07 PM PDT 24
Peak memory 210632 kb
Host smart-7cfda007-7d94-4621-802e-3dbd3fae2fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643277202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3643277202
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4041780378
Short name T690
Test name
Test status
Simulation time 47692289 ps
CPU time 0.76 seconds
Started Jun 10 05:37:06 PM PDT 24
Finished Jun 10 05:37:07 PM PDT 24
Peak memory 205984 kb
Host smart-18995b37-5fb2-4b66-ae9a-81011d232b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041780378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4041780378
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2252972724
Short name T239
Test name
Test status
Simulation time 64347326 ps
CPU time 2.89 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 214376 kb
Host smart-47f30b04-e721-4405-9125-7d1a805ec8f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252972724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2252972724
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.908329865
Short name T20
Test name
Test status
Simulation time 743402015 ps
CPU time 3.52 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 210344 kb
Host smart-a386eddc-769a-4552-a354-3aa15c1b02ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908329865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.908329865
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3997156264
Short name T575
Test name
Test status
Simulation time 237350574 ps
CPU time 2.72 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 214304 kb
Host smart-5f756230-f359-4db9-8f0c-7dab5a2112a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997156264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3997156264
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.989848119
Short name T835
Test name
Test status
Simulation time 30910263 ps
CPU time 2.3 seconds
Started Jun 10 05:37:11 PM PDT 24
Finished Jun 10 05:37:14 PM PDT 24
Peak memory 214336 kb
Host smart-e74fdb09-07b9-4174-ac3e-72a707945f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989848119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.989848119
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2277359300
Short name T361
Test name
Test status
Simulation time 219496087 ps
CPU time 6.12 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 214308 kb
Host smart-c4a15abf-6d1e-4142-b870-cfe7e61f7e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277359300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2277359300
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.210036258
Short name T53
Test name
Test status
Simulation time 97465390 ps
CPU time 5.16 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 208924 kb
Host smart-5265eda8-8595-4b10-a57f-891e9aa3ea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210036258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.210036258
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3432048629
Short name T600
Test name
Test status
Simulation time 102623575 ps
CPU time 5.09 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:09 PM PDT 24
Peak memory 210392 kb
Host smart-98f2c917-c98a-4873-94f4-4a670127fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432048629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3432048629
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1200424160
Short name T244
Test name
Test status
Simulation time 974612449 ps
CPU time 7.36 seconds
Started Jun 10 05:37:02 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 208756 kb
Host smart-68d6cd43-f4da-40e4-84b1-8616a0cd83aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200424160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1200424160
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.748278501
Short name T545
Test name
Test status
Simulation time 94746637 ps
CPU time 3.21 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 208540 kb
Host smart-7578f088-5169-4ac3-b8a8-16dce3ff9468
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748278501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.748278501
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.860225530
Short name T574
Test name
Test status
Simulation time 72888481 ps
CPU time 3.56 seconds
Started Jun 10 05:37:05 PM PDT 24
Finished Jun 10 05:37:09 PM PDT 24
Peak memory 208780 kb
Host smart-a712048d-747d-4e2c-924d-be588e302814
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860225530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.860225530
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.930504264
Short name T437
Test name
Test status
Simulation time 80699207 ps
CPU time 2.49 seconds
Started Jun 10 05:37:03 PM PDT 24
Finished Jun 10 05:37:06 PM PDT 24
Peak memory 206804 kb
Host smart-b50cb59e-31f9-470c-98ac-81447f63ffb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930504264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.930504264
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2350506830
Short name T891
Test name
Test status
Simulation time 56680689 ps
CPU time 1.83 seconds
Started Jun 10 05:37:04 PM PDT 24
Finished Jun 10 05:37:07 PM PDT 24
Peak memory 209936 kb
Host smart-e6497c9f-607b-43ea-befa-cd19d2a5fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350506830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2350506830
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3603672384
Short name T687
Test name
Test status
Simulation time 37341248 ps
CPU time 2.32 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 206896 kb
Host smart-e1038884-17ae-4386-9f9d-fc4656872ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603672384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3603672384
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3186676971
Short name T907
Test name
Test status
Simulation time 1066353275 ps
CPU time 23.01 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:30 PM PDT 24
Peak memory 222504 kb
Host smart-2e838cfc-e054-4819-9a27-15859a8d344f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186676971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3186676971
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2946989471
Short name T693
Test name
Test status
Simulation time 708495029 ps
CPU time 9.13 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:19 PM PDT 24
Peak memory 222660 kb
Host smart-8b66b859-6073-4e6d-b026-5e7bbeb8d385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946989471 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2946989471
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3402634432
Short name T78
Test name
Test status
Simulation time 102431606 ps
CPU time 3.63 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 208060 kb
Host smart-47d97af1-5672-4576-bb2a-846d461f7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402634432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3402634432
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2302732482
Short name T691
Test name
Test status
Simulation time 65178598 ps
CPU time 1.93 seconds
Started Jun 10 05:37:06 PM PDT 24
Finished Jun 10 05:37:08 PM PDT 24
Peak memory 214420 kb
Host smart-0a806fa5-e611-4700-a859-4b57d8750ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302732482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2302732482
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3123122989
Short name T507
Test name
Test status
Simulation time 33445079 ps
CPU time 0.73 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 205960 kb
Host smart-1b41d247-9fe8-4340-a1f1-49f06ea4b361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123122989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3123122989
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1241397030
Short name T175
Test name
Test status
Simulation time 2567396660 ps
CPU time 128.04 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:39:17 PM PDT 24
Peak memory 216008 kb
Host smart-01f40ce9-09d9-44cf-8f10-4d459fe415fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241397030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1241397030
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1038264343
Short name T30
Test name
Test status
Simulation time 62308756 ps
CPU time 1.99 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 216740 kb
Host smart-1ea3be52-1316-4bc5-89f8-661f2408b116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038264343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1038264343
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3810423713
Short name T174
Test name
Test status
Simulation time 61075836 ps
CPU time 2.34 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 219792 kb
Host smart-ecabaa06-92ee-4f84-bc9f-2e57fca26428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810423713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3810423713
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.962737760
Short name T319
Test name
Test status
Simulation time 173451848 ps
CPU time 3.25 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 222452 kb
Host smart-d319ee8f-7e1f-4369-9a17-dbfb214b5ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962737760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.962737760
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3852572114
Short name T205
Test name
Test status
Simulation time 107165123 ps
CPU time 2.9 seconds
Started Jun 10 05:37:14 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 216136 kb
Host smart-665c7552-3a30-4450-bb97-fb652acf2f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852572114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3852572114
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3788210825
Short name T645
Test name
Test status
Simulation time 150303419 ps
CPU time 6.01 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 218248 kb
Host smart-47eb3a6a-440a-4952-bd2e-975a174a4918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788210825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3788210825
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1161758967
Short name T682
Test name
Test status
Simulation time 59452062 ps
CPU time 2.72 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 208712 kb
Host smart-a73a2c78-66d7-4b34-b152-6dbf96d4a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161758967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1161758967
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4048789062
Short name T887
Test name
Test status
Simulation time 114674446 ps
CPU time 2.34 seconds
Started Jun 10 05:37:07 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 206964 kb
Host smart-2282dfe2-d4fe-40df-9ad9-c685fccb990e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048789062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4048789062
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2997355694
Short name T355
Test name
Test status
Simulation time 125479491 ps
CPU time 2.8 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 206848 kb
Host smart-a1458778-0acd-4954-9c55-c88aef8f7ea8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997355694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2997355694
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1848751666
Short name T651
Test name
Test status
Simulation time 373064871 ps
CPU time 3.5 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 206952 kb
Host smart-1c90ae47-18a0-40a3-8ebc-75e7452a3f65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848751666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1848751666
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3076298260
Short name T844
Test name
Test status
Simulation time 44641318 ps
CPU time 2.28 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 210112 kb
Host smart-1f556568-1daa-4f61-9e1a-fc5c4df67bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076298260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3076298260
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1899690454
Short name T696
Test name
Test status
Simulation time 184343330 ps
CPU time 2.51 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 206820 kb
Host smart-0b21e438-93c3-4d04-8e67-1101e60bcf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899690454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1899690454
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1781854813
Short name T180
Test name
Test status
Simulation time 779652284 ps
CPU time 10.9 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 217432 kb
Host smart-f96f1675-a7b7-48d2-a485-bb113fc09008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781854813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1781854813
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.728389005
Short name T105
Test name
Test status
Simulation time 2926464543 ps
CPU time 12.19 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 222676 kb
Host smart-95c783e3-4fd8-4561-a0e4-856796817f51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728389005 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.728389005
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3574770328
Short name T192
Test name
Test status
Simulation time 102796631 ps
CPU time 3.8 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 209244 kb
Host smart-ff325533-5756-4a88-b406-e74967b74c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574770328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3574770328
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3221755775
Short name T41
Test name
Test status
Simulation time 58857350 ps
CPU time 1.93 seconds
Started Jun 10 05:37:11 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 209988 kb
Host smart-01e2eddc-c796-4805-acc6-d00c78c2877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221755775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3221755775
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2495940494
Short name T597
Test name
Test status
Simulation time 35009176 ps
CPU time 0.76 seconds
Started Jun 10 05:37:11 PM PDT 24
Finished Jun 10 05:37:13 PM PDT 24
Peak memory 205940 kb
Host smart-8b8898dc-99ca-4578-9fa8-00acac1b10dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495940494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2495940494
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1616161503
Short name T385
Test name
Test status
Simulation time 233893174 ps
CPU time 3.86 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 214756 kb
Host smart-6c21fb65-75ec-42b1-b358-9b1b92e04d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616161503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1616161503
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1091886088
Short name T833
Test name
Test status
Simulation time 160270788 ps
CPU time 3.21 seconds
Started Jun 10 05:37:11 PM PDT 24
Finished Jun 10 05:37:14 PM PDT 24
Peak memory 214636 kb
Host smart-2380ae4e-54bb-45ec-9754-2316e7c5527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091886088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1091886088
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1269307016
Short name T66
Test name
Test status
Simulation time 53137569 ps
CPU time 2.15 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 206876 kb
Host smart-22ca27a9-a90d-48da-bba5-b0e9d8930b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269307016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1269307016
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3308129667
Short name T772
Test name
Test status
Simulation time 331070222 ps
CPU time 4.08 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 214340 kb
Host smart-284e0a19-af20-4607-85da-d12f0fd938bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308129667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3308129667
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1335714931
Short name T251
Test name
Test status
Simulation time 150718471 ps
CPU time 3.17 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 214360 kb
Host smart-2ce1abe8-3e04-4eef-879a-20a5ed2b123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335714931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1335714931
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1699876632
Short name T822
Test name
Test status
Simulation time 117003960 ps
CPU time 2.77 seconds
Started Jun 10 05:37:06 PM PDT 24
Finished Jun 10 05:37:10 PM PDT 24
Peak memory 215060 kb
Host smart-29117ea2-e88a-470b-8306-64c1b34b16ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699876632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1699876632
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.950155978
Short name T588
Test name
Test status
Simulation time 261208717 ps
CPU time 5.51 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 208164 kb
Host smart-0599951f-aedd-4c97-ba43-d7a893acb629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950155978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.950155978
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1406674088
Short name T757
Test name
Test status
Simulation time 365151567 ps
CPU time 3.63 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 208540 kb
Host smart-40bdfcb2-c440-429b-83c1-b09510d8547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406674088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1406674088
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3440592062
Short name T548
Test name
Test status
Simulation time 24464814 ps
CPU time 1.84 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 207040 kb
Host smart-a87eef35-1692-441e-809e-4ced4960a7be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440592062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3440592062
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3627006455
Short name T834
Test name
Test status
Simulation time 59533406 ps
CPU time 2.09 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 206848 kb
Host smart-68541711-c836-4b5a-8e97-34c2b6e00687
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627006455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3627006455
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2818172204
Short name T315
Test name
Test status
Simulation time 91878852 ps
CPU time 3.02 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 206748 kb
Host smart-d65573ff-ede9-4c9f-9ae7-1f56adec84eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818172204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2818172204
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3157827677
Short name T171
Test name
Test status
Simulation time 48424853 ps
CPU time 2.06 seconds
Started Jun 10 05:37:14 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 215812 kb
Host smart-24e1de82-98e2-4eb5-b35c-aec32b1bad91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157827677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3157827677
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1712486462
Short name T442
Test name
Test status
Simulation time 23897616 ps
CPU time 1.65 seconds
Started Jun 10 05:37:09 PM PDT 24
Finished Jun 10 05:37:11 PM PDT 24
Peak memory 206780 kb
Host smart-1ccdc30d-2f21-4e20-ad62-2fe92d762d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712486462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1712486462
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2424542635
Short name T540
Test name
Test status
Simulation time 235380786 ps
CPU time 5.48 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 208240 kb
Host smart-1b674494-be9e-4b05-ae1c-3fab50ef0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424542635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2424542635
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2412747772
Short name T377
Test name
Test status
Simulation time 40262717 ps
CPU time 1.76 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 210228 kb
Host smart-f822e1eb-92de-42b1-aec6-e51cc974e4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412747772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2412747772
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3008670256
Short name T521
Test name
Test status
Simulation time 15444433 ps
CPU time 0.74 seconds
Started Jun 10 05:37:14 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 205900 kb
Host smart-f32bc05b-a5ee-49a7-8869-39f935af3a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008670256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3008670256
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4015397754
Short name T383
Test name
Test status
Simulation time 918033852 ps
CPU time 4 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 214356 kb
Host smart-b5e5eea7-c5ab-4793-a93d-ac4bc15e1c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015397754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4015397754
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1628334710
Short name T480
Test name
Test status
Simulation time 749869393 ps
CPU time 8.18 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 219944 kb
Host smart-e561d092-b1c3-4cd5-97e3-4d8a93c764e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628334710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1628334710
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1338881104
Short name T370
Test name
Test status
Simulation time 466322773 ps
CPU time 4.08 seconds
Started Jun 10 05:37:14 PM PDT 24
Finished Jun 10 05:37:19 PM PDT 24
Peak memory 214276 kb
Host smart-ce32774a-f332-47cf-8309-79c5e8f470c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338881104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1338881104
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3594698439
Short name T837
Test name
Test status
Simulation time 113517405 ps
CPU time 3.25 seconds
Started Jun 10 05:37:08 PM PDT 24
Finished Jun 10 05:37:12 PM PDT 24
Peak memory 222380 kb
Host smart-c6dc3c09-88ef-43e3-923a-6bbd1b0d0f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594698439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3594698439
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2236497133
Short name T215
Test name
Test status
Simulation time 43216687 ps
CPU time 2.9 seconds
Started Jun 10 05:37:15 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 209172 kb
Host smart-f9c27a07-9a02-4cde-8f23-641652e51d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236497133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2236497133
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1504530543
Short name T410
Test name
Test status
Simulation time 1569471693 ps
CPU time 39.18 seconds
Started Jun 10 05:37:11 PM PDT 24
Finished Jun 10 05:37:50 PM PDT 24
Peak memory 208284 kb
Host smart-1b7c5d5c-4b8d-4fdd-a0d4-d8b508b74321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504530543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1504530543
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2959262945
Short name T352
Test name
Test status
Simulation time 3959626444 ps
CPU time 26.71 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:37 PM PDT 24
Peak memory 208264 kb
Host smart-165149e0-cc1f-4175-874d-6541ba135a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959262945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2959262945
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3270894662
Short name T642
Test name
Test status
Simulation time 131271735 ps
CPU time 2.67 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 207336 kb
Host smart-b14a6f31-06c7-4e9d-9f0a-2e3f23a858d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270894662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3270894662
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1988069492
Short name T1
Test name
Test status
Simulation time 31918250 ps
CPU time 2.39 seconds
Started Jun 10 05:37:15 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 207196 kb
Host smart-2ff6c245-4bf0-4823-ab8f-3d70933922f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988069492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1988069492
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4287075633
Short name T863
Test name
Test status
Simulation time 708766305 ps
CPU time 8.25 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 208336 kb
Host smart-8fdb73a1-471f-4c27-85af-91d94a4a9dc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287075633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4287075633
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.538897007
Short name T311
Test name
Test status
Simulation time 85524183 ps
CPU time 3.65 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 209548 kb
Host smart-983be445-c197-454f-b018-ec71a845b813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538897007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.538897007
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1699813574
Short name T506
Test name
Test status
Simulation time 30753397 ps
CPU time 2.13 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 206776 kb
Host smart-d1bc76e6-6337-4d1c-960c-22d211193999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699813574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1699813574
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3878030519
Short name T73
Test name
Test status
Simulation time 13217710897 ps
CPU time 64.21 seconds
Started Jun 10 05:37:15 PM PDT 24
Finished Jun 10 05:38:20 PM PDT 24
Peak memory 216372 kb
Host smart-929c2689-bd83-4759-824e-45ca6e19997f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878030519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3878030519
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3866769185
Short name T314
Test name
Test status
Simulation time 621411230 ps
CPU time 16.18 seconds
Started Jun 10 05:37:14 PM PDT 24
Finished Jun 10 05:37:30 PM PDT 24
Peak memory 222556 kb
Host smart-70dbd26d-6c56-4708-97e4-596910a1c9fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866769185 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3866769185
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3014173552
Short name T736
Test name
Test status
Simulation time 388323015 ps
CPU time 5.83 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:19 PM PDT 24
Peak memory 218016 kb
Host smart-179f6556-7a31-40bc-9b0e-2c7ed73ebcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014173552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3014173552
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2152732515
Short name T373
Test name
Test status
Simulation time 146529025 ps
CPU time 3.16 seconds
Started Jun 10 05:37:21 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 210336 kb
Host smart-6cb8a5e5-8b58-40fd-956d-432deb8b5b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152732515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2152732515
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2282335922
Short name T516
Test name
Test status
Simulation time 29695338 ps
CPU time 1.13 seconds
Started Jun 10 05:37:26 PM PDT 24
Finished Jun 10 05:37:27 PM PDT 24
Peak memory 206132 kb
Host smart-15dab9d6-c7f3-4534-b304-5ba184691576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282335922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2282335922
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1206853035
Short name T28
Test name
Test status
Simulation time 58268863 ps
CPU time 2.39 seconds
Started Jun 10 05:37:29 PM PDT 24
Finished Jun 10 05:37:32 PM PDT 24
Peak memory 214628 kb
Host smart-bab26329-1b35-4d8d-b131-d196ba88d1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206853035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1206853035
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.92667819
Short name T70
Test name
Test status
Simulation time 273629003 ps
CPU time 3.24 seconds
Started Jun 10 05:37:18 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 207628 kb
Host smart-006b16b7-3978-429a-b5ed-9e33c042cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92667819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.92667819
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1295695020
Short name T902
Test name
Test status
Simulation time 1086898346 ps
CPU time 4.39 seconds
Started Jun 10 05:37:20 PM PDT 24
Finished Jun 10 05:37:25 PM PDT 24
Peak memory 209832 kb
Host smart-4a8ff6fe-8205-40db-96e3-d9df22c94583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295695020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1295695020
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1969734741
Short name T760
Test name
Test status
Simulation time 93039984 ps
CPU time 2.64 seconds
Started Jun 10 05:37:18 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 217544 kb
Host smart-1fc500d7-3ff3-4342-9c6c-2230c67e193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969734741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1969734741
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2370584150
Short name T598
Test name
Test status
Simulation time 314433700 ps
CPU time 3.88 seconds
Started Jun 10 05:37:25 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 214360 kb
Host smart-3f2aed79-c883-4085-a77c-3eb16ac171b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370584150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2370584150
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1609135640
Short name T732
Test name
Test status
Simulation time 2463648280 ps
CPU time 6.79 seconds
Started Jun 10 05:37:17 PM PDT 24
Finished Jun 10 05:37:25 PM PDT 24
Peak memory 207808 kb
Host smart-f76e86b8-25b9-4776-ad99-2ac12bd80955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609135640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1609135640
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1944999812
Short name T350
Test name
Test status
Simulation time 47198938 ps
CPU time 2.87 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:16 PM PDT 24
Peak memory 206952 kb
Host smart-6a88a783-9246-431d-8123-9304c75948dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944999812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1944999812
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2725051674
Short name T767
Test name
Test status
Simulation time 54910022 ps
CPU time 2.89 seconds
Started Jun 10 05:37:11 PM PDT 24
Finished Jun 10 05:37:14 PM PDT 24
Peak memory 208880 kb
Host smart-a393a47a-ae44-4891-bb84-142ddf1a74f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725051674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2725051674
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.14708726
Short name T513
Test name
Test status
Simulation time 854631715 ps
CPU time 6.78 seconds
Started Jun 10 05:37:10 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 208984 kb
Host smart-3af962e1-7dfc-4d18-82a9-0c26d622a314
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.14708726
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1435187738
Short name T117
Test name
Test status
Simulation time 376166358 ps
CPU time 3.76 seconds
Started Jun 10 05:37:13 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 208832 kb
Host smart-9793aa3e-8d83-4df8-8f2e-43d9c5941e37
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435187738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1435187738
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1625580520
Short name T219
Test name
Test status
Simulation time 53714577 ps
CPU time 2.04 seconds
Started Jun 10 05:37:18 PM PDT 24
Finished Jun 10 05:37:20 PM PDT 24
Peak memory 215328 kb
Host smart-a59682f3-3ede-4d3c-ba8b-4d450337f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625580520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1625580520
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3434217207
Short name T728
Test name
Test status
Simulation time 213798039 ps
CPU time 2.59 seconds
Started Jun 10 05:37:12 PM PDT 24
Finished Jun 10 05:37:15 PM PDT 24
Peak memory 206912 kb
Host smart-8eea13d9-8c2a-4025-a435-18ad729446e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434217207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3434217207
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2624586889
Short name T333
Test name
Test status
Simulation time 91517628 ps
CPU time 4.22 seconds
Started Jun 10 05:37:29 PM PDT 24
Finished Jun 10 05:37:33 PM PDT 24
Peak memory 207676 kb
Host smart-0e2919dd-7d80-478e-9ae7-22f704327a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624586889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2624586889
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4032391293
Short name T918
Test name
Test status
Simulation time 282457322 ps
CPU time 2.05 seconds
Started Jun 10 05:37:16 PM PDT 24
Finished Jun 10 05:37:18 PM PDT 24
Peak memory 210200 kb
Host smart-41f4b8d3-1889-479b-a9a6-17af6d45122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032391293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4032391293
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3928607834
Short name T592
Test name
Test status
Simulation time 12945647 ps
CPU time 0.74 seconds
Started Jun 10 05:37:24 PM PDT 24
Finished Jun 10 05:37:25 PM PDT 24
Peak memory 205952 kb
Host smart-93b8a964-761f-41a9-ac59-95488b5341b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928607834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3928607834
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2766549481
Short name T415
Test name
Test status
Simulation time 3028487636 ps
CPU time 39 seconds
Started Jun 10 05:37:17 PM PDT 24
Finished Jun 10 05:37:57 PM PDT 24
Peak memory 214372 kb
Host smart-a83c4323-3bd1-4a1d-a897-c072944f02a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766549481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2766549481
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1021353196
Short name T906
Test name
Test status
Simulation time 195079712 ps
CPU time 2.14 seconds
Started Jun 10 05:37:36 PM PDT 24
Finished Jun 10 05:37:38 PM PDT 24
Peak memory 209044 kb
Host smart-24329d1d-1611-4642-8b67-2fb7a4aca010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021353196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1021353196
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3232309703
Short name T747
Test name
Test status
Simulation time 336265619 ps
CPU time 4.32 seconds
Started Jun 10 05:37:22 PM PDT 24
Finished Jun 10 05:37:26 PM PDT 24
Peak memory 206832 kb
Host smart-51939498-2c8a-41c5-9277-4416599da4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232309703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3232309703
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2954948701
Short name T300
Test name
Test status
Simulation time 1132070094 ps
CPU time 3.79 seconds
Started Jun 10 05:37:17 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 214300 kb
Host smart-430f8e41-5711-4d30-b27d-57da74975c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954948701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2954948701
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.641823877
Short name T599
Test name
Test status
Simulation time 164473509 ps
CPU time 3.28 seconds
Started Jun 10 05:37:20 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 209508 kb
Host smart-4a213d03-d00f-4f8f-90c9-1b9ca4c47ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641823877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.641823877
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1913087386
Short name T440
Test name
Test status
Simulation time 1093605860 ps
CPU time 28.66 seconds
Started Jun 10 05:37:28 PM PDT 24
Finished Jun 10 05:37:57 PM PDT 24
Peak memory 209120 kb
Host smart-8741607f-4ed4-4c52-bb21-8a144189959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913087386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1913087386
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.656190915
Short name T755
Test name
Test status
Simulation time 126959381 ps
CPU time 2.74 seconds
Started Jun 10 05:37:41 PM PDT 24
Finished Jun 10 05:37:45 PM PDT 24
Peak memory 206880 kb
Host smart-92668b73-c0d5-4453-a601-ea8e811e362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656190915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.656190915
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1432750273
Short name T621
Test name
Test status
Simulation time 463415831 ps
CPU time 3.69 seconds
Started Jun 10 05:37:17 PM PDT 24
Finished Jun 10 05:37:21 PM PDT 24
Peak memory 207028 kb
Host smart-7f223de9-659e-4286-889d-78ca8d16c2e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432750273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1432750273
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3866870356
Short name T583
Test name
Test status
Simulation time 38756661 ps
CPU time 1.87 seconds
Started Jun 10 05:37:22 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 206912 kb
Host smart-c013146c-dab7-457b-975c-d2f4b3b01dc4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866870356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3866870356
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1615291127
Short name T622
Test name
Test status
Simulation time 457735769 ps
CPU time 5.14 seconds
Started Jun 10 05:37:42 PM PDT 24
Finished Jun 10 05:37:48 PM PDT 24
Peak memory 207956 kb
Host smart-d509315f-3055-4729-84fd-aa4534a16e32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615291127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1615291127
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.364353354
Short name T654
Test name
Test status
Simulation time 33930468 ps
CPU time 1.62 seconds
Started Jun 10 05:37:22 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 208480 kb
Host smart-e3d00bcb-a2d4-4bc7-8a2b-5a60b3e6450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364353354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.364353354
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1437556845
Short name T15
Test name
Test status
Simulation time 73363299 ps
CPU time 2.15 seconds
Started Jun 10 05:37:35 PM PDT 24
Finished Jun 10 05:37:37 PM PDT 24
Peak memory 207908 kb
Host smart-eae69015-f50a-4bb4-99f6-c9e98eefa9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437556845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1437556845
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3741853319
Short name T68
Test name
Test status
Simulation time 913497089 ps
CPU time 19.9 seconds
Started Jun 10 05:37:36 PM PDT 24
Finished Jun 10 05:37:57 PM PDT 24
Peak memory 222620 kb
Host smart-25c6fc61-7f28-4d4d-8638-4e624f852275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741853319 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3741853319
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3918673787
Short name T189
Test name
Test status
Simulation time 1034109160 ps
CPU time 12.37 seconds
Started Jun 10 05:37:25 PM PDT 24
Finished Jun 10 05:37:38 PM PDT 24
Peak memory 214352 kb
Host smart-2d35f19a-22be-4622-933f-b0263b6e140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918673787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3918673787
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.294878958
Short name T187
Test name
Test status
Simulation time 102251574 ps
CPU time 3.51 seconds
Started Jun 10 05:37:34 PM PDT 24
Finished Jun 10 05:37:38 PM PDT 24
Peak memory 210148 kb
Host smart-c3798268-a6d8-4049-8ca3-8f7bad3a0cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294878958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.294878958
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.117004032
Short name T702
Test name
Test status
Simulation time 10843214 ps
CPU time 0.76 seconds
Started Jun 10 05:37:32 PM PDT 24
Finished Jun 10 05:37:33 PM PDT 24
Peak memory 205976 kb
Host smart-b6e92c3c-b41c-452a-8a0f-9598cc288ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117004032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.117004032
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2006730083
Short name T878
Test name
Test status
Simulation time 94800394 ps
CPU time 3.41 seconds
Started Jun 10 05:37:23 PM PDT 24
Finished Jun 10 05:37:26 PM PDT 24
Peak memory 207872 kb
Host smart-f6e3e452-5fb3-4a94-9924-64cf6bdf537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006730083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2006730083
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2996483910
Short name T302
Test name
Test status
Simulation time 132174634 ps
CPU time 2.53 seconds
Started Jun 10 05:37:34 PM PDT 24
Finished Jun 10 05:37:37 PM PDT 24
Peak memory 214316 kb
Host smart-3f5d8b0c-828f-43ab-b056-802bee3b7c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996483910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2996483910
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1974006499
Short name T324
Test name
Test status
Simulation time 39908853 ps
CPU time 2.89 seconds
Started Jun 10 05:37:21 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 214400 kb
Host smart-6cb4e65d-d7d9-4376-b76d-5d275a2a37e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974006499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1974006499
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3522560558
Short name T637
Test name
Test status
Simulation time 97986695 ps
CPU time 3.5 seconds
Started Jun 10 05:37:42 PM PDT 24
Finished Jun 10 05:37:47 PM PDT 24
Peak memory 214348 kb
Host smart-dbaafb39-e27f-428c-b698-41ce3ec75de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522560558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3522560558
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2128233749
Short name T402
Test name
Test status
Simulation time 314706803 ps
CPU time 5.18 seconds
Started Jun 10 05:37:24 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 209076 kb
Host smart-8b4b949a-e88a-4de6-af28-72d9b63b1dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128233749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2128233749
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.739942386
Short name T193
Test name
Test status
Simulation time 182607394 ps
CPU time 3.02 seconds
Started Jun 10 05:37:20 PM PDT 24
Finished Jun 10 05:37:24 PM PDT 24
Peak memory 206668 kb
Host smart-8771de99-c08c-4ba7-be4b-b4cabb1c8ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739942386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.739942386
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3907749301
Short name T11
Test name
Test status
Simulation time 851701793 ps
CPU time 7.84 seconds
Started Jun 10 05:37:19 PM PDT 24
Finished Jun 10 05:37:27 PM PDT 24
Peak memory 208916 kb
Host smart-c3de059b-0dff-4f64-af85-7ed616ec7cb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907749301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3907749301
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2246414945
Short name T443
Test name
Test status
Simulation time 91586989 ps
CPU time 2.66 seconds
Started Jun 10 05:37:22 PM PDT 24
Finished Jun 10 05:37:25 PM PDT 24
Peak memory 208760 kb
Host smart-aeaac586-c5f3-4f13-9a3d-0bdac7be0bb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246414945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2246414945
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.657336215
Short name T662
Test name
Test status
Simulation time 367992189 ps
CPU time 3.58 seconds
Started Jun 10 05:37:24 PM PDT 24
Finished Jun 10 05:37:28 PM PDT 24
Peak memory 207024 kb
Host smart-ee18b8ef-093f-4473-9919-27d7618cddba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657336215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.657336215
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.744419296
Short name T430
Test name
Test status
Simulation time 498719417 ps
CPU time 3.73 seconds
Started Jun 10 05:37:24 PM PDT 24
Finished Jun 10 05:37:28 PM PDT 24
Peak memory 215104 kb
Host smart-7d29787f-a17f-4414-871c-a23cee17bf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744419296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.744419296
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.934046566
Short name T704
Test name
Test status
Simulation time 82535225 ps
CPU time 3.35 seconds
Started Jun 10 05:37:30 PM PDT 24
Finished Jun 10 05:37:33 PM PDT 24
Peak memory 208452 kb
Host smart-930a87f6-b946-43f4-8eb4-76640d263932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934046566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.934046566
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1159915507
Short name T254
Test name
Test status
Simulation time 451234711 ps
CPU time 22.14 seconds
Started Jun 10 05:37:33 PM PDT 24
Finished Jun 10 05:37:56 PM PDT 24
Peak memory 215836 kb
Host smart-fad865c0-837f-4a8b-aa82-31179251a0e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159915507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1159915507
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.634516703
Short name T544
Test name
Test status
Simulation time 369369024 ps
CPU time 3.88 seconds
Started Jun 10 05:37:37 PM PDT 24
Finished Jun 10 05:37:41 PM PDT 24
Peak memory 209056 kb
Host smart-4a29f98b-13a0-44e8-b6f5-00ade58691a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634516703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.634516703
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1968785780
Short name T119
Test name
Test status
Simulation time 228868732 ps
CPU time 2.86 seconds
Started Jun 10 05:37:40 PM PDT 24
Finished Jun 10 05:37:44 PM PDT 24
Peak memory 210204 kb
Host smart-29825857-eb71-4adc-8173-025e3c7b40aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968785780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1968785780
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3587323264
Short name T514
Test name
Test status
Simulation time 13184682 ps
CPU time 0.83 seconds
Started Jun 10 05:37:30 PM PDT 24
Finished Jun 10 05:37:31 PM PDT 24
Peak memory 205932 kb
Host smart-03ac04f6-c4a3-49ab-82e4-770fa7cba6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587323264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3587323264
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.699769872
Short name T245
Test name
Test status
Simulation time 736723962 ps
CPU time 8.87 seconds
Started Jun 10 05:37:27 PM PDT 24
Finished Jun 10 05:37:37 PM PDT 24
Peak memory 214496 kb
Host smart-49075af3-69d0-414c-a77d-ac77e18d8fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699769872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.699769872
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3698331559
Short name T841
Test name
Test status
Simulation time 296691352 ps
CPU time 7.96 seconds
Started Jun 10 05:37:24 PM PDT 24
Finished Jun 10 05:37:32 PM PDT 24
Peak memory 220512 kb
Host smart-02ff4e07-990e-4f5b-bbdb-f603db52d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698331559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3698331559
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3724061241
Short name T543
Test name
Test status
Simulation time 320473928 ps
CPU time 10.19 seconds
Started Jun 10 05:37:35 PM PDT 24
Finished Jun 10 05:37:45 PM PDT 24
Peak memory 208844 kb
Host smart-b818a8bb-ac2e-4990-8667-66dfbc0406ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724061241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3724061241
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2405420750
Short name T813
Test name
Test status
Simulation time 88813715 ps
CPU time 2.73 seconds
Started Jun 10 05:37:26 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 214456 kb
Host smart-c1fd3064-08b3-4776-ae27-21d573c69049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405420750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2405420750
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2860002569
Short name T881
Test name
Test status
Simulation time 172064601 ps
CPU time 3.35 seconds
Started Jun 10 05:37:26 PM PDT 24
Finished Jun 10 05:37:30 PM PDT 24
Peak memory 222496 kb
Host smart-672c9e15-111f-41f2-9c77-00def87dd72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860002569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2860002569
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3154396473
Short name T327
Test name
Test status
Simulation time 140138249 ps
CPU time 3.15 seconds
Started Jun 10 05:37:26 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 214380 kb
Host smart-41ba6ebf-c759-4ef6-ae2f-b4dc157c31be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154396473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3154396473
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2402298511
Short name T304
Test name
Test status
Simulation time 485538181 ps
CPU time 5.71 seconds
Started Jun 10 05:37:31 PM PDT 24
Finished Jun 10 05:37:38 PM PDT 24
Peak memory 214356 kb
Host smart-eebcc6a9-be5d-48b0-96e1-0b5daf6a783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402298511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2402298511
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2024390750
Short name T719
Test name
Test status
Simulation time 1212958842 ps
CPU time 3.14 seconds
Started Jun 10 05:37:39 PM PDT 24
Finished Jun 10 05:37:44 PM PDT 24
Peak memory 206872 kb
Host smart-18f504a6-fbd6-4e63-9cde-a53a4fbce055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024390750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2024390750
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1728182430
Short name T546
Test name
Test status
Simulation time 287137615 ps
CPU time 2.78 seconds
Started Jun 10 05:37:26 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 206980 kb
Host smart-b8ef448d-7d9c-4d62-8850-3a5df4d9f334
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728182430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1728182430
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3195576288
Short name T387
Test name
Test status
Simulation time 1002797889 ps
CPU time 20.89 seconds
Started Jun 10 05:37:33 PM PDT 24
Finished Jun 10 05:37:55 PM PDT 24
Peak memory 208404 kb
Host smart-031d6aab-4b22-4a5f-a06d-f658e4b4b2d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195576288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3195576288
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.419905907
Short name T184
Test name
Test status
Simulation time 269121068 ps
CPU time 3.15 seconds
Started Jun 10 05:37:39 PM PDT 24
Finished Jun 10 05:37:44 PM PDT 24
Peak memory 208748 kb
Host smart-5fcd1520-3a79-4956-b45d-d41bb936e8c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419905907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.419905907
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1318233123
Short name T283
Test name
Test status
Simulation time 400105534 ps
CPU time 3.26 seconds
Started Jun 10 05:37:25 PM PDT 24
Finished Jun 10 05:37:29 PM PDT 24
Peak memory 209268 kb
Host smart-3561a704-d46b-4ce3-95a0-b793106bbddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318233123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1318233123
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.675562069
Short name T751
Test name
Test status
Simulation time 608524003 ps
CPU time 13.01 seconds
Started Jun 10 05:37:50 PM PDT 24
Finished Jun 10 05:38:04 PM PDT 24
Peak memory 207720 kb
Host smart-243e6e2a-a557-4f7c-99e4-c52abd80cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675562069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.675562069
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1079446719
Short name T232
Test name
Test status
Simulation time 567460816 ps
CPU time 22.93 seconds
Started Jun 10 05:37:41 PM PDT 24
Finished Jun 10 05:38:06 PM PDT 24
Peak memory 220960 kb
Host smart-780737d8-ad4d-43cb-bffd-25dd25f4fe90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079446719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1079446719
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.11417760
Short name T98
Test name
Test status
Simulation time 613527788 ps
CPU time 18.55 seconds
Started Jun 10 05:37:28 PM PDT 24
Finished Jun 10 05:37:46 PM PDT 24
Peak memory 220800 kb
Host smart-4327e4ac-7fae-4508-99ea-3b883a561607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11417760 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.11417760
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1848126821
Short name T725
Test name
Test status
Simulation time 317906759 ps
CPU time 4.02 seconds
Started Jun 10 05:37:39 PM PDT 24
Finished Jun 10 05:37:43 PM PDT 24
Peak memory 210028 kb
Host smart-fe21a9fc-6092-4bcc-be99-54b1ff4e3686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848126821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1848126821
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.564016193
Short name T749
Test name
Test status
Simulation time 190288304 ps
CPU time 2.83 seconds
Started Jun 10 05:37:32 PM PDT 24
Finished Jun 10 05:37:35 PM PDT 24
Peak memory 210516 kb
Host smart-89d85447-5469-462a-8f20-9abf402fea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564016193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.564016193
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1136313645
Short name T920
Test name
Test status
Simulation time 33315375 ps
CPU time 0.94 seconds
Started Jun 10 05:37:38 PM PDT 24
Finished Jun 10 05:37:40 PM PDT 24
Peak memory 206164 kb
Host smart-c8b1c685-7cd5-4a58-b2e9-f6a62abc2b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136313645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1136313645
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.474004815
Short name T888
Test name
Test status
Simulation time 27189416 ps
CPU time 2.12 seconds
Started Jun 10 05:37:30 PM PDT 24
Finished Jun 10 05:37:33 PM PDT 24
Peak memory 210128 kb
Host smart-6c5d9b15-bb30-49b9-b0d0-b8217a3c1290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474004815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.474004815
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.868165086
Short name T323
Test name
Test status
Simulation time 34110379 ps
CPU time 2.05 seconds
Started Jun 10 05:37:41 PM PDT 24
Finished Jun 10 05:37:44 PM PDT 24
Peak memory 222560 kb
Host smart-3a0fee6b-d149-4d52-a664-d504d022086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868165086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.868165086
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2333431121
Short name T781
Test name
Test status
Simulation time 174191451 ps
CPU time 4.2 seconds
Started Jun 10 05:37:30 PM PDT 24
Finished Jun 10 05:37:35 PM PDT 24
Peak memory 214356 kb
Host smart-d8401233-6422-483e-b9d1-9b54195fc178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333431121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2333431121
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3254448802
Short name T500
Test name
Test status
Simulation time 235194222 ps
CPU time 7.43 seconds
Started Jun 10 05:37:31 PM PDT 24
Finished Jun 10 05:37:39 PM PDT 24
Peak memory 214432 kb
Host smart-153edc45-1ac5-4535-9133-221a21077469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254448802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3254448802
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.695388771
Short name T266
Test name
Test status
Simulation time 1139210021 ps
CPU time 7.59 seconds
Started Jun 10 05:37:42 PM PDT 24
Finished Jun 10 05:37:51 PM PDT 24
Peak memory 209220 kb
Host smart-09ae788f-2224-4975-81b1-36a5bde4a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695388771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.695388771
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3133698132
Short name T390
Test name
Test status
Simulation time 649033924 ps
CPU time 16.6 seconds
Started Jun 10 05:37:42 PM PDT 24
Finished Jun 10 05:38:00 PM PDT 24
Peak memory 208208 kb
Host smart-4f120aba-ea7e-4988-a251-6846f9e5a5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133698132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3133698132
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.666826624
Short name T123
Test name
Test status
Simulation time 404502817 ps
CPU time 3.51 seconds
Started Jun 10 05:37:49 PM PDT 24
Finished Jun 10 05:37:53 PM PDT 24
Peak memory 208796 kb
Host smart-86870895-d643-4304-931c-316eadcc8ae3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666826624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.666826624
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.45330261
Short name T792
Test name
Test status
Simulation time 783913650 ps
CPU time 5.66 seconds
Started Jun 10 05:37:43 PM PDT 24
Finished Jun 10 05:37:50 PM PDT 24
Peak memory 207992 kb
Host smart-4c90681b-6dbd-4160-b54e-7f097aba7347
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45330261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.45330261
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2710108411
Short name T683
Test name
Test status
Simulation time 39600610 ps
CPU time 2.8 seconds
Started Jun 10 05:37:36 PM PDT 24
Finished Jun 10 05:37:40 PM PDT 24
Peak memory 208596 kb
Host smart-b9d0055b-532c-4eca-8a67-ec6bd76d076a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710108411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2710108411
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1778412135
Short name T409
Test name
Test status
Simulation time 85717541 ps
CPU time 2.46 seconds
Started Jun 10 05:37:46 PM PDT 24
Finished Jun 10 05:37:49 PM PDT 24
Peak memory 222460 kb
Host smart-64aa379b-5716-45fb-9a20-1880da182bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778412135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1778412135
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.324866457
Short name T473
Test name
Test status
Simulation time 136666422 ps
CPU time 3.28 seconds
Started Jun 10 05:37:30 PM PDT 24
Finished Jun 10 05:37:34 PM PDT 24
Peak memory 208240 kb
Host smart-bc9b8b6d-f8b8-45e9-b2cd-ec4b77782649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324866457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.324866457
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2002084491
Short name T326
Test name
Test status
Simulation time 797656463 ps
CPU time 15.74 seconds
Started Jun 10 05:37:30 PM PDT 24
Finished Jun 10 05:37:46 PM PDT 24
Peak memory 215348 kb
Host smart-c23ac299-32e6-44c8-a81e-052b21e0abba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002084491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2002084491
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2274619130
Short name T472
Test name
Test status
Simulation time 366047482 ps
CPU time 4.73 seconds
Started Jun 10 05:37:42 PM PDT 24
Finished Jun 10 05:37:48 PM PDT 24
Peak memory 218424 kb
Host smart-c59bcdbf-3a6c-4ace-a08f-d717dbe5d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274619130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2274619130
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.267616698
Short name T374
Test name
Test status
Simulation time 60131175 ps
CPU time 1.83 seconds
Started Jun 10 05:37:43 PM PDT 24
Finished Jun 10 05:37:46 PM PDT 24
Peak memory 209840 kb
Host smart-6c2cba17-a643-439d-af0c-e8b004936f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267616698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.267616698
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3671017013
Short name T173
Test name
Test status
Simulation time 15369941 ps
CPU time 0.78 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:07 PM PDT 24
Peak memory 205932 kb
Host smart-3838cf2a-08ac-4093-9f2c-307ad194c0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671017013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3671017013
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2335435039
Short name T292
Test name
Test status
Simulation time 216876519 ps
CPU time 4.46 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 208348 kb
Host smart-15baff6f-5f2f-457e-9147-88cff343bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335435039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2335435039
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.665106282
Short name T723
Test name
Test status
Simulation time 160589974 ps
CPU time 4.76 seconds
Started Jun 10 05:35:10 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 214312 kb
Host smart-6859451c-657c-4638-a00b-909384648dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665106282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.665106282
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1066616377
Short name T557
Test name
Test status
Simulation time 491777671 ps
CPU time 3.73 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:35:09 PM PDT 24
Peak memory 219664 kb
Host smart-9b171cc4-1f28-435b-8679-b6c1c7fdda9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066616377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1066616377
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1139578455
Short name T793
Test name
Test status
Simulation time 1320372934 ps
CPU time 32.84 seconds
Started Jun 10 05:35:04 PM PDT 24
Finished Jun 10 05:35:37 PM PDT 24
Peak memory 210056 kb
Host smart-e6c95540-5c6b-44b9-aa68-8588c393386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139578455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1139578455
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4095002179
Short name T567
Test name
Test status
Simulation time 179153358 ps
CPU time 2.8 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:16 PM PDT 24
Peak memory 206036 kb
Host smart-e86fa140-fa2d-45f4-9935-ebdd19449852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095002179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4095002179
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2626828404
Short name T568
Test name
Test status
Simulation time 467018668 ps
CPU time 6.67 seconds
Started Jun 10 05:35:00 PM PDT 24
Finished Jun 10 05:35:07 PM PDT 24
Peak memory 208716 kb
Host smart-6695579d-49c6-4787-8b0e-cba76b40c994
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626828404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2626828404
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2560214387
Short name T538
Test name
Test status
Simulation time 19292917678 ps
CPU time 64.25 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:36:09 PM PDT 24
Peak memory 208124 kb
Host smart-937c38ee-cf73-4d81-ad27-a920a03881e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560214387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2560214387
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.106274226
Short name T623
Test name
Test status
Simulation time 301454416 ps
CPU time 2.85 seconds
Started Jun 10 05:35:01 PM PDT 24
Finished Jun 10 05:35:04 PM PDT 24
Peak memory 208464 kb
Host smart-7bfc1fbb-b1ab-4f0b-a63f-aa44426d9080
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106274226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.106274226
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.4168813099
Short name T222
Test name
Test status
Simulation time 218013162 ps
CPU time 3.02 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:35:08 PM PDT 24
Peak memory 209312 kb
Host smart-fe7367bc-82c3-49d2-a879-e279d4ab1b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168813099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4168813099
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.687774311
Short name T535
Test name
Test status
Simulation time 127661116 ps
CPU time 3.61 seconds
Started Jun 10 05:35:11 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 208276 kb
Host smart-6463e544-6a27-4b75-a8da-8df907d6d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687774311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.687774311
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2245318897
Short name T734
Test name
Test status
Simulation time 1691833454 ps
CPU time 48.81 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:55 PM PDT 24
Peak memory 216784 kb
Host smart-4241942d-b04f-44cb-b9e6-ac45dd43ecb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245318897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2245318897
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3831836968
Short name T444
Test name
Test status
Simulation time 309657366 ps
CPU time 8.11 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 207964 kb
Host smart-486c4b60-89e2-4903-b861-d27ff684f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831836968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3831836968
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1557056596
Short name T146
Test name
Test status
Simulation time 338495487 ps
CPU time 3.53 seconds
Started Jun 10 05:35:04 PM PDT 24
Finished Jun 10 05:35:08 PM PDT 24
Peak memory 209972 kb
Host smart-cca7bbfc-5a1e-4d4f-8998-c608f7e667d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557056596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1557056596
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3660774239
Short name T777
Test name
Test status
Simulation time 39592604 ps
CPU time 0.81 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:10 PM PDT 24
Peak memory 205928 kb
Host smart-cb82718e-a09f-40d6-a67b-135e6b8afcfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660774239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3660774239
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4251053718
Short name T218
Test name
Test status
Simulation time 99168159 ps
CPU time 6.15 seconds
Started Jun 10 05:35:07 PM PDT 24
Finished Jun 10 05:35:13 PM PDT 24
Peak memory 214424 kb
Host smart-9769432e-75cb-4194-82dc-8b70fd044218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251053718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4251053718
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2324533138
Short name T657
Test name
Test status
Simulation time 134391411 ps
CPU time 2.05 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:21 PM PDT 24
Peak memory 214236 kb
Host smart-c63434e6-8639-49c8-a0cc-28058459a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324533138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2324533138
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.560647790
Short name T496
Test name
Test status
Simulation time 74341232 ps
CPU time 3.8 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:23 PM PDT 24
Peak memory 209920 kb
Host smart-73a31c0f-d415-46af-8166-f62aeaa89d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560647790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.560647790
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1609154102
Short name T900
Test name
Test status
Simulation time 31846993 ps
CPU time 2.5 seconds
Started Jun 10 05:35:08 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 214428 kb
Host smart-4f3b9b26-7aef-492c-a39b-a424c8656f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609154102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1609154102
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1346725281
Short name T322
Test name
Test status
Simulation time 69204098 ps
CPU time 3 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:10 PM PDT 24
Peak memory 214348 kb
Host smart-e30d8b07-5549-467f-abd3-fb7763bd5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346725281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1346725281
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1621217490
Short name T553
Test name
Test status
Simulation time 542539287 ps
CPU time 4.37 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 214372 kb
Host smart-b45f2d1f-4cf2-4278-b4ab-4fdbfc102489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621217490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1621217490
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.234096988
Short name T607
Test name
Test status
Simulation time 556932005 ps
CPU time 4.41 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 207836 kb
Host smart-02387811-33e6-4883-8b21-585fb9b82d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234096988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.234096988
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1278162360
Short name T253
Test name
Test status
Simulation time 178560612 ps
CPU time 4.92 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:24 PM PDT 24
Peak memory 208728 kb
Host smart-688f8a97-ac66-4ebd-944f-59548e92fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278162360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1278162360
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4063233903
Short name T638
Test name
Test status
Simulation time 347263830 ps
CPU time 4.53 seconds
Started Jun 10 05:35:07 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 208840 kb
Host smart-e1e02ea7-1c2e-4056-9f68-c4bc4f084d04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063233903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4063233903
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2875712937
Short name T307
Test name
Test status
Simulation time 24269765 ps
CPU time 1.96 seconds
Started Jun 10 05:35:05 PM PDT 24
Finished Jun 10 05:35:07 PM PDT 24
Peak memory 208484 kb
Host smart-66766c9c-6644-4d27-b01c-83e749bb2aca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875712937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2875712937
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1413331778
Short name T655
Test name
Test status
Simulation time 280281993 ps
CPU time 4.42 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 209160 kb
Host smart-bf379e04-5b7d-4d70-a30a-3460ffded26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413331778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1413331778
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1802621867
Short name T563
Test name
Test status
Simulation time 18746053 ps
CPU time 1.69 seconds
Started Jun 10 05:35:06 PM PDT 24
Finished Jun 10 05:35:09 PM PDT 24
Peak memory 206860 kb
Host smart-48bb0a83-9d0c-44b9-8407-a8a69ddf83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802621867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1802621867
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3254746874
Short name T201
Test name
Test status
Simulation time 817696900 ps
CPU time 26.39 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:36 PM PDT 24
Peak memory 214300 kb
Host smart-cb3dd37d-843c-4567-a20a-4c6d21bd52c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254746874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3254746874
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2404730006
Short name T879
Test name
Test status
Simulation time 373282531 ps
CPU time 23.04 seconds
Started Jun 10 05:35:03 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 222700 kb
Host smart-6b6ed451-b8b9-41ef-9b1d-ff3e0ece69e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404730006 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2404730006
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.114098117
Short name T746
Test name
Test status
Simulation time 123023329 ps
CPU time 4.42 seconds
Started Jun 10 05:35:07 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 208264 kb
Host smart-42ceb72a-7a4f-438a-aebe-0ea5d0b643e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114098117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.114098117
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3190172327
Short name T392
Test name
Test status
Simulation time 65108185 ps
CPU time 1.96 seconds
Started Jun 10 05:35:07 PM PDT 24
Finished Jun 10 05:35:09 PM PDT 24
Peak memory 209968 kb
Host smart-29a7d2a8-aeda-40bf-98e2-74bace7d4d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190172327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3190172327
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2478253478
Short name T675
Test name
Test status
Simulation time 8848512 ps
CPU time 0.71 seconds
Started Jun 10 05:35:10 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 205948 kb
Host smart-65da3079-f13a-4b54-a690-c1e64df55bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478253478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2478253478
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2591426399
Short name T271
Test name
Test status
Simulation time 648152321 ps
CPU time 33.53 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:49 PM PDT 24
Peak memory 214432 kb
Host smart-6f0eb984-08c2-4ea0-8d17-dad13a8db757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591426399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2591426399
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1183659918
Short name T783
Test name
Test status
Simulation time 178986995 ps
CPU time 3.38 seconds
Started Jun 10 05:35:11 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 209564 kb
Host smart-3f6537ca-1bc0-49c1-9f82-698e4d90db51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183659918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1183659918
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1587400813
Short name T67
Test name
Test status
Simulation time 242611120 ps
CPU time 3.08 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:16 PM PDT 24
Peak memory 214328 kb
Host smart-4d4813a1-6c61-4ab8-9f7d-50a352339a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587400813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1587400813
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1928484612
Short name T290
Test name
Test status
Simulation time 283631844 ps
CPU time 7.84 seconds
Started Jun 10 05:35:13 PM PDT 24
Finished Jun 10 05:35:21 PM PDT 24
Peak memory 220696 kb
Host smart-4a2bc35e-aa85-4675-afe5-f43bb19c8d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928484612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1928484612
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2091808448
Short name T660
Test name
Test status
Simulation time 30309859 ps
CPU time 1.89 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 214328 kb
Host smart-f97597fa-3b82-4bd2-a38d-0fb226290e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091808448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2091808448
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2933562086
Short name T96
Test name
Test status
Simulation time 431203314 ps
CPU time 3.1 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 219844 kb
Host smart-ef360626-6d67-413a-bae7-c06478488d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933562086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2933562086
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3069783506
Short name T289
Test name
Test status
Simulation time 245698441 ps
CPU time 4.57 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 218400 kb
Host smart-5c4ca50b-7b38-4951-92ef-52b3c6040cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069783506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3069783506
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1218929620
Short name T530
Test name
Test status
Simulation time 32145860 ps
CPU time 2.41 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:21 PM PDT 24
Peak memory 207448 kb
Host smart-0d7df442-1c8b-41a4-9d85-bb16a7a952f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218929620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1218929620
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.4115519725
Short name T769
Test name
Test status
Simulation time 263068358 ps
CPU time 3.53 seconds
Started Jun 10 05:35:10 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 208748 kb
Host smart-478e6e4e-ac20-481c-a271-7b05d0754d5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115519725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4115519725
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2931673612
Short name T843
Test name
Test status
Simulation time 204544465 ps
CPU time 5.94 seconds
Started Jun 10 05:35:10 PM PDT 24
Finished Jun 10 05:35:17 PM PDT 24
Peak memory 208480 kb
Host smart-f4034840-11a1-4e43-811e-adacb98aef02
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931673612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2931673612
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3942002180
Short name T604
Test name
Test status
Simulation time 71828280 ps
CPU time 2.32 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 208580 kb
Host smart-de478684-f7e9-46f2-afc1-c380c18c5a29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942002180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3942002180
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.703825625
Short name T591
Test name
Test status
Simulation time 171559148 ps
CPU time 4 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:19 PM PDT 24
Peak memory 218388 kb
Host smart-dc4a8c1f-3f3f-411c-9b95-67dbe2d73042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703825625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.703825625
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2552553135
Short name T486
Test name
Test status
Simulation time 1007311850 ps
CPU time 2.63 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:12 PM PDT 24
Peak memory 206804 kb
Host smart-067723f2-022d-4b38-9190-36b63e341350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552553135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2552553135
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.787938771
Short name T286
Test name
Test status
Simulation time 10200944632 ps
CPU time 291.71 seconds
Started Jun 10 05:35:10 PM PDT 24
Finished Jun 10 05:40:02 PM PDT 24
Peak memory 217000 kb
Host smart-dd548da7-efb2-4234-aa9a-28ac00d1dcab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787938771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.787938771
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2111817544
Short name T115
Test name
Test status
Simulation time 1701194426 ps
CPU time 18.89 seconds
Started Jun 10 05:35:11 PM PDT 24
Finished Jun 10 05:35:31 PM PDT 24
Peak memory 222876 kb
Host smart-9ab2e193-246f-4563-987e-88049cdf71bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111817544 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2111817544
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.346499344
Short name T126
Test name
Test status
Simulation time 329426650 ps
CPU time 4.25 seconds
Started Jun 10 05:35:08 PM PDT 24
Finished Jun 10 05:35:13 PM PDT 24
Peak memory 207320 kb
Host smart-185f787f-88f9-4fea-aa6b-73bb8a8a1040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346499344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.346499344
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.609753067
Short name T118
Test name
Test status
Simulation time 145163981 ps
CPU time 1.8 seconds
Started Jun 10 05:35:09 PM PDT 24
Finished Jun 10 05:35:11 PM PDT 24
Peak memory 210012 kb
Host smart-5baf65c0-10ec-4af6-9a20-10f6634d6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609753067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.609753067
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.865746620
Short name T759
Test name
Test status
Simulation time 14551300 ps
CPU time 0.94 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:20 PM PDT 24
Peak memory 206056 kb
Host smart-b1e76d0d-afec-40e7-ba1c-aba1e7bb5766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865746620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.865746620
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1724796103
Short name T366
Test name
Test status
Simulation time 57831813 ps
CPU time 3.82 seconds
Started Jun 10 05:35:22 PM PDT 24
Finished Jun 10 05:35:26 PM PDT 24
Peak memory 214220 kb
Host smart-52a053f4-2da1-4e0b-a038-ff0b8317f8f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724796103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1724796103
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1424249192
Short name T635
Test name
Test status
Simulation time 38651624 ps
CPU time 1.62 seconds
Started Jun 10 05:35:13 PM PDT 24
Finished Jun 10 05:35:15 PM PDT 24
Peak memory 207924 kb
Host smart-cd0491e1-8640-4eaf-a1ca-d3af4e7bb7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424249192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1424249192
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1037206383
Short name T301
Test name
Test status
Simulation time 188780419 ps
CPU time 4.48 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:20 PM PDT 24
Peak memory 214364 kb
Host smart-843ca140-bc6e-4401-8465-e7b8c94ed398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037206383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1037206383
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3687277084
Short name T49
Test name
Test status
Simulation time 377331089 ps
CPU time 2.92 seconds
Started Jun 10 05:35:14 PM PDT 24
Finished Jun 10 05:35:18 PM PDT 24
Peak memory 214288 kb
Host smart-1f9950a3-a0d1-433b-8c6a-f91ebb39fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687277084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3687277084
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.554999901
Short name T51
Test name
Test status
Simulation time 2851980090 ps
CPU time 4.86 seconds
Started Jun 10 05:35:22 PM PDT 24
Finished Jun 10 05:35:27 PM PDT 24
Peak memory 219860 kb
Host smart-9ebd7d65-5656-44a1-b59b-586bf59fb9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554999901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.554999901
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2668626582
Short name T569
Test name
Test status
Simulation time 206500406 ps
CPU time 5.09 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:18 PM PDT 24
Peak memory 207588 kb
Host smart-b1610df2-ec8b-4a28-b8c4-77610686c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668626582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2668626582
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.730857058
Short name T422
Test name
Test status
Simulation time 99460937 ps
CPU time 2.74 seconds
Started Jun 10 05:35:13 PM PDT 24
Finished Jun 10 05:35:16 PM PDT 24
Peak memory 208420 kb
Host smart-0a69e822-2c35-456b-98a9-d5256293fe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730857058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.730857058
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1018149899
Short name T523
Test name
Test status
Simulation time 188602044 ps
CPU time 2.58 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:18 PM PDT 24
Peak memory 208736 kb
Host smart-65585071-af57-464d-b271-b2cfbd14b86b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018149899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1018149899
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3756379968
Short name T831
Test name
Test status
Simulation time 390554224 ps
CPU time 6.08 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:22 PM PDT 24
Peak memory 208136 kb
Host smart-243693d0-791d-4cc6-8250-b615fe68cbf0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756379968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3756379968
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.32260850
Short name T396
Test name
Test status
Simulation time 380667937 ps
CPU time 6.97 seconds
Started Jun 10 05:35:12 PM PDT 24
Finished Jun 10 05:35:19 PM PDT 24
Peak memory 208636 kb
Host smart-8e6b23fd-9bc3-4a6a-a108-2f99480f9b53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.32260850
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2198754404
Short name T391
Test name
Test status
Simulation time 1743737669 ps
CPU time 5.16 seconds
Started Jun 10 05:35:13 PM PDT 24
Finished Jun 10 05:35:19 PM PDT 24
Peak memory 208100 kb
Host smart-92ddbffc-3b60-47b1-ba54-383b112f5124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198754404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2198754404
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.154861348
Short name T400
Test name
Test status
Simulation time 849215636 ps
CPU time 16.74 seconds
Started Jun 10 05:35:08 PM PDT 24
Finished Jun 10 05:35:25 PM PDT 24
Peak memory 207932 kb
Host smart-8c57f533-11dd-4b0d-b4de-8799f9378010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154861348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.154861348
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.651724350
Short name T462
Test name
Test status
Simulation time 79329406 ps
CPU time 0.79 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:16 PM PDT 24
Peak memory 205932 kb
Host smart-ab8e4c69-91c2-4dec-a45e-da842f12a82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651724350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.651724350
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2007239311
Short name T114
Test name
Test status
Simulation time 2236281342 ps
CPU time 15.69 seconds
Started Jun 10 05:35:16 PM PDT 24
Finished Jun 10 05:35:32 PM PDT 24
Peak memory 222712 kb
Host smart-3a436c83-2636-4c73-ad61-e1ecdbf75cc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007239311 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2007239311
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3665044145
Short name T716
Test name
Test status
Simulation time 684267283 ps
CPU time 6.02 seconds
Started Jun 10 05:35:22 PM PDT 24
Finished Jun 10 05:35:28 PM PDT 24
Peak memory 207752 kb
Host smart-7741eb75-42ff-459b-9943-6af2295162d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665044145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3665044145
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2302717822
Short name T532
Test name
Test status
Simulation time 186354028 ps
CPU time 2.44 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:17 PM PDT 24
Peak memory 210184 kb
Host smart-52726b05-96fa-4e3e-b0e8-9ee19752d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302717822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2302717822
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.151729450
Short name T452
Test name
Test status
Simulation time 8354720 ps
CPU time 0.7 seconds
Started Jun 10 05:35:17 PM PDT 24
Finished Jun 10 05:35:18 PM PDT 24
Peak memory 205944 kb
Host smart-2191b205-f026-4d3e-8edb-d3950523b58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151729450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.151729450
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2873614084
Short name T413
Test name
Test status
Simulation time 74170765 ps
CPU time 4.65 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:20 PM PDT 24
Peak memory 214340 kb
Host smart-bcd88cd5-9630-4282-9f64-c5b8d687847c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873614084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2873614084
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1359927464
Short name T775
Test name
Test status
Simulation time 161683585 ps
CPU time 2.28 seconds
Started Jun 10 05:35:17 PM PDT 24
Finished Jun 10 05:35:19 PM PDT 24
Peak memory 210156 kb
Host smart-4f64c8d9-363e-4b07-a2f3-b5de04bbc213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359927464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1359927464
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.465597990
Short name T471
Test name
Test status
Simulation time 81541864 ps
CPU time 2.53 seconds
Started Jun 10 05:35:18 PM PDT 24
Finished Jun 10 05:35:21 PM PDT 24
Peak memory 209560 kb
Host smart-bc80f630-f9a5-42bb-8cd3-62425c68cf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465597990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.465597990
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2742846934
Short name T369
Test name
Test status
Simulation time 8469861508 ps
CPU time 18.92 seconds
Started Jun 10 05:35:20 PM PDT 24
Finished Jun 10 05:35:39 PM PDT 24
Peak memory 214516 kb
Host smart-c2090743-d92a-40c9-8785-10ec3692c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742846934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2742846934
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.71763919
Short name T252
Test name
Test status
Simulation time 147646031 ps
CPU time 3.2 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:25 PM PDT 24
Peak memory 222548 kb
Host smart-1f55d99c-178d-49a8-aebf-9d83f6d31f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71763919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.71763919
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3584904727
Short name T407
Test name
Test status
Simulation time 75030634 ps
CPU time 3.34 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:25 PM PDT 24
Peak memory 209884 kb
Host smart-e492b085-4e97-4e99-9efc-99fe68b64d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584904727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3584904727
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3392259480
Short name T743
Test name
Test status
Simulation time 4840051988 ps
CPU time 7.05 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:26 PM PDT 24
Peak memory 208396 kb
Host smart-20412ac1-dc32-4509-b4d8-e5458db4c278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392259480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3392259480
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3740013495
Short name T653
Test name
Test status
Simulation time 2959649239 ps
CPU time 19.33 seconds
Started Jun 10 05:35:21 PM PDT 24
Finished Jun 10 05:35:41 PM PDT 24
Peak memory 208796 kb
Host smart-67d30aa6-e917-4230-afee-d8b9f46a1338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740013495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3740013495
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1347788393
Short name T463
Test name
Test status
Simulation time 203515944 ps
CPU time 2.85 seconds
Started Jun 10 05:35:11 PM PDT 24
Finished Jun 10 05:35:14 PM PDT 24
Peak memory 206800 kb
Host smart-fce61090-5356-45c1-ac4d-578f79785b3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347788393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1347788393
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2108898182
Short name T526
Test name
Test status
Simulation time 60422495 ps
CPU time 2.69 seconds
Started Jun 10 05:35:14 PM PDT 24
Finished Jun 10 05:35:17 PM PDT 24
Peak memory 206920 kb
Host smart-1490eb86-1917-49e1-9dca-6de5c782b103
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108898182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2108898182
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3986562394
Short name T389
Test name
Test status
Simulation time 72167990 ps
CPU time 2.81 seconds
Started Jun 10 05:35:15 PM PDT 24
Finished Jun 10 05:35:19 PM PDT 24
Peak memory 208564 kb
Host smart-3d401305-96a7-42fd-a64f-0606053c165e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986562394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3986562394
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2604160336
Short name T857
Test name
Test status
Simulation time 65809300 ps
CPU time 1.84 seconds
Started Jun 10 05:35:18 PM PDT 24
Finished Jun 10 05:35:20 PM PDT 24
Peak memory 207860 kb
Host smart-7baef06d-0855-41ef-a9f9-f31231c98685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604160336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2604160336
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3056616550
Short name T542
Test name
Test status
Simulation time 64952163 ps
CPU time 2.45 seconds
Started Jun 10 05:35:22 PM PDT 24
Finished Jun 10 05:35:25 PM PDT 24
Peak memory 208420 kb
Host smart-ebb437ea-1e98-4400-900f-5b8d9f510662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056616550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3056616550
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1102128245
Short name T688
Test name
Test status
Simulation time 337416991 ps
CPU time 15.85 seconds
Started Jun 10 05:35:18 PM PDT 24
Finished Jun 10 05:35:34 PM PDT 24
Peak memory 222564 kb
Host smart-4ee5f893-0191-4780-a652-501ded8ced25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102128245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1102128245
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2932764147
Short name T255
Test name
Test status
Simulation time 61535644 ps
CPU time 2.62 seconds
Started Jun 10 05:35:19 PM PDT 24
Finished Jun 10 05:35:22 PM PDT 24
Peak memory 219632 kb
Host smart-2f22284a-1411-433c-af1e-ec768a562d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932764147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2932764147
Directory /workspace/9.keymgr_sw_invalid_input/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%