Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4714

1

T2

5

T3

8

T4

1

auto[1]

616

1

T14

6

T39

1

T109

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4714

1

T2

5

T3

8

T4

1

auto[1]

616

1

T14

6

T39

1

T109

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4802

1

T2

4

T3

8

T4

1

auto[1]

528

1

T2

1

T13

2

T25

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4802

1

T2

4

T3

8

T4

1

auto[1]

528

1

T2

1

T13

2

T25

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	413	1			T2	1		T12	1		T39	1
auto[OpGenId]	1081	1			T2	1		T15	1		T39	1
auto[OpGenSwOut]	1144	1			T2	1		T4	1		T13	2
auto[OpGenHwOut]	2612	1			T2	2		T3	8		T13	5
auto[OpDisable]	80	1			T5	1		T42	1		T72	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	413	1			T2	1		T12	1		T39	1
auto[OpGenId]	1081	1			T2	1		T15	1		T39	1
auto[OpGenSwOut]	1144	1			T2	1		T4	1		T13	2
auto[OpGenHwOut]	2612	1			T2	2		T3	8		T13	5
auto[OpDisable]	80	1			T5	1		T42	1		T72	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4799

1

T2

5

T3

2

T4

1

auto[1]

531

1

T3

6

T13

2

T16

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4799

1

T2

5

T3

2

T4

1

auto[1]

531

1

T3

6

T13

2

T16

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5040

1

T2

5

T3

8

T4

1

auto[1]

290

1

T126

4

T157

3

T147

6

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1901	1			T2	1		T3	4		T4	1
auto[1]	664	1			T2	2		T3	3		T13	4
auto[2]	667	1			T13	2		T14	2		T16	2
auto[3]	715	1			T14	2		T39	1		T22	1
auto[4]	354	1			T2	1		T3	1		T16	1
auto[5]	315	1			T14	1		T15	1		T16	4
auto[6]	367	1			T22	1		T90	2		T5	1
auto[7]	347	1			T2	1		T90	1		T25	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1383	1			T2	2		T3	1		T14	1
clear_one[1]	664	1			T2	2		T3	3		T13	4
clear_one[2]	667	1			T13	2		T14	2		T16	2
clear_one[3]	715	1			T14	2		T39	1		T22	1
clear_none	1901	1			T2	1		T3	4		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1010	1			T13	3		T14	3		T16	3
auto[StInit]	645	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	569	1			T3	1		T12	1		T14	1
auto[StOwnerIntKey]	514	1			T2	1		T3	1		T14	1
auto[StOwnerKey]	483	1			T3	1		T13	1		T14	1
auto[StDisabled]	1828	1			T2	3		T3	4		T13	3
auto[StInvalid]	281	1			T32	1		T26	4		T44	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1010	1			T13	3		T14	3		T16	3
auto[StInit]	645	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	569	1			T3	1		T12	1		T14	1
auto[StOwnerIntKey]	514	1			T2	1		T3	1		T14	1
auto[StOwnerKey]	483	1			T3	1		T13	1		T14	1
auto[StDisabled]	1828	1			T2	3		T3	4		T13	3
auto[StInvalid]	281	1			T32	1		T26	4		T44	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[1] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[1] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T249	1		T250	1		T251	1
auto[0]	auto[StReset]	auto[OpGenId]	148	1			T144	1		T146	1		T48	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	156	1			T22	1		T25	1		T5	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	262	1			T13	1		T14	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T2	1		T25	1		T57	1
auto[0]	auto[StInit]	auto[OpGenId]	80	1			T15	1		T18	1		T110	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	107	1			T4	1		T136	1		T5	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	182	1			T3	1		T39	1		T90	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T12	1		T50	1		T252	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T57	1		T211	1		T253	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	56	1			T91	1		T5	1		T206	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	67	1			T3	1		T16	1		T109	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	19	1			T57	1		T126	1		T140	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	39	1			T39	1		T126	1		T64	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	38	1			T5	1		T145	1		T253	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	60	1			T5	1		T254	1		T59	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	14	1			T147	1		T54	1		T255	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T48	1		T50	1		T64	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T213	1		T64	1		T75	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	55	1			T14	1		T220	1		T256	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T39	1		T208	1		T257	1
auto[0]	auto[StDisabled]	auto[OpGenId]	66	1			T5	1		T140	1		T87	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T5	2		T48	2		T139	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	183	1			T3	2		T14	1		T5	1
auto[0]	auto[StDisabled]	auto[OpDisable]	34	1			T42	1		T72	1		T65	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	13	1			T97	2		T258	2		T259	1
auto[0]	auto[StInvalid]	auto[OpGenId]	23	1			T26	1		T46	1		T260	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	27	1			T32	1		T26	1		T100	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T44	1		T45	1		T46	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T84	1		T85	1		T60	2
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T44	1		T49	1		T124	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	57	1			T13	1		T14	1		T256	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T85	1		T58	1		T222	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T80	1		T261	1		T262	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T144	1		T124	1		T263	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	30	1			T14	1		T264	1		T265	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T266	1		T267	1		T268	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T135	1		T269	1		T270	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T84	1		T49	1		T271	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T264	1		T50	1		T209	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T5	1		T272	1		T273	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T206	1		T216	1		T274	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T124	1		T275	1		T200	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T3	1		T16	1		T220	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T82	1		T200	1		T276	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T84	1		T50	1		T119	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T277	1		T278	1		T279	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T13	1		T137	1		T143	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	17	1			T5	1		T134	1		T280	1
auto[1]	auto[StDisabled]	auto[OpGenId]	51	1			T2	1		T5	1		T139	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T13	2		T91	2		T140	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T2	1		T3	2		T14	1
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T281	1		T78	1		T282	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T283	1		T284	1		T285	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T259	1		T286	1		T287	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T288	1		T289	1		T290	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T98	2		T100	1		T92	1
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T50	1		T99	1		T291	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T50	1		T292	1		T58	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	48	1			T13	1		T5	1		T44	1
auto[2]	auto[StInit]	auto[OpAdvance]	11	1			T22	1		T157	3		T222	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T95	1		T234	1		T196	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T147	1		T104	1		T165	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T16	1		T22	1		T209	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T244	1		T293	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T210	1		T294	1		T147	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T48	1		T295	1		T124	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T14	1		T136	1		T56	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T296	1		T297	1		T298	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T93	1		T76	1		T78	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T299	1		T50	1		T280	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T300	1		T301	1		T48	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T91	1		T54	1		T302	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	17	1			T50	1		T64	1		T74	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T29	1		T209	2		T280	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T90	1		T5	1		T301	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	22	1			T206	1		T157	1		T54	1
auto[2]	auto[StDisabled]	auto[OpGenId]	47	1			T5	1		T210	1		T212	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T144	2		T253	1		T48	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T13	1		T14	1		T16	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T134	1		T303	1		T193	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	2	1			T289	1		T285	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T99	1		T304	1		T305	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T306	1		T287	1		T307	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T46	1		T308	1		T309	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T260	1		T216	1		T292	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T22	1		T209	1		T149	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	67	1			T90	1		T213	1		T310	1
auto[3]	auto[StInit]	auto[OpAdvance]	3	1			T24	1		T311	1		T245	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T84	1		T74	1		T201	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	9	1			T65	1		T50	1		T64	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T256	1		T219	1		T294	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T312	1		T313	1		T280	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T272	1		T314	1		T315	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T50	1		T316	1		T135	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T137	1		T67	1		T64	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T213	1		T104	1		T317	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T84	1		T58	1		T78	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T5	1		T208	1		T214	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T14	1		T90	1		T143	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T318	1		T270	1		-	-
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T211	1		T84	1		T319	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T5	1		T216	1		T320	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T39	1		T264	1		T321	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	27	1			T139	1		T88	1		T50	1
auto[3]	auto[StDisabled]	auto[OpGenId]	51	1			T5	2		T84	1		T66	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T136	1		T48	1		T322	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T14	1		T25	1		T5	2
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T5	1		T319	1		T200	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T44	1		T323	1		T284	1
auto[3]	auto[StInvalid]	auto[OpGenId]	15	1			T288	1		T260	1		T92	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T288	1		T98	1		T92	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T26	1		T44	1		T308	1
auto[4]	auto[StReset]	auto[OpGenId]	5	1			T73	1		T78	1		T234	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T54	1		T74	1		T95	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	19	1			T16	1		T49	1		T68	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T226	1		T324	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T24	1		T325	1		T242	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T208	1		T326	1		T241	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T54	1		T271	1		T95	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T74	1		T200	1		T78	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T5	1		T64	1		T54	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T275	1		T327	2		T328	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T329	1		T301	1		T330	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T331	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T147	1		T149	1		T249	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T2	1		T41	1		T147	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T332	1		T333	1		T334	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T331	1		T335	2		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T48	1		T41	1		T124	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T212	1		T302	1		T274	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T3	1		T221	1		T336	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	17	1			T5	1		T66	1		T67	1
auto[4]	auto[StDisabled]	auto[OpGenId]	22	1			T136	1		T67	1		T299	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T210	1		T110	1		T271	2
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T90	1		T137	1		T220	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T50	1		T326	1		T80	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T258	1		T337	1		T338	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T339	1		T340	1		T341	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T26	1		T260	1		T98	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T258	1		T98	1		T99	1
auto[5]	auto[StReset]	auto[OpGenId]	13	1			T271	1		T325	1		T342	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T289	1		T343	1		T102	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T14	1		T16	1		T254	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T344	2		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T105	1		T80	1		T262	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T200	1		T242	1		T345	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	6	1			T68	1		T124	1		T135	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T255	1		T224	1		T234	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T146	1		T98	1		T346	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T58	1		T347	1		T348	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	12	1			T143	1		T321	1		T349	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T350	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T68	1		T351	1		T196	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T15	1		T142	1		T172	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T109	1		T329	1		T264	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T352	1		T353	1		T96	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T66	1		T354	1		T355	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T5	2		T50	1		T149	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T16	1		T334	1		T229	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T136	1		T356	1		T149	2
auto[5]	auto[StDisabled]	auto[OpGenId]	18	1			T316	1		T357	1		T149	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T23	1		T64	1		T292	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T16	2		T5	1		T137	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T59	1		T49	1		T209	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T309	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T44	1		T97	1		T100	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T358	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T259	1		T94	1		T309	1
auto[6]	auto[StReset]	auto[OpAdvance]	2	1			T359	2		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T60	1		T222	1		T30	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T69	1		T54	1		T252	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	21	1			T254	1		T50	1		T336	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T360	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T361	1		T362	1		T363	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T22	1		T80	1		T241	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T330	1		T200	1		T364	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T124	1		T365	2		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T78	1		T366	1		T234	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T76	1		T317	1		T242	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T90	1		T256	1		T367	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T368	1		T369	2		T237	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T343	1		T370	1		T47	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T42	1		T212	1		T322	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T137	1		T221	1		T48	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T371	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T315	1		T372	1		T373	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T140	1		T207	1		T291	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T374	1		T200	1		T375	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	15	1			T68	1		T376	3		T355	1
auto[6]	auto[StDisabled]	auto[OpGenId]	41	1			T5	1		T146	1		T66	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T124	1		T316	1		T296	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T90	1		T143	1		T210	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T228	1		T377	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T378	1		T379	1		T380	1
auto[6]	auto[StInvalid]	auto[OpGenId]	10	1			T97	1		T289	1		T259	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T341	1		T287	1		T338	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T339	1		T341	1		T290	1
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T73	1		T159	1		T289	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	7	1			T348	1		T104	1		T80	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T256	1		T264	1		T330	1
auto[7]	auto[StInit]	auto[OpAdvance]	6	1			T164	1		T381	2		T382	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T91	1		T234	1		T383	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T42	1		T95	1		T384	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T300	1		T301	1		T385	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T381	1		T251	1		T359	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T299	1		T372	1		T373	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T5	1		T58	1		T357	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T219	1		T386	1		T387	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T217	1		T388	1		T389	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T50	1		T200	1		T30	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T248	1		T359	1		T390	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T50	1		T271	1		T124	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T228	1		T384	2		T328	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T209	1		T234	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T25	1		T5	1		T74	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T329	1		T158	1		T7	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	7	1			T84	1		T389	1		T384	3
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T392	1		T124	1		T255	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T5	2		T218	1		T213	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T2	1		T90	1		T143	2
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T393	1		T242	1		T371	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T288	2		T378	2		T394	1
auto[7]	auto[StInvalid]	auto[OpGenId]	1	1			T395	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T44	1		T379	1		T304	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T286	1		T287	1		T283	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1383

1

T2

2

T3

1

T14

1

clear_one[1]

auto[0]

auto[0]

auto[0]

414

1

T2

1

T13

1

T14

3

clear_one[1]

auto[0]

auto[0]

auto[1]

107

1

T3

3

T13

1

T16

2

clear_one[1]

auto[0]

auto[1]

auto[0]

107

1

T2

1

T13

2

T5

3

clear_one[1]

auto[0]

auto[1]

auto[1]

36

1

T5

1

T82

1

T209

2

clear_one[2]

auto[0]

auto[0]

auto[0]

370

1

T13

1

T16

1

T22

2

clear_one[2]

auto[0]

auto[0]

auto[1]

121

1

T13

1

T16

1

T90

1

clear_one[2]

auto[1]

auto[0]

auto[0]

134

1

T14

2

T39

1

T43

1

clear_one[2]

auto[1]

auto[0]

auto[1]

42

1

T5

1

T144

2

T253

1

clear_one[3]

auto[0]

auto[0]

auto[0]

420

1

T39

1

T22

1

T90

2

clear_one[3]

auto[0]

auto[1]

auto[0]

126

1

T5

2

T208

1

T220

1

clear_one[3]

auto[1]

auto[0]

auto[0]

142

1

T14

2

T137

2

T23

1

clear_one[3]

auto[1]

auto[1]

auto[0]

27

1

T25

1

T5

2

T84

1

clear_none

auto[0]

auto[0]

auto[0]

1331

1

T2

1

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

127

1

T3

3

T16

1

T39

1

clear_none

auto[0]

auto[1]

auto[0]

138

1

T208

2

T220

2

T219

2

clear_none

auto[0]

auto[1]

auto[1]

34

1

T91

1

T5

1

T209

1

clear_none

auto[1]

auto[0]

auto[0]

165

1

T14

2

T109

1

T137

1

clear_none

auto[1]

auto[0]

auto[1]

46

1

T68

1

T252

1

T134

1

clear_none

auto[1]

auto[1]

auto[0]

42

1

T212

1

T48

1

T352

1

clear_none

auto[1]

auto[1]

auto[1]

18

1

T5

1

T257

2

T64

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1280	1			T2	2		T3	1		T14	1
clear_all	auto[1]	103	1			T147	1		T149	5		T327	4
clear_one[1]	auto[0]	640	1			T2	2		T3	3		T13	4
clear_one[1]	auto[1]	24	1			T276	2		T396	4		T369	3
clear_one[2]	auto[0]	630	1			T13	2		T14	2		T16	2
clear_one[2]	auto[1]	37	1			T157	3		T147	2		T356	3
clear_one[3]	auto[0]	693	1			T14	2		T39	1		T22	1
clear_one[3]	auto[1]	22	1			T276	1		T397	1		T398	7
clear_none	auto[0]	1797	1			T2	1		T3	4		T4	1
clear_none	auto[1]	104	1			T126	4		T147	3		T148	1