Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11071

1

T1

6

T2

5

T3

2

auto[Attestation]

7641

1

T1

1

T2

15

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2812	1			T2	3		T4	1		T12	3
auto[Aes]	3453	1			T2	3		T12	4		T13	5
auto[Kmac]	3310	1			T1	2		T2	6		T4	2
auto[Otbn]	3294	1			T1	1		T2	2		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7628	1			T1	1		T2	8		T3	8
auto[OpGenId]	5843	1			T1	4		T2	6		T13	2
auto[OpGenSwOut]	5768	1			T1	2		T2	7		T4	1
auto[OpGenHwOut]	7101	1			T1	1		T2	7		T3	8
auto[OpDisable]	143	1			T5	2		T42	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10621

1

T1

1

T2

16

T3

8

auto[OpDoneFail]

15862

1

T1

7

T2

12

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6429	1			T1	7		T2	1		T3	1
auto[StInit]	3724	1			T1	1		T2	1		T3	2
auto[StCreatorRootKey]	3227	1			T2	6		T3	2		T4	4
auto[StOwnerIntKey]	2724	1			T2	3		T3	2		T12	1
auto[StOwnerKey]	2443	1			T2	5		T3	2		T12	5
auto[StDisabled]	7936	1			T2	12		T3	7		T13	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	300	1			T22	2		T91	1		T144	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	103	1			T4	1		T5	4		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T17	1		T91	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	73	1			T15	1		T91	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T25	1		T5	3		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	212	1			T39	1		T136	1		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	321	1			T13	1		T22	2		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T12	1		T32	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T91	1		T208	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	79	1			T2	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T5	1		T65	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	247	1			T89	1		T91	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	317	1			T1	2		T13	1		T22	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	93	1			T22	1		T5	2		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T25	1		T210	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T39	1		T33	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T25	1		T83	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	217	1			T89	1		T136	1		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	277	1			T13	2		T22	1		T146	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	95	1			T22	1		T136	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T17	1		T33	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T91	1		T5	3		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	51	1			T136	1		T5	3		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	204	1			T25	1		T91	2		T5	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	88	1			T5	2		T48	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T12	1		T17	2		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	97	1			T2	1		T5	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	87	1			T136	2		T5	3		T145	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T208	1		T140	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	226	1			T2	1		T13	1		T136	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	60	1			T5	2		T64	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	94	1			T17	1		T136	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	90	1			T2	1		T5	3		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T5	3		T208	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	60	1			T5	1		T144	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	213	1			T39	1		T91	2		T5	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T5	2		T48	5		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	81	1			T12	1		T17	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T17	1		T5	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	54	1			T39	1		T5	1		T144	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T2	2		T25	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	185	1			T13	1		T25	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T5	2		T48	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	91	1			T22	1		T136	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T5	2		T48	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T42	1		T37	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T214	1		T215	1		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	214	1			T2	1		T91	1		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	304	1			T13	1		T145	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	101	1			T39	1		T22	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T33	1		T56	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T15	1		T5	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T17	1		T211	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	178	1			T39	1		T25	1		T91	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	501	1			T13	3		T14	4		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	114	1			T14	1		T26	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	113	1			T109	1		T217	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	106	1			T14	1		T136	1		T144	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	88	1			T12	2		T14	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	300	1			T2	1		T14	2		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	495	1			T210	1		T219	7		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T22	2		T33	1		T5	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T4	1		T136	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T220	1		T219	1		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	93	1			T13	1		T109	2		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	255	1			T2	2		T5	4		T145	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	461	1			T1	1		T13	2		T16	6
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T16	1		T22	2		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T3	1		T4	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T3	1		T15	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	74	1			T17	1		T90	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	287	1			T13	1		T16	3		T90	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T5	1		T64	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	96	1			T12	2		T13	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T211	1		T157	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T91	1		T5	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T2	1		T208	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	210	1			T5	2		T144	1		T146	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T5	5		T64	4		T124	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	109	1			T18	1		T136	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	104	1			T14	1		T136	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	79	1			T109	1		T5	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	93	1			T12	1		T17	1		T146	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	276	1			T14	2		T39	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	60	1			T5	1		T48	1		T222	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T32	1		T220	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T2	1		T4	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T136	1		T48	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T12	1		T17	2		T109	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	284	1			T2	1		T25	1		T5	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	78	1			T5	3		T48	2		T64	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T3	1		T5	1		T143	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	132	1			T2	1		T4	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T16	1		T90	1		T146	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T3	1		T12	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	288	1			T3	4		T16	1		T90	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	188	1			T15	1		T17	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	637	1			T4	1		T39	1		T22	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	219	1			T2	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	692	1			T12	1		T13	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	214	1			T39	1		T33	1		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	643	1			T1	2		T13	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	177	1			T17	1		T33	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	590	1			T13	2		T22	2		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	221	1			T2	1		T136	2		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	446	1			T2	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	198	1			T2	1		T5	6		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	387	1			T17	1		T39	1		T91	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	185	1			T2	2		T17	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	359	1			T12	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T5	1		T42	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	407	1			T2	1		T22	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	162	1			T15	1		T17	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	599	1			T13	1		T39	2		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	295	1			T12	2		T14	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	927	1			T2	1		T13	3		T14	7
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	273	1			T4	1		T13	1		T109	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	885	1			T2	2		T22	2		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	255	1			T3	2		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	884	1			T1	1		T13	3		T16	10
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	180	1			T2	1		T91	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	379	1			T12	2		T13	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	259	1			T12	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T14	2		T39	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	259	1			T2	1		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	492	1			T2	1		T32	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	500	1			T3	5		T16	1		T90	1