Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32524

1

T1

8

T2

32

T3

19

auto[1]

288

1

T126

6

T157

2

T158

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32531	1			T1	8		T2	32		T3	19
auto[134217728:268435455]	11	1			T327	1		T331	1		T276	1
auto[268435456:402653183]	12	1			T327	1		T255	1		T335	1
auto[402653184:536870911]	10	1			T149	2		T327	1		T311	2
auto[536870912:671088639]	11	1			T398	1		T311	3		T298	1
auto[671088640:805306367]	4	1			T126	1		T356	1		T384	1
auto[805306368:939524095]	12	1			T147	2		T148	1		T276	1
auto[939524096:1073741823]	10	1			T126	1		T331	1		T376	1
auto[1073741824:1207959551]	11	1			T149	1		T327	2		T398	1
auto[1207959552:1342177279]	7	1			T376	1		T369	1		T298	1
auto[1342177280:1476395007]	12	1			T126	1		T327	1		T398	1
auto[1476395008:1610612735]	1	1			T355	1		-	-		-	-
auto[1610612736:1744830463]	7	1			T327	1		T331	1		T297	1
auto[1744830464:1879048191]	10	1			T126	1		T157	1		T148	1
auto[1879048192:2013265919]	11	1			T327	1		T355	1		T369	1
auto[2013265920:2147483647]	9	1			T147	1		T419	1		T396	1
auto[2147483648:2281701375]	4	1			T331	1		T398	1		T420	1
auto[2281701376:2415919103]	5	1			T315	1		T421	1		T311	1
auto[2415919104:2550136831]	8	1			T331	1		T376	1		T255	1
auto[2550136832:2684354559]	14	1			T157	1		T147	1		T384	1
auto[2684354560:2818572287]	8	1			T158	1		T327	1		T331	1
auto[2818572288:2952790015]	9	1			T327	1		T369	1		T297	1
auto[2952790016:3087007743]	9	1			T149	1		T327	1		T376	1
auto[3087007744:3221225471]	9	1			T327	2		T376	1		T396	1
auto[3221225472:3355443199]	6	1			T327	1		T381	1		T251	1
auto[3355443200:3489660927]	13	1			T158	1		T331	1		T376	2
auto[3489660928:3623878655]	10	1			T148	1		T327	1		T422	2
auto[3623878656:3758096383]	12	1			T126	1		T376	1		T255	1
auto[3758096384:3892314111]	10	1			T149	1		T327	1		T255	1
auto[3892314112:4026531839]	6	1			T356	1		T335	1		T298	1
auto[4026531840:4160749567]	12	1			T126	1		T384	1		T355	2
auto[4160749568:4294967295]	8	1			T376	2		T423	1		T424	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32524	1			T1	8		T2	32		T3	19
auto[0:134217727]	auto[1]	7	1			T147	1		T335	1		T298	1
auto[134217728:268435455]	auto[1]	11	1			T327	1		T331	1		T276	1
auto[268435456:402653183]	auto[1]	12	1			T327	1		T255	1		T335	1
auto[402653184:536870911]	auto[1]	10	1			T149	2		T327	1		T311	2
auto[536870912:671088639]	auto[1]	11	1			T398	1		T311	3		T298	1
auto[671088640:805306367]	auto[1]	4	1			T126	1		T356	1		T384	1
auto[805306368:939524095]	auto[1]	12	1			T147	2		T148	1		T276	1
auto[939524096:1073741823]	auto[1]	10	1			T126	1		T331	1		T376	1
auto[1073741824:1207959551]	auto[1]	11	1			T149	1		T327	2		T398	1
auto[1207959552:1342177279]	auto[1]	7	1			T376	1		T369	1		T298	1
auto[1342177280:1476395007]	auto[1]	12	1			T126	1		T327	1		T398	1
auto[1476395008:1610612735]	auto[1]	1	1			T355	1		-	-		-	-
auto[1610612736:1744830463]	auto[1]	7	1			T327	1		T331	1		T297	1
auto[1744830464:1879048191]	auto[1]	10	1			T126	1		T157	1		T148	1
auto[1879048192:2013265919]	auto[1]	11	1			T327	1		T355	1		T369	1
auto[2013265920:2147483647]	auto[1]	9	1			T147	1		T419	1		T396	1
auto[2147483648:2281701375]	auto[1]	4	1			T331	1		T398	1		T420	1
auto[2281701376:2415919103]	auto[1]	5	1			T315	1		T421	1		T311	1
auto[2415919104:2550136831]	auto[1]	8	1			T331	1		T376	1		T255	1
auto[2550136832:2684354559]	auto[1]	14	1			T157	1		T147	1		T384	1
auto[2684354560:2818572287]	auto[1]	8	1			T158	1		T327	1		T331	1
auto[2818572288:2952790015]	auto[1]	9	1			T327	1		T369	1		T297	1
auto[2952790016:3087007743]	auto[1]	9	1			T149	1		T327	1		T376	1
auto[3087007744:3221225471]	auto[1]	9	1			T327	2		T376	1		T396	1
auto[3221225472:3355443199]	auto[1]	6	1			T327	1		T381	1		T251	1
auto[3355443200:3489660927]	auto[1]	13	1			T158	1		T331	1		T376	2
auto[3489660928:3623878655]	auto[1]	10	1			T148	1		T327	1		T422	2
auto[3623878656:3758096383]	auto[1]	12	1			T126	1		T376	1		T255	1
auto[3758096384:3892314111]	auto[1]	10	1			T149	1		T327	1		T255	1
auto[3892314112:4026531839]	auto[1]	6	1			T356	1		T335	1		T298	1
auto[4026531840:4160749567]	auto[1]	12	1			T126	1		T384	1		T355	2
auto[4160749568:4294967295]	auto[1]	8	1			T376	2		T423	1		T424	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1606

1

T2

3

T4

2

T12

1

auto[1]

1776

1

T2

4

T12

2

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T17	1		T39	1		T26	1
auto[134217728:268435455]	112	1			T26	1		T45	1		T48	1
auto[268435456:402653183]	122	1			T15	1		T26	1		T210	1
auto[402653184:536870911]	79	1			T109	1		T5	1		T20	1
auto[536870912:671088639]	111	1			T4	1		T5	1		T6	1
auto[671088640:805306367]	93	1			T15	1		T22	1		T5	3
auto[805306368:939524095]	101	1			T32	1		T26	1		T5	2
auto[939524096:1073741823]	124	1			T18	1		T5	2		T144	1
auto[1073741824:1207959551]	105	1			T136	1		T5	1		T57	1
auto[1207959552:1342177279]	105	1			T32	1		T5	2		T126	1
auto[1342177280:1476395007]	126	1			T18	1		T5	1		T144	1
auto[1476395008:1610612735]	109	1			T91	2		T5	1		T46	1
auto[1610612736:1744830463]	95	1			T2	1		T5	2		T211	1
auto[1744830464:1879048191]	106	1			T5	1		T206	1		T57	1
auto[1879048192:2013265919]	109	1			T2	2		T91	1		T5	2
auto[2013265920:2147483647]	111	1			T32	1		T22	1		T109	1
auto[2147483648:2281701375]	94	1			T2	1		T15	1		T211	1
auto[2281701376:2415919103]	99	1			T26	1		T5	2		T206	1
auto[2415919104:2550136831]	123	1			T22	1		T5	1		T34	1
auto[2550136832:2684354559]	117	1			T91	1		T5	1		T206	1
auto[2684354560:2818572287]	107	1			T5	2		T126	1		T23	1
auto[2818572288:2952790015]	98	1			T32	1		T22	1		T5	2
auto[2952790016:3087007743]	122	1			T25	2		T26	1		T48	2
auto[3087007744:3221225471]	93	1			T82	1		T322	1		T97	1
auto[3221225472:3355443199]	99	1			T5	2		T144	1		T57	1
auto[3355443200:3489660927]	89	1			T2	1		T109	1		T26	1
auto[3489660928:3623878655]	112	1			T32	1		T25	1		T5	1
auto[3623878656:3758096383]	101	1			T5	1		T45	1		T48	1
auto[3758096384:3892314111]	110	1			T12	1		T5	1		T6	1
auto[3892314112:4026531839]	101	1			T2	2		T4	1		T12	1
auto[4026531840:4160749567]	109	1			T39	1		T22	1		T5	5
auto[4160749568:4294967295]	111	1			T12	1		T5	1		T217	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T17	1		T26	1		T5	1
auto[0:134217727]	auto[1]	43	1			T39	1		T5	1		T44	1
auto[134217728:268435455]	auto[0]	60	1			T45	1		T84	1		T46	1
auto[134217728:268435455]	auto[1]	52	1			T26	1		T48	1		T140	1
auto[268435456:402653183]	auto[0]	56	1			T26	1		T87	1		T60	1
auto[268435456:402653183]	auto[1]	66	1			T15	1		T210	1		T209	1
auto[402653184:536870911]	auto[0]	37	1			T48	1		T215	1		T24	1
auto[402653184:536870911]	auto[1]	42	1			T109	1		T5	1		T20	1
auto[536870912:671088639]	auto[0]	53	1			T4	1		T6	1		T64	1
auto[536870912:671088639]	auto[1]	58	1			T5	1		T82	1		T288	1
auto[671088640:805306367]	auto[0]	40	1			T15	1		T5	1		T139	1
auto[671088640:805306367]	auto[1]	53	1			T22	1		T5	2		T56	1
auto[805306368:939524095]	auto[0]	44	1			T32	1		T5	1		T65	1
auto[805306368:939524095]	auto[1]	57	1			T26	1		T5	1		T144	1
auto[939524096:1073741823]	auto[0]	50	1			T18	1		T5	1		T144	1
auto[939524096:1073741823]	auto[1]	74	1			T5	1		T253	1		T72	1
auto[1073741824:1207959551]	auto[0]	48	1			T5	1		T44	1		T84	1
auto[1073741824:1207959551]	auto[1]	57	1			T136	1		T57	1		T42	1
auto[1207959552:1342177279]	auto[0]	61	1			T32	1		T5	1		T126	1
auto[1207959552:1342177279]	auto[1]	44	1			T5	1		T82	1		T213	1
auto[1342177280:1476395007]	auto[0]	62	1			T19	1		T87	1		T64	1
auto[1342177280:1476395007]	auto[1]	64	1			T18	1		T5	1		T144	1
auto[1476395008:1610612735]	auto[0]	48	1			T5	1		T85	1		T49	1
auto[1476395008:1610612735]	auto[1]	61	1			T91	2		T46	1		T257	1
auto[1610612736:1744830463]	auto[0]	43	1			T2	1		T59	1		T85	1
auto[1610612736:1744830463]	auto[1]	52	1			T5	2		T211	1		T23	1
auto[1744830464:1879048191]	auto[0]	50	1			T206	1		T43	1		T157	1
auto[1744830464:1879048191]	auto[1]	56	1			T5	1		T57	1		T211	1
auto[1879048192:2013265919]	auto[0]	42	1			T5	1		T146	1		T45	1
auto[1879048192:2013265919]	auto[1]	67	1			T2	2		T91	1		T5	1
auto[2013265920:2147483647]	auto[0]	54	1			T32	1		T109	1		T5	2
auto[2013265920:2147483647]	auto[1]	57	1			T22	1		T91	1		T146	1
auto[2147483648:2281701375]	auto[0]	46	1			T69	1		T258	1		T24	1
auto[2147483648:2281701375]	auto[1]	48	1			T2	1		T15	1		T211	1
auto[2281701376:2415919103]	auto[0]	49	1			T26	1		T211	1		T44	1
auto[2281701376:2415919103]	auto[1]	50	1			T5	2		T206	1		T253	1
auto[2415919104:2550136831]	auto[0]	61	1			T217	1		T87	1		T97	1
auto[2415919104:2550136831]	auto[1]	62	1			T22	1		T5	1		T34	1
auto[2550136832:2684354559]	auto[0]	54	1			T5	1		T206	1		T257	1
auto[2550136832:2684354559]	auto[1]	63	1			T91	1		T208	1		T48	1
auto[2684354560:2818572287]	auto[0]	50	1			T5	1		T84	1		T213	1
auto[2684354560:2818572287]	auto[1]	57	1			T5	1		T126	1		T23	1
auto[2818572288:2952790015]	auto[0]	48	1			T5	1		T144	1		T146	1
auto[2818572288:2952790015]	auto[1]	50	1			T32	1		T22	1		T5	1
auto[2952790016:3087007743]	auto[0]	62	1			T25	1		T48	1		T209	1
auto[2952790016:3087007743]	auto[1]	60	1			T25	1		T26	1		T48	1
auto[3087007744:3221225471]	auto[0]	46	1			T97	1		T64	1		T209	1
auto[3087007744:3221225471]	auto[1]	47	1			T82	1		T322	1		T67	1
auto[3221225472:3355443199]	auto[0]	52	1			T5	1		T144	1		T57	1
auto[3221225472:3355443199]	auto[1]	47	1			T5	1		T42	1		T99	1
auto[3355443200:3489660927]	auto[0]	36	1			T109	1		T26	1		T59	1
auto[3355443200:3489660927]	auto[1]	53	1			T2	1		T140	1		T213	1
auto[3489660928:3623878655]	auto[0]	60	1			T32	1		T146	1		T19	1
auto[3489660928:3623878655]	auto[1]	52	1			T25	1		T5	1		T144	1
auto[3623878656:3758096383]	auto[0]	44	1			T5	1		T84	1		T69	1
auto[3623878656:3758096383]	auto[1]	57	1			T45	1		T48	1		T35	1
auto[3758096384:3892314111]	auto[0]	55	1			T12	1		T6	1		T110	1
auto[3758096384:3892314111]	auto[1]	55	1			T5	1		T67	3		T50	1
auto[3892314112:4026531839]	auto[0]	52	1			T2	2		T4	1		T15	1
auto[3892314112:4026531839]	auto[1]	49	1			T12	1		T23	1		T48	1
auto[4026531840:4160749567]	auto[0]	56	1			T22	1		T5	1		T146	1
auto[4026531840:4160749567]	auto[1]	53	1			T39	1		T5	4		T56	1
auto[4160749568:4294967295]	auto[0]	41	1			T65	1		T158	1		T68	1
auto[4160749568:4294967295]	auto[1]	70	1			T12	1		T5	1		T217	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1591

1

T2

4

T4

2

T12

1

auto[1]

1793

1

T2

3

T12

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T91	1		T5	1		T146	1
auto[134217728:268435455]	96	1			T2	1		T12	1		T5	2
auto[268435456:402653183]	93	1			T4	1		T26	1		T91	1
auto[402653184:536870911]	114	1			T22	1		T26	1		T5	1
auto[536870912:671088639]	111	1			T32	1		T18	1		T136	1
auto[671088640:805306367]	113	1			T2	2		T39	1		T26	1
auto[805306368:939524095]	105	1			T26	1		T5	1		T44	1
auto[939524096:1073741823]	112	1			T91	1		T5	1		T56	1
auto[1073741824:1207959551]	117	1			T2	1		T15	1		T39	1
auto[1207959552:1342177279]	123	1			T4	1		T32	1		T25	1
auto[1342177280:1476395007]	91	1			T22	1		T5	2		T84	1
auto[1476395008:1610612735]	95	1			T5	1		T217	1		T253	1
auto[1610612736:1744830463]	111	1			T5	1		T19	1		T66	1
auto[1744830464:1879048191]	119	1			T17	1		T91	1		T5	1
auto[1879048192:2013265919]	109	1			T22	1		T109	1		T25	1
auto[2013265920:2147483647]	98	1			T32	1		T5	1		T23	1
auto[2147483648:2281701375]	104	1			T15	1		T22	1		T5	1
auto[2281701376:2415919103]	99	1			T5	1		T322	1		T207	2
auto[2415919104:2550136831]	102	1			T15	1		T5	1		T144	1
auto[2550136832:2684354559]	87	1			T12	1		T44	1		T126	1
auto[2684354560:2818572287]	104	1			T5	3		T144	1		T210	1
auto[2818572288:2952790015]	107	1			T5	2		T144	1		T48	1
auto[2952790016:3087007743]	117	1			T26	2		T18	1		T6	1
auto[3087007744:3221225471]	119	1			T2	2		T15	1		T5	3
auto[3221225472:3355443199]	110	1			T91	1		T5	2		T48	1
auto[3355443200:3489660927]	96	1			T12	1		T146	1		T44	1
auto[3489660928:3623878655]	92	1			T26	1		T5	1		T206	1
auto[3623878656:3758096383]	122	1			T109	2		T25	1		T5	2
auto[3758096384:3892314111]	118	1			T2	1		T32	2		T5	1
auto[3892314112:4026531839]	117	1			T5	2		T57	2		T23	1
auto[4026531840:4160749567]	96	1			T5	2		T56	1		T44	1
auto[4160749568:4294967295]	96	1			T5	2		T144	2		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T146	1		T43	1		T84	1
auto[0:134217727]	auto[1]	48	1			T91	1		T5	1		T42	1
auto[134217728:268435455]	auto[0]	45	1			T5	2		T294	1		T99	1
auto[134217728:268435455]	auto[1]	51	1			T2	1		T12	1		T211	1
auto[268435456:402653183]	auto[0]	40	1			T4	1		T6	1		T59	1
auto[268435456:402653183]	auto[1]	53	1			T26	1		T91	1		T146	1
auto[402653184:536870911]	auto[0]	60	1			T26	1		T5	1		T146	1
auto[402653184:536870911]	auto[1]	54	1			T22	1		T144	1		T48	1
auto[536870912:671088639]	auto[0]	57	1			T32	1		T5	2		T44	1
auto[536870912:671088639]	auto[1]	54	1			T18	1		T136	1		T217	1
auto[671088640:805306367]	auto[0]	59	1			T2	2		T34	1		T110	1
auto[671088640:805306367]	auto[1]	54	1			T39	1		T26	1		T212	1
auto[805306368:939524095]	auto[0]	48	1			T26	1		T64	1		T209	2
auto[805306368:939524095]	auto[1]	57	1			T5	1		T44	1		T48	1
auto[939524096:1073741823]	auto[0]	58	1			T91	1		T5	1		T206	1
auto[939524096:1073741823]	auto[1]	54	1			T56	1		T253	1		T44	1
auto[1073741824:1207959551]	auto[0]	50	1			T22	1		T5	1		T45	1
auto[1073741824:1207959551]	auto[1]	67	1			T2	1		T15	1		T39	1
auto[1207959552:1342177279]	auto[0]	63	1			T4	1		T32	1		T88	1
auto[1207959552:1342177279]	auto[1]	60	1			T25	1		T56	1		T46	1
auto[1342177280:1476395007]	auto[0]	50	1			T5	1		T84	1		T59	1
auto[1342177280:1476395007]	auto[1]	41	1			T22	1		T5	1		T64	1
auto[1476395008:1610612735]	auto[0]	40	1			T217	1		T139	1		T88	1
auto[1476395008:1610612735]	auto[1]	55	1			T5	1		T253	1		T126	1
auto[1610612736:1744830463]	auto[0]	63	1			T19	1		T66	1		T157	1
auto[1610612736:1744830463]	auto[1]	48	1			T5	1		T260	1		T50	1
auto[1744830464:1879048191]	auto[0]	64	1			T17	1		T208	1		T217	1
auto[1744830464:1879048191]	auto[1]	55	1			T91	1		T5	1		T211	1
auto[1879048192:2013265919]	auto[0]	40	1			T109	1		T146	1		T23	1
auto[1879048192:2013265919]	auto[1]	69	1			T22	1		T25	1		T5	1
auto[2013265920:2147483647]	auto[0]	53	1			T32	1		T23	1		T160	1
auto[2013265920:2147483647]	auto[1]	45	1			T5	1		T260	1		T50	1
auto[2147483648:2281701375]	auto[0]	42	1			T5	1		T19	1		T157	1
auto[2147483648:2281701375]	auto[1]	62	1			T15	1		T22	1		T211	1
auto[2281701376:2415919103]	auto[0]	41	1			T207	1		T54	1		T7	1
auto[2281701376:2415919103]	auto[1]	58	1			T5	1		T322	1		T207	1
auto[2415919104:2550136831]	auto[0]	46	1			T144	1		T110	1		T100	1
auto[2415919104:2550136831]	auto[1]	56	1			T15	1		T5	1		T206	1
auto[2550136832:2684354559]	auto[0]	46	1			T44	1		T45	1		T84	1
auto[2550136832:2684354559]	auto[1]	41	1			T12	1		T126	1		T87	2
auto[2684354560:2818572287]	auto[0]	46	1			T5	1		T144	1		T49	1
auto[2684354560:2818572287]	auto[1]	58	1			T5	2		T210	1		T64	1
auto[2818572288:2952790015]	auto[0]	42	1			T5	1		T139	1		T46	1
auto[2818572288:2952790015]	auto[1]	65	1			T5	1		T144	1		T48	1
auto[2952790016:3087007743]	auto[0]	53	1			T26	1		T18	1		T6	1
auto[2952790016:3087007743]	auto[1]	64	1			T26	1		T43	1		T48	1
auto[3087007744:3221225471]	auto[0]	48	1			T2	1		T15	1		T5	1
auto[3087007744:3221225471]	auto[1]	71	1			T2	1		T5	2		T48	1
auto[3221225472:3355443199]	auto[0]	42	1			T48	1		T209	1		T266	1
auto[3221225472:3355443199]	auto[1]	68	1			T91	1		T5	2		T84	1
auto[3355443200:3489660927]	auto[0]	45	1			T12	1		T146	1		T44	1
auto[3355443200:3489660927]	auto[1]	51	1			T140	1		T87	1		T288	1
auto[3489660928:3623878655]	auto[0]	33	1			T26	1		T46	1		T69	1
auto[3489660928:3623878655]	auto[1]	59	1			T5	1		T206	1		T64	1
auto[3623878656:3758096383]	auto[0]	60	1			T25	1		T5	1		T69	1
auto[3623878656:3758096383]	auto[1]	62	1			T109	2		T5	1		T110	1
auto[3758096384:3892314111]	auto[0]	64	1			T2	1		T32	1		T84	1
auto[3758096384:3892314111]	auto[1]	54	1			T32	1		T5	1		T72	1
auto[3892314112:4026531839]	auto[0]	57	1			T5	1		T260	1		T64	1
auto[3892314112:4026531839]	auto[1]	60	1			T5	1		T57	2		T23	1
auto[4026531840:4160749567]	auto[0]	52	1			T322	1		T67	1		T299	1
auto[4026531840:4160749567]	auto[1]	44	1			T5	2		T56	1		T44	1
auto[4160749568:4294967295]	auto[0]	41	1			T144	1		T48	1		T312	1
auto[4160749568:4294967295]	auto[1]	55	1			T5	2		T144	1		T57	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1611

1

T2

2

T4

2

T15

2

auto[1]

1771

1

T2

5

T12

3

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T15	1		T17	1		T25	1
auto[134217728:268435455]	112	1			T2	1		T22	1		T5	1
auto[268435456:402653183]	94	1			T5	1		T146	1		T211	1
auto[402653184:536870911]	106	1			T12	1		T91	1		T18	1
auto[536870912:671088639]	115	1			T25	1		T5	1		T44	1
auto[671088640:805306367]	113	1			T34	1		T44	1		T48	2
auto[805306368:939524095]	99	1			T32	1		T26	1		T57	1
auto[939524096:1073741823]	91	1			T57	1		T44	1		T82	1
auto[1073741824:1207959551]	87	1			T2	1		T26	1		T5	1
auto[1207959552:1342177279]	121	1			T15	1		T22	1		T26	1
auto[1342177280:1476395007]	99	1			T32	2		T208	1		T253	1
auto[1476395008:1610612735]	103	1			T109	1		T5	1		T253	1
auto[1610612736:1744830463]	104	1			T39	1		T32	1		T26	1
auto[1744830464:1879048191]	110	1			T22	1		T5	2		T206	2
auto[1879048192:2013265919]	112	1			T12	1		T15	1		T39	1
auto[2013265920:2147483647]	101	1			T2	1		T4	1		T5	1
auto[2147483648:2281701375]	106	1			T12	1		T5	1		T146	1
auto[2281701376:2415919103]	95	1			T5	2		T44	1		T60	1
auto[2415919104:2550136831]	120	1			T109	1		T5	1		T206	1
auto[2550136832:2684354559]	119	1			T26	1		T91	1		T5	2
auto[2684354560:2818572287]	96	1			T18	1		T5	3		T146	1
auto[2818572288:2952790015]	99	1			T15	1		T26	1		T5	2
auto[2952790016:3087007743]	106	1			T109	1		T5	2		T144	2
auto[3087007744:3221225471]	111	1			T144	1		T146	1		T45	2
auto[3221225472:3355443199]	96	1			T2	1		T25	1		T26	1
auto[3355443200:3489660927]	117	1			T5	2		T23	1		T48	1
auto[3489660928:3623878655]	103	1			T5	3		T48	1		T139	1
auto[3623878656:3758096383]	109	1			T4	1		T32	1		T22	1
auto[3758096384:3892314111]	100	1			T22	1		T5	2		T208	1
auto[3892314112:4026531839]	103	1			T2	3		T5	5		T144	1
auto[4026531840:4160749567]	102	1			T5	1		T146	1		T210	1
auto[4160749568:4294967295]	113	1			T5	1		T19	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T17	1		T5	1		T210	1
auto[0:134217727]	auto[1]	65	1			T15	1		T25	1		T91	2
auto[134217728:268435455]	auto[0]	53	1			T85	1		T60	1		T66	1
auto[134217728:268435455]	auto[1]	59	1			T2	1		T22	1		T5	1
auto[268435456:402653183]	auto[0]	41	1			T146	1		T157	1		T54	1
auto[268435456:402653183]	auto[1]	53	1			T5	1		T211	1		T139	1
auto[402653184:536870911]	auto[0]	49	1			T91	1		T217	1		T45	1
auto[402653184:536870911]	auto[1]	57	1			T12	1		T18	1		T136	1
auto[536870912:671088639]	auto[0]	59	1			T25	1		T44	1		T46	1
auto[536870912:671088639]	auto[1]	56	1			T5	1		T126	1		T84	1
auto[671088640:805306367]	auto[0]	53	1			T44	1		T110	1		T69	1
auto[671088640:805306367]	auto[1]	60	1			T34	1		T48	2		T65	1
auto[805306368:939524095]	auto[0]	45	1			T32	1		T26	1		T215	1
auto[805306368:939524095]	auto[1]	54	1			T57	1		T211	1		T20	1
auto[939524096:1073741823]	auto[0]	39	1			T95	1		T425	1		T96	1
auto[939524096:1073741823]	auto[1]	52	1			T57	1		T44	1		T82	1
auto[1073741824:1207959551]	auto[0]	43	1			T87	1		T257	1		T207	1
auto[1073741824:1207959551]	auto[1]	44	1			T2	1		T26	1		T5	1
auto[1207959552:1342177279]	auto[0]	57	1			T15	1		T22	1		T139	1
auto[1207959552:1342177279]	auto[1]	64	1			T26	1		T5	1		T19	1
auto[1342177280:1476395007]	auto[0]	46	1			T32	2		T59	1		T209	1
auto[1342177280:1476395007]	auto[1]	53	1			T208	1		T253	1		T42	1
auto[1476395008:1610612735]	auto[0]	48	1			T45	1		T84	1		T209	1
auto[1476395008:1610612735]	auto[1]	55	1			T109	1		T5	1		T253	1
auto[1610612736:1744830463]	auto[0]	52	1			T26	1		T5	1		T146	1
auto[1610612736:1744830463]	auto[1]	52	1			T39	1		T32	1		T57	1
auto[1744830464:1879048191]	auto[0]	50	1			T22	1		T5	1		T217	1
auto[1744830464:1879048191]	auto[1]	60	1			T5	1		T206	2		T23	1
auto[1879048192:2013265919]	auto[0]	51	1			T15	1		T5	1		T6	1
auto[1879048192:2013265919]	auto[1]	61	1			T12	1		T39	1		T29	1
auto[2013265920:2147483647]	auto[0]	43	1			T4	1		T5	1		T126	1
auto[2013265920:2147483647]	auto[1]	58	1			T2	1		T48	1		T260	1
auto[2147483648:2281701375]	auto[0]	44	1			T44	1		T69	1		T257	1
auto[2147483648:2281701375]	auto[1]	62	1			T12	1		T5	1		T146	1
auto[2281701376:2415919103]	auto[0]	44	1			T5	1		T44	1		T209	1
auto[2281701376:2415919103]	auto[1]	51	1			T5	1		T60	1		T35	1
auto[2415919104:2550136831]	auto[0]	66	1			T109	1		T5	1		T206	1
auto[2415919104:2550136831]	auto[1]	54	1			T212	1		T319	1		T354	1
auto[2550136832:2684354559]	auto[0]	52	1			T26	1		T5	1		T144	1
auto[2550136832:2684354559]	auto[1]	67	1			T91	1		T5	1		T212	1
auto[2684354560:2818572287]	auto[0]	51	1			T18	1		T213	1		T426	1
auto[2684354560:2818572287]	auto[1]	45	1			T5	3		T146	1		T23	1
auto[2818572288:2952790015]	auto[0]	50	1			T26	1		T5	1		T49	1
auto[2818572288:2952790015]	auto[1]	49	1			T15	1		T5	1		T144	1
auto[2952790016:3087007743]	auto[0]	54	1			T5	1		T144	1		T139	1
auto[2952790016:3087007743]	auto[1]	52	1			T109	1		T5	1		T144	1
auto[3087007744:3221225471]	auto[0]	55	1			T144	1		T45	1		T97	1
auto[3087007744:3221225471]	auto[1]	56	1			T146	1		T45	1		T260	1
auto[3221225472:3355443199]	auto[0]	48	1			T2	1		T25	1		T43	1
auto[3221225472:3355443199]	auto[1]	48	1			T26	1		T5	2		T322	1
auto[3355443200:3489660927]	auto[0]	56	1			T5	1		T48	1		T84	1
auto[3355443200:3489660927]	auto[1]	61	1			T5	1		T23	1		T64	1
auto[3489660928:3623878655]	auto[0]	55	1			T5	1		T139	1		T213	1
auto[3489660928:3623878655]	auto[1]	48	1			T5	2		T48	1		T64	1
auto[3623878656:3758096383]	auto[0]	56	1			T4	1		T32	1		T5	1
auto[3623878656:3758096383]	auto[1]	53	1			T22	1		T91	1		T56	1
auto[3758096384:3892314111]	auto[0]	48	1			T5	1		T253	1		T84	1
auto[3758096384:3892314111]	auto[1]	52	1			T22	1		T5	1		T208	1
auto[3892314112:4026531839]	auto[0]	51	1			T2	1		T5	3		T84	1
auto[3892314112:4026531839]	auto[1]	52	1			T2	2		T5	2		T144	1
auto[4026531840:4160749567]	auto[0]	49	1			T5	1		T146	1		T69	1
auto[4026531840:4160749567]	auto[1]	53	1			T210	1		T212	1		T66	1
auto[4160749568:4294967295]	auto[0]	48	1			T19	1		T84	1		T64	1
auto[4160749568:4294967295]	auto[1]	65	1			T5	1		T48	1		T84	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1604

1

T2

3

T4

1

T12

1

auto[1]

1779

1

T2

4

T4

1

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T22	1		T5	1		T211	1
auto[134217728:268435455]	111	1			T22	1		T5	2		T253	1
auto[268435456:402653183]	106	1			T2	1		T136	1		T5	1
auto[402653184:536870911]	84	1			T15	1		T91	1		T5	1
auto[536870912:671088639]	112	1			T15	2		T109	1		T25	1
auto[671088640:805306367]	136	1			T2	1		T22	1		T5	1
auto[805306368:939524095]	118	1			T91	1		T5	3		T144	1
auto[939524096:1073741823]	107	1			T39	1		T32	2		T22	1
auto[1073741824:1207959551]	101	1			T91	1		T5	2		T34	1
auto[1207959552:1342177279]	110	1			T2	1		T25	1		T5	2
auto[1342177280:1476395007]	106	1			T4	1		T12	2		T5	1
auto[1476395008:1610612735]	98	1			T109	1		T26	1		T18	1
auto[1610612736:1744830463]	122	1			T5	1		T144	1		T206	2
auto[1744830464:1879048191]	96	1			T5	2		T253	1		T257	1
auto[1879048192:2013265919]	90	1			T44	1		T48	1		T110	1
auto[2013265920:2147483647]	100	1			T18	1		T146	1		T210	1
auto[2147483648:2281701375]	99	1			T17	1		T25	1		T26	1
auto[2281701376:2415919103]	109	1			T2	2		T4	1		T56	1
auto[2415919104:2550136831]	104	1			T5	3		T45	1		T84	1
auto[2550136832:2684354559]	125	1			T12	1		T32	1		T5	1
auto[2684354560:2818572287]	93	1			T32	1		T144	2		T44	1
auto[2818572288:2952790015]	85	1			T5	4		T45	2		T65	1
auto[2952790016:3087007743]	116	1			T2	1		T57	1		T48	1
auto[3087007744:3221225471]	85	1			T109	1		T56	1		T23	1
auto[3221225472:3355443199]	102	1			T91	1		T34	1		T146	1
auto[3355443200:3489660927]	113	1			T5	3		T57	1		T20	1
auto[3489660928:3623878655]	113	1			T26	1		T5	1		T144	1
auto[3623878656:3758096383]	131	1			T32	1		T5	1		T146	1
auto[3758096384:3892314111]	95	1			T26	2		T91	1		T5	3
auto[3892314112:4026531839]	103	1			T22	1		T26	1		T5	1
auto[4026531840:4160749567]	89	1			T39	1		T5	2		T144	1
auto[4160749568:4294967295]	108	1			T2	1		T15	1		T26	1