dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2962 1 T2 7 T4 2 T12 3
auto[1] 293 1 T126 5 T157 5 T158 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 113 1 T5 2 T45 1 T85 1
auto[134217728:268435455] 100 1 T15 1 T91 1 T5 2
auto[268435456:402653183] 99 1 T5 3 T146 1 T211 1
auto[402653184:536870911] 109 1 T109 1 T5 1 T146 1
auto[536870912:671088639] 94 1 T5 1 T211 1 T212 2
auto[671088640:805306367] 88 1 T146 1 T139 1 T82 1
auto[805306368:939524095] 105 1 T32 1 T206 1 T43 1
auto[939524096:1073741823] 95 1 T26 1 T91 1 T144 1
auto[1073741824:1207959551] 98 1 T22 2 T5 2 T23 2
auto[1207959552:1342177279] 98 1 T206 1 T253 1 T59 1
auto[1342177280:1476395007] 115 1 T2 1 T32 1 T91 1
auto[1476395008:1610612735] 90 1 T5 2 T144 1 T45 1
auto[1610612736:1744830463] 127 1 T25 1 T5 2 T144 1
auto[1744830464:1879048191] 87 1 T4 1 T91 1 T5 3
auto[1879048192:2013265919] 120 1 T2 1 T109 1 T5 1
auto[2013265920:2147483647] 116 1 T22 1 T26 2 T5 1
auto[2147483648:2281701375] 98 1 T2 2 T25 1 T26 1
auto[2281701376:2415919103] 86 1 T18 1 T144 1 T210 1
auto[2415919104:2550136831] 91 1 T22 1 T5 1 T126 1
auto[2550136832:2684354559] 96 1 T17 1 T5 1 T48 1
auto[2684354560:2818572287] 103 1 T5 1 T146 1 T57 1
auto[2818572288:2952790015] 103 1 T84 1 T46 1 T49 1
auto[2952790016:3087007743] 104 1 T12 2 T32 1 T26 1
auto[3087007744:3221225471] 98 1 T12 1 T5 3 T217 1
auto[3221225472:3355443199] 104 1 T4 1 T208 2 T139 1
auto[3355443200:3489660927] 103 1 T2 1 T39 1 T32 1
auto[3489660928:3623878655] 100 1 T32 1 T136 1 T211 1
auto[3623878656:3758096383] 108 1 T2 1 T39 1 T5 2
auto[3758096384:3892314111] 98 1 T2 1 T26 2 T5 1
auto[3892314112:4026531839] 102 1 T22 1 T84 1 T87 1
auto[4026531840:4160749567] 108 1 T109 1 T5 1 T110 1
auto[4160749568:4294967295] 99 1 T25 1 T5 1 T144 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 105 1 T5 2 T45 1 T85 1
auto[0:134217727] auto[1] 8 1 T327 2 T255 1 T311 1
auto[134217728:268435455] auto[0] 92 1 T15 1 T91 1 T5 2
auto[134217728:268435455] auto[1] 8 1 T149 1 T398 1 T249 1
auto[268435456:402653183] auto[0] 90 1 T5 3 T146 1 T211 1
auto[268435456:402653183] auto[1] 9 1 T398 1 T423 1 T424 1
auto[402653184:536870911] auto[0] 97 1 T109 1 T5 1 T146 1
auto[402653184:536870911] auto[1] 12 1 T126 1 T149 1 T376 1
auto[536870912:671088639] auto[0] 83 1 T5 1 T211 1 T212 2
auto[536870912:671088639] auto[1] 11 1 T157 1 T327 1 T250 1
auto[671088640:805306367] auto[0] 83 1 T146 1 T139 1 T82 1
auto[671088640:805306367] auto[1] 5 1 T369 1 T423 1 T298 2
auto[805306368:939524095] auto[0] 94 1 T32 1 T206 1 T43 1
auto[805306368:939524095] auto[1] 11 1 T327 2 T398 1 T298 1
auto[939524096:1073741823] auto[0] 85 1 T26 1 T91 1 T144 1
auto[939524096:1073741823] auto[1] 10 1 T149 2 T376 1 T255 1
auto[1073741824:1207959551] auto[0] 86 1 T22 2 T5 2 T23 2
auto[1073741824:1207959551] auto[1] 12 1 T157 1 T255 1 T398 2
auto[1207959552:1342177279] auto[0] 87 1 T206 1 T253 1 T59 1
auto[1207959552:1342177279] auto[1] 11 1 T147 1 T148 1 T255 1
auto[1342177280:1476395007] auto[0] 102 1 T2 1 T32 1 T91 1
auto[1342177280:1476395007] auto[1] 13 1 T327 1 T255 1 T335 2
auto[1476395008:1610612735] auto[0] 81 1 T5 2 T144 1 T45 1
auto[1476395008:1610612735] auto[1] 9 1 T157 1 T148 1 T331 1
auto[1610612736:1744830463] auto[0] 116 1 T25 1 T5 2 T144 1
auto[1610612736:1744830463] auto[1] 11 1 T147 1 T376 1 T396 1
auto[1744830464:1879048191] auto[0] 81 1 T4 1 T91 1 T5 3
auto[1744830464:1879048191] auto[1] 6 1 T126 1 T398 1 T250 1
auto[1879048192:2013265919] auto[0] 110 1 T2 1 T109 1 T5 1
auto[1879048192:2013265919] auto[1] 10 1 T327 1 T376 1 T335 1
auto[2013265920:2147483647] auto[0] 109 1 T22 1 T26 2 T5 1
auto[2013265920:2147483647] auto[1] 7 1 T356 1 T424 2 T431 1
auto[2147483648:2281701375] auto[0] 88 1 T2 2 T25 1 T26 1
auto[2147483648:2281701375] auto[1] 10 1 T158 1 T396 1 T398 1
auto[2281701376:2415919103] auto[0] 84 1 T18 1 T144 1 T210 1
auto[2281701376:2415919103] auto[1] 2 1 T335 1 T438 1 - -
auto[2415919104:2550136831] auto[0] 82 1 T22 1 T5 1 T43 1
auto[2415919104:2550136831] auto[1] 9 1 T126 1 T147 1 T396 1
auto[2550136832:2684354559] auto[0] 90 1 T17 1 T5 1 T48 1
auto[2550136832:2684354559] auto[1] 6 1 T158 1 T327 1 T344 1
auto[2684354560:2818572287] auto[0] 92 1 T5 1 T146 1 T57 1
auto[2684354560:2818572287] auto[1] 11 1 T126 1 T327 1 T255 2
auto[2818572288:2952790015] auto[0] 97 1 T84 1 T46 1 T49 1
auto[2818572288:2952790015] auto[1] 6 1 T255 1 T315 1 T424 1
auto[2952790016:3087007743] auto[0] 89 1 T12 2 T32 1 T26 1
auto[2952790016:3087007743] auto[1] 15 1 T149 1 T327 1 T376 1
auto[3087007744:3221225471] auto[0] 93 1 T12 1 T5 3 T217 1
auto[3087007744:3221225471] auto[1] 5 1 T148 1 T327 1 T251 1
auto[3221225472:3355443199] auto[0] 96 1 T4 1 T208 2 T139 1
auto[3221225472:3355443199] auto[1] 8 1 T327 1 T419 1 T381 2
auto[3355443200:3489660927] auto[0] 95 1 T2 1 T39 1 T32 1
auto[3355443200:3489660927] auto[1] 8 1 T157 1 T255 1 T384 1
auto[3489660928:3623878655] auto[0] 91 1 T32 1 T136 1 T211 1
auto[3489660928:3623878655] auto[1] 9 1 T147 1 T148 1 T149 2
auto[3623878656:3758096383] auto[0] 98 1 T2 1 T39 1 T5 2
auto[3623878656:3758096383] auto[1] 10 1 T126 1 T157 1 T327 1
auto[3758096384:3892314111] auto[0] 90 1 T2 1 T26 2 T5 1
auto[3758096384:3892314111] auto[1] 8 1 T331 1 T384 1 T369 1
auto[3892314112:4026531839] auto[0] 91 1 T22 1 T84 1 T87 1
auto[3892314112:4026531839] auto[1] 11 1 T149 1 T327 1 T376 1
auto[4026531840:4160749567] auto[0] 97 1 T109 1 T5 1 T110 1
auto[4026531840:4160749567] auto[1] 11 1 T331 1 T376 1 T419 1
auto[4160749568:4294967295] auto[0] 88 1 T25 1 T5 1 T144 1
auto[4160749568:4294967295] auto[1] 11 1 T148 1 T376 1 T384 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%