Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6960

1

T2

14

T4

3

T12

5

auto[1]

313

1

T126

6

T157

5

T147

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2919	1			T2	5		T4	2		T12	2
auto[134217728:268435455]	163	1			T12	1		T17	1		T44	2
auto[268435456:402653183]	167	1			T32	2		T26	1		T91	1
auto[402653184:536870911]	150	1			T15	1		T17	1		T32	2
auto[536870912:671088639]	144	1			T22	1		T26	1		T91	1
auto[671088640:805306367]	163	1			T2	1		T26	1		T5	2
auto[805306368:939524095]	164	1			T4	1		T136	1		T206	1
auto[939524096:1073741823]	118	1			T26	1		T136	1		T5	3
auto[1073741824:1207959551]	117	1			T91	1		T5	2		T34	1
auto[1207959552:1342177279]	155	1			T2	2		T22	1		T5	1
auto[1342177280:1476395007]	161	1			T2	1		T32	2		T25	1
auto[1476395008:1610612735]	160	1			T2	1		T32	1		T109	1
auto[1610612736:1744830463]	136	1			T26	1		T5	1		T144	1
auto[1744830464:1879048191]	126	1			T32	1		T22	1		T26	1
auto[1879048192:2013265919]	133	1			T2	1		T91	1		T146	1
auto[2013265920:2147483647]	120	1			T2	1		T22	1		T5	2
auto[2147483648:2281701375]	125	1			T109	1		T144	1		T44	1
auto[2281701376:2415919103]	135	1			T15	1		T5	2		T144	2
auto[2415919104:2550136831]	130	1			T12	1		T5	2		T206	2
auto[2550136832:2684354559]	127	1			T22	1		T5	1		T217	1
auto[2684354560:2818572287]	129	1			T39	1		T25	1		T26	1
auto[2818572288:2952790015]	139	1			T109	1		T25	1		T91	2
auto[2952790016:3087007743]	144	1			T39	1		T32	1		T26	1
auto[3087007744:3221225471]	127	1			T22	2		T26	1		T91	1
auto[3221225472:3355443199]	128	1			T25	2		T91	1		T5	3
auto[3355443200:3489660927]	119	1			T2	1		T5	2		T146	1
auto[3489660928:3623878655]	142	1			T5	2		T146	3		T206	1
auto[3623878656:3758096383]	137	1			T2	1		T126	1		T64	2
auto[3758096384:3892314111]	128	1			T91	1		T136	1		T5	2
auto[3892314112:4026531839]	157	1			T22	3		T5	4		T144	2
auto[4026531840:4160749567]	150	1			T5	1		T144	1		T146	1
auto[4160749568:4294967295]	160	1			T12	1		T25	1		T91	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2914	1			T2	5		T4	2		T12	2
auto[0:134217727]	auto[1]	5	1			T157	1		T419	1		T297	1
auto[134217728:268435455]	auto[0]	149	1			T12	1		T17	1		T44	2
auto[134217728:268435455]	auto[1]	14	1			T147	1		T149	1		T327	1
auto[268435456:402653183]	auto[0]	156	1			T32	2		T26	1		T91	1
auto[268435456:402653183]	auto[1]	11	1			T149	1		T376	1		T276	1
auto[402653184:536870911]	auto[0]	143	1			T15	1		T17	1		T32	2
auto[402653184:536870911]	auto[1]	7	1			T126	1		T356	1		T311	1
auto[536870912:671088639]	auto[0]	132	1			T22	1		T26	1		T91	1
auto[536870912:671088639]	auto[1]	12	1			T396	1		T250	1		T311	1
auto[671088640:805306367]	auto[0]	153	1			T2	1		T26	1		T5	2
auto[671088640:805306367]	auto[1]	10	1			T147	1		T335	2		T369	1
auto[805306368:939524095]	auto[0]	152	1			T4	1		T136	1		T206	1
auto[805306368:939524095]	auto[1]	12	1			T147	1		T149	1		T327	1
auto[939524096:1073741823]	auto[0]	110	1			T26	1		T136	1		T5	3
auto[939524096:1073741823]	auto[1]	8	1			T327	1		T376	2		T398	1
auto[1073741824:1207959551]	auto[0]	105	1			T91	1		T5	2		T34	1
auto[1073741824:1207959551]	auto[1]	12	1			T157	2		T331	1		T376	2
auto[1207959552:1342177279]	auto[0]	144	1			T2	2		T22	1		T5	1
auto[1207959552:1342177279]	auto[1]	11	1			T149	1		T327	1		T331	1
auto[1342177280:1476395007]	auto[0]	150	1			T2	1		T32	2		T25	1
auto[1342177280:1476395007]	auto[1]	11	1			T148	1		T376	1		T255	1
auto[1476395008:1610612735]	auto[0]	146	1			T2	1		T32	1		T109	1
auto[1476395008:1610612735]	auto[1]	14	1			T356	1		T149	1		T327	2
auto[1610612736:1744830463]	auto[0]	126	1			T26	1		T5	1		T144	1
auto[1610612736:1744830463]	auto[1]	10	1			T331	1		T255	1		T396	1
auto[1744830464:1879048191]	auto[0]	120	1			T32	1		T22	1		T26	1
auto[1744830464:1879048191]	auto[1]	6	1			T126	1		T148	1		T396	1
auto[1879048192:2013265919]	auto[0]	122	1			T2	1		T91	1		T146	1
auto[1879048192:2013265919]	auto[1]	11	1			T126	1		T149	2		T255	1
auto[2013265920:2147483647]	auto[0]	111	1			T2	1		T22	1		T5	2
auto[2013265920:2147483647]	auto[1]	9	1			T331	1		T255	1		T335	1
auto[2147483648:2281701375]	auto[0]	113	1			T109	1		T144	1		T44	1
auto[2147483648:2281701375]	auto[1]	12	1			T327	1		T376	1		T396	1
auto[2281701376:2415919103]	auto[0]	130	1			T15	1		T5	2		T144	2
auto[2281701376:2415919103]	auto[1]	5	1			T369	1		T423	1		T297	1
auto[2415919104:2550136831]	auto[0]	120	1			T12	1		T5	2		T206	2
auto[2415919104:2550136831]	auto[1]	10	1			T147	1		T376	2		T398	1
auto[2550136832:2684354559]	auto[0]	118	1			T22	1		T5	1		T217	1
auto[2550136832:2684354559]	auto[1]	9	1			T149	1		T423	2		T249	1
auto[2684354560:2818572287]	auto[0]	124	1			T39	1		T25	1		T26	1
auto[2684354560:2818572287]	auto[1]	5	1			T149	1		T396	1		T355	1
auto[2818572288:2952790015]	auto[0]	129	1			T109	1		T25	1		T91	2
auto[2818572288:2952790015]	auto[1]	10	1			T327	1		T376	2		T384	1
auto[2952790016:3087007743]	auto[0]	138	1			T39	1		T32	1		T26	1
auto[2952790016:3087007743]	auto[1]	6	1			T327	1		T384	1		T298	1
auto[3087007744:3221225471]	auto[0]	122	1			T22	2		T26	1		T91	1
auto[3087007744:3221225471]	auto[1]	5	1			T149	1		T251	1		T420	1
auto[3221225472:3355443199]	auto[0]	118	1			T25	2		T91	1		T5	3
auto[3221225472:3355443199]	auto[1]	10	1			T331	1		T376	1		T276	1
auto[3355443200:3489660927]	auto[0]	104	1			T2	1		T5	2		T146	1
auto[3355443200:3489660927]	auto[1]	15	1			T147	1		T148	1		T376	2
auto[3489660928:3623878655]	auto[0]	131	1			T5	2		T146	3		T206	1
auto[3489660928:3623878655]	auto[1]	11	1			T126	1		T157	1		T148	1
auto[3623878656:3758096383]	auto[0]	125	1			T2	1		T126	1		T64	2
auto[3623878656:3758096383]	auto[1]	12	1			T147	1		T327	2		T355	1
auto[3758096384:3892314111]	auto[0]	124	1			T91	1		T136	1		T5	2
auto[3758096384:3892314111]	auto[1]	4	1			T335	1		T250	1		T428	1
auto[3892314112:4026531839]	auto[0]	150	1			T22	3		T5	4		T144	2
auto[3892314112:4026531839]	auto[1]	7	1			T126	1		T157	1		T369	2
auto[4026531840:4160749567]	auto[0]	138	1			T5	1		T144	1		T146	1
auto[4026531840:4160749567]	auto[1]	12	1			T149	1		T398	1		T429	1
auto[4160749568:4294967295]	auto[0]	143	1			T12	1		T25	1		T91	3
auto[4160749568:4294967295]	auto[1]	17	1			T126	1		T356	1		T327	1