Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4662

1

T2

12

T4

2

T15

6

auto[1]

2102

1

T2

2

T4

2

T12

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	218	1			T4	2		T22	2		T5	2
auto[134217728:268435455]	226	1			T25	2		T136	2		T5	2
auto[268435456:402653183]	202	1			T5	6		T217	2		T210	2
auto[402653184:536870911]	202	1			T12	2		T5	4		T206	2
auto[536870912:671088639]	212	1			T18	2		T5	2		T44	2
auto[671088640:805306367]	234	1			T2	2		T26	2		T5	4
auto[805306368:939524095]	212	1			T2	2		T12	2		T5	2
auto[939524096:1073741823]	238	1			T26	2		T146	2		T44	2
auto[1073741824:1207959551]	200	1			T5	2		T208	2		T43	2
auto[1207959552:1342177279]	204	1			T15	2		T32	4		T18	2
auto[1342177280:1476395007]	244	1			T15	2		T26	2		T5	2
auto[1476395008:1610612735]	206	1			T5	2		T211	2		T253	2
auto[1610612736:1744830463]	184	1			T4	2		T15	2		T32	2
auto[1744830464:1879048191]	184	1			T56	2		T23	2		T45	2
auto[1879048192:2013265919]	230	1			T12	2		T25	2		T5	2
auto[2013265920:2147483647]	248	1			T5	2		T253	2		T85	2
auto[2147483648:2281701375]	234	1			T5	4		T146	2		T206	2
auto[2281701376:2415919103]	224	1			T2	2		T5	4		T144	2
auto[2415919104:2550136831]	188	1			T22	2		T5	4		T45	4
auto[2550136832:2684354559]	152	1			T5	4		T48	2		T99	2
auto[2684354560:2818572287]	218	1			T22	2		T34	2		T57	2
auto[2818572288:2952790015]	186	1			T109	2		T26	2		T91	4
auto[2952790016:3087007743]	202	1			T26	2		T91	2		T146	2
auto[3087007744:3221225471]	186	1			T39	2		T26	2		T210	2
auto[3221225472:3355443199]	220	1			T15	2		T22	2		T5	6
auto[3355443200:3489660927]	174	1			T5	2		T23	2		T48	2
auto[3489660928:3623878655]	224	1			T2	2		T146	2		T212	2
auto[3623878656:3758096383]	246	1			T2	2		T32	4		T25	2
auto[3758096384:3892314111]	222	1			T17	2		T5	4		T44	2
auto[3892314112:4026531839]	238	1			T91	2		T5	2		T217	2
auto[4026531840:4160749567]	214	1			T2	2		T39	2		T109	2
auto[4160749568:4294967295]	192	1			T2	2		T109	2		T91	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	140	1			T5	2		T144	2		T206	2
auto[0:134217727]	auto[1]	78	1			T4	2		T22	2		T146	2
auto[134217728:268435455]	auto[0]	158	1			T25	2		T5	2		T139	2
auto[134217728:268435455]	auto[1]	68	1			T136	2		T144	2		T253	2
auto[268435456:402653183]	auto[0]	140	1			T5	6		T257	2		T97	2
auto[268435456:402653183]	auto[1]	62	1			T217	2		T210	2		T60	2
auto[402653184:536870911]	auto[0]	144	1			T5	4		T206	2		T44	2
auto[402653184:536870911]	auto[1]	58	1			T12	2		T6	2		T209	2
auto[536870912:671088639]	auto[0]	140	1			T18	2		T5	2		T44	2
auto[536870912:671088639]	auto[1]	72	1			T110	2		T322	2		T67	2
auto[671088640:805306367]	auto[0]	166	1			T2	2		T26	2		T5	4
auto[671088640:805306367]	auto[1]	68	1			T217	2		T23	2		T84	2
auto[805306368:939524095]	auto[0]	148	1			T2	2		T5	2		T59	2
auto[805306368:939524095]	auto[1]	64	1			T12	2		T40	2		T158	2
auto[939524096:1073741823]	auto[0]	164	1			T26	2		T44	2		T42	2
auto[939524096:1073741823]	auto[1]	74	1			T146	2		T110	2		T49	2
auto[1073741824:1207959551]	auto[0]	118	1			T5	2		T208	2		T45	2
auto[1073741824:1207959551]	auto[1]	82	1			T43	2		T48	2		T266	2
auto[1207959552:1342177279]	auto[0]	128	1			T32	4		T18	2		T144	2
auto[1207959552:1342177279]	auto[1]	76	1			T15	2		T322	2		T50	2
auto[1342177280:1476395007]	auto[0]	176	1			T15	2		T5	2		T211	2
auto[1342177280:1476395007]	auto[1]	68	1			T26	2		T213	2		T50	4
auto[1476395008:1610612735]	auto[0]	140	1			T5	2		T253	2		T257	2
auto[1476395008:1610612735]	auto[1]	66	1			T211	2		T82	2		T207	2
auto[1610612736:1744830463]	auto[0]	130	1			T4	2		T15	2		T32	2
auto[1610612736:1744830463]	auto[1]	54	1			T22	2		T49	2		T209	2
auto[1744830464:1879048191]	auto[0]	126	1			T23	2		T45	2		T139	2
auto[1744830464:1879048191]	auto[1]	58	1			T56	2		T360	2		T222	2
auto[1879048192:2013265919]	auto[0]	158	1			T25	2		T56	2		T57	2
auto[1879048192:2013265919]	auto[1]	72	1			T12	2		T5	2		T56	2
auto[2013265920:2147483647]	auto[0]	182	1			T5	2		T253	2		T160	2
auto[2013265920:2147483647]	auto[1]	66	1			T85	2		T87	2		T299	2
auto[2147483648:2281701375]	auto[0]	166	1			T5	4		T206	2		T60	2
auto[2147483648:2281701375]	auto[1]	68	1			T146	2		T6	2		T43	2
auto[2281701376:2415919103]	auto[0]	160	1			T5	4		T144	2		T208	2
auto[2281701376:2415919103]	auto[1]	64	1			T2	2		T19	2		T65	2
auto[2415919104:2550136831]	auto[0]	140	1			T5	4		T45	4		T88	2
auto[2415919104:2550136831]	auto[1]	48	1			T22	2		T99	2		T360	2
auto[2550136832:2684354559]	auto[0]	96	1			T5	2		T99	2		T319	2
auto[2550136832:2684354559]	auto[1]	56	1			T5	2		T48	2		T427	2
auto[2684354560:2818572287]	auto[0]	150	1			T34	2		T211	2		T45	2
auto[2684354560:2818572287]	auto[1]	68	1			T22	2		T57	2		T44	2
auto[2818572288:2952790015]	auto[0]	140	1			T109	2		T5	4		T34	2
auto[2818572288:2952790015]	auto[1]	46	1			T26	2		T91	4		T5	2
auto[2952790016:3087007743]	auto[0]	132	1			T26	2		T213	2		T260	2
auto[2952790016:3087007743]	auto[1]	70	1			T91	2		T146	2		T20	2
auto[3087007744:3221225471]	auto[0]	120	1			T48	2		T257	2		T207	2
auto[3087007744:3221225471]	auto[1]	66	1			T39	2		T26	2		T210	2
auto[3221225472:3355443199]	auto[0]	152	1			T15	2		T5	6		T126	2
auto[3221225472:3355443199]	auto[1]	68	1			T22	2		T206	2		T57	2
auto[3355443200:3489660927]	auto[0]	116	1			T5	2		T23	2		T60	2
auto[3355443200:3489660927]	auto[1]	58	1			T48	2		T87	2		T213	2
auto[3489660928:3623878655]	auto[0]	168	1			T2	2		T59	2		T88	2
auto[3489660928:3623878655]	auto[1]	56	1			T146	2		T212	2		T65	2
auto[3623878656:3758096383]	auto[0]	172	1			T2	2		T32	4		T5	6
auto[3623878656:3758096383]	auto[1]	74	1			T25	2		T5	2		T146	2
auto[3758096384:3892314111]	auto[0]	152	1			T5	2		T48	2		T82	2
auto[3758096384:3892314111]	auto[1]	70	1			T17	2		T5	2		T44	2
auto[3892314112:4026531839]	auto[0]	166	1			T5	2		T48	2		T209	2
auto[3892314112:4026531839]	auto[1]	72	1			T91	2		T217	2		T87	2
auto[4026531840:4160749567]	auto[0]	152	1			T2	2		T109	2		T5	2
auto[4026531840:4160749567]	auto[1]	62	1			T39	2		T5	2		T67	2
auto[4160749568:4294967295]	auto[0]	122	1			T2	2		T109	2		T5	2
auto[4160749568:4294967295]	auto[1]	70	1			T91	2		T19	2		T50	2