Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.11 98.62 100.00 99.02 98.41 91.19


Total test records in report: 1088
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T1006 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1968113913 Jun 11 12:44:58 PM PDT 24 Jun 11 12:45:01 PM PDT 24 76018672 ps
T1007 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.220051446 Jun 11 12:45:06 PM PDT 24 Jun 11 12:45:10 PM PDT 24 545280886 ps
T1008 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.512947344 Jun 11 12:45:05 PM PDT 24 Jun 11 12:45:09 PM PDT 24 29797668 ps
T1009 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2935006680 Jun 11 12:45:04 PM PDT 24 Jun 11 12:45:07 PM PDT 24 10379741 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1010498000 Jun 11 12:45:15 PM PDT 24 Jun 11 12:45:22 PM PDT 24 450393223 ps
T1011 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.741344930 Jun 11 12:45:00 PM PDT 24 Jun 11 12:45:06 PM PDT 24 231784322 ps
T1012 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1771944217 Jun 11 12:44:45 PM PDT 24 Jun 11 12:44:49 PM PDT 24 110676172 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3407016320 Jun 11 12:45:00 PM PDT 24 Jun 11 12:45:03 PM PDT 24 35686686 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1780618655 Jun 11 12:44:56 PM PDT 24 Jun 11 12:44:59 PM PDT 24 30862503 ps
T1015 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2319563849 Jun 11 12:45:00 PM PDT 24 Jun 11 12:45:08 PM PDT 24 193245411 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3770313633 Jun 11 12:44:48 PM PDT 24 Jun 11 12:44:51 PM PDT 24 29847381 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2020252090 Jun 11 12:45:08 PM PDT 24 Jun 11 12:45:14 PM PDT 24 220517649 ps
T1018 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3979191866 Jun 11 12:45:11 PM PDT 24 Jun 11 12:45:16 PM PDT 24 179158295 ps
T1019 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3281422789 Jun 11 12:45:07 PM PDT 24 Jun 11 12:45:11 PM PDT 24 28268790 ps
T1020 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3550307323 Jun 11 12:45:18 PM PDT 24 Jun 11 12:45:21 PM PDT 24 34998690 ps
T1021 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3769959705 Jun 11 12:44:59 PM PDT 24 Jun 11 12:45:08 PM PDT 24 384339694 ps
T1022 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1234558153 Jun 11 12:45:10 PM PDT 24 Jun 11 12:45:15 PM PDT 24 260709034 ps
T1023 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.678646882 Jun 11 12:45:04 PM PDT 24 Jun 11 12:45:07 PM PDT 24 16373464 ps
T1024 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.25899228 Jun 11 12:45:00 PM PDT 24 Jun 11 12:45:06 PM PDT 24 293341132 ps
T1025 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3055217582 Jun 11 12:44:57 PM PDT 24 Jun 11 12:45:00 PM PDT 24 19446429 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1496498575 Jun 11 12:44:42 PM PDT 24 Jun 11 12:44:46 PM PDT 24 47772454 ps
T1027 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1374312288 Jun 11 12:44:54 PM PDT 24 Jun 11 12:44:57 PM PDT 24 54999251 ps
T1028 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1137094434 Jun 11 12:45:03 PM PDT 24 Jun 11 12:45:07 PM PDT 24 199472042 ps
T1029 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1854152094 Jun 11 12:45:01 PM PDT 24 Jun 11 12:45:05 PM PDT 24 108052625 ps
T1030 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2983842965 Jun 11 12:45:06 PM PDT 24 Jun 11 12:45:09 PM PDT 24 33180837 ps
T1031 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.755692960 Jun 11 12:45:01 PM PDT 24 Jun 11 12:45:11 PM PDT 24 380668621 ps
T1032 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3857886876 Jun 11 12:45:08 PM PDT 24 Jun 11 12:45:16 PM PDT 24 245458321 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3907637899 Jun 11 12:44:53 PM PDT 24 Jun 11 12:44:56 PM PDT 24 223970354 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3948059758 Jun 11 12:44:57 PM PDT 24 Jun 11 12:45:12 PM PDT 24 2405255456 ps
T1035 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1335178611 Jun 11 12:45:23 PM PDT 24 Jun 11 12:45:26 PM PDT 24 37602677 ps
T1036 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.921705095 Jun 11 12:44:53 PM PDT 24 Jun 11 12:44:56 PM PDT 24 55529162 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1018408830 Jun 11 12:45:06 PM PDT 24 Jun 11 12:45:11 PM PDT 24 217312850 ps
T1038 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3862669075 Jun 11 12:45:19 PM PDT 24 Jun 11 12:45:27 PM PDT 24 8590646 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2547963697 Jun 11 12:44:53 PM PDT 24 Jun 11 12:44:55 PM PDT 24 32388569 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2062904574 Jun 11 12:44:46 PM PDT 24 Jun 11 12:44:50 PM PDT 24 61643067 ps
T1041 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.813009685 Jun 11 12:45:03 PM PDT 24 Jun 11 12:45:06 PM PDT 24 10001034 ps
T1042 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1136900016 Jun 11 12:44:59 PM PDT 24 Jun 11 12:45:02 PM PDT 24 28995728 ps
T1043 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3440026346 Jun 11 12:45:30 PM PDT 24 Jun 11 12:45:37 PM PDT 24 105858043 ps
T1044 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1350209475 Jun 11 12:45:05 PM PDT 24 Jun 11 12:45:08 PM PDT 24 59083049 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1030663437 Jun 11 12:45:03 PM PDT 24 Jun 11 12:45:07 PM PDT 24 95201300 ps
T1046 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1196933693 Jun 11 12:45:19 PM PDT 24 Jun 11 12:45:24 PM PDT 24 66749964 ps
T1047 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1395456249 Jun 11 12:45:17 PM PDT 24 Jun 11 12:45:21 PM PDT 24 68125509 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1459412328 Jun 11 12:44:56 PM PDT 24 Jun 11 12:45:05 PM PDT 24 9390706 ps
T1049 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2496327762 Jun 11 12:44:54 PM PDT 24 Jun 11 12:44:59 PM PDT 24 531944112 ps
T174 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.14761941 Jun 11 12:45:24 PM PDT 24 Jun 11 12:45:31 PM PDT 24 202564649 ps
T176 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.753452726 Jun 11 12:45:12 PM PDT 24 Jun 11 12:45:20 PM PDT 24 900657494 ps
T1050 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2046327236 Jun 11 12:45:00 PM PDT 24 Jun 11 12:45:04 PM PDT 24 36758699 ps
T1051 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2373627249 Jun 11 12:45:03 PM PDT 24 Jun 11 12:45:06 PM PDT 24 65211239 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.53200791 Jun 11 12:45:01 PM PDT 24 Jun 11 12:45:10 PM PDT 24 205207079 ps
T1053 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1305971511 Jun 11 12:44:56 PM PDT 24 Jun 11 12:44:59 PM PDT 24 243995962 ps
T1054 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4111448921 Jun 11 12:45:27 PM PDT 24 Jun 11 12:45:33 PM PDT 24 854593977 ps
T1055 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.582547542 Jun 11 12:44:57 PM PDT 24 Jun 11 12:44:59 PM PDT 24 26364947 ps
T1056 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2225328146 Jun 11 12:45:19 PM PDT 24 Jun 11 12:45:22 PM PDT 24 40276563 ps
T1057 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.727107150 Jun 11 12:45:29 PM PDT 24 Jun 11 12:45:32 PM PDT 24 49063425 ps
T1058 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.272476558 Jun 11 12:44:56 PM PDT 24 Jun 11 12:45:02 PM PDT 24 794960317 ps
T1059 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3017941788 Jun 11 12:45:15 PM PDT 24 Jun 11 12:45:19 PM PDT 24 56422358 ps
T1060 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2535582700 Jun 11 12:45:09 PM PDT 24 Jun 11 12:45:17 PM PDT 24 775042590 ps
T180 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.706137365 Jun 11 12:44:51 PM PDT 24 Jun 11 12:44:58 PM PDT 24 554548114 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3214800655 Jun 11 12:45:02 PM PDT 24 Jun 11 12:45:05 PM PDT 24 172442642 ps
T1062 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1482861689 Jun 11 12:44:45 PM PDT 24 Jun 11 12:44:49 PM PDT 24 42367758 ps
T1063 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3119192891 Jun 11 12:45:13 PM PDT 24 Jun 11 12:45:18 PM PDT 24 44183673 ps
T1064 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.431116756 Jun 11 12:44:46 PM PDT 24 Jun 11 12:44:53 PM PDT 24 283791461 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1890334371 Jun 11 12:44:58 PM PDT 24 Jun 11 12:45:01 PM PDT 24 220628074 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.531099928 Jun 11 12:45:07 PM PDT 24 Jun 11 12:45:26 PM PDT 24 911306352 ps
T1067 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3188877056 Jun 11 12:45:27 PM PDT 24 Jun 11 12:45:37 PM PDT 24 359056912 ps
T1068 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1216326914 Jun 11 12:45:12 PM PDT 24 Jun 11 12:45:15 PM PDT 24 8089117 ps
T1069 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2986032495 Jun 11 12:45:10 PM PDT 24 Jun 11 12:45:13 PM PDT 24 14661798 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2302865747 Jun 11 12:44:48 PM PDT 24 Jun 11 12:44:51 PM PDT 24 29775881 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1519424254 Jun 11 12:45:16 PM PDT 24 Jun 11 12:45:26 PM PDT 24 397244759 ps
T1072 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3182078437 Jun 11 12:45:18 PM PDT 24 Jun 11 12:45:27 PM PDT 24 426569996 ps
T1073 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1724621559 Jun 11 12:45:16 PM PDT 24 Jun 11 12:45:19 PM PDT 24 51945531 ps
T1074 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1733618025 Jun 11 12:45:21 PM PDT 24 Jun 11 12:45:26 PM PDT 24 116318382 ps
T1075 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1923272916 Jun 11 12:45:07 PM PDT 24 Jun 11 12:45:15 PM PDT 24 349702759 ps
T1076 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3715150678 Jun 11 12:45:19 PM PDT 24 Jun 11 12:45:22 PM PDT 24 21076520 ps
T171 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.110408125 Jun 11 12:45:14 PM PDT 24 Jun 11 12:45:21 PM PDT 24 243100790 ps
T1077 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1780377213 Jun 11 12:45:07 PM PDT 24 Jun 11 12:45:10 PM PDT 24 10524032 ps
T183 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.612466142 Jun 11 12:45:11 PM PDT 24 Jun 11 12:45:19 PM PDT 24 2204152700 ps
T1078 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1773737089 Jun 11 12:45:13 PM PDT 24 Jun 11 12:45:16 PM PDT 24 9439503 ps
T1079 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2617431571 Jun 11 12:45:24 PM PDT 24 Jun 11 12:45:27 PM PDT 24 20476975 ps
T1080 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2257873861 Jun 11 12:45:08 PM PDT 24 Jun 11 12:45:12 PM PDT 24 202245884 ps
T1081 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1452130937 Jun 11 12:45:09 PM PDT 24 Jun 11 12:45:20 PM PDT 24 1533462494 ps
T1082 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2152695257 Jun 11 12:45:20 PM PDT 24 Jun 11 12:45:25 PM PDT 24 67559568 ps
T1083 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3313745031 Jun 11 12:44:54 PM PDT 24 Jun 11 12:44:58 PM PDT 24 34068169 ps
T1084 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2282143519 Jun 11 12:45:15 PM PDT 24 Jun 11 12:45:20 PM PDT 24 114450843 ps
T1085 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3606106493 Jun 11 12:45:20 PM PDT 24 Jun 11 12:45:33 PM PDT 24 418576155 ps
T1086 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.827862756 Jun 11 12:45:20 PM PDT 24 Jun 11 12:45:26 PM PDT 24 88440877 ps
T1087 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2272735445 Jun 11 12:45:13 PM PDT 24 Jun 11 12:45:16 PM PDT 24 10188442 ps
T1088 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3052705102 Jun 11 12:45:15 PM PDT 24 Jun 11 12:45:21 PM PDT 24 521720324 ps

Test location /workspace/coverage/default/17.keymgr_lc_disable.2736702720
Short name T15
Test name
Test status
Simulation time 238654673 ps
CPU time 3.01 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:48:42 PM PDT 24
Peak memory 218272 kb
Host smart-13ea99f9-99f6-42dd-8aff-6550f74627d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736702720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2736702720
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4191324455
Short name T5
Test name
Test status
Simulation time 5753631668 ps
CPU time 50.9 seconds
Started Jun 11 12:49:45 PM PDT 24
Finished Jun 11 12:50:38 PM PDT 24
Peak memory 216892 kb
Host smart-09ff2593-ce71-4db2-a2ae-98e2c5fec809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191324455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4191324455
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1918633237
Short name T48
Test name
Test status
Simulation time 606703135 ps
CPU time 21.02 seconds
Started Jun 11 12:49:31 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 222572 kb
Host smart-e3cd07fe-87db-411a-8cbf-1166ca38ea87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918633237 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1918633237
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2983904315
Short name T9
Test name
Test status
Simulation time 8020521540 ps
CPU time 19.46 seconds
Started Jun 11 12:47:50 PM PDT 24
Finished Jun 11 12:48:12 PM PDT 24
Peak memory 239784 kb
Host smart-2e9ff372-d73b-42b9-afde-87418393fa99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983904315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2983904315
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_random.3794003474
Short name T2
Test name
Test status
Simulation time 3964595994 ps
CPU time 38.72 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 209324 kb
Host smart-cba5db2e-bab3-4ca6-b3b8-4abf4a7fdc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794003474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3794003474
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3098418502
Short name T54
Test name
Test status
Simulation time 489955670 ps
CPU time 17.69 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 217600 kb
Host smart-f8be3ca8-0805-43d7-8551-ec5b19cf8ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098418502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3098418502
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1263587267
Short name T50
Test name
Test status
Simulation time 3779060880 ps
CPU time 32.64 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:35 PM PDT 24
Peak memory 216048 kb
Host smart-23262428-8276-4144-b7f8-d3f4f87df7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263587267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1263587267
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.319303386
Short name T58
Test name
Test status
Simulation time 315943673 ps
CPU time 19.27 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:26 PM PDT 24
Peak memory 222900 kb
Host smart-0338189d-907e-4b2c-af2c-fb023f974a58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319303386 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.319303386
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2894708610
Short name T44
Test name
Test status
Simulation time 137856163 ps
CPU time 3.24 seconds
Started Jun 11 12:49:34 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 215244 kb
Host smart-481707b8-753e-4ea3-ad55-f1cad64883fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894708610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2894708610
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1985731301
Short name T327
Test name
Test status
Simulation time 163566771 ps
CPU time 8.56 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 214412 kb
Host smart-d5569fc7-9fa8-4214-8c54-bf8b6f884beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985731301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1985731301
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2587099745
Short name T122
Test name
Test status
Simulation time 675556163 ps
CPU time 4.79 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 214180 kb
Host smart-2fd32d23-8295-4daa-beb7-c1df2da90492
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587099745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2587099745
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.147148869
Short name T64
Test name
Test status
Simulation time 935522373 ps
CPU time 13.14 seconds
Started Jun 11 12:48:26 PM PDT 24
Finished Jun 11 12:48:42 PM PDT 24
Peak memory 216280 kb
Host smart-722b037b-b8bb-4530-b6c3-08181dcb5671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147148869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.147148869
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.838049541
Short name T8
Test name
Test status
Simulation time 115105297 ps
CPU time 4.23 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 214976 kb
Host smart-80c1f9fc-2e1d-4743-98c9-f036f9d9ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838049541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.838049541
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2085276597
Short name T22
Test name
Test status
Simulation time 137838768 ps
CPU time 4.35 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 214388 kb
Host smart-14945fdd-48e2-49e1-a007-107bf0b08977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085276597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2085276597
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3730216139
Short name T19
Test name
Test status
Simulation time 291182884 ps
CPU time 2.73 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 217100 kb
Host smart-1beaad04-ce96-456e-a40a-78625a604866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730216139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3730216139
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.229405814
Short name T293
Test name
Test status
Simulation time 698113569 ps
CPU time 9.36 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 215020 kb
Host smart-56dce58d-2a3c-4080-bd8e-9c402a56f757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229405814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.229405814
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2279827613
Short name T382
Test name
Test status
Simulation time 2246360171 ps
CPU time 56.69 seconds
Started Jun 11 12:49:32 PM PDT 24
Finished Jun 11 12:50:30 PM PDT 24
Peak memory 222648 kb
Host smart-b2cdd110-ae5a-44d3-a70e-7fdeaa48ed48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279827613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2279827613
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2250985904
Short name T26
Test name
Test status
Simulation time 342925398 ps
CPU time 4.27 seconds
Started Jun 11 12:48:22 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 222416 kb
Host smart-873a16bf-c2c4-4d27-8af2-35ee5703c554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250985904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2250985904
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.896869434
Short name T128
Test name
Test status
Simulation time 577057699 ps
CPU time 3.27 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:45:00 PM PDT 24
Peak memory 214204 kb
Host smart-976b635f-2da6-45d2-87f0-2d207561117e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896869434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.896869434
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2476866500
Short name T74
Test name
Test status
Simulation time 21729448425 ps
CPU time 259.37 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:53:49 PM PDT 24
Peak memory 218044 kb
Host smart-469aa211-4a1d-43c8-a299-c935bab04fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476866500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2476866500
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1416098987
Short name T369
Test name
Test status
Simulation time 3945587571 ps
CPU time 99.31 seconds
Started Jun 11 12:49:58 PM PDT 24
Finished Jun 11 12:51:39 PM PDT 24
Peak memory 215864 kb
Host smart-6dd6a80c-d141-4eea-9bf1-c00b98d98401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416098987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1416098987
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.527053214
Short name T205
Test name
Test status
Simulation time 4155490313 ps
CPU time 20.45 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 211764 kb
Host smart-e856f7ea-5f47-400f-bacc-e7183ec8abd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527053214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.527053214
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2704075044
Short name T355
Test name
Test status
Simulation time 197583098 ps
CPU time 3.8 seconds
Started Jun 11 12:49:23 PM PDT 24
Finished Jun 11 12:49:28 PM PDT 24
Peak memory 214368 kb
Host smart-2a236b0a-553a-43cd-8934-8f6f48129b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704075044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2704075044
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3493796811
Short name T209
Test name
Test status
Simulation time 1159351863 ps
CPU time 16.79 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 222688 kb
Host smart-0e742eda-369f-4477-a643-507055e24008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493796811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3493796811
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3899633296
Short name T124
Test name
Test status
Simulation time 421708352 ps
CPU time 24.55 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 222680 kb
Host smart-cbc53132-e62e-4a99-9fa4-96e36942a285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899633296 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3899633296
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3563854351
Short name T35
Test name
Test status
Simulation time 146262181 ps
CPU time 5.17 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:14 PM PDT 24
Peak memory 209272 kb
Host smart-701dabef-ef31-4bb7-b5b6-513d5997fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563854351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3563854351
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3160375333
Short name T420
Test name
Test status
Simulation time 169076693 ps
CPU time 8.26 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 214820 kb
Host smart-1d93906b-07d5-4862-872d-b9790939e3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160375333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3160375333
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1161060324
Short name T160
Test name
Test status
Simulation time 489755855 ps
CPU time 4.08 seconds
Started Jun 11 12:49:58 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 217588 kb
Host smart-60294d25-fb85-4d11-8ce9-419736c43e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161060324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1161060324
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1809339536
Short name T359
Test name
Test status
Simulation time 583133589 ps
CPU time 9.85 seconds
Started Jun 11 12:49:57 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 215796 kb
Host smart-bf3db61c-779e-4aee-b8d9-dd0d4603757d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809339536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1809339536
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2506640335
Short name T30
Test name
Test status
Simulation time 52891068 ps
CPU time 3.06 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 209176 kb
Host smart-c5f21725-61fc-425e-9117-1c11e33f8649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506640335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2506640335
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2206549659
Short name T103
Test name
Test status
Simulation time 106603575 ps
CPU time 4.31 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 209556 kb
Host smart-6b40e132-1bcd-4866-bb90-17a3417808dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206549659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2206549659
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2883019553
Short name T68
Test name
Test status
Simulation time 439356334 ps
CPU time 17.16 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:38 PM PDT 24
Peak memory 222592 kb
Host smart-50da53e7-9308-49d8-8796-faf51090b704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883019553 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2883019553
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3523005631
Short name T384
Test name
Test status
Simulation time 259124146 ps
CPU time 4.25 seconds
Started Jun 11 12:49:30 PM PDT 24
Finished Jun 11 12:49:36 PM PDT 24
Peak memory 215884 kb
Host smart-06380608-06d9-4196-b09c-dfba8900cabb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523005631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3523005631
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4069788826
Short name T78
Test name
Test status
Simulation time 784980343 ps
CPU time 36.89 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 216952 kb
Host smart-9a2b0780-2c25-48d0-9a0c-434f0e0245d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069788826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4069788826
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1014994377
Short name T396
Test name
Test status
Simulation time 853952734 ps
CPU time 4.98 seconds
Started Jun 11 12:50:15 PM PDT 24
Finished Jun 11 12:50:22 PM PDT 24
Peak memory 222472 kb
Host smart-15b129bb-7dff-4a72-96ef-3fb0eeacb4e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014994377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1014994377
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.732815041
Short name T99
Test name
Test status
Simulation time 172266785 ps
CPU time 6.16 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 222560 kb
Host smart-5e523a5d-4aa7-4b55-9411-c746a066c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732815041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.732815041
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3893615921
Short name T106
Test name
Test status
Simulation time 28961665 ps
CPU time 0.7 seconds
Started Jun 11 12:48:42 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 206008 kb
Host smart-a4e76c87-ac48-4eef-828c-3d1bdc544c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893615921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3893615921
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.110408125
Short name T171
Test name
Test status
Simulation time 243100790 ps
CPU time 4.33 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 213824 kb
Host smart-7d63de21-ae50-4bfd-96cf-8570248c4e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110408125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.110408125
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4153459110
Short name T242
Test name
Test status
Simulation time 1517266430 ps
CPU time 42.36 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 221720 kb
Host smart-8ddb8e9e-6f69-400b-bf8f-1bb2cc1a103c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153459110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4153459110
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1881876586
Short name T223
Test name
Test status
Simulation time 690295736 ps
CPU time 5.66 seconds
Started Jun 11 12:48:08 PM PDT 24
Finished Jun 11 12:48:15 PM PDT 24
Peak memory 214376 kb
Host smart-8e204427-b86f-44f2-8ce8-a14cd7861936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881876586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1881876586
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2620721099
Short name T234
Test name
Test status
Simulation time 7410341757 ps
CPU time 74.73 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:49:49 PM PDT 24
Peak memory 216892 kb
Host smart-fed7bcec-76f7-4551-83d8-ce452316a038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620721099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2620721099
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1957177670
Short name T182
Test name
Test status
Simulation time 357075316 ps
CPU time 4.41 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 213812 kb
Host smart-83fd34f2-e31d-4dca-9e23-49d858741e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957177670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1957177670
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3976770862
Short name T264
Test name
Test status
Simulation time 415437766 ps
CPU time 4.54 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:26 PM PDT 24
Peak memory 208796 kb
Host smart-34c2da5b-cb42-4e5f-a4ef-248d7f1dfedd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976770862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3976770862
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.396702338
Short name T325
Test name
Test status
Simulation time 4059612005 ps
CPU time 11.19 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 215160 kb
Host smart-40da5cd2-2103-4d70-8945-b4245d854359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396702338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.396702338
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1434105591
Short name T165
Test name
Test status
Simulation time 99314387 ps
CPU time 4.43 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 222704 kb
Host smart-0ea4571e-4f87-46cb-9012-92d8732521f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434105591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1434105591
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3043695306
Short name T159
Test name
Test status
Simulation time 56412102 ps
CPU time 3.93 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:04 PM PDT 24
Peak memory 218192 kb
Host smart-2623d6f9-cbe6-4e53-b28f-e6b6fe5be2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043695306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3043695306
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2731504761
Short name T311
Test name
Test status
Simulation time 256727797 ps
CPU time 14.29 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:35 PM PDT 24
Peak memory 214316 kb
Host smart-e7f82b29-341a-4714-9d36-2acf7855e056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731504761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2731504761
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3895573340
Short name T335
Test name
Test status
Simulation time 246438865 ps
CPU time 12.16 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 214248 kb
Host smart-5675256d-e9b9-4985-ba2f-156500fcb000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895573340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3895573340
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3825832204
Short name T378
Test name
Test status
Simulation time 583745890 ps
CPU time 3.55 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 214280 kb
Host smart-19c2e270-ac7b-4d2b-9f3e-7c8d6ac18370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825832204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3825832204
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3423020528
Short name T47
Test name
Test status
Simulation time 1301403051 ps
CPU time 45.87 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 220496 kb
Host smart-d8530f56-dd1f-4356-abee-e5aec4030590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423020528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3423020528
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3221098580
Short name T261
Test name
Test status
Simulation time 147251818 ps
CPU time 5.69 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 222780 kb
Host smart-48c79010-2718-413c-8704-a14dce160c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221098580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3221098580
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1559254921
Short name T187
Test name
Test status
Simulation time 846131757 ps
CPU time 8.97 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 215256 kb
Host smart-659c160e-e441-4483-875f-3806e9ff6744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559254921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1559254921
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.447969707
Short name T94
Test name
Test status
Simulation time 116421645 ps
CPU time 3.53 seconds
Started Jun 11 12:48:53 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 214316 kb
Host smart-671bd0f4-b1e9-44d2-a14f-6151fb7adbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447969707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.447969707
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3693658971
Short name T161
Test name
Test status
Simulation time 29813443 ps
CPU time 2.62 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 217772 kb
Host smart-8d138119-f2bc-41a6-b490-110c246c2e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693658971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3693658971
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2402545515
Short name T57
Test name
Test status
Simulation time 150672409 ps
CPU time 3.09 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 217720 kb
Host smart-eee46302-8435-41f3-a4e1-6cd726d93ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402545515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2402545515
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1971421855
Short name T163
Test name
Test status
Simulation time 101844279 ps
CPU time 3.89 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 218512 kb
Host smart-7529bd29-1fa2-427c-9fa0-408ee3255e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971421855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1971421855
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.8098360
Short name T87
Test name
Test status
Simulation time 9170405602 ps
CPU time 28.42 seconds
Started Jun 11 12:48:48 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 208928 kb
Host smart-6a00f6bf-6853-4bcb-9652-38a06a7b72f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8098360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.8098360
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1839543047
Short name T23
Test name
Test status
Simulation time 1765355300 ps
CPU time 7.74 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 214380 kb
Host smart-b0aefca2-cb72-4beb-be9d-086616bb740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839543047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1839543047
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1598677340
Short name T287
Test name
Test status
Simulation time 133641875 ps
CPU time 3.38 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 214412 kb
Host smart-fe746904-f136-46af-99f8-ecd6ee465bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598677340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1598677340
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2259607711
Short name T371
Test name
Test status
Simulation time 7087947436 ps
CPU time 166.08 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:51:57 PM PDT 24
Peak memory 221600 kb
Host smart-d1f3b7ce-73b9-48c1-83bd-b28b1624e8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259607711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2259607711
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4268857239
Short name T6
Test name
Test status
Simulation time 146741317 ps
CPU time 3.71 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 214412 kb
Host smart-9757134c-c344-4b2d-a3aa-7d29ff3685a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268857239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4268857239
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3932963407
Short name T162
Test name
Test status
Simulation time 150965421 ps
CPU time 3.58 seconds
Started Jun 11 12:48:39 PM PDT 24
Finished Jun 11 12:48:44 PM PDT 24
Peak memory 222728 kb
Host smart-72461c32-0e5b-470c-81f2-2bedcb5f8472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932963407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3932963407
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3411819655
Short name T181
Test name
Test status
Simulation time 126408948 ps
CPU time 2.75 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 210064 kb
Host smart-99cce9f7-7590-4385-8694-420e1282d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411819655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3411819655
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.14761941
Short name T174
Test name
Test status
Simulation time 202564649 ps
CPU time 4.67 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:31 PM PDT 24
Peak memory 213752 kb
Host smart-0f9715c8-5860-40f3-a934-80daa863701f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.14761941
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3937744438
Short name T178
Test name
Test status
Simulation time 293357953 ps
CPU time 2.71 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213808 kb
Host smart-3747a361-9186-418c-9178-3bc7b97eef4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937744438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3937744438
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.753452726
Short name T176
Test name
Test status
Simulation time 900657494 ps
CPU time 6.28 seconds
Started Jun 11 12:45:12 PM PDT 24
Finished Jun 11 12:45:20 PM PDT 24
Peak memory 213704 kb
Host smart-6289ce44-a104-4a92-9349-40cfcaaaf503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753452726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
753452726
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.356977463
Short name T11
Test name
Test status
Simulation time 1055476429 ps
CPU time 11.81 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:18 PM PDT 24
Peak memory 238672 kb
Host smart-eb59bbf7-e8d7-4b31-9f4c-2891868cdf54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356977463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.356977463
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1673983592
Short name T246
Test name
Test status
Simulation time 605605442 ps
CPU time 24.48 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:30 PM PDT 24
Peak memory 215908 kb
Host smart-c474c6d7-b4f1-4cad-a4e1-8330d1c9c88e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673983592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1673983592
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3366242804
Short name T340
Test name
Test status
Simulation time 197116598 ps
CPU time 3.67 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 214304 kb
Host smart-e2de2523-2d69-4057-8c3f-e7288ad99fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366242804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3366242804
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3241267714
Short name T268
Test name
Test status
Simulation time 13659215638 ps
CPU time 79.79 seconds
Started Jun 11 12:49:29 PM PDT 24
Finished Jun 11 12:50:50 PM PDT 24
Peak memory 215272 kb
Host smart-bdddd4e8-e0a9-46f4-bc10-98882a471d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241267714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3241267714
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.4193163889
Short name T200
Test name
Test status
Simulation time 3843398085 ps
CPU time 41.14 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 222552 kb
Host smart-5ecf5012-b5fd-49b8-80a9-ce6ff8a2e4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193163889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4193163889
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1597549247
Short name T60
Test name
Test status
Simulation time 66045265 ps
CPU time 3.63 seconds
Started Jun 11 12:49:30 PM PDT 24
Finished Jun 11 12:49:35 PM PDT 24
Peak memory 220416 kb
Host smart-728d802b-ccee-4cfa-9b95-62b3b7ff142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597549247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1597549247
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.612466142
Short name T183
Test name
Test status
Simulation time 2204152700 ps
CPU time 5.95 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213784 kb
Host smart-c5baf88c-dbaf-4a9a-8dd4-364dd941cc0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612466142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.612466142
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1605642123
Short name T226
Test name
Test status
Simulation time 218721720 ps
CPU time 5.66 seconds
Started Jun 11 12:48:36 PM PDT 24
Finished Jun 11 12:48:43 PM PDT 24
Peak memory 209032 kb
Host smart-f1d6fe18-c0b3-42a6-9bb5-307e04c21fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605642123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1605642123
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1040990872
Short name T309
Test name
Test status
Simulation time 288934816 ps
CPU time 2.46 seconds
Started Jun 11 12:48:36 PM PDT 24
Finished Jun 11 12:48:40 PM PDT 24
Peak memory 214388 kb
Host smart-bdae7df0-5fde-4d8f-97f8-f6c9e5540ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040990872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1040990872
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3983360960
Short name T262
Test name
Test status
Simulation time 180641053265 ps
CPU time 950.65 seconds
Started Jun 11 12:48:32 PM PDT 24
Finished Jun 11 01:04:25 PM PDT 24
Peak memory 230708 kb
Host smart-1c1a88ac-aae5-4b91-be75-13f77c3c91e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983360960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3983360960
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1279424189
Short name T298
Test name
Test status
Simulation time 83419030 ps
CPU time 5.03 seconds
Started Jun 11 12:48:38 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 214356 kb
Host smart-e66c241f-1b72-4989-a690-a4bd3f584232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279424189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1279424189
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2174691201
Short name T283
Test name
Test status
Simulation time 371982689 ps
CPU time 4.22 seconds
Started Jun 11 12:48:51 PM PDT 24
Finished Jun 11 12:48:57 PM PDT 24
Peak memory 222468 kb
Host smart-7fc47709-8bf9-473c-9364-2b4673ebd7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174691201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2174691201
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1319502318
Short name T333
Test name
Test status
Simulation time 51195253 ps
CPU time 2.8 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 208424 kb
Host smart-51dc7dd5-36f2-44b6-a320-fef892f32a04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319502318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1319502318
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3134838099
Short name T62
Test name
Test status
Simulation time 141260087 ps
CPU time 2.33 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 210520 kb
Host smart-ed43fe11-9609-43cf-8db8-6664e6bcef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134838099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3134838099
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.203373427
Short name T270
Test name
Test status
Simulation time 1227966335 ps
CPU time 15.44 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 222200 kb
Host smart-bc5cd6a8-5ca8-423c-bf0b-297702aea478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203373427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.203373427
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1388834324
Short name T188
Test name
Test status
Simulation time 274657042 ps
CPU time 10.4 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 213900 kb
Host smart-f5d95ab2-9b4b-420a-a329-22acb61edb92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388834324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1388834324
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2012131250
Short name T71
Test name
Test status
Simulation time 117787620 ps
CPU time 2.08 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 215648 kb
Host smart-af9adb6f-cefe-4c1e-ab96-66a7046ee9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012131250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2012131250
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1767920932
Short name T543
Test name
Test status
Simulation time 313811150 ps
CPU time 2.82 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:08 PM PDT 24
Peak memory 208052 kb
Host smart-a46072a6-7472-4467-a6b6-ab92904780b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767920932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1767920932
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1259156085
Short name T241
Test name
Test status
Simulation time 2195144681 ps
CPU time 39.62 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 215608 kb
Host smart-da262429-5d95-4ed3-b1e6-e3b4d9126886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259156085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1259156085
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1407257502
Short name T863
Test name
Test status
Simulation time 85987663 ps
CPU time 4.2 seconds
Started Jun 11 12:48:36 PM PDT 24
Finished Jun 11 12:48:43 PM PDT 24
Peak memory 214348 kb
Host smart-e07fcba8-71cf-45e2-9985-7ad1ad203633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407257502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1407257502
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3889536804
Short name T358
Test name
Test status
Simulation time 65900685 ps
CPU time 2.08 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:48 PM PDT 24
Peak memory 214684 kb
Host smart-84c5bfbe-d598-4601-bdb6-4ed8655cd1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889536804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3889536804
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.430157635
Short name T377
Test name
Test status
Simulation time 145325054 ps
CPU time 2.91 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:48:42 PM PDT 24
Peak memory 207328 kb
Host smart-cf16890a-c9f8-43c1-aed9-2f910231d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430157635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.430157635
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4151605118
Short name T395
Test name
Test status
Simulation time 74506143 ps
CPU time 3.64 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 214412 kb
Host smart-f0b457c4-c262-43e2-b793-963f05113dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151605118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4151605118
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4112286805
Short name T249
Test name
Test status
Simulation time 726296745 ps
CPU time 3.52 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 214380 kb
Host smart-3669bd16-27a3-43eb-9b8e-bca2eef5f37e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112286805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4112286805
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.228565463
Short name T525
Test name
Test status
Simulation time 187012573 ps
CPU time 6.71 seconds
Started Jun 11 12:49:03 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 214316 kb
Host smart-4466c72a-015a-4a9e-af77-ee2c46effabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228565463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.228565463
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1937503720
Short name T235
Test name
Test status
Simulation time 8130994789 ps
CPU time 70.04 seconds
Started Jun 11 12:48:53 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 222512 kb
Host smart-2ca1b1cd-2f30-4ba8-8398-ba4102d39de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937503720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1937503720
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1567516034
Short name T244
Test name
Test status
Simulation time 514121192 ps
CPU time 4.75 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 210676 kb
Host smart-7a6fd7b2-2804-4c3d-b9f7-2568187dea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567516034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1567516034
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3200422726
Short name T285
Test name
Test status
Simulation time 76993995 ps
CPU time 3.45 seconds
Started Jun 11 12:48:54 PM PDT 24
Finished Jun 11 12:48:59 PM PDT 24
Peak memory 214440 kb
Host smart-db3ae17d-ddb9-4eb9-b802-ad3235ca13ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200422726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3200422726
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1324484515
Short name T527
Test name
Test status
Simulation time 83757023 ps
CPU time 3.16 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 219780 kb
Host smart-de5904ce-bf1f-4d6e-8be5-8cb7036124cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324484515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1324484515
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1204107908
Short name T773
Test name
Test status
Simulation time 468425640 ps
CPU time 24.74 seconds
Started Jun 11 12:49:08 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 214968 kb
Host smart-d985db30-03f5-4659-b847-d5cbdb82b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204107908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1204107908
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3321674245
Short name T350
Test name
Test status
Simulation time 51732804 ps
CPU time 2.91 seconds
Started Jun 11 12:49:08 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 207100 kb
Host smart-7714eb1d-22c5-4ed5-b6ad-9cf8d6d14ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321674245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3321674245
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.969222816
Short name T7
Test name
Test status
Simulation time 531832176 ps
CPU time 11.55 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:31 PM PDT 24
Peak memory 222648 kb
Host smart-0eb6d7a5-ff3e-40f5-a63c-d72ac6c7099c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969222816 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.969222816
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.688322226
Short name T362
Test name
Test status
Simulation time 123786674 ps
CPU time 3.82 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 219752 kb
Host smart-e2b415cf-3270-4e60-a621-96f83fc98425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688322226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.688322226
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1089114979
Short name T213
Test name
Test status
Simulation time 227175190 ps
CPU time 5.75 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 210436 kb
Host smart-ff7874da-289d-4c1c-b66f-70664889101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089114979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1089114979
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.135923677
Short name T331
Test name
Test status
Simulation time 394567131 ps
CPU time 4.09 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:01 PM PDT 24
Peak memory 215196 kb
Host smart-fa6348de-f52e-42ea-b824-427c1d016804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135923677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.135923677
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1490241617
Short name T344
Test name
Test status
Simulation time 166989338 ps
CPU time 3.32 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:12 PM PDT 24
Peak memory 222636 kb
Host smart-eae42552-a76d-4a0c-89c5-bbd049f4a6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490241617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1490241617
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_random.1660546076
Short name T360
Test name
Test status
Simulation time 503633146 ps
CPU time 16.84 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:32 PM PDT 24
Peak memory 210720 kb
Host smart-7c1080b8-ec01-4d8b-b17b-37ba9b1af316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660546076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1660546076
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2991119732
Short name T164
Test name
Test status
Simulation time 69883856 ps
CPU time 3.74 seconds
Started Jun 11 12:48:10 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 218252 kb
Host smart-e140acf3-e195-4bc7-9fd3-9d9281be27d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991119732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2991119732
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.431116756
Short name T1064
Test name
Test status
Simulation time 283791461 ps
CPU time 4.03 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:53 PM PDT 24
Peak memory 205640 kb
Host smart-c24395d3-34b8-433e-a431-22ccb5ae6d15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431116756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.431116756
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3948059758
Short name T1034
Test name
Test status
Simulation time 2405255456 ps
CPU time 12.96 seconds
Started Jun 11 12:44:57 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 205664 kb
Host smart-fc72b549-0da7-40f8-a79f-0f131974f122
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948059758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
948059758
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4001453346
Short name T933
Test name
Test status
Simulation time 29980625 ps
CPU time 1.4 seconds
Started Jun 11 12:44:49 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 205532 kb
Host smart-1467d0e9-f7e8-468b-ad48-d6c4ff625cb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001453346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.4
001453346
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1137094434
Short name T1028
Test name
Test status
Simulation time 199472042 ps
CPU time 1.59 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 213928 kb
Host smart-289115c1-4204-422b-a20c-a46ce524e752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137094434 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1137094434
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1496498575
Short name T1026
Test name
Test status
Simulation time 47772454 ps
CPU time 1.08 seconds
Started Jun 11 12:44:42 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 205560 kb
Host smart-a278a3d4-b1af-49c7-9031-6ed3a7bee238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496498575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1496498575
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2302865747
Short name T1070
Test name
Test status
Simulation time 29775881 ps
CPU time 0.78 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 205240 kb
Host smart-82a858de-3193-4fa9-9abe-635e884adbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302865747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2302865747
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.586631779
Short name T965
Test name
Test status
Simulation time 366280621 ps
CPU time 3.03 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:58 PM PDT 24
Peak memory 205624 kb
Host smart-8162514b-e304-430e-ba4e-cf13856abf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586631779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.586631779
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1305971511
Short name T1053
Test name
Test status
Simulation time 243995962 ps
CPU time 1.64 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:44:59 PM PDT 24
Peak memory 214172 kb
Host smart-b5c69ba5-74b4-4eb6-8b84-60f9f5364d08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305971511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1305971511
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.25899228
Short name T1024
Test name
Test status
Simulation time 293341132 ps
CPU time 4.29 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 219720 kb
Host smart-47782671-7f35-4ffd-ac4e-0d083ed36c7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25899228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_shadow_reg_errors_with_csr_rw.25899228
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3556895474
Short name T957
Test name
Test status
Simulation time 122143508 ps
CPU time 4.11 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 214144 kb
Host smart-dcbe4ff4-af9a-4f74-b775-e44e01b960bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556895474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3556895474
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3975174450
Short name T184
Test name
Test status
Simulation time 787760170 ps
CPU time 5.72 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 205588 kb
Host smart-5f6ebaed-c4da-4d72-b4fa-adf3027566b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975174450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3975174450
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3289597353
Short name T983
Test name
Test status
Simulation time 1807265916 ps
CPU time 10.3 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205564 kb
Host smart-abded0cf-f21c-4c4c-b2b5-e5f92345df67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289597353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
289597353
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2730763373
Short name T926
Test name
Test status
Simulation time 4147684437 ps
CPU time 12.69 seconds
Started Jun 11 12:45:10 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 205620 kb
Host smart-6b4efb51-7bae-4426-9d40-608f71453509
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730763373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
730763373
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.466810865
Short name T978
Test name
Test status
Simulation time 34607147 ps
CPU time 1.52 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:14 PM PDT 24
Peak memory 205676 kb
Host smart-bfd12a7a-3386-45b4-bedf-583ffe46afba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466810865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.466810865
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1890334371
Short name T1065
Test name
Test status
Simulation time 220628074 ps
CPU time 1.52 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 205632 kb
Host smart-58515517-0554-4145-b58c-e5a48c51d599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890334371 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1890334371
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3055217582
Short name T1025
Test name
Test status
Simulation time 19446429 ps
CPU time 1.01 seconds
Started Jun 11 12:44:57 PM PDT 24
Finished Jun 11 12:45:00 PM PDT 24
Peak memory 205336 kb
Host smart-f4d6501b-f05a-4219-b138-24c22997e371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055217582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3055217582
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.582547542
Short name T1055
Test name
Test status
Simulation time 26364947 ps
CPU time 0.71 seconds
Started Jun 11 12:44:57 PM PDT 24
Finished Jun 11 12:44:59 PM PDT 24
Peak memory 205212 kb
Host smart-10a77327-cd09-4bf0-a15c-9e964ace897b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582547542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.582547542
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2062904574
Short name T1040
Test name
Test status
Simulation time 61643067 ps
CPU time 1.8 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 205560 kb
Host smart-449e6349-e089-4620-a8ff-e375b5cc911e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062904574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2062904574
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3081176018
Short name T997
Test name
Test status
Simulation time 597006273 ps
CPU time 2.12 seconds
Started Jun 11 12:44:47 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 214440 kb
Host smart-6cddf94b-d2de-44f0-af32-bd2c13617f4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081176018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3081176018
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.53200791
Short name T1052
Test name
Test status
Simulation time 205207079 ps
CPU time 5.94 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 220292 kb
Host smart-def25dc5-ea38-4d8f-a1d4-6b2c8e67f7e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53200791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.ke
ymgr_shadow_reg_errors_with_csr_rw.53200791
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1069284464
Short name T921
Test name
Test status
Simulation time 222678631 ps
CPU time 3.12 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 222200 kb
Host smart-c2a5502b-33c9-4ec1-b1a1-0950849ece61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069284464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1069284464
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3095315234
Short name T168
Test name
Test status
Simulation time 1076531323 ps
CPU time 10.96 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:33 PM PDT 24
Peak memory 205560 kb
Host smart-0d54499e-1eb2-4a17-a419-9d5b70a2d9ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095315234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3095315234
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.446231557
Short name T937
Test name
Test status
Simulation time 541010431 ps
CPU time 2.05 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 217356 kb
Host smart-238a32fc-653a-476f-9eed-bfcaae629f0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446231557 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.446231557
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4114911438
Short name T958
Test name
Test status
Simulation time 35518883 ps
CPU time 0.85 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 205400 kb
Host smart-446debec-c908-4239-b340-ee92e0448c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114911438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4114911438
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.184185796
Short name T929
Test name
Test status
Simulation time 48809792 ps
CPU time 0.73 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:04 PM PDT 24
Peak memory 205300 kb
Host smart-50afe1a2-e25d-46fd-9715-3a3cdea71696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184185796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.184185796
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1010498000
Short name T1010
Test name
Test status
Simulation time 450393223 ps
CPU time 4.15 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205588 kb
Host smart-92c54643-2911-4778-bb08-8e37e33d35b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010498000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1010498000
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1968113913
Short name T1006
Test name
Test status
Simulation time 76018672 ps
CPU time 1.74 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 214144 kb
Host smart-d5e487b2-4d3b-4b71-bce5-6d57f4726f17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968113913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1968113913
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.551612492
Short name T1001
Test name
Test status
Simulation time 159422043 ps
CPU time 8.36 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 214112 kb
Host smart-5b0d4c99-909b-481b-aec1-9dac94db50da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551612492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.551612492
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.437092877
Short name T956
Test name
Test status
Simulation time 204149082 ps
CPU time 2.68 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 221976 kb
Host smart-43271f9e-4c3b-4864-9a6e-960972fec000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437092877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.437092877
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.711502427
Short name T945
Test name
Test status
Simulation time 2774952838 ps
CPU time 4.19 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 213836 kb
Host smart-418fc8b6-f0ab-4af7-989c-a6752c6dcfa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711502427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.711502427
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3284546085
Short name T405
Test name
Test status
Simulation time 33770776 ps
CPU time 2.07 seconds
Started Jun 11 12:45:02 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 213784 kb
Host smart-511b5c4c-cef3-4275-b46e-5efdfe894c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284546085 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3284546085
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4108805722
Short name T151
Test name
Test status
Simulation time 11429278 ps
CPU time 0.99 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 205428 kb
Host smart-a19e1150-1521-4a62-965a-4f2766921b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108805722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4108805722
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1136900016
Short name T1042
Test name
Test status
Simulation time 28995728 ps
CPU time 0.78 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 205284 kb
Host smart-0130267b-57f1-4722-80dd-7d1881223898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136900016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1136900016
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1245450534
Short name T944
Test name
Test status
Simulation time 88132424 ps
CPU time 2.79 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:04 PM PDT 24
Peak memory 205628 kb
Host smart-27edd34c-6b2f-4d9b-a484-5b7a6f130688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245450534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1245450534
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.892577843
Short name T125
Test name
Test status
Simulation time 267966978 ps
CPU time 4.61 seconds
Started Jun 11 12:45:18 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 214112 kb
Host smart-62afd739-dfc3-411f-8b45-1ef1a8c423fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892577843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.892577843
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2535582700
Short name T1060
Test name
Test status
Simulation time 775042590 ps
CPU time 5.86 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 214172 kb
Host smart-83a1c97d-b164-4000-a516-023fe716bf20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535582700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2535582700
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3374087400
Short name T938
Test name
Test status
Simulation time 434388009 ps
CPU time 2.12 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 213820 kb
Host smart-5900e80e-c0e6-4269-981d-6e10eb7042a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374087400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3374087400
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3515459877
Short name T941
Test name
Test status
Simulation time 17086713 ps
CPU time 1.38 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 213808 kb
Host smart-5f249c97-c5e2-4817-85ce-4bd8d9c42d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515459877 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3515459877
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.678646882
Short name T1023
Test name
Test status
Simulation time 16373464 ps
CPU time 0.94 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 205264 kb
Host smart-c9195780-c45a-44df-9bbe-f6e579396ec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678646882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.678646882
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.472445383
Short name T952
Test name
Test status
Simulation time 16651777 ps
CPU time 0.91 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 205268 kb
Host smart-094be82a-e251-4b3a-b155-408ca119445f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472445383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.472445383
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2410363528
Short name T153
Test name
Test status
Simulation time 40906615 ps
CPU time 1.34 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:56 PM PDT 24
Peak memory 205540 kb
Host smart-808d099a-46fe-4fa5-bdfe-a9dcf8982442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410363528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2410363528
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3857886876
Short name T1032
Test name
Test status
Simulation time 245458321 ps
CPU time 5.57 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 214016 kb
Host smart-2bb146ad-b0d3-4b98-bf84-34bac4eafa08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857886876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3857886876
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2744651991
Short name T132
Test name
Test status
Simulation time 337690280 ps
CPU time 3.96 seconds
Started Jun 11 12:45:12 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 214076 kb
Host smart-97b54696-cfd1-4513-adf6-b95191a853b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744651991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2744651991
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.741344930
Short name T1011
Test name
Test status
Simulation time 231784322 ps
CPU time 2.72 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 213824 kb
Host smart-9e591de0-8323-4cc0-b0fd-1a510ad106cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741344930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.741344930
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.706137365
Short name T180
Test name
Test status
Simulation time 554548114 ps
CPU time 5.47 seconds
Started Jun 11 12:44:51 PM PDT 24
Finished Jun 11 12:44:58 PM PDT 24
Peak memory 213728 kb
Host smart-367f2d4b-13bd-4154-911b-ea8c98714f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706137365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.706137365
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1374312288
Short name T1027
Test name
Test status
Simulation time 54999251 ps
CPU time 1.32 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 213736 kb
Host smart-b8c23d5f-1a9d-42a4-a7a5-e48694907967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374312288 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1374312288
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2169449739
Short name T977
Test name
Test status
Simulation time 15163446 ps
CPU time 1.09 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 205552 kb
Host smart-e61ace52-f568-4172-8cf1-d18f2c170fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169449739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2169449739
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2976579114
Short name T935
Test name
Test status
Simulation time 20174959 ps
CPU time 0.73 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 205216 kb
Host smart-527f07a3-ce5c-4d97-ac24-63ce74569f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976579114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2976579114
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3907637899
Short name T1033
Test name
Test status
Simulation time 223970354 ps
CPU time 1.25 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:56 PM PDT 24
Peak memory 205560 kb
Host smart-8e3b0302-5a8b-4c0c-a242-d67ec4a3d340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907637899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3907637899
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3606106493
Short name T1085
Test name
Test status
Simulation time 418576155 ps
CPU time 9.71 seconds
Started Jun 11 12:45:20 PM PDT 24
Finished Jun 11 12:45:33 PM PDT 24
Peak memory 214164 kb
Host smart-aee0e7e8-4a1e-4670-8172-76166cb2ea0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606106493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3606106493
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2189612748
Short name T995
Test name
Test status
Simulation time 1585155445 ps
CPU time 3.29 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 215928 kb
Host smart-81ed2822-2f53-444f-b16d-d40990e180f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189612748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2189612748
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.14375067
Short name T970
Test name
Test status
Simulation time 43559472 ps
CPU time 1.94 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 213904 kb
Host smart-b47ee540-8978-499f-a392-53fb5126f072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375067 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.14375067
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4273366189
Short name T943
Test name
Test status
Simulation time 57807758 ps
CPU time 1.56 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 205628 kb
Host smart-4dc34354-672d-486d-8a7f-f1d1fa1fd08c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273366189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4273366189
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2046327236
Short name T1050
Test name
Test status
Simulation time 36758699 ps
CPU time 0.8 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:04 PM PDT 24
Peak memory 205292 kb
Host smart-c41ef193-8897-444b-b194-7680df3b5471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046327236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2046327236
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1234558153
Short name T1022
Test name
Test status
Simulation time 260709034 ps
CPU time 2.27 seconds
Started Jun 11 12:45:10 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 205520 kb
Host smart-c98afa00-3d1a-4ee0-9134-6e5232e92c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234558153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1234558153
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.921705095
Short name T1036
Test name
Test status
Simulation time 55529162 ps
CPU time 1.28 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:56 PM PDT 24
Peak memory 214160 kb
Host smart-54fcb9a3-9223-41b2-81b8-a1c9f08ab161
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921705095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.921705095
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2319563849
Short name T1015
Test name
Test status
Simulation time 193245411 ps
CPU time 5.14 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 220256 kb
Host smart-702a9343-7074-4102-a964-31b7687b1a24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319563849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2319563849
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1733618025
Short name T1074
Test name
Test status
Simulation time 116318382 ps
CPU time 2.48 seconds
Started Jun 11 12:45:21 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 213852 kb
Host smart-adec5e67-82de-48e0-a32c-1bcb3e26e05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733618025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1733618025
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1196933693
Short name T1046
Test name
Test status
Simulation time 66749964 ps
CPU time 2.5 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:24 PM PDT 24
Peak memory 213548 kb
Host smart-d2be5bfa-d948-4afd-960d-747c66689e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196933693 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1196933693
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3281422789
Short name T1019
Test name
Test status
Simulation time 28268790 ps
CPU time 1.05 seconds
Started Jun 11 12:45:07 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 205600 kb
Host smart-4630164e-8278-496d-a6ed-2cf4873cc9cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281422789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3281422789
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3407016320
Short name T1013
Test name
Test status
Simulation time 35686686 ps
CPU time 0.73 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:03 PM PDT 24
Peak memory 205204 kb
Host smart-c857e44b-40b2-4441-9d71-15740d60a5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407016320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3407016320
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.4191019191
Short name T155
Test name
Test status
Simulation time 85263561 ps
CPU time 2.43 seconds
Started Jun 11 12:45:12 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205656 kb
Host smart-ae8bcc18-25ab-459b-8945-0ec907987920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191019191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.4191019191
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2278073364
Short name T133
Test name
Test status
Simulation time 85381975 ps
CPU time 1.83 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 214160 kb
Host smart-a3dbdef8-dfba-4b89-90d0-b3b24d102b4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278073364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2278073364
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.272476558
Short name T1058
Test name
Test status
Simulation time 794960317 ps
CPU time 4.18 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 214240 kb
Host smart-3bcd3afc-6a5d-4788-b609-b07f89ecc823
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272476558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.272476558
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1018408830
Short name T1037
Test name
Test status
Simulation time 217312850 ps
CPU time 2.54 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 213796 kb
Host smart-40f1de39-7bc2-44d6-881a-f330878a3055
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018408830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1018408830
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2617431571
Short name T1079
Test name
Test status
Simulation time 20476975 ps
CPU time 1.16 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 213828 kb
Host smart-072d2218-7b9f-4004-9d7c-690684ea7b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617431571 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2617431571
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3852498297
Short name T946
Test name
Test status
Simulation time 40855871 ps
CPU time 0.98 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205288 kb
Host smart-ad92997e-a8e6-4280-ae72-6393a25a942d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852498297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3852498297
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3440026346
Short name T1043
Test name
Test status
Simulation time 105858043 ps
CPU time 0.69 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 205284 kb
Host smart-7746e051-efbe-4191-a861-e248e9576df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440026346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3440026346
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2070956504
Short name T154
Test name
Test status
Simulation time 82924352 ps
CPU time 3.4 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 205600 kb
Host smart-bc790b07-187d-4074-9f2c-5adbb84af13b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070956504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2070956504
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4111448921
Short name T1054
Test name
Test status
Simulation time 854593977 ps
CPU time 4.36 seconds
Started Jun 11 12:45:27 PM PDT 24
Finished Jun 11 12:45:33 PM PDT 24
Peak memory 214020 kb
Host smart-544c2d48-2f34-4a9e-9c83-2720c30452dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111448921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4111448921
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.216667192
Short name T966
Test name
Test status
Simulation time 165684434 ps
CPU time 3.61 seconds
Started Jun 11 12:45:12 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 214144 kb
Host smart-33c7b391-6792-4a41-b200-01cf3c049d4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216667192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.216667192
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1418512868
Short name T961
Test name
Test status
Simulation time 503917401 ps
CPU time 3 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 213824 kb
Host smart-6a5a9fd0-c5e8-418a-ba69-edbc9f31f91f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418512868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1418512868
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2188556632
Short name T175
Test name
Test status
Simulation time 334483934 ps
CPU time 10.95 seconds
Started Jun 11 12:45:02 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 213800 kb
Host smart-67572e91-bb8e-47e0-88b9-13855cb3e13a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188556632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2188556632
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2257873861
Short name T1080
Test name
Test status
Simulation time 202245884 ps
CPU time 1.76 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 213796 kb
Host smart-fe075945-b45c-4226-b7fb-cca18d830e7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257873861 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2257873861
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.993346898
Short name T1000
Test name
Test status
Simulation time 17083110 ps
CPU time 1.06 seconds
Started Jun 11 12:45:27 PM PDT 24
Finished Jun 11 12:45:30 PM PDT 24
Peak memory 205444 kb
Host smart-952930f2-36b6-4d7b-8391-a51c9ab679a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993346898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.993346898
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3163336372
Short name T979
Test name
Test status
Simulation time 66938128 ps
CPU time 0.99 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205288 kb
Host smart-c685fa7d-efa2-43d4-9e27-b2b0d4a5be7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163336372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3163336372
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2879876956
Short name T960
Test name
Test status
Simulation time 45602138 ps
CPU time 1.65 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 205644 kb
Host smart-9f5bc435-281b-4873-b6f7-62492ee8f2e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879876956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2879876956
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.827862756
Short name T1086
Test name
Test status
Simulation time 88440877 ps
CPU time 2.73 seconds
Started Jun 11 12:45:20 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 218484 kb
Host smart-6d32b427-0d68-4485-9184-44d91ab5a4f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827862756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.827862756
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1592304071
Short name T954
Test name
Test status
Simulation time 1764096962 ps
CPU time 15.82 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:32 PM PDT 24
Peak memory 214072 kb
Host smart-32e1edaf-c03f-4532-bb86-0a69fe37b902
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592304071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1592304071
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3119192891
Short name T1063
Test name
Test status
Simulation time 44183673 ps
CPU time 2.98 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 213704 kb
Host smart-f8e1c028-3db7-4c47-9327-bc5f1ac1ac88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119192891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3119192891
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2282143519
Short name T1084
Test name
Test status
Simulation time 114450843 ps
CPU time 2.25 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:20 PM PDT 24
Peak memory 213852 kb
Host smart-1caf0c5b-48db-48b9-894e-81943ead7fb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282143519 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2282143519
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3828030551
Short name T1003
Test name
Test status
Simulation time 87731452 ps
CPU time 0.99 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 205384 kb
Host smart-a2c304d7-4f46-47ec-8fbc-0006420271d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828030551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3828030551
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2272735445
Short name T1087
Test name
Test status
Simulation time 10188442 ps
CPU time 0.71 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205220 kb
Host smart-bb31a721-0cfc-4e80-b018-0b52248ba121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272735445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2272735445
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3208654226
Short name T948
Test name
Test status
Simulation time 119475963 ps
CPU time 3.35 seconds
Started Jun 11 12:45:23 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 205600 kb
Host smart-e1ba43da-a221-4514-af79-b0d5b707f497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208654226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3208654226
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4006434704
Short name T123
Test name
Test status
Simulation time 322660241 ps
CPU time 2.75 seconds
Started Jun 11 12:45:21 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 214224 kb
Host smart-91306958-e656-4432-be30-e4e823ef6852
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006434704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4006434704
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2200714369
Short name T127
Test name
Test status
Simulation time 323475809 ps
CPU time 3.66 seconds
Started Jun 11 12:45:10 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 220232 kb
Host smart-f24ba934-d074-4ac8-9f2e-43876b48a140
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200714369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2200714369
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3615755578
Short name T982
Test name
Test status
Simulation time 303331312 ps
CPU time 3.85 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 213780 kb
Host smart-f05c1c99-c571-41f2-94a2-e9c050da0e71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615755578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3615755578
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3182078437
Short name T1072
Test name
Test status
Simulation time 426569996 ps
CPU time 6.41 seconds
Started Jun 11 12:45:18 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 205524 kb
Host smart-db942937-830d-4274-85f4-a51d6a9326cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182078437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3182078437
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3017941788
Short name T1059
Test name
Test status
Simulation time 56422358 ps
CPU time 1.63 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213876 kb
Host smart-b56bd558-e261-4819-bf76-ad4a2fcc3a4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017941788 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3017941788
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.611107687
Short name T955
Test name
Test status
Simulation time 28821108 ps
CPU time 1.1 seconds
Started Jun 11 12:45:21 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 205548 kb
Host smart-b813ff12-850c-453f-a595-4aa9a8445bd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611107687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.611107687
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2905040176
Short name T936
Test name
Test status
Simulation time 190451230 ps
CPU time 0.8 seconds
Started Jun 11 12:45:18 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 205196 kb
Host smart-217f10aa-d5c3-4b43-a91d-289df99bd3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905040176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2905040176
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1600954238
Short name T980
Test name
Test status
Simulation time 20814603 ps
CPU time 1.56 seconds
Started Jun 11 12:45:16 PM PDT 24
Finished Jun 11 12:45:20 PM PDT 24
Peak memory 205688 kb
Host smart-b0e79d31-6c06-41fa-9e99-6a72edd3733c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600954238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1600954238
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3052705102
Short name T1088
Test name
Test status
Simulation time 521720324 ps
CPU time 3.27 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 214092 kb
Host smart-36495540-8ff4-4cf2-bc0f-eaee3b6a7509
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052705102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3052705102
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2040993938
Short name T987
Test name
Test status
Simulation time 90880094 ps
CPU time 4.12 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 214128 kb
Host smart-059c9fcb-ee8e-49c1-88af-20b5be37e0a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040993938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2040993938
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1754234777
Short name T984
Test name
Test status
Simulation time 174150419 ps
CPU time 1.94 seconds
Started Jun 11 12:45:23 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 213864 kb
Host smart-95c37094-a22e-4b8f-b141-143d5bbfeedb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754234777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1754234777
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.485409505
Short name T186
Test name
Test status
Simulation time 204495158 ps
CPU time 4.82 seconds
Started Jun 11 12:45:07 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 213732 kb
Host smart-9fd32b27-617c-4b7b-a6e6-2255ac38757d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485409505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.485409505
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.755692960
Short name T1031
Test name
Test status
Simulation time 380668621 ps
CPU time 7.62 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 205628 kb
Host smart-54383684-edc6-4580-a6c9-012adcf1eb5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755692960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.755692960
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1452130937
Short name T1081
Test name
Test status
Simulation time 1533462494 ps
CPU time 8.82 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:20 PM PDT 24
Peak memory 205592 kb
Host smart-21d1d738-d24c-4a38-aa27-64207278527e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452130937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
452130937
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1809737394
Short name T976
Test name
Test status
Simulation time 17328752 ps
CPU time 1.12 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:05 PM PDT 24
Peak memory 205552 kb
Host smart-f23d6ac9-5c7d-4ef7-b1c9-ab9027f73be1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809737394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
809737394
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1771944217
Short name T1012
Test name
Test status
Simulation time 110676172 ps
CPU time 1.23 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 213808 kb
Host smart-e251a858-65a6-4ec9-87c8-b1d2bd777e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771944217 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1771944217
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1350209475
Short name T1044
Test name
Test status
Simulation time 59083049 ps
CPU time 1.23 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 205680 kb
Host smart-8c01c17a-fb63-4700-88c7-63e498d6610c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350209475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1350209475
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2935006680
Short name T1009
Test name
Test status
Simulation time 10379741 ps
CPU time 0.86 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 205488 kb
Host smart-9e997b86-80cd-491f-867d-bf4c14d14e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935006680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2935006680
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3590300081
Short name T998
Test name
Test status
Simulation time 88017429 ps
CPU time 1.38 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 205668 kb
Host smart-6b6b0135-d667-4b01-886a-b749070df90a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590300081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3590300081
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2506105536
Short name T129
Test name
Test status
Simulation time 101313039 ps
CPU time 2.86 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 214424 kb
Host smart-061c2442-89be-4837-9a59-79821a1e4aa0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506105536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2506105536
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1786540380
Short name T964
Test name
Test status
Simulation time 266913277 ps
CPU time 8.84 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 214108 kb
Host smart-ded50781-bafd-4f6a-8aba-3ba55d594e03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786540380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1786540380
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2746771506
Short name T923
Test name
Test status
Simulation time 272004569 ps
CPU time 1.82 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:43 PM PDT 24
Peak memory 213996 kb
Host smart-9a7e54fa-5813-4c3d-8b2a-db693dd931f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746771506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2746771506
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2239700573
Short name T167
Test name
Test status
Simulation time 102652095 ps
CPU time 3.06 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:14 PM PDT 24
Peak memory 205520 kb
Host smart-6876b64e-b66c-4268-bc00-318e75770d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239700573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2239700573
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.736559016
Short name T968
Test name
Test status
Simulation time 12988415 ps
CPU time 0.73 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 205248 kb
Host smart-aac0e3f9-9789-49ad-a59d-351af65a98fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736559016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.736559016
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3942980468
Short name T949
Test name
Test status
Simulation time 18226488 ps
CPU time 0.92 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205408 kb
Host smart-509f5c68-37ae-44da-87cc-679764880402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942980468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3942980468
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1724621559
Short name T1073
Test name
Test status
Simulation time 51945531 ps
CPU time 0.74 seconds
Started Jun 11 12:45:16 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 205212 kb
Host smart-14fd5718-1a88-46b1-b24f-ac7f835944d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724621559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1724621559
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1780377213
Short name T1077
Test name
Test status
Simulation time 10524032 ps
CPU time 0.84 seconds
Started Jun 11 12:45:07 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 205288 kb
Host smart-0b93ae5a-9b71-4c38-9d20-9925bc59c556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780377213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1780377213
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.727107150
Short name T1057
Test name
Test status
Simulation time 49063425 ps
CPU time 0.68 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:45:32 PM PDT 24
Peak memory 205292 kb
Host smart-573b9771-bd96-4b88-bc87-77f004493a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727107150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.727107150
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3715150678
Short name T1076
Test name
Test status
Simulation time 21076520 ps
CPU time 0.8 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205280 kb
Host smart-a9cfa157-1b9b-4fc6-bd1a-1e3dd3716dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715150678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3715150678
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1880407602
Short name T942
Test name
Test status
Simulation time 36762388 ps
CPU time 0.71 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 205244 kb
Host smart-7b8c7465-c467-4e99-b518-cdb7ca194ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880407602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1880407602
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2413395744
Short name T988
Test name
Test status
Simulation time 11298154 ps
CPU time 0.77 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205296 kb
Host smart-51d60b7a-ce25-412e-8a50-ced18f962f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413395744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2413395744
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1216326914
Short name T1068
Test name
Test status
Simulation time 8089117 ps
CPU time 0.83 seconds
Started Jun 11 12:45:12 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 205204 kb
Host smart-aa5d6130-9769-47ff-8522-b63313bff703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216326914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1216326914
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2483841183
Short name T927
Test name
Test status
Simulation time 34753909 ps
CPU time 0.75 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 205240 kb
Host smart-fd4fcff4-7670-4ab9-8b52-95af25404e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483841183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2483841183
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1519424254
Short name T1071
Test name
Test status
Simulation time 397244759 ps
CPU time 7.61 seconds
Started Jun 11 12:45:16 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 205624 kb
Host smart-a0d25b41-31f5-42fd-8b47-2daac3347b81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519424254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
519424254
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1884679199
Short name T993
Test name
Test status
Simulation time 21562246609 ps
CPU time 32.98 seconds
Started Jun 11 12:44:52 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 205672 kb
Host smart-8a8da9a9-ad7e-4401-b0e8-4c8fdd6b3932
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884679199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
884679199
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1780618655
Short name T1014
Test name
Test status
Simulation time 30862503 ps
CPU time 1.12 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:44:59 PM PDT 24
Peak memory 213768 kb
Host smart-9fd1845f-5bcb-47cd-8e93-c8cd43be50a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780618655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
780618655
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3892777350
Short name T971
Test name
Test status
Simulation time 56582142 ps
CPU time 2.45 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 213908 kb
Host smart-f458a6b4-96fd-4dfa-b2ef-a5e2ae21c61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892777350 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3892777350
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1482861689
Short name T1062
Test name
Test status
Simulation time 42367758 ps
CPU time 0.94 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 205288 kb
Host smart-e519bf57-fb2e-4af9-8918-c9478dfd21a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482861689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1482861689
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3770313633
Short name T1016
Test name
Test status
Simulation time 29847381 ps
CPU time 0.76 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 205168 kb
Host smart-2cb98605-aa0f-49b6-8f78-d840c5e1e6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770313633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3770313633
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3393815925
Short name T994
Test name
Test status
Simulation time 18260350 ps
CPU time 1.38 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213844 kb
Host smart-944025c8-1eb4-4547-86a7-a46d54a13a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393815925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3393815925
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1411777924
Short name T990
Test name
Test status
Simulation time 532946121 ps
CPU time 1.46 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 214092 kb
Host smart-b4c1c972-8c18-4033-a50e-686e92eca0d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411777924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1411777924
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1923272916
Short name T1075
Test name
Test status
Simulation time 349702759 ps
CPU time 5.09 seconds
Started Jun 11 12:45:07 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 220480 kb
Host smart-9cad4f8d-e626-42da-8cbd-bf6e20c641ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923272916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1923272916
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1025227382
Short name T934
Test name
Test status
Simulation time 130181259 ps
CPU time 2.27 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 213908 kb
Host smart-cb10ef27-4a8d-4c7f-b2ad-26cf2518a0da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025227382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1025227382
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2684146188
Short name T972
Test name
Test status
Simulation time 377028896 ps
CPU time 2.72 seconds
Started Jun 11 12:44:57 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 215056 kb
Host smart-99eb1d1a-699e-40eb-b34f-9adb3b947146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684146188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2684146188
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1335178611
Short name T1035
Test name
Test status
Simulation time 37602677 ps
CPU time 0.79 seconds
Started Jun 11 12:45:23 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 205204 kb
Host smart-84b9fd3e-0198-433e-9c7c-759ec9b66c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335178611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1335178611
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2794945672
Short name T963
Test name
Test status
Simulation time 31123783 ps
CPU time 0.72 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 205212 kb
Host smart-bb8b618a-d23b-4d95-9508-c780ec7e5f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794945672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2794945672
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4176733976
Short name T940
Test name
Test status
Simulation time 9996198 ps
CPU time 0.85 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 205204 kb
Host smart-2c0745b8-da82-4b8f-954e-5f3bd8fc3c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176733976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4176733976
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2138459922
Short name T939
Test name
Test status
Simulation time 30059940 ps
CPU time 0.71 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205248 kb
Host smart-b9b94ec6-3fdb-4aad-a29d-1ef2abd0a0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138459922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2138459922
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.242114931
Short name T999
Test name
Test status
Simulation time 9269309 ps
CPU time 0.79 seconds
Started Jun 11 12:45:20 PM PDT 24
Finished Jun 11 12:45:23 PM PDT 24
Peak memory 205204 kb
Host smart-15a77db3-a909-4fbb-8e1e-2d7ea0d30fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242114931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.242114931
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3862669075
Short name T1038
Test name
Test status
Simulation time 8590646 ps
CPU time 0.67 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 205152 kb
Host smart-4031b831-4d3e-44f8-a952-c37dd90193fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862669075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3862669075
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1488033675
Short name T931
Test name
Test status
Simulation time 20662660 ps
CPU time 0.83 seconds
Started Jun 11 12:45:10 PM PDT 24
Finished Jun 11 12:45:13 PM PDT 24
Peak memory 205212 kb
Host smart-59cbbb2d-9fea-4b73-9124-1a790960ee50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488033675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1488033675
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1773737089
Short name T1078
Test name
Test status
Simulation time 9439503 ps
CPU time 0.7 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205100 kb
Host smart-f9c2dea8-519f-423b-8734-14c18c7fc75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773737089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1773737089
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.557200205
Short name T973
Test name
Test status
Simulation time 8907162 ps
CPU time 0.72 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 205248 kb
Host smart-2367bf9c-104b-4b73-a274-48214505cc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557200205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.557200205
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2423598826
Short name T920
Test name
Test status
Simulation time 14132481 ps
CPU time 0.87 seconds
Started Jun 11 12:45:12 PM PDT 24
Finished Jun 11 12:45:20 PM PDT 24
Peak memory 205436 kb
Host smart-770b5037-d5d2-4c91-9bd6-54c0d3aedde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423598826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2423598826
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1310938705
Short name T156
Test name
Test status
Simulation time 135522229 ps
CPU time 4.04 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 205636 kb
Host smart-0182c781-e486-4864-8845-37077303f989
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310938705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
310938705
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.929373029
Short name T925
Test name
Test status
Simulation time 679887290 ps
CPU time 15.8 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 205640 kb
Host smart-30c5496d-9bef-4193-a55b-e2482e434540
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929373029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.929373029
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2373627249
Short name T1051
Test name
Test status
Simulation time 65211239 ps
CPU time 1.04 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 205620 kb
Host smart-a1b71b1e-7a87-46f2-a804-37ba3549f288
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373627249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
373627249
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.220051446
Short name T1007
Test name
Test status
Simulation time 545280886 ps
CPU time 2.18 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 213808 kb
Host smart-2ec34132-8ec4-4149-a955-b42393d9bc68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220051446 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.220051446
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1395456249
Short name T1047
Test name
Test status
Simulation time 68125509 ps
CPU time 1.21 seconds
Started Jun 11 12:45:17 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 205620 kb
Host smart-a636c416-8596-4870-88ac-99206fdcc219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395456249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1395456249
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1459412328
Short name T1048
Test name
Test status
Simulation time 9390706 ps
CPU time 0.76 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:45:05 PM PDT 24
Peak memory 205212 kb
Host smart-b097f279-e46c-447f-b856-b4551ae0db2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459412328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1459412328
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2020252090
Short name T1017
Test name
Test status
Simulation time 220517649 ps
CPU time 3.56 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:14 PM PDT 24
Peak memory 205640 kb
Host smart-62822a94-865d-42ee-9746-c21d617e5ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020252090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2020252090
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.421455342
Short name T975
Test name
Test status
Simulation time 111337294 ps
CPU time 3.09 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:13 PM PDT 24
Peak memory 214212 kb
Host smart-0cd1c57b-6a0a-4530-afd6-f498b0eda4d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421455342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.421455342
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3188877056
Short name T1067
Test name
Test status
Simulation time 359056912 ps
CPU time 7.97 seconds
Started Jun 11 12:45:27 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 214444 kb
Host smart-80c6a3d5-5357-4193-81e2-ab15a97d7f3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188877056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3188877056
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3016192448
Short name T969
Test name
Test status
Simulation time 19886075 ps
CPU time 1.65 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 213832 kb
Host smart-aaedd09d-22c7-48de-950c-a5c2ed93b808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016192448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3016192448
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3429258236
Short name T996
Test name
Test status
Simulation time 3305522686 ps
CPU time 7.96 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213728 kb
Host smart-b6cc7297-7d8c-4103-b9d4-d301c09e24b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429258236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3429258236
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3550307323
Short name T1020
Test name
Test status
Simulation time 34998690 ps
CPU time 0.71 seconds
Started Jun 11 12:45:18 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 205192 kb
Host smart-dcab4160-2392-4995-bbd9-c8128cbef4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550307323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3550307323
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1575715535
Short name T1004
Test name
Test status
Simulation time 68916225 ps
CPU time 0.68 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:14 PM PDT 24
Peak memory 205156 kb
Host smart-f471a5dd-6ac2-4048-bd78-0e58918af0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575715535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1575715535
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1012876086
Short name T962
Test name
Test status
Simulation time 11796190 ps
CPU time 0.69 seconds
Started Jun 11 12:45:25 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 205280 kb
Host smart-b9df49fc-114c-48b3-b95b-4c5f6f4c0655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012876086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1012876086
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1823104424
Short name T932
Test name
Test status
Simulation time 12573586 ps
CPU time 0.83 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 205272 kb
Host smart-9d4c641f-bcbd-4b06-a166-a461e66c1eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823104424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1823104424
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1387510809
Short name T930
Test name
Test status
Simulation time 61774861 ps
CPU time 0.82 seconds
Started Jun 11 12:45:22 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 205284 kb
Host smart-ef88237e-fc5a-4b20-a4a8-a81da8c7010c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387510809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1387510809
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2225328146
Short name T1056
Test name
Test status
Simulation time 40276563 ps
CPU time 0.76 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205168 kb
Host smart-b2bd9cfb-72a9-4ce2-b1c8-7af18cb3e39f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225328146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2225328146
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1068254203
Short name T985
Test name
Test status
Simulation time 19860628 ps
CPU time 0.7 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 205204 kb
Host smart-11a93fa6-109d-4209-9403-47551062cedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068254203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1068254203
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1711971315
Short name T1005
Test name
Test status
Simulation time 30592546 ps
CPU time 0.8 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205268 kb
Host smart-fb2471ed-3339-4c64-be0b-fdc77e184ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711971315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1711971315
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2558418254
Short name T959
Test name
Test status
Simulation time 61109954 ps
CPU time 0.77 seconds
Started Jun 11 12:45:16 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 205268 kb
Host smart-9a851acb-d527-48bb-819a-a82858d2d990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558418254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2558418254
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2983842965
Short name T1030
Test name
Test status
Simulation time 33180837 ps
CPU time 0.82 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 205204 kb
Host smart-d9140ba2-a86e-487e-bb54-103bb5fbcf3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983842965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2983842965
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2851445041
Short name T974
Test name
Test status
Simulation time 504019032 ps
CPU time 2.49 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213896 kb
Host smart-8bfb281e-706f-4259-973b-ee5e7671052d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851445041 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2851445041
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2986032495
Short name T1069
Test name
Test status
Simulation time 14661798 ps
CPU time 1.05 seconds
Started Jun 11 12:45:10 PM PDT 24
Finished Jun 11 12:45:13 PM PDT 24
Peak memory 205544 kb
Host smart-aa35c2de-b7b0-4210-aefc-7d46d9d9f4cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986032495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2986032495
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.813009685
Short name T1041
Test name
Test status
Simulation time 10001034 ps
CPU time 0.71 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 205252 kb
Host smart-90cd00ce-0821-4387-be10-673b91f354a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813009685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.813009685
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.348944970
Short name T981
Test name
Test status
Simulation time 68853315 ps
CPU time 1.32 seconds
Started Jun 11 12:45:18 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 205640 kb
Host smart-6e79c119-e0f1-4a51-9260-0399b170346a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348944970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.348944970
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1209000071
Short name T130
Test name
Test status
Simulation time 185651184 ps
CPU time 3.19 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 214440 kb
Host smart-9950ff6c-d0a4-4437-8928-496488a450cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209000071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1209000071
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.638369491
Short name T922
Test name
Test status
Simulation time 164731695 ps
CPU time 2.89 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:20 PM PDT 24
Peak memory 221976 kb
Host smart-4dd3ce00-93b2-4e0b-a06e-a0648783e7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638369491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.638369491
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3373758405
Short name T1002
Test name
Test status
Simulation time 275408280 ps
CPU time 10.14 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 213744 kb
Host smart-cbb81ede-2603-4185-9357-fbb0edd7521f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373758405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3373758405
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2229452647
Short name T989
Test name
Test status
Simulation time 48795765 ps
CPU time 1.68 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 213840 kb
Host smart-dd5df27b-d5ed-4eb9-abaf-466cf6c86794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229452647 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2229452647
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1503401564
Short name T173
Test name
Test status
Simulation time 21210713 ps
CPU time 1.02 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 205428 kb
Host smart-8d67b789-0bf1-40a2-9ad0-c865d7e94255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503401564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1503401564
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.489243520
Short name T924
Test name
Test status
Simulation time 28982421 ps
CPU time 0.72 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 205200 kb
Host smart-52efabb5-d1eb-4acf-a798-5a985b3bb720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489243520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.489243520
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1875130397
Short name T152
Test name
Test status
Simulation time 57195571 ps
CPU time 2.17 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:10 PM PDT 24
Peak memory 205492 kb
Host smart-f56ef5fe-4f52-426c-9a76-997dc71b7d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875130397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1875130397
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2050498025
Short name T131
Test name
Test status
Simulation time 397618369 ps
CPU time 2.2 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 214208 kb
Host smart-6c1c4f4c-54db-42e0-aa89-3d7c2e722e85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050498025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2050498025
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1741469173
Short name T986
Test name
Test status
Simulation time 843467940 ps
CPU time 6.03 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 214152 kb
Host smart-da721f1f-d4f7-44bc-93c1-649a5af8a0a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741469173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1741469173
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1114373796
Short name T950
Test name
Test status
Simulation time 46386702 ps
CPU time 2.75 seconds
Started Jun 11 12:45:21 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 213712 kb
Host smart-2f99b446-6793-49db-99fd-8b9740e38ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114373796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1114373796
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.512947344
Short name T1008
Test name
Test status
Simulation time 29797668 ps
CPU time 1.92 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 213948 kb
Host smart-01f4e6ae-3488-4ad8-8c7f-d0aece3099ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512947344 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.512947344
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1854152094
Short name T1029
Test name
Test status
Simulation time 108052625 ps
CPU time 1.4 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:05 PM PDT 24
Peak memory 205544 kb
Host smart-55d8411f-bbeb-42b5-a3cb-6a2c99569343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854152094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1854152094
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2314388523
Short name T953
Test name
Test status
Simulation time 20893446 ps
CPU time 0.89 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:23 PM PDT 24
Peak memory 205040 kb
Host smart-6c079043-d5bc-4f9c-b430-650b95b6aa87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314388523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2314388523
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3313745031
Short name T1083
Test name
Test status
Simulation time 34068169 ps
CPU time 1.58 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:58 PM PDT 24
Peak memory 205460 kb
Host smart-1139f743-1406-483f-a368-e0295e2f3121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313745031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3313745031
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1179623467
Short name T121
Test name
Test status
Simulation time 39215663 ps
CPU time 1.31 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:45:00 PM PDT 24
Peak memory 214096 kb
Host smart-0514bd78-cea7-45b0-a283-245496d4f62a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179623467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1179623467
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3769959705
Short name T1021
Test name
Test status
Simulation time 384339694 ps
CPU time 6.73 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 214304 kb
Host smart-862548a9-1580-4dd3-92f3-c40490e2cbae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769959705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3769959705
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3982150672
Short name T951
Test name
Test status
Simulation time 109544086 ps
CPU time 3.29 seconds
Started Jun 11 12:45:08 PM PDT 24
Finished Jun 11 12:45:14 PM PDT 24
Peak memory 213736 kb
Host smart-117cc838-b47e-48f7-9399-20b80f708d60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982150672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3982150672
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.403513599
Short name T166
Test name
Test status
Simulation time 102102077 ps
CPU time 1.84 seconds
Started Jun 11 12:45:07 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 218180 kb
Host smart-f2b7d1f9-8616-4a36-be43-7278b01ec606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403513599 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.403513599
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.196219563
Short name T928
Test name
Test status
Simulation time 39275508 ps
CPU time 1.01 seconds
Started Jun 11 12:45:06 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 205336 kb
Host smart-a537c468-ce43-4dbc-83b5-ab29cfc9003c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196219563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.196219563
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2344367668
Short name T991
Test name
Test status
Simulation time 31599738 ps
CPU time 0.81 seconds
Started Jun 11 12:45:21 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 205312 kb
Host smart-77419f89-ba9c-4403-9509-f08b3227aa8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344367668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2344367668
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4106802526
Short name T150
Test name
Test status
Simulation time 59769878 ps
CPU time 2.31 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:24 PM PDT 24
Peak memory 205556 kb
Host smart-b6e3448a-ae21-47f8-9850-4c00a3557902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106802526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.4106802526
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3979191866
Short name T1018
Test name
Test status
Simulation time 179158295 ps
CPU time 3.18 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 214168 kb
Host smart-2b917b03-0ef9-45df-83da-bac2d4398c19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979191866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3979191866
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3199989271
Short name T947
Test name
Test status
Simulation time 1656517067 ps
CPU time 8.4 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:45:05 PM PDT 24
Peak memory 214120 kb
Host smart-552653ba-0de5-4ba6-b2e7-56d536c4a070
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199989271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3199989271
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2496327762
Short name T1049
Test name
Test status
Simulation time 531944112 ps
CPU time 3.52 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:59 PM PDT 24
Peak memory 213724 kb
Host smart-2f9a0fa5-ba85-47b3-848e-8c3597afceb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496327762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2496327762
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4291726786
Short name T967
Test name
Test status
Simulation time 105711074 ps
CPU time 1.56 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:17 PM PDT 24
Peak memory 213656 kb
Host smart-e98a808c-219e-429b-a9a9-e1aec2750e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291726786 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4291726786
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3214800655
Short name T1061
Test name
Test status
Simulation time 172442642 ps
CPU time 1.01 seconds
Started Jun 11 12:45:02 PM PDT 24
Finished Jun 11 12:45:05 PM PDT 24
Peak memory 205540 kb
Host smart-9a0fbead-7db8-41bd-9de9-385f48015cb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214800655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3214800655
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2547963697
Short name T1039
Test name
Test status
Simulation time 32388569 ps
CPU time 0.81 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:55 PM PDT 24
Peak memory 205196 kb
Host smart-7a682d09-329f-475d-9372-9e560c03a61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547963697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2547963697
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2152695257
Short name T1082
Test name
Test status
Simulation time 67559568 ps
CPU time 1.84 seconds
Started Jun 11 12:45:20 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 205536 kb
Host smart-33713570-b13c-4b06-bef8-87f5adbbe785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152695257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2152695257
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2759578220
Short name T992
Test name
Test status
Simulation time 349969997 ps
CPU time 2.83 seconds
Started Jun 11 12:45:02 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 214220 kb
Host smart-cda46eec-fab8-4ebb-b6c7-59f314a62c78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759578220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2759578220
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.531099928
Short name T1066
Test name
Test status
Simulation time 911306352 ps
CPU time 16.44 seconds
Started Jun 11 12:45:07 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 214164 kb
Host smart-31a6d289-86db-4579-b2d8-0e3a55803211
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531099928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.531099928
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1030663437
Short name T1045
Test name
Test status
Simulation time 95201300 ps
CPU time 1.86 seconds
Started Jun 11 12:45:03 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 213784 kb
Host smart-dd53f18f-d63e-40a1-8f28-3374f17413be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030663437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1030663437
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4112835905
Short name T179
Test name
Test status
Simulation time 330414560 ps
CPU time 4.32 seconds
Started Jun 11 12:45:19 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 213824 kb
Host smart-e3b273dd-02eb-41ee-afa8-0157137f9613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112835905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.4112835905
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3995500950
Short name T448
Test name
Test status
Simulation time 56386228 ps
CPU time 0.7 seconds
Started Jun 11 12:47:58 PM PDT 24
Finished Jun 11 12:48:01 PM PDT 24
Peak memory 205976 kb
Host smart-2dff4928-2d1f-4011-aa8d-de1cae03818c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995500950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3995500950
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.776922974
Short name T276
Test name
Test status
Simulation time 37197177 ps
CPU time 2.94 seconds
Started Jun 11 12:48:03 PM PDT 24
Finished Jun 11 12:48:08 PM PDT 24
Peak memory 214372 kb
Host smart-297a8672-9977-4151-ba6e-6da6a089edee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776922974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.776922974
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.120736824
Short name T265
Test name
Test status
Simulation time 573523160 ps
CPU time 2.31 seconds
Started Jun 11 12:47:55 PM PDT 24
Finished Jun 11 12:48:00 PM PDT 24
Peak memory 214412 kb
Host smart-550a1cb3-2fe0-441f-a7e5-a3d33fb01e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120736824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.120736824
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1477798169
Short name T570
Test name
Test status
Simulation time 144958281 ps
CPU time 5.06 seconds
Started Jun 11 12:48:08 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 214272 kb
Host smart-bd99c985-b333-4a9c-87b5-3d58885d5c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477798169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1477798169
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2293399704
Short name T581
Test name
Test status
Simulation time 53823987 ps
CPU time 3.05 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 209900 kb
Host smart-6abd49b4-fd17-4aeb-b14b-9b4452d79a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293399704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2293399704
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2971073184
Short name T439
Test name
Test status
Simulation time 1098710807 ps
CPU time 27.45 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 214340 kb
Host smart-22de66b9-5e9b-4cd5-9b5c-b0e3ebf124fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971073184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2971073184
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.723238268
Short name T295
Test name
Test status
Simulation time 537499099 ps
CPU time 4.35 seconds
Started Jun 11 12:47:57 PM PDT 24
Finished Jun 11 12:48:03 PM PDT 24
Peak memory 208692 kb
Host smart-60b38822-09cb-4b7d-be8e-ffe106ef97dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723238268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.723238268
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2609346150
Short name T765
Test name
Test status
Simulation time 351757626 ps
CPU time 4.24 seconds
Started Jun 11 12:47:52 PM PDT 24
Finished Jun 11 12:47:59 PM PDT 24
Peak memory 209176 kb
Host smart-d495a684-6e4c-4ac7-9dd6-5e144733f580
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609346150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2609346150
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.173393392
Short name T686
Test name
Test status
Simulation time 20994302 ps
CPU time 1.78 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:15 PM PDT 24
Peak memory 206936 kb
Host smart-9f37f46e-92b3-4ace-bb75-98799105d6bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173393392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.173393392
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3584004063
Short name T688
Test name
Test status
Simulation time 1126559500 ps
CPU time 2.78 seconds
Started Jun 11 12:47:53 PM PDT 24
Finished Jun 11 12:47:59 PM PDT 24
Peak memory 209500 kb
Host smart-adf57769-0fd3-4211-ad6e-36308b0e74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584004063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3584004063
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1708053421
Short name T839
Test name
Test status
Simulation time 419139983 ps
CPU time 2.94 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:05 PM PDT 24
Peak memory 206796 kb
Host smart-1b4c3e08-da01-4175-bb64-6d682b58870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708053421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1708053421
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3907420765
Short name T273
Test name
Test status
Simulation time 4278325589 ps
CPU time 86.29 seconds
Started Jun 11 12:47:57 PM PDT 24
Finished Jun 11 12:49:26 PM PDT 24
Peak memory 209852 kb
Host smart-d07961fd-b9bb-49a7-a459-93889593280b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907420765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3907420765
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3415156181
Short name T680
Test name
Test status
Simulation time 210097555 ps
CPU time 6.08 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:15 PM PDT 24
Peak memory 209748 kb
Host smart-874c02e3-0319-45fc-be53-309942551af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415156181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3415156181
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3058982563
Short name T138
Test name
Test status
Simulation time 181418781 ps
CPU time 2.39 seconds
Started Jun 11 12:47:58 PM PDT 24
Finished Jun 11 12:48:02 PM PDT 24
Peak memory 210056 kb
Host smart-9260d16d-31c6-450a-a93f-ad743123edef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058982563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3058982563
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3708081647
Short name T905
Test name
Test status
Simulation time 23681375 ps
CPU time 1 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 206204 kb
Host smart-0119c2b0-be87-452d-8fec-4b04c5329c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708081647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3708081647
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2413461563
Short name T303
Test name
Test status
Simulation time 424928958 ps
CPU time 13.63 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 218296 kb
Host smart-70484527-7e96-4ad7-b5b2-8076e43dcccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413461563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2413461563
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2828457922
Short name T305
Test name
Test status
Simulation time 180195027 ps
CPU time 2.94 seconds
Started Jun 11 12:47:55 PM PDT 24
Finished Jun 11 12:48:01 PM PDT 24
Peak memory 214396 kb
Host smart-261574da-8460-4c50-a01e-a5f2848a5bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828457922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2828457922
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.483310057
Short name T100
Test name
Test status
Simulation time 38168192 ps
CPU time 2.17 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:04 PM PDT 24
Peak memory 214284 kb
Host smart-e2a04e9b-a690-45f0-8845-563be2d3412a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483310057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.483310057
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1157552133
Short name T846
Test name
Test status
Simulation time 28450413 ps
CPU time 2.14 seconds
Started Jun 11 12:48:01 PM PDT 24
Finished Jun 11 12:48:05 PM PDT 24
Peak memory 208284 kb
Host smart-71a58aa3-265f-4ec4-9289-9f86ece4c5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157552133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1157552133
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1162729184
Short name T559
Test name
Test status
Simulation time 247124127 ps
CPU time 3.16 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:04 PM PDT 24
Peak memory 218432 kb
Host smart-60d7d795-1be7-4b46-98ba-9bce127f58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162729184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1162729184
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3484532742
Short name T345
Test name
Test status
Simulation time 496945631 ps
CPU time 4.98 seconds
Started Jun 11 12:47:51 PM PDT 24
Finished Jun 11 12:47:58 PM PDT 24
Peak memory 208560 kb
Host smart-aef59e0c-aaa2-4869-b7a4-c4d7c90807a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484532742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3484532742
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1360851415
Short name T609
Test name
Test status
Simulation time 4023981831 ps
CPU time 25.71 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 208716 kb
Host smart-c3198360-ba29-4545-b4ef-cc557c33d868
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360851415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1360851415
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1542377164
Short name T850
Test name
Test status
Simulation time 711211366 ps
CPU time 18.05 seconds
Started Jun 11 12:48:03 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 208600 kb
Host smart-58bd4269-4fe4-476b-b7fe-0abe3f170c57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542377164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1542377164
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3832293947
Short name T665
Test name
Test status
Simulation time 157803453 ps
CPU time 2.28 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 206796 kb
Host smart-afbb6ea2-1ff8-41c5-b5fa-8bfdb6a62fcb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832293947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3832293947
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1177014765
Short name T816
Test name
Test status
Simulation time 59608930 ps
CPU time 3.18 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:05 PM PDT 24
Peak memory 215944 kb
Host smart-36342e33-4f51-4b7e-bfe6-ff3f3a3b2571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177014765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1177014765
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2280569456
Short name T89
Test name
Test status
Simulation time 38875601 ps
CPU time 2 seconds
Started Jun 11 12:47:57 PM PDT 24
Finished Jun 11 12:48:01 PM PDT 24
Peak memory 206928 kb
Host smart-ab215db5-8714-46ac-ba07-477b53cb4f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280569456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2280569456
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3032678324
Short name T667
Test name
Test status
Simulation time 185720191 ps
CPU time 2.49 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 207100 kb
Host smart-20055168-e4ad-4e9b-8aff-444a013971db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032678324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3032678324
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3438023347
Short name T895
Test name
Test status
Simulation time 44535173 ps
CPU time 2.13 seconds
Started Jun 11 12:47:51 PM PDT 24
Finished Jun 11 12:47:55 PM PDT 24
Peak memory 210316 kb
Host smart-c2c5a2f6-2c05-497b-8656-86f458362011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438023347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3438023347
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3408854179
Short name T628
Test name
Test status
Simulation time 11604452 ps
CPU time 0.74 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:24 PM PDT 24
Peak memory 205988 kb
Host smart-c09e19d5-9f5e-4468-9582-eb833ba23ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408854179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3408854179
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3948759289
Short name T376
Test name
Test status
Simulation time 1542498623 ps
CPU time 73.99 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 214472 kb
Host smart-4e2a4e52-e831-4218-af90-fdb8371f1816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948759289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3948759289
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3415488048
Short name T59
Test name
Test status
Simulation time 67620079 ps
CPU time 2.52 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 207256 kb
Host smart-7b27ae7f-75a7-4a27-959d-25f1c037dbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415488048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3415488048
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1217806685
Short name T867
Test name
Test status
Simulation time 64526481 ps
CPU time 2.47 seconds
Started Jun 11 12:48:31 PM PDT 24
Finished Jun 11 12:48:36 PM PDT 24
Peak memory 214396 kb
Host smart-bfd62834-c1c7-403f-b203-7edf8476910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217806685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1217806685
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.757917299
Short name T339
Test name
Test status
Simulation time 51086156 ps
CPU time 2.04 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 214140 kb
Host smart-f3a6bd12-d8a7-43c6-860c-adfb87348ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757917299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.757917299
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.996135652
Short name T619
Test name
Test status
Simulation time 265340474 ps
CPU time 3.51 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:28 PM PDT 24
Peak memory 218500 kb
Host smart-64906103-ee13-4f09-bc63-85c6488061b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996135652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.996135652
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2690950260
Short name T719
Test name
Test status
Simulation time 428763077 ps
CPU time 6.07 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:24 PM PDT 24
Peak memory 208040 kb
Host smart-55843959-c24e-46b5-b289-33e623386ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690950260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2690950260
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3408804851
Short name T878
Test name
Test status
Simulation time 386640412 ps
CPU time 2.84 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 206968 kb
Host smart-3f9a6a9e-72a5-44b9-b837-7679600eaf9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408804851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3408804851
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3374244803
Short name T386
Test name
Test status
Simulation time 147119600 ps
CPU time 4.47 seconds
Started Jun 11 12:48:35 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 208564 kb
Host smart-b69d28d4-3f00-4531-80fb-cf4372f3ddff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374244803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3374244803
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1326205427
Short name T301
Test name
Test status
Simulation time 1048488212 ps
CPU time 6.35 seconds
Started Jun 11 12:48:40 PM PDT 24
Finished Jun 11 12:48:48 PM PDT 24
Peak memory 208756 kb
Host smart-86fd62e6-ffe6-4f78-9a59-2f73733dcf87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326205427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1326205427
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4159130254
Short name T753
Test name
Test status
Simulation time 280537917 ps
CPU time 3.35 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 210332 kb
Host smart-98389908-bf47-4275-9bdf-14e72398d7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159130254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4159130254
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1694647393
Short name T553
Test name
Test status
Simulation time 462599907 ps
CPU time 2.96 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:48:37 PM PDT 24
Peak memory 208100 kb
Host smart-022d9203-ad4b-439c-80e3-8e86fdd12d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694647393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1694647393
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.917758990
Short name T292
Test name
Test status
Simulation time 895259420 ps
CPU time 6.63 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:31 PM PDT 24
Peak memory 216412 kb
Host smart-b15973ab-0376-4692-a953-ec2a930e2a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917758990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.917758990
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2376790210
Short name T194
Test name
Test status
Simulation time 773139661 ps
CPU time 13.67 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 223208 kb
Host smart-067a0ecb-a1ec-4304-93ff-f5b57ce33fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376790210 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2376790210
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1973849510
Short name T210
Test name
Test status
Simulation time 505099769 ps
CPU time 4.26 seconds
Started Jun 11 12:48:19 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 209116 kb
Host smart-81d201b8-4b03-49e5-98b6-c0802a28956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973849510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1973849510
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.995026115
Short name T851
Test name
Test status
Simulation time 521779006 ps
CPU time 5.29 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 211024 kb
Host smart-a3201f7a-394a-459f-b7eb-a78a70232318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995026115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.995026115
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1732557782
Short name T664
Test name
Test status
Simulation time 50650151 ps
CPU time 0.82 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 205972 kb
Host smart-ed6580e3-6e35-4b1f-b5b4-2f5ada97869c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732557782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1732557782
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.522382905
Short name T436
Test name
Test status
Simulation time 1598118691 ps
CPU time 77.16 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 214296 kb
Host smart-b1095e2a-1027-41ec-a4a0-06208580b563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522382905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.522382905
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3806664665
Short name T34
Test name
Test status
Simulation time 3390366315 ps
CPU time 6.96 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 209212 kb
Host smart-b91e0756-05f2-4258-9687-e9d01b06c0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806664665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3806664665
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1332920572
Short name T790
Test name
Test status
Simulation time 98945637 ps
CPU time 2.1 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 219820 kb
Host smart-73bdc801-d25e-4288-b37c-8cbe109eff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332920572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1332920572
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2245552537
Short name T417
Test name
Test status
Simulation time 157912435 ps
CPU time 2.95 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 214536 kb
Host smart-7ab2636f-1708-43c5-a685-f6705769fe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245552537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2245552537
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1294587697
Short name T794
Test name
Test status
Simulation time 120169885 ps
CPU time 4.26 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:28 PM PDT 24
Peak memory 220100 kb
Host smart-663c15a7-1a0f-42cd-bb7e-e44fbc7cdc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294587697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1294587697
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3301708944
Short name T649
Test name
Test status
Simulation time 1987203894 ps
CPU time 20.02 seconds
Started Jun 11 12:48:53 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 207448 kb
Host smart-2ab0e4c9-2bcd-4838-a5e7-3b2777fcbb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301708944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3301708944
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1214120518
Short name T909
Test name
Test status
Simulation time 29920356 ps
CPU time 2.12 seconds
Started Jun 11 12:48:22 PM PDT 24
Finished Jun 11 12:48:28 PM PDT 24
Peak memory 206976 kb
Host smart-3981b50a-e78b-44aa-94b0-892b2a3e7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214120518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1214120518
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2582930052
Short name T364
Test name
Test status
Simulation time 219139091 ps
CPU time 2.96 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 208932 kb
Host smart-51bd1103-8542-4aba-baab-97fc0a4e9348
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582930052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2582930052
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2189693416
Short name T636
Test name
Test status
Simulation time 61189679 ps
CPU time 3.39 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 208840 kb
Host smart-75a0dfa9-c9d2-40d2-982c-8775ea2daf2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189693416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2189693416
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2220321901
Short name T578
Test name
Test status
Simulation time 87131120 ps
CPU time 2.34 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 208076 kb
Host smart-64f49cce-2e33-46e9-9530-ca769982b52b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220321901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2220321901
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3911401919
Short name T751
Test name
Test status
Simulation time 599575391 ps
CPU time 6.34 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 218620 kb
Host smart-904cac0a-f1e0-4d86-b8d1-b2998772af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911401919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3911401919
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.691326169
Short name T857
Test name
Test status
Simulation time 267140742 ps
CPU time 3.13 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 208628 kb
Host smart-5f0990c4-e2e0-4509-9814-67180712a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691326169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.691326169
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2873338069
Short name T545
Test name
Test status
Simulation time 991524838 ps
CPU time 6.76 seconds
Started Jun 11 12:48:31 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 210076 kb
Host smart-497d9adc-b1b8-4c08-86c3-1d30bbf7d7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873338069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2873338069
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3671232074
Short name T682
Test name
Test status
Simulation time 2390985585 ps
CPU time 6.91 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 211004 kb
Host smart-f705d468-c859-4abd-8a0a-1de1a6854c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671232074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3671232074
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.946079962
Short name T774
Test name
Test status
Simulation time 14678458 ps
CPU time 0.74 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 205996 kb
Host smart-b603f167-7283-43f3-b8d7-63b4f66cb687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946079962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.946079962
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3253469631
Short name T424
Test name
Test status
Simulation time 149101535 ps
CPU time 7.18 seconds
Started Jun 11 12:48:32 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 214400 kb
Host smart-dfd2173e-7db7-4a68-879b-910df243b2a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253469631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3253469631
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1631397738
Short name T230
Test name
Test status
Simulation time 1011380134 ps
CPU time 3.62 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 220144 kb
Host smart-6b4d0c7a-5fdd-4092-abcf-d6978bba3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631397738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1631397738
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.933536786
Short name T464
Test name
Test status
Simulation time 60442897 ps
CPU time 2.72 seconds
Started Jun 11 12:48:28 PM PDT 24
Finished Jun 11 12:48:33 PM PDT 24
Peak memory 209820 kb
Host smart-96dbf12e-8a91-42fb-bebd-269a3b7c817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933536786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.933536786
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.4033660973
Short name T757
Test name
Test status
Simulation time 101423840 ps
CPU time 2.48 seconds
Started Jun 11 12:48:34 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 214356 kb
Host smart-9e0b323c-4b02-4e44-a061-b25583e58857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033660973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.4033660973
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3544964062
Short name T627
Test name
Test status
Simulation time 387446974 ps
CPU time 10.16 seconds
Started Jun 11 12:48:27 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 208072 kb
Host smart-67aa8d72-6b48-452b-affb-6e58be4143e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544964062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3544964062
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2815886889
Short name T494
Test name
Test status
Simulation time 65418515 ps
CPU time 3.35 seconds
Started Jun 11 12:48:40 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 208684 kb
Host smart-0430c7a7-3d88-4c23-9450-aefbea9304d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815886889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2815886889
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.272462119
Short name T523
Test name
Test status
Simulation time 5861501405 ps
CPU time 38.04 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 208252 kb
Host smart-ff54f3eb-4329-492c-861b-b170e0b9ce92
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272462119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.272462119
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3129148146
Short name T334
Test name
Test status
Simulation time 100904867 ps
CPU time 3.78 seconds
Started Jun 11 12:48:29 PM PDT 24
Finished Jun 11 12:48:35 PM PDT 24
Peak memory 208712 kb
Host smart-7ccf792f-3ee7-4ad8-b32d-b0178d19bd86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129148146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3129148146
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.430870206
Short name T661
Test name
Test status
Simulation time 166699549 ps
CPU time 4 seconds
Started Jun 11 12:48:30 PM PDT 24
Finished Jun 11 12:48:36 PM PDT 24
Peak memory 207176 kb
Host smart-6fa75aaa-0703-48fa-b974-6c63116cc5cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430870206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.430870206
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1381000849
Short name T411
Test name
Test status
Simulation time 126538532 ps
CPU time 3.05 seconds
Started Jun 11 12:48:28 PM PDT 24
Finished Jun 11 12:48:33 PM PDT 24
Peak memory 209700 kb
Host smart-dfca9626-9b8d-4614-b3c3-27cb5fbe4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381000849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1381000849
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.266260793
Short name T766
Test name
Test status
Simulation time 46509144 ps
CPU time 2.55 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 206796 kb
Host smart-b61da1d6-4569-48ff-9663-e591bd80c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266260793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.266260793
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1494988602
Short name T275
Test name
Test status
Simulation time 104568599 ps
CPU time 4.51 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:31 PM PDT 24
Peak memory 208776 kb
Host smart-47b2d629-ddd8-47ad-961f-f9819fa9a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494988602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1494988602
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.220043646
Short name T761
Test name
Test status
Simulation time 217555805 ps
CPU time 2.58 seconds
Started Jun 11 12:48:18 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 210184 kb
Host smart-ae628e52-fc64-43a2-9533-28dc4cd0c81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220043646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.220043646
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2911404864
Short name T590
Test name
Test status
Simulation time 52038495 ps
CPU time 0.82 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:49 PM PDT 24
Peak memory 206000 kb
Host smart-e388bb0d-cf3e-4f1c-9655-714601996dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911404864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2911404864
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3517717459
Short name T434
Test name
Test status
Simulation time 36705323897 ps
CPU time 122.95 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:50:46 PM PDT 24
Peak memory 215272 kb
Host smart-e424ed09-a477-4897-ac41-9514645770e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517717459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3517717459
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3598219011
Short name T691
Test name
Test status
Simulation time 246860612 ps
CPU time 5.78 seconds
Started Jun 11 12:48:52 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 214640 kb
Host smart-f35c0a5f-512c-45ee-afaf-875ac7d8382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598219011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3598219011
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.650543864
Short name T762
Test name
Test status
Simulation time 57743871 ps
CPU time 1.47 seconds
Started Jun 11 12:48:30 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 207632 kb
Host smart-8ed9565c-ffa9-4011-8946-423846e65f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650543864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.650543864
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3642078867
Short name T604
Test name
Test status
Simulation time 141987668 ps
CPU time 5.92 seconds
Started Jun 11 12:48:29 PM PDT 24
Finished Jun 11 12:48:37 PM PDT 24
Peak memory 214396 kb
Host smart-5d095e48-c9bd-436b-abdd-5ed0635b9e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642078867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3642078867
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2171281242
Short name T744
Test name
Test status
Simulation time 61910603 ps
CPU time 2.59 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 215356 kb
Host smart-dcd8ecb9-9bdb-4c3e-8c77-527ba00bb56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171281242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2171281242
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.297920733
Short name T683
Test name
Test status
Simulation time 43729504 ps
CPU time 3.14 seconds
Started Jun 11 12:48:49 PM PDT 24
Finished Jun 11 12:48:54 PM PDT 24
Peak memory 214412 kb
Host smart-139f6927-a9cf-45af-90ab-622a20212abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297920733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.297920733
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3488799455
Short name T477
Test name
Test status
Simulation time 93700886 ps
CPU time 3.76 seconds
Started Jun 11 12:48:29 PM PDT 24
Finished Jun 11 12:48:35 PM PDT 24
Peak memory 206964 kb
Host smart-2643177d-2e02-4b1f-a02e-b3520a29d221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488799455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3488799455
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3477169489
Short name T650
Test name
Test status
Simulation time 64410656 ps
CPU time 3.33 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 208092 kb
Host smart-096fa13e-cd27-4875-a6e5-bab9ee53e8e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477169489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3477169489
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.802943674
Short name T544
Test name
Test status
Simulation time 26373594 ps
CPU time 2.03 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 207476 kb
Host smart-a8264986-2f98-4c9b-8afb-eeadb66b7299
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802943674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.802943674
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1615440454
Short name T321
Test name
Test status
Simulation time 51549779 ps
CPU time 2.65 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 208116 kb
Host smart-12586f2e-eff5-405b-a0de-4363007c1ec0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615440454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1615440454
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3309566524
Short name T324
Test name
Test status
Simulation time 276057117 ps
CPU time 2.53 seconds
Started Jun 11 12:48:40 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 218280 kb
Host smart-e9dbdb64-c2f3-4b06-8f6f-5c47a9c7c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309566524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3309566524
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4060585197
Short name T408
Test name
Test status
Simulation time 299905386 ps
CPU time 2.75 seconds
Started Jun 11 12:48:34 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 208508 kb
Host smart-b7c25e63-ed55-4a9a-97dd-69d7c9a755a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060585197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4060585197
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2031228418
Short name T247
Test name
Test status
Simulation time 857381468 ps
CPU time 25.52 seconds
Started Jun 11 12:48:28 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 220888 kb
Host smart-41476bc6-57e1-4b14-a84f-195bd2d57525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031228418 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2031228418
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4084332019
Short name T801
Test name
Test status
Simulation time 62052581 ps
CPU time 2.35 seconds
Started Jun 11 12:48:30 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 209808 kb
Host smart-a47dfd41-dc79-4e8a-ba2a-b34fea3d540f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084332019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4084332019
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2620040353
Short name T887
Test name
Test status
Simulation time 35665613 ps
CPU time 0.79 seconds
Started Jun 11 12:48:42 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 206016 kb
Host smart-9099a180-b76c-4f18-bfd5-7df86b98b04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620040353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2620040353
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1264727723
Short name T149
Test name
Test status
Simulation time 262232492 ps
CPU time 7.69 seconds
Started Jun 11 12:48:48 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 215968 kb
Host smart-812244af-0de1-48b0-9a30-31ccf59b9252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264727723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1264727723
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3924631269
Short name T788
Test name
Test status
Simulation time 77481768 ps
CPU time 2.93 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 210048 kb
Host smart-42154856-a048-4f69-917f-d2480e8b7de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924631269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3924631269
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1356023388
Short name T489
Test name
Test status
Simulation time 248930743 ps
CPU time 5.47 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:48:44 PM PDT 24
Peak memory 209276 kb
Host smart-f029c47a-9176-41a0-b289-b1f23b4f79d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356023388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1356023388
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4226216916
Short name T837
Test name
Test status
Simulation time 152770424 ps
CPU time 2.54 seconds
Started Jun 11 12:48:38 PM PDT 24
Finished Jun 11 12:48:43 PM PDT 24
Peak memory 214408 kb
Host smart-8886dfcd-8bdd-413a-b22f-18bba1174a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226216916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4226216916
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1014065744
Short name T227
Test name
Test status
Simulation time 446422368 ps
CPU time 3.35 seconds
Started Jun 11 12:48:40 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 209588 kb
Host smart-163a58eb-2313-4153-8e8e-8f82cccf3c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014065744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1014065744
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3302994810
Short name T499
Test name
Test status
Simulation time 1187660317 ps
CPU time 6.88 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:08 PM PDT 24
Peak memory 218596 kb
Host smart-2817d036-b7a8-4a0f-a5e6-300091dd08c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302994810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3302994810
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.588965473
Short name T407
Test name
Test status
Simulation time 28975692 ps
CPU time 1.97 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:48:59 PM PDT 24
Peak memory 208576 kb
Host smart-754403d5-b24d-4125-a198-e2693ffc8385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588965473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.588965473
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3723560949
Short name T566
Test name
Test status
Simulation time 161279405 ps
CPU time 2.31 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 207644 kb
Host smart-9e537262-afe5-42fb-83b4-db3a4400c542
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723560949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3723560949
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1449372664
Short name T505
Test name
Test status
Simulation time 77589781 ps
CPU time 2.94 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 207152 kb
Host smart-671cd947-61f7-4d1a-a2af-150f3fa3a116
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449372664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1449372664
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2018732637
Short name T375
Test name
Test status
Simulation time 653750610 ps
CPU time 5.01 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:07 PM PDT 24
Peak memory 208020 kb
Host smart-3753ec75-6014-48e0-b374-30c424150d7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018732637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2018732637
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2756149625
Short name T531
Test name
Test status
Simulation time 141432911 ps
CPU time 3.02 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 208128 kb
Host smart-07048372-9dc3-4c42-af52-c169476b92fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756149625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2756149625
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.4182136695
Short name T804
Test name
Test status
Simulation time 281442574 ps
CPU time 2.3 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 206844 kb
Host smart-e7a59b33-1a8c-4844-8069-79dfddc88e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182136695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.4182136695
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4088500975
Short name T510
Test name
Test status
Simulation time 175822948 ps
CPU time 7.14 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 222680 kb
Host smart-5b680476-0641-4945-9c36-21efe84f4c9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088500975 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4088500975
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3779661144
Short name T296
Test name
Test status
Simulation time 998929377 ps
CPU time 20.36 seconds
Started Jun 11 12:48:28 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 209200 kb
Host smart-a5baa659-6bbc-412d-8824-9bb764ccb77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779661144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3779661144
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.561294426
Short name T805
Test name
Test status
Simulation time 157070202 ps
CPU time 4.29 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:07 PM PDT 24
Peak memory 210140 kb
Host smart-b69beef4-85d6-404d-bc01-2ed983cd7656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561294426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.561294426
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2948747526
Short name T126
Test name
Test status
Simulation time 246227961 ps
CPU time 4.1 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:48:43 PM PDT 24
Peak memory 214596 kb
Host smart-17025596-d2c4-4394-89fa-3903702e68b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948747526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2948747526
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1225238721
Short name T307
Test name
Test status
Simulation time 113140824 ps
CPU time 1.79 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 214544 kb
Host smart-a3e72f54-ef3f-42ee-9c86-2b1bc9acff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225238721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1225238721
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4216631565
Short name T610
Test name
Test status
Simulation time 152861826 ps
CPU time 2.37 seconds
Started Jun 11 12:48:27 PM PDT 24
Finished Jun 11 12:48:32 PM PDT 24
Peak memory 216216 kb
Host smart-2fa49c9e-b4f2-4533-a31c-e86da0daa5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216631565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4216631565
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3574060880
Short name T911
Test name
Test status
Simulation time 809096108 ps
CPU time 8.69 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 218300 kb
Host smart-61ce6a51-b8af-4f03-8c4e-8dfcaa586e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574060880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3574060880
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2600244267
Short name T316
Test name
Test status
Simulation time 76582645 ps
CPU time 3.59 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:56 PM PDT 24
Peak memory 207320 kb
Host smart-87df1ffa-1f76-4319-88bf-123c22230d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600244267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2600244267
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1160242353
Short name T856
Test name
Test status
Simulation time 852433074 ps
CPU time 6.07 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 208468 kb
Host smart-a62eeb6b-9b25-4d23-9d38-ef16a187eb86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160242353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1160242353
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1383977255
Short name T454
Test name
Test status
Simulation time 69886724 ps
CPU time 2.57 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 207008 kb
Host smart-379487c7-4dce-454b-9beb-ed03cffca1c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383977255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1383977255
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1069974118
Short name T574
Test name
Test status
Simulation time 381650947 ps
CPU time 5.85 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 208328 kb
Host smart-afbb60ad-fc74-4a29-a679-d82dc507e33a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069974118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1069974118
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2517599644
Short name T748
Test name
Test status
Simulation time 275352106 ps
CPU time 4.82 seconds
Started Jun 11 12:48:30 PM PDT 24
Finished Jun 11 12:48:37 PM PDT 24
Peak memory 218564 kb
Host smart-514b5352-06bb-41b8-956c-83e624dae984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517599644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2517599644
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.334710493
Short name T557
Test name
Test status
Simulation time 53796646 ps
CPU time 2.67 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 208448 kb
Host smart-075b7bd0-a660-4762-b66c-e88252b9f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334710493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.334710493
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.251606776
Short name T198
Test name
Test status
Simulation time 228705491 ps
CPU time 8.6 seconds
Started Jun 11 12:48:32 PM PDT 24
Finished Jun 11 12:48:42 PM PDT 24
Peak memory 222664 kb
Host smart-90583753-841d-4b97-b5dc-e35b8b68312d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251606776 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.251606776
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3623322383
Short name T767
Test name
Test status
Simulation time 1332738624 ps
CPU time 8.34 seconds
Started Jun 11 12:49:02 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 210176 kb
Host smart-450bf2ba-7c74-46f5-8f54-cba83b479fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623322383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3623322383
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4038418022
Short name T599
Test name
Test status
Simulation time 92668067 ps
CPU time 2.54 seconds
Started Jun 11 12:48:25 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 210396 kb
Host smart-85e47dad-29c3-4a2e-a47c-ba795565f64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038418022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4038418022
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2755135042
Short name T492
Test name
Test status
Simulation time 10928856 ps
CPU time 0.75 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 205892 kb
Host smart-5964ffb9-ff4c-47de-82a2-310bc705a2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755135042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2755135042
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2805261640
Short name T431
Test name
Test status
Simulation time 122671765 ps
CPU time 3.96 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 214304 kb
Host smart-7a102760-8549-42e4-aa4d-c45011b22750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805261640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2805261640
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1609523572
Short name T836
Test name
Test status
Simulation time 137018901 ps
CPU time 3.64 seconds
Started Jun 11 12:48:35 PM PDT 24
Finished Jun 11 12:48:40 PM PDT 24
Peak memory 217036 kb
Host smart-4d35bf81-aaef-4df3-967c-021fec247245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609523572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1609523572
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2440184138
Short name T693
Test name
Test status
Simulation time 125741117 ps
CPU time 2.99 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 209820 kb
Host smart-41f5edcd-6e6b-4d30-b935-97d47f4c39f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440184138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2440184138
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2617401494
Short name T831
Test name
Test status
Simulation time 170093534 ps
CPU time 5.33 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:48:49 PM PDT 24
Peak memory 214384 kb
Host smart-2cbfcf72-18ad-492c-9f43-4323061d0b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617401494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2617401494
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3302122148
Short name T789
Test name
Test status
Simulation time 131187826 ps
CPU time 2.25 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:48 PM PDT 24
Peak memory 214276 kb
Host smart-b8b3fc63-b984-4584-a7d8-04c76514f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302122148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3302122148
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3857491715
Short name T56
Test name
Test status
Simulation time 84657611 ps
CPU time 2.95 seconds
Started Jun 11 12:48:36 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 215980 kb
Host smart-cc0c87b3-ca7e-4795-a2a6-eda91bb899e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857491715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3857491715
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1550184441
Short name T257
Test name
Test status
Simulation time 552676013 ps
CPU time 6.23 seconds
Started Jun 11 12:48:31 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 214388 kb
Host smart-49acfc1f-b68f-48c9-ab40-c8f0c48eccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550184441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1550184441
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1448487514
Short name T145
Test name
Test status
Simulation time 145186078 ps
CPU time 3.22 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:49 PM PDT 24
Peak memory 207632 kb
Host smart-b79c0e1f-b91d-4e0e-98ad-faddf064cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448487514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1448487514
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.425047161
Short name T476
Test name
Test status
Simulation time 3002065185 ps
CPU time 53.6 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 208596 kb
Host smart-2ba65b7a-8e59-4570-a91a-9c6101657094
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425047161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.425047161
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2126501394
Short name T517
Test name
Test status
Simulation time 112651111 ps
CPU time 3.57 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:49 PM PDT 24
Peak memory 207856 kb
Host smart-1cd04bf4-e2cd-4318-85d6-d550a13ba9d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126501394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2126501394
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1544536167
Short name T256
Test name
Test status
Simulation time 88181765 ps
CPU time 3.87 seconds
Started Jun 11 12:48:35 PM PDT 24
Finished Jun 11 12:48:40 PM PDT 24
Peak memory 208740 kb
Host smart-734ee7a6-7f6a-4680-8edb-27c22d63d23a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544536167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1544536167
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2884302499
Short name T655
Test name
Test status
Simulation time 107573890 ps
CPU time 2.54 seconds
Started Jun 11 12:48:58 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 214356 kb
Host smart-612df10c-b340-4390-a1a1-63b41a65521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884302499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2884302499
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4208684501
Short name T893
Test name
Test status
Simulation time 90215039 ps
CPU time 1.82 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:48 PM PDT 24
Peak memory 208472 kb
Host smart-e98bd710-3518-44b3-877d-03f1d0ed19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208684501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4208684501
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3003771225
Short name T623
Test name
Test status
Simulation time 184533668 ps
CPU time 4.16 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 207168 kb
Host smart-0ae5907b-e74a-4b43-a42c-7a2881a32dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003771225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3003771225
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3641574661
Short name T197
Test name
Test status
Simulation time 2085680786 ps
CPU time 18.32 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 222112 kb
Host smart-a5471fae-3ba5-4e61-95c8-2cd700b21286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641574661 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3641574661
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1576507959
Short name T25
Test name
Test status
Simulation time 339253008 ps
CPU time 13.14 seconds
Started Jun 11 12:48:49 PM PDT 24
Finished Jun 11 12:49:04 PM PDT 24
Peak memory 214344 kb
Host smart-1d85e0bc-65bb-44ee-bfa1-a9538a9592c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576507959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1576507959
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4050334303
Short name T190
Test name
Test status
Simulation time 198192203 ps
CPU time 2.77 seconds
Started Jun 11 12:48:38 PM PDT 24
Finished Jun 11 12:48:43 PM PDT 24
Peak memory 210352 kb
Host smart-de3c0f1b-3697-4d50-a571-8c912e43f846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050334303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4050334303
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1794675674
Short name T466
Test name
Test status
Simulation time 22444021 ps
CPU time 0.88 seconds
Started Jun 11 12:48:53 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 205992 kb
Host smart-a3266927-52e1-42b5-856f-6e73c9a2dfeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794675674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1794675674
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.761966776
Short name T586
Test name
Test status
Simulation time 653627070 ps
CPU time 7.02 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 214364 kb
Host smart-f0c8f14b-84cd-428f-857e-8f384e573c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761966776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.761966776
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_random.3971240375
Short name T252
Test name
Test status
Simulation time 394150721 ps
CPU time 4.6 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:48:44 PM PDT 24
Peak memory 218436 kb
Host smart-8cfe7fcd-543b-4294-a68c-697a1524f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971240375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3971240375
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2162761472
Short name T658
Test name
Test status
Simulation time 364075267 ps
CPU time 6.84 seconds
Started Jun 11 12:48:34 PM PDT 24
Finished Jun 11 12:48:42 PM PDT 24
Peak memory 206900 kb
Host smart-993415e4-6699-474d-a6df-43392420010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162761472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2162761472
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3970839299
Short name T711
Test name
Test status
Simulation time 614550265 ps
CPU time 15.92 seconds
Started Jun 11 12:48:52 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 208932 kb
Host smart-1a541d4b-25b6-418a-900e-c7bf634d7227
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970839299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3970839299
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2749659453
Short name T916
Test name
Test status
Simulation time 1027375566 ps
CPU time 4.93 seconds
Started Jun 11 12:48:39 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 207072 kb
Host smart-fe9b5a13-3a8b-41a9-8056-8e4cae2e108a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749659453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2749659453
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2277120204
Short name T529
Test name
Test status
Simulation time 92942605 ps
CPU time 3.91 seconds
Started Jun 11 12:48:32 PM PDT 24
Finished Jun 11 12:48:38 PM PDT 24
Peak memory 208500 kb
Host smart-4d6879af-c58f-4876-b5b9-eaf375982761
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277120204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2277120204
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1551411764
Short name T641
Test name
Test status
Simulation time 500305547 ps
CPU time 2.3 seconds
Started Jun 11 12:48:49 PM PDT 24
Finished Jun 11 12:48:54 PM PDT 24
Peak memory 208824 kb
Host smart-de2087d0-6f01-4382-87a7-c48561dc7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551411764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1551411764
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.880887840
Short name T741
Test name
Test status
Simulation time 130160980 ps
CPU time 2.67 seconds
Started Jun 11 12:48:36 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 206960 kb
Host smart-87a089b7-d558-4ef5-96c7-3ce1b1b51174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880887840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.880887840
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.776032802
Short name T795
Test name
Test status
Simulation time 8737594060 ps
CPU time 104.36 seconds
Started Jun 11 12:49:02 PM PDT 24
Finished Jun 11 12:50:49 PM PDT 24
Peak memory 222612 kb
Host smart-d42dd071-5701-4549-b8df-3c0cf2fd9fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776032802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.776032802
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2757457676
Short name T639
Test name
Test status
Simulation time 276659151 ps
CPU time 8.59 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 214296 kb
Host smart-b7671a9c-30f1-4286-839f-524c1bf45ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757457676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2757457676
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3737782161
Short name T400
Test name
Test status
Simulation time 396087291 ps
CPU time 3.51 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 209976 kb
Host smart-e034c83b-d09b-418f-921f-0c6d0a942d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737782161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3737782161
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.370093576
Short name T563
Test name
Test status
Simulation time 92862469 ps
CPU time 0.98 seconds
Started Jun 11 12:49:01 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 206068 kb
Host smart-a9a8bf4c-1315-4748-9ea8-91d645df2bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370093576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.370093576
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1234188672
Short name T576
Test name
Test status
Simulation time 61688327 ps
CPU time 2.43 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 219916 kb
Host smart-b2a2c3d4-5e4f-4d26-9316-8524cbb3154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234188672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1234188672
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1926751442
Short name T46
Test name
Test status
Simulation time 384307843 ps
CPU time 3.09 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 214388 kb
Host smart-cf1a8e82-22af-4f24-a7cd-a07d1a7eeda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926751442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1926751442
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.537643411
Short name T238
Test name
Test status
Simulation time 117323796 ps
CPU time 4.2 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 207668 kb
Host smart-ea573d56-8842-4a06-9e07-400d7ad8e914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537643411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.537643411
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3051899363
Short name T212
Test name
Test status
Simulation time 200896355 ps
CPU time 4.8 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 209672 kb
Host smart-92a88205-293f-4d93-ba53-bd20b53bf8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051899363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3051899363
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2972606733
Short name T13
Test name
Test status
Simulation time 125621704 ps
CPU time 3.17 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 208644 kb
Host smart-92778708-bbcd-4f75-9806-12e9c1937df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972606733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2972606733
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3941091562
Short name T374
Test name
Test status
Simulation time 141815477 ps
CPU time 3.61 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 208700 kb
Host smart-f424ddc1-f4d3-4f44-83f2-d9b29978b439
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941091562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3941091562
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4252223188
Short name T418
Test name
Test status
Simulation time 63516902 ps
CPU time 3.1 seconds
Started Jun 11 12:48:55 PM PDT 24
Finished Jun 11 12:48:59 PM PDT 24
Peak memory 208800 kb
Host smart-94e7b08a-4b38-4c22-9723-4953dbb99f5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252223188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4252223188
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2247252869
Short name T785
Test name
Test status
Simulation time 2057224069 ps
CPU time 27.55 seconds
Started Jun 11 12:48:39 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 208216 kb
Host smart-3f341392-bcdd-4e66-8d12-9b393637e5a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247252869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2247252869
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2538079245
Short name T313
Test name
Test status
Simulation time 15940058 ps
CPU time 1.37 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 209472 kb
Host smart-f79b40cb-ece4-499d-bffb-84e37d290ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538079245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2538079245
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3372446534
Short name T637
Test name
Test status
Simulation time 3290891343 ps
CPU time 28.63 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 208896 kb
Host smart-1d8abd7a-ab23-4dc5-88d5-b4381deefc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372446534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3372446534
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3946724675
Short name T807
Test name
Test status
Simulation time 390289838 ps
CPU time 7.64 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 218704 kb
Host smart-8df23beb-88b0-4ca9-b36e-9de13a257c23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946724675 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3946724675
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.930933956
Short name T852
Test name
Test status
Simulation time 211230343 ps
CPU time 4.48 seconds
Started Jun 11 12:48:55 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 214344 kb
Host smart-63b2f2e0-be5a-480b-95dc-fffa84afea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930933956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.930933956
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1858433399
Short name T706
Test name
Test status
Simulation time 162002272 ps
CPU time 3.99 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:49 PM PDT 24
Peak memory 210492 kb
Host smart-aedb497f-dfd7-4b36-b7c8-7010904e4871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858433399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1858433399
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2697163690
Short name T465
Test name
Test status
Simulation time 15136227 ps
CPU time 0.94 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 206064 kb
Host smart-4a99231d-755d-40fc-8097-661d1870da84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697163690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2697163690
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2159486061
Short name T158
Test name
Test status
Simulation time 35480532 ps
CPU time 2.77 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 214344 kb
Host smart-7833757f-3bae-46cf-9040-bd8de12c14ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159486061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2159486061
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1504268866
Short name T885
Test name
Test status
Simulation time 1773873112 ps
CPU time 2.74 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 214508 kb
Host smart-892360c1-1b14-470d-87a4-0bb7f6042e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504268866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1504268866
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1823658897
Short name T73
Test name
Test status
Simulation time 88690597 ps
CPU time 1.95 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 214408 kb
Host smart-7a30deca-1531-407f-b230-eefff44cbb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823658897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1823658897
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3884175481
Short name T497
Test name
Test status
Simulation time 150416212 ps
CPU time 5.68 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:48:56 PM PDT 24
Peak memory 209596 kb
Host smart-658421ef-e969-4f8d-a450-e5400b69bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884175481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3884175481
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.167789237
Short name T232
Test name
Test status
Simulation time 218541923 ps
CPU time 2.61 seconds
Started Jun 11 12:48:53 PM PDT 24
Finished Jun 11 12:48:57 PM PDT 24
Peak memory 220040 kb
Host smart-48ac7f11-2775-43fc-add4-bba412cb89ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167789237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.167789237
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.692613459
Short name T208
Test name
Test status
Simulation time 616957512 ps
CPU time 4.97 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:54 PM PDT 24
Peak memory 214400 kb
Host smart-aafef9e6-ab6f-4ec5-98cf-d58babcae9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692613459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.692613459
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.214021325
Short name T277
Test name
Test status
Simulation time 29703203 ps
CPU time 2.14 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 207064 kb
Host smart-90b8f680-1373-4b1f-a493-d41184f05295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214021325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.214021325
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2629742099
Short name T475
Test name
Test status
Simulation time 168259063 ps
CPU time 4.45 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 208028 kb
Host smart-f3f2fb8d-d35f-416b-bb17-b785fa80ff20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629742099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2629742099
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1653637264
Short name T522
Test name
Test status
Simulation time 26279907 ps
CPU time 1.88 seconds
Started Jun 11 12:48:49 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 208472 kb
Host smart-d59dc7d8-3cbf-4500-9793-add0573c18d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653637264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1653637264
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1319324010
Short name T113
Test name
Test status
Simulation time 310643839 ps
CPU time 3.85 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 206848 kb
Host smart-c919dfdf-7039-4139-b807-1dcfb3dec53d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319324010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1319324010
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4270111639
Short name T626
Test name
Test status
Simulation time 117068100 ps
CPU time 2.48 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 222548 kb
Host smart-62872f93-7a54-4d73-9df9-8b3e5ecb6803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270111639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4270111639
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.225202203
Short name T904
Test name
Test status
Simulation time 6271076965 ps
CPU time 12.7 seconds
Started Jun 11 12:49:23 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 208544 kb
Host smart-b634d3e7-1998-4c20-b882-2bb0733a6af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225202203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.225202203
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2327479375
Short name T564
Test name
Test status
Simulation time 410578948 ps
CPU time 9.92 seconds
Started Jun 11 12:49:01 PM PDT 24
Finished Jun 11 12:49:14 PM PDT 24
Peak memory 208500 kb
Host smart-03c38a20-bcef-4971-a369-72ee645d6c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327479375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2327479375
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2936835175
Short name T811
Test name
Test status
Simulation time 536427346 ps
CPU time 3.37 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 210040 kb
Host smart-7ab90ea5-4583-483b-83a2-0e522bb8333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936835175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2936835175
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.326696900
Short name T441
Test name
Test status
Simulation time 9002627 ps
CPU time 0.72 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:14 PM PDT 24
Peak memory 205916 kb
Host smart-1661443c-bc67-42eb-ae81-8a9a599f2c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326696900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.326696900
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.250190607
Short name T871
Test name
Test status
Simulation time 53117139 ps
CPU time 3.46 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 214760 kb
Host smart-4129ca92-3c5e-43e8-8466-1fb3b44ee3b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250190607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.250190607
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3709488161
Short name T36
Test name
Test status
Simulation time 123353419 ps
CPU time 4.52 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:21 PM PDT 24
Peak memory 209564 kb
Host smart-7d127125-5094-4984-93b3-1056d9e6961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709488161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3709488161
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2968334114
Short name T65
Test name
Test status
Simulation time 99582980 ps
CPU time 3.93 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 210108 kb
Host smart-6ef7a01e-4ef0-4cd2-a02e-07ef24af0ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968334114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2968334114
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2541282123
Short name T571
Test name
Test status
Simulation time 399740592 ps
CPU time 5.06 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 214380 kb
Host smart-6a62eb00-0c54-42c8-af2d-d02406b383e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541282123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2541282123
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.604497833
Short name T98
Test name
Test status
Simulation time 1378466614 ps
CPU time 4.45 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 222412 kb
Host smart-bdadf217-083a-4cc5-ad05-b08c5fb787f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604497833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.604497833
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.2647245568
Short name T727
Test name
Test status
Simulation time 390500991 ps
CPU time 9.77 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:21 PM PDT 24
Peak memory 214396 kb
Host smart-175b23c9-6bff-41ee-ad96-86bede1657d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647245568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2647245568
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.788093466
Short name T111
Test name
Test status
Simulation time 5815002978 ps
CPU time 22.54 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 233008 kb
Host smart-e45bf31a-bd61-47ef-bf54-7c415c867ac5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788093466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.788093466
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2504924180
Short name T274
Test name
Test status
Simulation time 107300060 ps
CPU time 1.64 seconds
Started Jun 11 12:47:58 PM PDT 24
Finished Jun 11 12:48:02 PM PDT 24
Peak memory 206980 kb
Host smart-e717034d-cf40-4645-b848-25a6ce3a8f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504924180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2504924180
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3510816574
Short name T534
Test name
Test status
Simulation time 208657102 ps
CPU time 2.67 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:14 PM PDT 24
Peak memory 208884 kb
Host smart-2eebefbc-b11c-42bb-b813-31f2d233bdac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510816574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3510816574
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.389399424
Short name T336
Test name
Test status
Simulation time 747569090 ps
CPU time 3.25 seconds
Started Jun 11 12:47:57 PM PDT 24
Finished Jun 11 12:48:03 PM PDT 24
Peak memory 208660 kb
Host smart-a3235ca6-e087-4868-b615-c14748a57765
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389399424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.389399424
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3481580139
Short name T481
Test name
Test status
Simulation time 669313587 ps
CPU time 16.28 seconds
Started Jun 11 12:47:53 PM PDT 24
Finished Jun 11 12:48:12 PM PDT 24
Peak memory 208980 kb
Host smart-8d9d4541-b86d-4c15-a1f6-c62ad3420f48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481580139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3481580139
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1900468749
Short name T85
Test name
Test status
Simulation time 69635585 ps
CPU time 3.16 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:17 PM PDT 24
Peak memory 218596 kb
Host smart-890ae263-a7d8-4af8-aea3-8347b42bbaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900468749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1900468749
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3869702246
Short name T729
Test name
Test status
Simulation time 1206387382 ps
CPU time 19.35 seconds
Started Jun 11 12:47:53 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 208496 kb
Host smart-4d67d74c-0e03-4dd7-b7b4-df1f309fa368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869702246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3869702246
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1058923535
Short name T787
Test name
Test status
Simulation time 893066965 ps
CPU time 30.99 seconds
Started Jun 11 12:48:08 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 216336 kb
Host smart-2963b217-b2da-4e48-b938-fb6e4a32a87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058923535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1058923535
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.53510177
Short name T915
Test name
Test status
Simulation time 105531981 ps
CPU time 4.31 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 209872 kb
Host smart-da7b09b7-727b-4ab4-90c4-4980503bfbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53510177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.53510177
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.649125911
Short name T404
Test name
Test status
Simulation time 71676163 ps
CPU time 2.32 seconds
Started Jun 11 12:48:18 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 209968 kb
Host smart-a754bd44-03b7-431c-b4e9-567cbb5b160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649125911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.649125911
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3656933307
Short name T721
Test name
Test status
Simulation time 36619653 ps
CPU time 0.73 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:03 PM PDT 24
Peak memory 205988 kb
Host smart-d36b2e02-7191-46f5-8e96-29aa4b512893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656933307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3656933307
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3868298628
Short name T437
Test name
Test status
Simulation time 66407030 ps
CPU time 4.57 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:07 PM PDT 24
Peak memory 215732 kb
Host smart-314591dd-6059-4d3d-a775-e421377661ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868298628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3868298628
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3695213827
Short name T758
Test name
Test status
Simulation time 262630243 ps
CPU time 2.55 seconds
Started Jun 11 12:48:48 PM PDT 24
Finished Jun 11 12:48:53 PM PDT 24
Peak memory 209508 kb
Host smart-e1ac3d7a-7b43-4dc2-9019-e13ab871e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695213827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3695213827
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3413848427
Short name T282
Test name
Test status
Simulation time 207104499 ps
CPU time 1.76 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 207624 kb
Host smart-df9e08f2-7912-4d11-98cb-4a32b4e6f7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413848427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3413848427
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3840537973
Short name T267
Test name
Test status
Simulation time 19415776801 ps
CPU time 80.39 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 214456 kb
Host smart-87956057-b3bd-441a-847a-ae181112d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840537973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3840537973
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.382374818
Short name T730
Test name
Test status
Simulation time 94056384 ps
CPU time 3.57 seconds
Started Jun 11 12:48:51 PM PDT 24
Finished Jun 11 12:48:56 PM PDT 24
Peak memory 220564 kb
Host smart-16eb36fe-cd1a-4b4b-9469-f574506c697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382374818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.382374818
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3384214239
Short name T269
Test name
Test status
Simulation time 95293204 ps
CPU time 5.2 seconds
Started Jun 11 12:48:44 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 222560 kb
Host smart-64d5f345-53a6-46bd-b84e-cf267f6dd4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384214239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3384214239
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3344651327
Short name T139
Test name
Test status
Simulation time 6236046580 ps
CPU time 43.04 seconds
Started Jun 11 12:48:37 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 218328 kb
Host smart-7089b38d-a3a6-4e1c-a6df-3f51579a49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344651327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3344651327
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2945809776
Short name T821
Test name
Test status
Simulation time 46610043 ps
CPU time 2.53 seconds
Started Jun 11 12:49:01 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 206856 kb
Host smart-f3c9bf08-b2a2-4808-9839-0d8d54585418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945809776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2945809776
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2228253778
Short name T569
Test name
Test status
Simulation time 2905658008 ps
CPU time 31.07 seconds
Started Jun 11 12:48:40 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 208880 kb
Host smart-5ca6b7fb-623c-45f2-ae17-6091571ae600
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228253778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2228253778
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4216298407
Short name T568
Test name
Test status
Simulation time 260970422 ps
CPU time 2.95 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 207012 kb
Host smart-8429a8b2-17d7-4f83-a7d9-8a022d66d542
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216298407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4216298407
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1266195013
Short name T537
Test name
Test status
Simulation time 602284151 ps
CPU time 8.36 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 208124 kb
Host smart-0bcbba14-078f-43fc-9c2d-92de2b8c9e7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266195013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1266195013
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1967788554
Short name T17
Test name
Test status
Simulation time 44029103 ps
CPU time 2.16 seconds
Started Jun 11 12:49:07 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 216248 kb
Host smart-731ed37a-aa5f-456a-bd24-112de15d7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967788554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1967788554
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1477060008
Short name T692
Test name
Test status
Simulation time 322076135 ps
CPU time 2.63 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 208620 kb
Host smart-d9d02c89-f06d-4b92-b2a9-772cb64938c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477060008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1477060008
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1196855759
Short name T709
Test name
Test status
Simulation time 537218290 ps
CPU time 2.94 seconds
Started Jun 11 12:48:42 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 208384 kb
Host smart-e7507d20-7f00-4e6b-9daa-3aaaa4d6bc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196855759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1196855759
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3462567560
Short name T318
Test name
Test status
Simulation time 462035264 ps
CPU time 5.23 seconds
Started Jun 11 12:48:54 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 208200 kb
Host smart-08db6895-f99c-4d74-bf49-7f45a844aca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462567560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3462567560
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1873422263
Short name T399
Test name
Test status
Simulation time 82230901 ps
CPU time 2.07 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 210948 kb
Host smart-24d6cb60-ce04-42cd-95a2-7d8a94bcd950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873422263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1873422263
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.330258069
Short name T495
Test name
Test status
Simulation time 45386415 ps
CPU time 0.77 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:03 PM PDT 24
Peak memory 205976 kb
Host smart-335cdcf6-33e7-4465-ae6f-1b00f4f55978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330258069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.330258069
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.530079628
Short name T433
Test name
Test status
Simulation time 507279096 ps
CPU time 4.01 seconds
Started Jun 11 12:48:54 PM PDT 24
Finished Jun 11 12:48:59 PM PDT 24
Peak memory 215360 kb
Host smart-2b7263b5-81fd-4934-936d-d873272b653d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530079628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.530079628
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.199698215
Short name T718
Test name
Test status
Simulation time 64640163 ps
CPU time 2.36 seconds
Started Jun 11 12:49:02 PM PDT 24
Finished Jun 11 12:49:07 PM PDT 24
Peak memory 216920 kb
Host smart-ce88b630-e044-490a-9449-e1ea80024ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199698215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.199698215
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3723242946
Short name T827
Test name
Test status
Simulation time 239582971 ps
CPU time 3.14 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 210196 kb
Host smart-296e6fd6-5880-4e21-9319-2f2078e03f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723242946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3723242946
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.553040295
Short name T717
Test name
Test status
Simulation time 198196129 ps
CPU time 3.5 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 208832 kb
Host smart-f7832c96-3a0a-45cf-b777-d72d0bfc8e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553040295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.553040295
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2750525277
Short name T575
Test name
Test status
Simulation time 93151484 ps
CPU time 2.61 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:48:59 PM PDT 24
Peak memory 208664 kb
Host smart-ff5c7602-4792-443b-a14d-4186dbaf2486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750525277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2750525277
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3551028363
Short name T690
Test name
Test status
Simulation time 1327061470 ps
CPU time 4.74 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 209276 kb
Host smart-4554d060-2714-4af2-b30b-ce8059d637df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551028363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3551028363
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2995005412
Short name T445
Test name
Test status
Simulation time 1651746529 ps
CPU time 40.07 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:49:30 PM PDT 24
Peak memory 207828 kb
Host smart-288c9f4b-777a-4080-966d-b0e3e629a67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995005412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2995005412
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.62305469
Short name T521
Test name
Test status
Simulation time 213353643 ps
CPU time 5.65 seconds
Started Jun 11 12:48:48 PM PDT 24
Finished Jun 11 12:48:56 PM PDT 24
Peak memory 207888 kb
Host smart-08e70ca9-35b7-48b2-a064-e8d215a7fcb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62305469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.62305469
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3277452478
Short name T472
Test name
Test status
Simulation time 31877581 ps
CPU time 2 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 208092 kb
Host smart-6d4ecf97-bd18-4b1d-8121-f2961c906bbb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277452478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3277452478
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4172759222
Short name T596
Test name
Test status
Simulation time 54634111 ps
CPU time 2.4 seconds
Started Jun 11 12:48:47 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 207540 kb
Host smart-38d2ab0c-a683-43dd-b028-a3df03b484c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172759222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4172759222
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1923281432
Short name T793
Test name
Test status
Simulation time 19169961 ps
CPU time 1.68 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 207772 kb
Host smart-768ad40d-d57d-4f1c-ac5c-a475467e7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923281432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1923281432
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4256671017
Short name T617
Test name
Test status
Simulation time 467530037 ps
CPU time 3.38 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 208900 kb
Host smart-8d9b1a5f-fc2a-4a00-9beb-5e7b1f1c5870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256671017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4256671017
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2363375254
Short name T75
Test name
Test status
Simulation time 1167169516 ps
CPU time 7.65 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 216276 kb
Host smart-da935f7d-a19c-42e3-ac36-79efb2845c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363375254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2363375254
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1256526576
Short name T763
Test name
Test status
Simulation time 1179269269 ps
CPU time 15.57 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 222752 kb
Host smart-4d5e8853-2a87-4080-ac03-28a391c5e604
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256526576 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1256526576
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3054074060
Short name T91
Test name
Test status
Simulation time 291291391 ps
CPU time 7.63 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 209772 kb
Host smart-e17ddb3a-84b4-4eeb-982e-8d7ea98ac7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054074060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3054074060
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.930307559
Short name T919
Test name
Test status
Simulation time 2905803783 ps
CPU time 12.27 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 211300 kb
Host smart-20d2563f-e025-4e86-981a-c5bbbe739b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930307559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.930307559
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2836512551
Short name T443
Test name
Test status
Simulation time 60277957 ps
CPU time 0.95 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 206152 kb
Host smart-b875e5c3-b44d-432c-8948-eb688c266010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836512551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2836512551
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3308993695
Short name T791
Test name
Test status
Simulation time 231974756 ps
CPU time 2.36 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:49:00 PM PDT 24
Peak memory 214408 kb
Host smart-087717e7-3649-4be3-8755-ef39bc62db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308993695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3308993695
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.147629498
Short name T337
Test name
Test status
Simulation time 162861226 ps
CPU time 2.45 seconds
Started Jun 11 12:48:58 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 214264 kb
Host smart-1551e5c9-f1c9-4539-ba4e-06c500ee1ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147629498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.147629498
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.37600231
Short name T813
Test name
Test status
Simulation time 312558900 ps
CPU time 6.02 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 207704 kb
Host smart-b59d2017-230d-4009-b04b-6fc8c67e18d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37600231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.37600231
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3738961579
Short name T474
Test name
Test status
Simulation time 1741894126 ps
CPU time 42.71 seconds
Started Jun 11 12:48:54 PM PDT 24
Finished Jun 11 12:49:38 PM PDT 24
Peak memory 207924 kb
Host smart-475729cc-0720-4696-aa74-2d7609ba5c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738961579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3738961579
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1811212779
Short name T330
Test name
Test status
Simulation time 312191530 ps
CPU time 3.68 seconds
Started Jun 11 12:48:49 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 208676 kb
Host smart-2d1ffcab-9ade-448c-bae5-16f6a9934d6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811212779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1811212779
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1633073789
Short name T725
Test name
Test status
Simulation time 449215946 ps
CPU time 6.41 seconds
Started Jun 11 12:48:49 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 208844 kb
Host smart-b38d9d6c-54cd-42bc-99ae-a6d109e0c4fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633073789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1633073789
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2151882810
Short name T533
Test name
Test status
Simulation time 311665694 ps
CPU time 2.6 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 206960 kb
Host smart-00662398-c6df-48df-8a0e-451b8c12fbd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151882810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2151882810
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2921789441
Short name T740
Test name
Test status
Simulation time 70003683 ps
CPU time 2.78 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 210324 kb
Host smart-fa337b1c-32b5-455e-b5dc-58e89db134ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921789441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2921789441
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2690941514
Short name T874
Test name
Test status
Simulation time 32311958 ps
CPU time 2.16 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 206808 kb
Host smart-c1bb39cc-69a1-4443-a837-3cd17296001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690941514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2690941514
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.606926818
Short name T849
Test name
Test status
Simulation time 745761595 ps
CPU time 8.69 seconds
Started Jun 11 12:48:46 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 208164 kb
Host smart-ba2f7eca-d5f8-4385-9add-33070a7d766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606926818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.606926818
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2638751044
Short name T747
Test name
Test status
Simulation time 97945177 ps
CPU time 2.51 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 210356 kb
Host smart-d871b227-c3fd-4436-b431-4fee3c8dfb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638751044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2638751044
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2560526581
Short name T550
Test name
Test status
Simulation time 46791962 ps
CPU time 0.91 seconds
Started Jun 11 12:49:02 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 205996 kb
Host smart-25bb4e84-f9f4-40c4-a283-7d09ccb2cc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560526581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2560526581
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2280401584
Short name T31
Test name
Test status
Simulation time 125163461 ps
CPU time 5.61 seconds
Started Jun 11 12:49:08 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 218648 kb
Host smart-594db454-9242-460e-842c-4cee2e3e72f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280401584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2280401584
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1835515843
Short name T42
Test name
Test status
Simulation time 91167118 ps
CPU time 2.08 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 209536 kb
Host smart-5d400f40-1b9f-4ee2-8704-c59cfc6e94c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835515843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1835515843
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2725789376
Short name T755
Test name
Test status
Simulation time 212154854 ps
CPU time 3.52 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 209052 kb
Host smart-915fb9cb-8c77-4093-98c6-1f4b1d2d7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725789376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2725789376
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.889279582
Short name T524
Test name
Test status
Simulation time 354662576 ps
CPU time 4.33 seconds
Started Jun 11 12:49:08 PM PDT 24
Finished Jun 11 12:49:14 PM PDT 24
Peak memory 214404 kb
Host smart-c29191dd-41a1-4cb6-bbce-467121a59249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889279582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.889279582
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.703023841
Short name T716
Test name
Test status
Simulation time 902019773 ps
CPU time 2.69 seconds
Started Jun 11 12:49:01 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 216080 kb
Host smart-48a9190e-2d53-421b-b270-6a4b3e0ba863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703023841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.703023841
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2439932186
Short name T671
Test name
Test status
Simulation time 352917830 ps
CPU time 4.5 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 207780 kb
Host smart-ce7ce005-e0c4-4666-b1f6-decbdd1e8720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439932186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2439932186
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3737598472
Short name T483
Test name
Test status
Simulation time 520275832 ps
CPU time 11.05 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 208912 kb
Host smart-649c7402-f589-4cd0-90e3-9bb431f6dac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737598472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3737598472
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4083540975
Short name T735
Test name
Test status
Simulation time 71131383 ps
CPU time 3.32 seconds
Started Jun 11 12:48:51 PM PDT 24
Finished Jun 11 12:48:56 PM PDT 24
Peak memory 208848 kb
Host smart-d4bf2632-fbaa-48e6-8e58-8246112d3d0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083540975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4083540975
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2143716434
Short name T632
Test name
Test status
Simulation time 412229717 ps
CPU time 4.43 seconds
Started Jun 11 12:49:02 PM PDT 24
Finished Jun 11 12:49:08 PM PDT 24
Peak memory 208920 kb
Host smart-30b7b0aa-92da-4301-a232-e22705d51311
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143716434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2143716434
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3747994839
Short name T540
Test name
Test status
Simulation time 65910075 ps
CPU time 2.53 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 208564 kb
Host smart-56c87349-cc7b-4cdf-9374-bdf4649027b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747994839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3747994839
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3317364121
Short name T823
Test name
Test status
Simulation time 62037880 ps
CPU time 2.58 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 208476 kb
Host smart-ad712459-565b-44f3-bd8f-cec1053309bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317364121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3317364121
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.892819573
Short name T676
Test name
Test status
Simulation time 71472981 ps
CPU time 3.36 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 207628 kb
Host smart-3bc96e47-32de-4ce3-9209-d4a9bdb7b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892819573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.892819573
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2566891483
Short name T410
Test name
Test status
Simulation time 893642550 ps
CPU time 7.1 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 211052 kb
Host smart-fbf1d72a-5fc6-45a8-b817-6d2c04734130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566891483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2566891483
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1617604703
Short name T538
Test name
Test status
Simulation time 9506338 ps
CPU time 0.81 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 205920 kb
Host smart-72bb2550-af82-46a2-84f2-b3a0def2d602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617604703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1617604703
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3375101005
Short name T356
Test name
Test status
Simulation time 41343239 ps
CPU time 3.12 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 214296 kb
Host smart-a2eb027b-d33c-4f21-a7b4-6ebfbfeaa315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375101005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3375101005
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2320329777
Short name T883
Test name
Test status
Simulation time 193821589 ps
CPU time 3.88 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 222828 kb
Host smart-281efd87-ea1b-4357-8d6b-42181ee66e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320329777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2320329777
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.279509100
Short name T281
Test name
Test status
Simulation time 173588929 ps
CPU time 5.42 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 209992 kb
Host smart-537cb894-a3ce-4146-b59f-926ea71dc57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279509100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.279509100
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1099800432
Short name T829
Test name
Test status
Simulation time 58322171 ps
CPU time 2.99 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 214396 kb
Host smart-5551f592-aeeb-4cd0-88f9-f2bfd042e899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099800432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1099800432
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3206861096
Short name T838
Test name
Test status
Simulation time 114497506 ps
CPU time 2.29 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 222484 kb
Host smart-d088c8b8-e8c9-4076-8c51-2da5656b874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206861096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3206861096
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1551974537
Short name T670
Test name
Test status
Simulation time 161684741 ps
CPU time 4.96 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 209804 kb
Host smart-3a136871-2fe7-446d-ba87-dfaf8208edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551974537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1551974537
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1622738063
Short name T797
Test name
Test status
Simulation time 2281599003 ps
CPU time 48.87 seconds
Started Jun 11 12:49:25 PM PDT 24
Finished Jun 11 12:50:15 PM PDT 24
Peak memory 210328 kb
Host smart-fe6b86a8-ef3a-49b3-b23b-8ccd12795fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622738063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1622738063
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2246395163
Short name T872
Test name
Test status
Simulation time 277061003 ps
CPU time 3.22 seconds
Started Jun 11 12:48:55 PM PDT 24
Finished Jun 11 12:48:59 PM PDT 24
Peak memory 208568 kb
Host smart-5c96afb3-73f8-433f-9fdc-05feafa322fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246395163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2246395163
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1040877121
Short name T349
Test name
Test status
Simulation time 550328841 ps
CPU time 8.27 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 208360 kb
Host smart-a4d3c917-76d5-4b86-a9e6-4a41f2870d5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040877121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1040877121
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.729944627
Short name T598
Test name
Test status
Simulation time 65693049 ps
CPU time 2.35 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 207012 kb
Host smart-564f6644-2c46-4307-81b0-b8e2e77b5f87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729944627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.729944627
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3154785680
Short name T803
Test name
Test status
Simulation time 273352373 ps
CPU time 4.79 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 214424 kb
Host smart-6b1fc46e-534f-44d9-89bc-1f5eef07effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154785680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3154785680
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3538025539
Short name T478
Test name
Test status
Simulation time 470588449 ps
CPU time 10.64 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 208124 kb
Host smart-a410d062-5cad-45f3-9e25-790471f807fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538025539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3538025539
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.575532941
Short name T373
Test name
Test status
Simulation time 2373881207 ps
CPU time 24.16 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 222564 kb
Host smart-f7a61151-c292-499c-8180-dcce0ad7edf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575532941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.575532941
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3087967331
Short name T195
Test name
Test status
Simulation time 477981989 ps
CPU time 7.78 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 217664 kb
Host smart-331b3297-e759-4d3e-abc4-30995c854c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087967331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3087967331
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.185060709
Short name T146
Test name
Test status
Simulation time 174678180 ps
CPU time 5.29 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:08 PM PDT 24
Peak memory 218532 kb
Host smart-80071e57-7dbe-4543-9e33-e3b9c34e2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185060709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.185060709
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.412371091
Short name T776
Test name
Test status
Simulation time 54138867 ps
CPU time 2.4 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 210368 kb
Host smart-82fff2a1-9e42-4e38-8a52-107988ba1824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412371091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.412371091
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1784289850
Short name T764
Test name
Test status
Simulation time 33491008 ps
CPU time 0.79 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 205988 kb
Host smart-a0b8fa1a-0906-487f-8aff-ebde435049b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784289850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1784289850
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3214980433
Short name T611
Test name
Test status
Simulation time 212541569 ps
CPU time 4.91 seconds
Started Jun 11 12:48:55 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 210532 kb
Host smart-09a307f9-2499-4fad-bbef-fc672caceb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214980433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3214980433
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3642866941
Short name T323
Test name
Test status
Simulation time 92645343 ps
CPU time 1.87 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 214376 kb
Host smart-b1a80682-4187-4d17-9e0b-0f9369303e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642866941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3642866941
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.938567079
Short name T289
Test name
Test status
Simulation time 486220197 ps
CPU time 4.22 seconds
Started Jun 11 12:49:03 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 214388 kb
Host smart-dd19ac10-02b6-49b1-8984-307097f188cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938567079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.938567079
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_random.1571639460
Short name T215
Test name
Test status
Simulation time 846655314 ps
CPU time 4.67 seconds
Started Jun 11 12:48:52 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 210160 kb
Host smart-be17e7a1-842e-4b8d-81ee-1cd1b0b369ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571639460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1571639460
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1525837599
Short name T647
Test name
Test status
Simulation time 1680403322 ps
CPU time 43.29 seconds
Started Jun 11 12:48:59 PM PDT 24
Finished Jun 11 12:49:44 PM PDT 24
Peak memory 208692 kb
Host smart-090b2aad-c3e5-4179-a0ea-8bb12fbd4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525837599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1525837599
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1765679664
Short name T446
Test name
Test status
Simulation time 1679811428 ps
CPU time 10.75 seconds
Started Jun 11 12:49:03 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 208104 kb
Host smart-f64c42c1-b54b-42fb-ad5c-6cb8ca80e0bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765679664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1765679664
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4119506465
Short name T469
Test name
Test status
Simulation time 1236373657 ps
CPU time 14.41 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 209208 kb
Host smart-9c9952e1-fd9e-4f7f-9333-230c74da86f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119506465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4119506465
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1948374861
Short name T715
Test name
Test status
Simulation time 370555414 ps
CPU time 5.91 seconds
Started Jun 11 12:48:58 PM PDT 24
Finished Jun 11 12:49:04 PM PDT 24
Peak memory 208700 kb
Host smart-04a7cef7-085a-471b-a50b-dcb1dc5a03b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948374861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1948374861
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3712918394
Short name T826
Test name
Test status
Simulation time 122303925 ps
CPU time 2.51 seconds
Started Jun 11 12:48:50 PM PDT 24
Finished Jun 11 12:48:54 PM PDT 24
Peak memory 209468 kb
Host smart-78f402c3-0390-4596-a00a-499a112578a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712918394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3712918394
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2980715823
Short name T613
Test name
Test status
Simulation time 1084844334 ps
CPU time 9.31 seconds
Started Jun 11 12:49:07 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 208008 kb
Host smart-da0863df-3b01-4fc9-a941-6c370531fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980715823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2980715823
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.4073629747
Short name T646
Test name
Test status
Simulation time 1328297660 ps
CPU time 26.15 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 209048 kb
Host smart-e1a2ca42-dd6b-4153-a3f2-f2656a0e2035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073629747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.4073629747
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2302459295
Short name T810
Test name
Test status
Simulation time 84452104 ps
CPU time 4.04 seconds
Started Jun 11 12:48:52 PM PDT 24
Finished Jun 11 12:48:57 PM PDT 24
Peak memory 209240 kb
Host smart-c1269d3b-f65f-44b5-8aa8-90d5c64b298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302459295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2302459295
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1961708063
Short name T799
Test name
Test status
Simulation time 115605886 ps
CPU time 2.75 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 210408 kb
Host smart-313c8d5c-c0fe-45fa-925f-f2f9ba777d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961708063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1961708063
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2669652181
Short name T786
Test name
Test status
Simulation time 69796889 ps
CPU time 0.86 seconds
Started Jun 11 12:49:07 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 205984 kb
Host smart-c288a7f9-41c9-4b6d-b3e1-a96bb28fbacc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669652181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2669652181
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.849543287
Short name T733
Test name
Test status
Simulation time 3665571552 ps
CPU time 18.62 seconds
Started Jun 11 12:49:01 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 208512 kb
Host smart-4fd176fa-991b-4864-abf1-fcd039ff73ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849543287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.849543287
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1504602234
Short name T881
Test name
Test status
Simulation time 188776474 ps
CPU time 5.45 seconds
Started Jun 11 12:49:07 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 221956 kb
Host smart-ae461022-506f-4f2e-9e2c-573edda47e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504602234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1504602234
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3610898702
Short name T240
Test name
Test status
Simulation time 491110232 ps
CPU time 3.27 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 208516 kb
Host smart-852997a5-9a5b-413b-aeb5-49be2d215245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610898702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3610898702
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1636909388
Short name T645
Test name
Test status
Simulation time 46437954 ps
CPU time 2.82 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 207344 kb
Host smart-69d5d4e4-5a26-49db-a8be-afb959581588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636909388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1636909388
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3969388966
Short name T414
Test name
Test status
Simulation time 60990219 ps
CPU time 2.99 seconds
Started Jun 11 12:48:53 PM PDT 24
Finished Jun 11 12:48:57 PM PDT 24
Peak memory 206964 kb
Host smart-8dac2f3d-0739-4630-abbe-2a5f7c291b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969388966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3969388966
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.549352011
Short name T455
Test name
Test status
Simulation time 203931833 ps
CPU time 2.77 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 206820 kb
Host smart-a1f812cc-93b3-43de-ab6b-313a8dfe8698
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549352011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.549352011
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1198581270
Short name T498
Test name
Test status
Simulation time 241893507 ps
CPU time 2.75 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 206992 kb
Host smart-465c48a3-1b36-4dab-b95e-cb7338c06c2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198581270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1198581270
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.448399711
Short name T332
Test name
Test status
Simulation time 162312535 ps
CPU time 1.78 seconds
Started Jun 11 12:48:51 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 207040 kb
Host smart-91c832e5-bcb5-410d-9219-f48ecef6d475
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448399711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.448399711
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4214506764
Short name T412
Test name
Test status
Simulation time 171070477 ps
CPU time 3.65 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:25 PM PDT 24
Peak memory 209004 kb
Host smart-0b9c1c7c-db9f-46ff-8922-0a895d1aa924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214506764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4214506764
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1898089933
Short name T83
Test name
Test status
Simulation time 154184934 ps
CPU time 2.32 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 206780 kb
Host smart-0dfad38e-f77f-4416-83a3-1a31ba3001fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898089933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1898089933
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3630848330
Short name T302
Test name
Test status
Simulation time 1660037819 ps
CPU time 22.73 seconds
Started Jun 11 12:48:57 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 216196 kb
Host smart-f2900335-a288-4aaa-afa5-6df044bdfa85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630848330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3630848330
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1296274135
Short name T388
Test name
Test status
Simulation time 202108844 ps
CPU time 3.51 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:25 PM PDT 24
Peak memory 207836 kb
Host smart-fc807f3a-acd0-4216-8752-40d2adec5069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296274135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1296274135
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1875550055
Short name T901
Test name
Test status
Simulation time 34693861 ps
CPU time 1.59 seconds
Started Jun 11 12:49:04 PM PDT 24
Finished Jun 11 12:49:08 PM PDT 24
Peak memory 209960 kb
Host smart-86243d5f-14fe-45f1-abec-e13463a4c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875550055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1875550055
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2140080991
Short name T749
Test name
Test status
Simulation time 14899714 ps
CPU time 0.71 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 205988 kb
Host smart-9a3bfe51-93b7-4355-866f-8cfc2dc4b02d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140080991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2140080991
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1034543422
Short name T397
Test name
Test status
Simulation time 106677559 ps
CPU time 2.3 seconds
Started Jun 11 12:49:07 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 214404 kb
Host smart-d3f2101f-9f22-4789-8923-06220fc4e4f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034543422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1034543422
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.723271486
Short name T580
Test name
Test status
Simulation time 2303987827 ps
CPU time 10.15 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:29 PM PDT 24
Peak memory 214836 kb
Host smart-969d018d-8668-49ee-98fd-6c4a5bb91337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723271486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.723271486
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4017451596
Short name T819
Test name
Test status
Simulation time 104301277 ps
CPU time 2.63 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 209100 kb
Host smart-bfbb7865-76df-40bd-aac4-614cc80a047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017451596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4017451596
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.328290295
Short name T92
Test name
Test status
Simulation time 53742326 ps
CPU time 2.09 seconds
Started Jun 11 12:49:00 PM PDT 24
Finished Jun 11 12:49:05 PM PDT 24
Peak memory 214308 kb
Host smart-8314adc7-2548-4890-bf01-080248ee3827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328290295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.328290295
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2683573896
Short name T243
Test name
Test status
Simulation time 316067331 ps
CPU time 8.54 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 220464 kb
Host smart-716c50b2-aaac-450b-97bb-76e13c001524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683573896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2683573896
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1680875870
Short name T597
Test name
Test status
Simulation time 623475947 ps
CPU time 10.22 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 218528 kb
Host smart-0a8917f7-99b2-4087-9440-5831a37aae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680875870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1680875870
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1196831830
Short name T519
Test name
Test status
Simulation time 65416664 ps
CPU time 2.83 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 208228 kb
Host smart-9dabff33-c65d-4d06-8a83-ed5abbf6c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196831830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1196831830
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2689899295
Short name T118
Test name
Test status
Simulation time 75005226 ps
CPU time 2.31 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 207036 kb
Host smart-23a46e54-74c5-4b55-b248-e90608f187de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689899295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2689899295
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2231732646
Short name T536
Test name
Test status
Simulation time 208262751 ps
CPU time 2.69 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 206960 kb
Host smart-1a2e84e4-6536-4320-8d73-d423fbe19742
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231732646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2231732646
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1021870479
Short name T633
Test name
Test status
Simulation time 210341641 ps
CPU time 6.08 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 208224 kb
Host smart-6ac7b94a-ff21-4891-8144-55113005caf0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021870479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1021870479
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3704362183
Short name T346
Test name
Test status
Simulation time 334130339 ps
CPU time 4.49 seconds
Started Jun 11 12:48:56 PM PDT 24
Finished Jun 11 12:49:02 PM PDT 24
Peak memory 218608 kb
Host smart-879bccf8-62d0-4261-a5ce-fedb697f4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704362183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3704362183
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.657053086
Short name T616
Test name
Test status
Simulation time 335209421 ps
CPU time 4.23 seconds
Started Jun 11 12:49:03 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 208588 kb
Host smart-584f3b29-292c-41fc-ad5f-42801a6407ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657053086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.657053086
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.420595683
Short name T144
Test name
Test status
Simulation time 566738397 ps
CPU time 6.61 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 218168 kb
Host smart-09d51731-d5e3-4d4c-9ac4-099126ba84cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420595683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.420595683
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1663924783
Short name T401
Test name
Test status
Simulation time 68277053 ps
CPU time 1.78 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 209944 kb
Host smart-12ef24b6-036d-4159-8310-d06264bd54d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663924783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1663924783
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2372725637
Short name T484
Test name
Test status
Simulation time 11604142 ps
CPU time 0.88 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 205920 kb
Host smart-009cccd5-b8a7-4031-8f32-2efdd55c68d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372725637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2372725637
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.102509488
Short name T892
Test name
Test status
Simulation time 213579925 ps
CPU time 2.76 seconds
Started Jun 11 12:49:01 PM PDT 24
Finished Jun 11 12:49:07 PM PDT 24
Peak memory 214424 kb
Host smart-f0389428-0c5d-4a5e-9025-3ad9da44e06c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102509488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.102509488
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4133471721
Short name T742
Test name
Test status
Simulation time 76690147 ps
CPU time 3.38 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:26 PM PDT 24
Peak memory 208944 kb
Host smart-c558f426-62ae-4edd-8bb3-ed37ee312085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133471721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4133471721
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3231612947
Short name T326
Test name
Test status
Simulation time 330717967 ps
CPU time 3.47 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 218340 kb
Host smart-c370f00f-ea25-4d92-a807-946a8452c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231612947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3231612947
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2213102059
Short name T288
Test name
Test status
Simulation time 88993319 ps
CPU time 1.93 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 214952 kb
Host smart-7c22afde-2757-48cb-98aa-75a7754c6dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213102059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2213102059
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1472705760
Short name T229
Test name
Test status
Simulation time 72249212 ps
CPU time 2.68 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 209644 kb
Host smart-9feb42c0-7dd1-484f-8415-8fb0548b549f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472705760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1472705760
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.686185132
Short name T847
Test name
Test status
Simulation time 316741682 ps
CPU time 4.29 seconds
Started Jun 11 12:49:26 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 208088 kb
Host smart-82c1756c-2322-4246-9dc7-9f6910586e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686185132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.686185132
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3223093185
Short name T263
Test name
Test status
Simulation time 30712742 ps
CPU time 1.96 seconds
Started Jun 11 12:49:03 PM PDT 24
Finished Jun 11 12:49:07 PM PDT 24
Peak memory 208740 kb
Host smart-2c5d5a3f-cbd5-4a4d-9d7d-f74ebd899b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223093185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3223093185
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3407903876
Short name T556
Test name
Test status
Simulation time 334781655 ps
CPU time 2.94 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 206864 kb
Host smart-0ce9068f-f317-4cc3-84d0-54fd6bf1701b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407903876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3407903876
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2327688565
Short name T835
Test name
Test status
Simulation time 147491889 ps
CPU time 4.23 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 208812 kb
Host smart-baad4823-6db2-435b-a2b6-6380967b709f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327688565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2327688565
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4154446717
Short name T830
Test name
Test status
Simulation time 947059411 ps
CPU time 5.26 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 208612 kb
Host smart-85846066-e4cb-4194-8650-08257afc29d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154446717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4154446717
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.300919372
Short name T899
Test name
Test status
Simulation time 257506358 ps
CPU time 3.58 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 208812 kb
Host smart-69a9ae79-76e3-4388-858a-a5b591981b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300919372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.300919372
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3081318675
Short name T815
Test name
Test status
Simulation time 192716756 ps
CPU time 6 seconds
Started Jun 11 12:49:03 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 206920 kb
Host smart-222af39a-a438-4546-a717-3f7baafd3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081318675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3081318675
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.299779208
Short name T245
Test name
Test status
Simulation time 2328175950 ps
CPU time 32.98 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 222576 kb
Host smart-4706a8d3-7c2e-49bc-a0e3-8e770b223ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299779208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.299779208
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3665139421
Short name T79
Test name
Test status
Simulation time 133663573 ps
CPU time 8.23 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:28 PM PDT 24
Peak memory 222700 kb
Host smart-94da1812-6c22-41ea-96f1-a11a594636d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665139421 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3665139421
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2417764193
Short name T470
Test name
Test status
Simulation time 2043907832 ps
CPU time 25.18 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 208244 kb
Host smart-6bc91311-997f-4e49-9789-91e519179574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417764193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2417764193
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.307135189
Short name T61
Test name
Test status
Simulation time 131248434 ps
CPU time 2.18 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 210284 kb
Host smart-6dcf1727-d385-4812-818f-8229eae14a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307135189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.307135189
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3937041491
Short name T687
Test name
Test status
Simulation time 23093049 ps
CPU time 0.85 seconds
Started Jun 11 12:49:06 PM PDT 24
Finished Jun 11 12:49:09 PM PDT 24
Peak memory 206016 kb
Host smart-1a518934-2534-4e0b-8aee-adbdd4d35bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937041491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3937041491
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2868760350
Short name T148
Test name
Test status
Simulation time 109191900 ps
CPU time 3.7 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 214392 kb
Host smart-62b59b21-00ff-4656-bbc8-776bee4e692d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868760350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2868760350
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1025407760
Short name T705
Test name
Test status
Simulation time 83463213 ps
CPU time 1.56 seconds
Started Jun 11 12:49:33 PM PDT 24
Finished Jun 11 12:49:36 PM PDT 24
Peak memory 209616 kb
Host smart-f679e02d-19b1-4b38-b155-4853a31bcb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025407760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1025407760
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3828938763
Short name T770
Test name
Test status
Simulation time 146574278 ps
CPU time 5.72 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 209744 kb
Host smart-29d6df6d-bae5-4265-9bfa-9f8d6a5a236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828938763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3828938763
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.274821297
Short name T66
Test name
Test status
Simulation time 57198025 ps
CPU time 3.53 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 208324 kb
Host smart-c7b25a87-8c79-40e5-aafd-8f713536dc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274821297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.274821297
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1585635304
Short name T501
Test name
Test status
Simulation time 293662766 ps
CPU time 3.81 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 214412 kb
Host smart-71c04535-e106-4a7e-ad12-0deba26d1524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585635304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1585635304
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2121785295
Short name T588
Test name
Test status
Simulation time 66404476 ps
CPU time 3.07 seconds
Started Jun 11 12:49:07 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 208064 kb
Host smart-c40fedfa-7bd5-4c33-b9ba-ff222f4cdb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121785295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2121785295
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2937456157
Short name T792
Test name
Test status
Simulation time 39903539 ps
CPU time 2.57 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 208600 kb
Host smart-7e84f9fe-f14b-467a-89fb-9448f670a719
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937456157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2937456157
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4184625944
Short name T90
Test name
Test status
Simulation time 2439791030 ps
CPU time 29.77 seconds
Started Jun 11 12:49:05 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 208604 kb
Host smart-034afd46-c8aa-4b22-a031-698f0606d547
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184625944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4184625944
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.483975542
Short name T312
Test name
Test status
Simulation time 86442113 ps
CPU time 1.76 seconds
Started Jun 11 12:49:32 PM PDT 24
Finished Jun 11 12:49:35 PM PDT 24
Peak memory 209656 kb
Host smart-36ad0cc3-ad44-46a4-a259-f2e335acba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483975542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.483975542
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3077983241
Short name T862
Test name
Test status
Simulation time 182835622 ps
CPU time 3.92 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 206928 kb
Host smart-8bd56c01-2feb-4701-abf1-7af8190ddd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077983241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3077983241
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1491117010
Short name T222
Test name
Test status
Simulation time 798740443 ps
CPU time 22.4 seconds
Started Jun 11 12:49:25 PM PDT 24
Finished Jun 11 12:49:49 PM PDT 24
Peak memory 215452 kb
Host smart-dd1a0d0f-88cb-4fc1-a42a-97238ed84443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491117010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1491117010
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2789534543
Short name T199
Test name
Test status
Simulation time 3865927977 ps
CPU time 22.81 seconds
Started Jun 11 12:49:27 PM PDT 24
Finished Jun 11 12:49:51 PM PDT 24
Peak memory 222684 kb
Host smart-1ea3f6d7-4ec3-4c2b-bd3e-89f2335e29bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789534543 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2789534543
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3377359457
Short name T352
Test name
Test status
Simulation time 92036298 ps
CPU time 3.59 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:25 PM PDT 24
Peak memory 209300 kb
Host smart-3a9aecc0-1dde-408b-8c24-ea4b55c89dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377359457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3377359457
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.843013069
Short name T37
Test name
Test status
Simulation time 40044723 ps
CPU time 2.17 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:14 PM PDT 24
Peak memory 210172 kb
Host smart-aa2d2912-6a8e-44ff-9d4e-b17c99a4529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843013069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.843013069
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1198510808
Short name T496
Test name
Test status
Simulation time 16532097 ps
CPU time 0.68 seconds
Started Jun 11 12:48:17 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 206000 kb
Host smart-47e27aba-0ef6-4771-b868-4f59f7567155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198510808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1198510808
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3170384768
Short name T398
Test name
Test status
Simulation time 2316779312 ps
CPU time 122.08 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 215364 kb
Host smart-e8309f70-64e9-4428-9ef9-aad5a11f1773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170384768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3170384768
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1697379468
Short name T806
Test name
Test status
Simulation time 451160939 ps
CPU time 9.91 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:21 PM PDT 24
Peak memory 222944 kb
Host smart-67c8f5aa-a315-4b01-b14e-8a5d564796af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697379468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1697379468
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4087609079
Short name T351
Test name
Test status
Simulation time 257418699 ps
CPU time 2.39 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:04 PM PDT 24
Peak memory 207988 kb
Host smart-729f7908-8ae4-4694-b2bc-dbb805b8305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087609079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4087609079
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2802638152
Short name T308
Test name
Test status
Simulation time 254448109 ps
CPU time 2.03 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 214396 kb
Host smart-cfb0fb18-45ad-4b8a-b4e8-a93be0bb15d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802638152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2802638152
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1226501402
Short name T589
Test name
Test status
Simulation time 209540420 ps
CPU time 1.85 seconds
Started Jun 11 12:48:06 PM PDT 24
Finished Jun 11 12:48:09 PM PDT 24
Peak memory 221956 kb
Host smart-a2b855a5-ec62-4408-bed5-b995611bb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226501402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1226501402
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1646141186
Short name T491
Test name
Test status
Simulation time 392182864 ps
CPU time 4.76 seconds
Started Jun 11 12:48:10 PM PDT 24
Finished Jun 11 12:48:17 PM PDT 24
Peak memory 208924 kb
Host smart-fb462d64-7dc9-4288-8e9b-1dab503e6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646141186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1646141186
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3600499881
Short name T630
Test name
Test status
Simulation time 162506057 ps
CPU time 6.55 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 218224 kb
Host smart-1ea25ea4-e5b1-4039-b679-52f4612f9b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600499881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3600499881
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.736779872
Short name T10
Test name
Test status
Simulation time 561988443 ps
CPU time 7.38 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 233552 kb
Host smart-f32e70d3-0f66-4538-a330-adaa1a378a1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736779872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.736779872
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3421897683
Short name T554
Test name
Test status
Simulation time 23658735 ps
CPU time 1.79 seconds
Started Jun 11 12:48:26 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 207464 kb
Host smart-0672b854-5b87-4453-ba4c-285196c78e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421897683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3421897683
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.524710522
Short name T607
Test name
Test status
Simulation time 91078751 ps
CPU time 2.63 seconds
Started Jun 11 12:48:22 PM PDT 24
Finished Jun 11 12:48:32 PM PDT 24
Peak memory 208840 kb
Host smart-c1f31f97-3851-4a60-9f93-43b78fde008e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524710522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.524710522
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3672565238
Short name T551
Test name
Test status
Simulation time 268956834 ps
CPU time 2.47 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 208784 kb
Host smart-5e465ad1-d155-4ead-8844-0f7f197f5203
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672565238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3672565238
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3652403954
Short name T601
Test name
Test status
Simulation time 157642492 ps
CPU time 6.5 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 207116 kb
Host smart-c0e198bf-91f6-4364-91b1-6f2775795b16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652403954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3652403954
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3258125377
Short name T473
Test name
Test status
Simulation time 1946929398 ps
CPU time 4.49 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 214368 kb
Host smart-69124038-a7d0-43c8-b777-84f42a5a5b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258125377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3258125377
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2966112626
Short name T456
Test name
Test status
Simulation time 202805956 ps
CPU time 4.23 seconds
Started Jun 11 12:48:17 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 208676 kb
Host smart-84379420-341b-4d17-9d2a-bc8f00a54900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966112626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2966112626
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3210971687
Short name T202
Test name
Test status
Simulation time 6328458492 ps
CPU time 30.74 seconds
Started Jun 11 12:48:22 PM PDT 24
Finished Jun 11 12:48:56 PM PDT 24
Peak memory 219772 kb
Host smart-9c9f40bc-38c8-4220-b811-2bf15e0c1031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210971687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3210971687
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2485990797
Short name T914
Test name
Test status
Simulation time 133796026 ps
CPU time 3.54 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:17 PM PDT 24
Peak memory 209384 kb
Host smart-6aa5abf0-3288-4ef8-940b-62acbec1e0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485990797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2485990797
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2205544263
Short name T783
Test name
Test status
Simulation time 23355573 ps
CPU time 0.81 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 205956 kb
Host smart-026ab68b-dd5e-4e17-a576-7546827d689c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205544263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2205544263
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.326520231
Short name T435
Test name
Test status
Simulation time 57365115 ps
CPU time 2.42 seconds
Started Jun 11 12:49:10 PM PDT 24
Finished Jun 11 12:49:14 PM PDT 24
Peak memory 214296 kb
Host smart-a26453ee-929e-4d13-88a6-b109aceb49cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326520231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.326520231
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1863263345
Short name T663
Test name
Test status
Simulation time 208381418 ps
CPU time 2.07 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 214364 kb
Host smart-628a19a8-df10-4b43-adba-aa5c1cf1c675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863263345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1863263345
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1332755807
Short name T81
Test name
Test status
Simulation time 53661125 ps
CPU time 2.77 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:28 PM PDT 24
Peak memory 209100 kb
Host smart-5e105031-9732-45d6-9d82-136761003553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332755807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1332755807
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3809230260
Short name T102
Test name
Test status
Simulation time 96918950 ps
CPU time 4.73 seconds
Started Jun 11 12:49:25 PM PDT 24
Finished Jun 11 12:49:31 PM PDT 24
Peak memory 214252 kb
Host smart-5985f2f0-96da-4425-ae8d-e4e80c54194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809230260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3809230260
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.992271684
Short name T615
Test name
Test status
Simulation time 40603737 ps
CPU time 2.99 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 212000 kb
Host smart-af3184ee-49c9-47aa-88d9-1ef4e6b88e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992271684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.992271684
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2566492561
Short name T191
Test name
Test status
Simulation time 78296905 ps
CPU time 3.69 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 209848 kb
Host smart-1ec9e363-25e7-4507-a4c7-21a5a77ce266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566492561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2566492561
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3795284754
Short name T354
Test name
Test status
Simulation time 299800851 ps
CPU time 4.35 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 209140 kb
Host smart-09b94887-a08f-4f98-829a-0f3bce6e44d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795284754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3795284754
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.802344624
Short name T503
Test name
Test status
Simulation time 57215665 ps
CPU time 2.85 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 206144 kb
Host smart-00293e85-bf52-4e2a-8d78-639ef1b143fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802344624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.802344624
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2402519402
Short name T14
Test name
Test status
Simulation time 127325963 ps
CPU time 2.41 seconds
Started Jun 11 12:49:22 PM PDT 24
Finished Jun 11 12:49:26 PM PDT 24
Peak memory 207784 kb
Host smart-b01cf9ea-727d-4443-8e65-f7d838f8ae62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402519402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2402519402
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3286861185
Short name T387
Test name
Test status
Simulation time 144949096 ps
CPU time 2.57 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 208776 kb
Host smart-d5e23de2-db88-4ff4-80d2-30e2e7276717
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286861185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3286861185
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1793643363
Short name T449
Test name
Test status
Simulation time 780999320 ps
CPU time 8.39 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 208364 kb
Host smart-20d30e79-305d-4a7a-8bb3-bc0bd0432a7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793643363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1793643363
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.961556668
Short name T541
Test name
Test status
Simulation time 30493669 ps
CPU time 2.16 seconds
Started Jun 11 12:49:09 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 209864 kb
Host smart-8a7ab08f-af37-4f5c-9a54-81568e8f0043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961556668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.961556668
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1694821887
Short name T624
Test name
Test status
Simulation time 1356406989 ps
CPU time 33.61 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:51 PM PDT 24
Peak memory 208444 kb
Host smart-5979ea07-0bd5-4152-8b14-d4f24762da70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694821887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1694821887
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2883294951
Short name T734
Test name
Test status
Simulation time 1623534781 ps
CPU time 10.82 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 222636 kb
Host smart-c1cc1460-49cd-495a-8f69-fabdd612be86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883294951 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2883294951
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3750321909
Short name T115
Test name
Test status
Simulation time 502855537 ps
CPU time 9.18 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 209172 kb
Host smart-f7a05349-1d50-4113-92df-a57e84a5c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750321909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3750321909
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2271007468
Short name T402
Test name
Test status
Simulation time 64522603 ps
CPU time 2.4 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 209948 kb
Host smart-453517ea-878d-4377-9a4b-3db124036f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271007468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2271007468
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3717494548
Short name T480
Test name
Test status
Simulation time 18006610 ps
CPU time 0.76 seconds
Started Jun 11 12:49:26 PM PDT 24
Finished Jun 11 12:49:28 PM PDT 24
Peak memory 205984 kb
Host smart-459c1eaf-3b63-41d4-9725-4276a3fa33c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717494548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3717494548
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.833949888
Short name T315
Test name
Test status
Simulation time 293213683 ps
CPU time 6.64 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 214304 kb
Host smart-51aa864e-2719-4b2a-a996-f59699a6d108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833949888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.833949888
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1360717554
Short name T192
Test name
Test status
Simulation time 109817853 ps
CPU time 1.75 seconds
Started Jun 11 12:49:31 PM PDT 24
Finished Jun 11 12:49:35 PM PDT 24
Peak memory 217936 kb
Host smart-2d46ebe0-3655-4a51-a2e5-3f1031d361ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360717554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1360717554
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3036840671
Short name T393
Test name
Test status
Simulation time 32798529 ps
CPU time 2.18 seconds
Started Jun 11 12:49:31 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 208444 kb
Host smart-948cb679-c112-4da9-a47c-e1a3daa33aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036840671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3036840671
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.545395505
Short name T548
Test name
Test status
Simulation time 123547414 ps
CPU time 2.91 seconds
Started Jun 11 12:49:27 PM PDT 24
Finished Jun 11 12:49:31 PM PDT 24
Peak memory 214412 kb
Host smart-0dac4c34-b968-4531-810b-c9489d975926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545395505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.545395505
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2174195179
Short name T32
Test name
Test status
Simulation time 831899116 ps
CPU time 5.36 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 214332 kb
Host smart-f2bd814c-a0f6-4757-8378-84b0f58407e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174195179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2174195179
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.668049813
Short name T848
Test name
Test status
Simulation time 48319806 ps
CPU time 2.34 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 210324 kb
Host smart-8d211e06-63de-472e-b2a9-72705a6081f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668049813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.668049813
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3722870139
Short name T737
Test name
Test status
Simulation time 118192040 ps
CPU time 3.88 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 207876 kb
Host smart-d0e11010-6c72-4712-bd58-3075e02afd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722870139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3722870139
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2545643504
Short name T440
Test name
Test status
Simulation time 98779370 ps
CPU time 2.71 seconds
Started Jun 11 12:49:08 PM PDT 24
Finished Jun 11 12:49:13 PM PDT 24
Peak memory 206868 kb
Host smart-87b47cef-cd3f-4097-b430-f42984ddbdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545643504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2545643504
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2804414904
Short name T506
Test name
Test status
Simulation time 787653689 ps
CPU time 3 seconds
Started Jun 11 12:49:11 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 207028 kb
Host smart-ff3c12ec-fa12-4c21-8bbe-0cd6b3fba3cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804414904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2804414904
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4205035202
Short name T642
Test name
Test status
Simulation time 553583903 ps
CPU time 12.23 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 208644 kb
Host smart-9f7f8927-77f9-475f-9857-aa0cde678035
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205035202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4205035202
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1194780422
Short name T409
Test name
Test status
Simulation time 70095245 ps
CPU time 3.56 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 208416 kb
Host smart-3aacfae6-3518-4d11-9211-2f74dc255a96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194780422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1194780422
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1998765898
Short name T694
Test name
Test status
Simulation time 116735072 ps
CPU time 4.23 seconds
Started Jun 11 12:49:41 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 214508 kb
Host smart-9becf872-7ea1-43a7-affb-beda1db8eed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998765898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1998765898
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.146322517
Short name T539
Test name
Test status
Simulation time 136820655 ps
CPU time 1.91 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 206964 kb
Host smart-f5867c2e-de95-4b2a-8efb-268de1e62806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146322517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.146322517
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2186199154
Short name T365
Test name
Test status
Simulation time 3716003569 ps
CPU time 98.2 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:50:57 PM PDT 24
Peak memory 222588 kb
Host smart-d2094f7d-8a8c-4ea5-a89a-d55ba02724b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186199154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2186199154
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2681184891
Short name T271
Test name
Test status
Simulation time 2861352921 ps
CPU time 20.99 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:35 PM PDT 24
Peak memory 209856 kb
Host smart-20773640-769b-481f-95d9-eba15537e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681184891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2681184891
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.386965113
Short name T912
Test name
Test status
Simulation time 70150530 ps
CPU time 1.79 seconds
Started Jun 11 12:49:34 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 210332 kb
Host smart-88932c0e-6532-4721-a06f-5c3115669f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386965113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.386965113
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2305681585
Short name T584
Test name
Test status
Simulation time 12754590 ps
CPU time 0.87 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 205968 kb
Host smart-50f0dc20-9811-49b0-8d92-efe9903d50c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305681585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2305681585
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2023080272
Short name T419
Test name
Test status
Simulation time 140907564 ps
CPU time 2.81 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 214312 kb
Host smart-4695c0e4-1298-4923-9a70-08d7a1173cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023080272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2023080272
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2725516105
Short name T546
Test name
Test status
Simulation time 142029628 ps
CPU time 3.09 seconds
Started Jun 11 12:49:23 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 217332 kb
Host smart-c2084694-2f8f-4267-b158-993bc4e0f84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725516105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2725516105
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1216237593
Short name T620
Test name
Test status
Simulation time 23159341 ps
CPU time 1.33 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 207648 kb
Host smart-2ba3d812-95bb-445a-8884-432b5382b441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216237593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1216237593
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2797775998
Short name T708
Test name
Test status
Simulation time 619756607 ps
CPU time 8.97 seconds
Started Jun 11 12:49:23 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 208840 kb
Host smart-0ffdb894-67d5-4f95-a7a6-60a5c703df89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797775998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2797775998
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1434363502
Short name T703
Test name
Test status
Simulation time 201536937 ps
CPU time 2.13 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 211132 kb
Host smart-84b77682-cd48-408d-8fe8-6c5dea3d5b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434363502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1434363502
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2325324930
Short name T824
Test name
Test status
Simulation time 91482316 ps
CPU time 2.86 seconds
Started Jun 11 12:49:23 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 207824 kb
Host smart-754dc327-e6bd-412e-8d51-47a7134e6779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325324930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2325324930
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1613804216
Short name T88
Test name
Test status
Simulation time 360388488 ps
CPU time 3.52 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 208912 kb
Host smart-319a7f01-c9ae-46d3-8d29-41905dff5a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613804216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1613804216
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4275395872
Short name T366
Test name
Test status
Simulation time 190712230 ps
CPU time 5.13 seconds
Started Jun 11 12:49:34 PM PDT 24
Finished Jun 11 12:49:40 PM PDT 24
Peak memory 207936 kb
Host smart-7f81fecd-4aa4-404c-b2ec-c106a807d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275395872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4275395872
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2924718566
Short name T555
Test name
Test status
Simulation time 24685514 ps
CPU time 1.94 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 208892 kb
Host smart-998b5553-d95f-4921-a3d1-f7c0eb820026
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924718566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2924718566
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.647652045
Short name T532
Test name
Test status
Simulation time 6585865805 ps
CPU time 38.53 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 208008 kb
Host smart-ac216dc2-62a1-4c4d-984f-2955a2e50e1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647652045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.647652045
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.55074239
Short name T385
Test name
Test status
Simulation time 678299271 ps
CPU time 5.23 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 208900 kb
Host smart-5219a4d1-1db9-4efe-afb5-bda253b64db9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55074239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.55074239
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1844933638
Short name T685
Test name
Test status
Simulation time 80308594 ps
CPU time 3.39 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 210312 kb
Host smart-4bf7948a-7393-4d0a-aeaa-8c0b24ab8536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844933638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1844933638
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2979467418
Short name T467
Test name
Test status
Simulation time 115208796 ps
CPU time 4.31 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 208220 kb
Host smart-0083d71c-c195-4dd4-8355-948a70b33601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979467418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2979467418
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.458662409
Short name T217
Test name
Test status
Simulation time 394192060 ps
CPU time 3.95 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 207576 kb
Host smart-4dfd276d-fe3b-4e6b-aa1f-2e7bf9d26211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458662409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.458662409
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1610620116
Short name T51
Test name
Test status
Simulation time 26551423 ps
CPU time 1.73 seconds
Started Jun 11 12:49:20 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 209912 kb
Host smart-051d5198-c9e0-414b-a573-cf8fb364f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610620116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1610620116
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.336225111
Short name T442
Test name
Test status
Simulation time 33241749 ps
CPU time 0.89 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 206012 kb
Host smart-850d2a53-3204-44e6-b261-2f1e0f812314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336225111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.336225111
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2766467780
Short name T29
Test name
Test status
Simulation time 166519650 ps
CPU time 2.33 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:18 PM PDT 24
Peak memory 214404 kb
Host smart-4b5af1b9-5036-43bc-aed7-fd0d70c60992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766467780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2766467780
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3465602326
Short name T117
Test name
Test status
Simulation time 34502415 ps
CPU time 1.79 seconds
Started Jun 11 12:49:36 PM PDT 24
Finished Jun 11 12:49:40 PM PDT 24
Peak memory 209356 kb
Host smart-49216bfc-dacd-41fd-a43b-ef63b7c19f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465602326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3465602326
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4158970736
Short name T379
Test name
Test status
Simulation time 118864987 ps
CPU time 2.01 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:30 PM PDT 24
Peak memory 214388 kb
Host smart-fc014f8e-9b01-41fc-8b0e-6f8ad2603dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158970736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4158970736
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2461374012
Short name T259
Test name
Test status
Simulation time 264059419 ps
CPU time 3.13 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 214360 kb
Host smart-0a2ef773-f864-4cac-8ad1-c391e3774b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461374012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2461374012
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2321367733
Short name T40
Test name
Test status
Simulation time 92610635 ps
CPU time 3.59 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 209680 kb
Host smart-6ae9817f-242a-43b7-a925-66ab81c34815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321367733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2321367733
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2849863291
Short name T606
Test name
Test status
Simulation time 604441454 ps
CPU time 7.46 seconds
Started Jun 11 12:49:34 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 208776 kb
Host smart-a4bc2b6a-2855-4a90-9bef-f8db314a1927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849863291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2849863291
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2690534766
Short name T415
Test name
Test status
Simulation time 49355050 ps
CPU time 2.69 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 206952 kb
Host smart-692ce879-d7ad-4e4a-b132-960ba9db1131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690534766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2690534766
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4095316830
Short name T137
Test name
Test status
Simulation time 558121046 ps
CPU time 4.27 seconds
Started Jun 11 12:49:33 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 208236 kb
Host smart-e2637824-2970-41e0-bb36-782faef2b246
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095316830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4095316830
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2076965122
Short name T825
Test name
Test status
Simulation time 494695784 ps
CPU time 4.19 seconds
Started Jun 11 12:49:27 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 208548 kb
Host smart-fdfe9a67-271f-455c-bfb7-a9d7df493f2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076965122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2076965122
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4085869124
Short name T558
Test name
Test status
Simulation time 991290103 ps
CPU time 31.91 seconds
Started Jun 11 12:49:26 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 208860 kb
Host smart-8b69f53f-14d0-441c-ab4c-7691813310c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085869124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4085869124
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1656714715
Short name T695
Test name
Test status
Simulation time 559201399 ps
CPU time 4.37 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 214400 kb
Host smart-88e5b9e7-d6a0-48ca-9e20-8a0e46103ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656714715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1656714715
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1740894616
Short name T579
Test name
Test status
Simulation time 57479786 ps
CPU time 2.45 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:44 PM PDT 24
Peak memory 208540 kb
Host smart-5109b1bb-363b-40ae-ae98-8ee7f0b689e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740894616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1740894616
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1194753431
Short name T391
Test name
Test status
Simulation time 198247129 ps
CPU time 9.19 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:51 PM PDT 24
Peak memory 215240 kb
Host smart-372c157d-bccc-47ea-bf08-664afdf263b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194753431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1194753431
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2006446033
Short name T552
Test name
Test status
Simulation time 811761532 ps
CPU time 9.98 seconds
Started Jun 11 12:49:21 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 218792 kb
Host smart-bdface3a-8ff8-4935-af1c-f481218e2432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006446033 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2006446033
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3167258739
Short name T389
Test name
Test status
Simulation time 226849322 ps
CPU time 3.9 seconds
Started Jun 11 12:49:26 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 210264 kb
Host smart-99fcf47a-6ace-47e3-8423-9bd72812a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167258739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3167258739
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.295001005
Short name T879
Test name
Test status
Simulation time 389628569 ps
CPU time 1.66 seconds
Started Jun 11 12:49:31 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 209860 kb
Host smart-b2ad677f-a27c-4e8a-939c-c7c5e4f57a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295001005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.295001005
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.228204537
Short name T648
Test name
Test status
Simulation time 21100579 ps
CPU time 1.01 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:49:30 PM PDT 24
Peak memory 206120 kb
Host smart-e81b0582-c07b-464f-a59b-25d878cdcc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228204537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.228204537
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3880494408
Short name T255
Test name
Test status
Simulation time 2465337163 ps
CPU time 31.75 seconds
Started Jun 11 12:49:27 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 214884 kb
Host smart-e42fe04f-b059-4e9b-b483-76d47be652f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880494408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3880494408
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3942217863
Short name T27
Test name
Test status
Simulation time 154101536 ps
CPU time 3.73 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 221588 kb
Host smart-36eba0b1-ffc1-45f6-801b-e3af4e0fa775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942217863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3942217863
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.68522487
Short name T712
Test name
Test status
Simulation time 767957743 ps
CPU time 22.9 seconds
Started Jun 11 12:49:20 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 214320 kb
Host smart-21ed417a-db42-4378-bc3e-e7b833760e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68522487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.68522487
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1558137059
Short name T93
Test name
Test status
Simulation time 114682374 ps
CPU time 3.04 seconds
Started Jun 11 12:49:33 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 208644 kb
Host smart-8dc30efd-cbc6-4f28-828a-b7cb6dc704e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558137059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1558137059
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2016613768
Short name T906
Test name
Test status
Simulation time 37222088 ps
CPU time 2.5 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 220784 kb
Host smart-d7ead93e-e8b0-4beb-827d-4a35b3c8251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016613768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2016613768
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1215710377
Short name T67
Test name
Test status
Simulation time 245664178 ps
CPU time 3.04 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 208096 kb
Host smart-e7938efa-6e35-4e23-b6f4-ccf7492be39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215710377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1215710377
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2206702777
Short name T372
Test name
Test status
Simulation time 2516126383 ps
CPU time 11.77 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:30 PM PDT 24
Peak memory 207172 kb
Host smart-2be93fb2-1435-4087-af3b-eca3c4a0b6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206702777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2206702777
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.566961170
Short name T392
Test name
Test status
Simulation time 173072143 ps
CPU time 3.5 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 208052 kb
Host smart-482dd918-06bb-40fa-9957-948646dd32d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566961170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.566961170
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2690498402
Short name T675
Test name
Test status
Simulation time 2730177036 ps
CPU time 16.64 seconds
Started Jun 11 12:49:21 PM PDT 24
Finished Jun 11 12:49:40 PM PDT 24
Peak memory 207948 kb
Host smart-f00100c8-36e3-4ddf-890b-98eb013ee76d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690498402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2690498402
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4105848380
Short name T886
Test name
Test status
Simulation time 276206075 ps
CPU time 3.21 seconds
Started Jun 11 12:49:18 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 207056 kb
Host smart-79d2fa5b-8b08-4333-ad3b-69e448374a62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105848380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4105848380
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.978080806
Short name T635
Test name
Test status
Simulation time 860851797 ps
CPU time 6.88 seconds
Started Jun 11 12:49:26 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 208276 kb
Host smart-f4a4fafc-bbb5-4910-a505-185718066228
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978080806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.978080806
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.857776848
Short name T600
Test name
Test status
Simulation time 24185461 ps
CPU time 1.69 seconds
Started Jun 11 12:49:31 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 209404 kb
Host smart-a7ac5c0d-2da6-45b6-b6f8-a61bf8734688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857776848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.857776848
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.823572951
Short name T520
Test name
Test status
Simulation time 93261506 ps
CPU time 2.99 seconds
Started Jun 11 12:49:35 PM PDT 24
Finished Jun 11 12:49:40 PM PDT 24
Peak memory 206820 kb
Host smart-14ddb0b0-211d-42ae-9be7-b22dfceb9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823572951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.823572951
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.117432567
Short name T185
Test name
Test status
Simulation time 604928523 ps
CPU time 9.28 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:25 PM PDT 24
Peak memory 211000 kb
Host smart-b217f239-13ea-4166-b3fd-1dea875f400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117432567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.117432567
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3142197794
Short name T876
Test name
Test status
Simulation time 10966331 ps
CPU time 0.89 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:15 PM PDT 24
Peak memory 205896 kb
Host smart-33a8d9ea-067a-4c36-b914-89851e69b001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142197794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3142197794
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3400609997
Short name T157
Test name
Test status
Simulation time 239605804 ps
CPU time 4.07 seconds
Started Jun 11 12:49:21 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 215372 kb
Host smart-08fc5f96-565a-4e35-af75-449e176d9194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400609997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3400609997
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.958178169
Short name T20
Test name
Test status
Simulation time 77489884 ps
CPU time 2.61 seconds
Started Jun 11 12:49:24 PM PDT 24
Finished Jun 11 12:49:28 PM PDT 24
Peak memory 219344 kb
Host smart-12fce297-75ff-46d2-af2e-294600653fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958178169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.958178169
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1574984131
Short name T69
Test name
Test status
Simulation time 1203151572 ps
CPU time 10.16 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 219732 kb
Host smart-1f51d24f-8fda-4d0a-a1f4-5df2aa5ecf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574984131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1574984131
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3427360488
Short name T101
Test name
Test status
Simulation time 1451884720 ps
CPU time 11.57 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 222548 kb
Host smart-51daaa9b-516b-478f-a8f2-94f70be60dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427360488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3427360488
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3222492396
Short name T666
Test name
Test status
Simulation time 438619575 ps
CPU time 2.21 seconds
Started Jun 11 12:49:19 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 214540 kb
Host smart-ddc09985-abe2-4b53-a062-1c8d6ead294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222492396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3222492396
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1190330135
Short name T583
Test name
Test status
Simulation time 303256620 ps
CPU time 4.29 seconds
Started Jun 11 12:49:15 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 222480 kb
Host smart-8aff6945-23d8-48d8-bdad-fdf3e9cbdbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190330135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1190330135
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2312969270
Short name T802
Test name
Test status
Simulation time 70011825 ps
CPU time 3.29 seconds
Started Jun 11 12:49:34 PM PDT 24
Finished Jun 11 12:49:38 PM PDT 24
Peak memory 208396 kb
Host smart-1c2ea011-0264-4beb-930f-3f92757688bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312969270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2312969270
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.439047704
Short name T447
Test name
Test status
Simulation time 93457809 ps
CPU time 3.25 seconds
Started Jun 11 12:49:29 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 208412 kb
Host smart-e02ff76c-22c4-4ad0-bf4d-6934dc09593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439047704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.439047704
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2514098883
Short name T684
Test name
Test status
Simulation time 147956702 ps
CPU time 4.43 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 209012 kb
Host smart-b5519d35-1aff-4b9a-8b16-74c3864223a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514098883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2514098883
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3583575741
Short name T814
Test name
Test status
Simulation time 319199627 ps
CPU time 7.44 seconds
Started Jun 11 12:49:29 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 208140 kb
Host smart-9ac8cf8d-36e7-4786-b323-008d6325db73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583575741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3583575741
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4198689820
Short name T796
Test name
Test status
Simulation time 160610971 ps
CPU time 2.9 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 206968 kb
Host smart-9fdc7d32-d5f7-42d4-a5f4-eb6cccfefa25
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198689820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4198689820
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2360607942
Short name T291
Test name
Test status
Simulation time 57109061 ps
CPU time 2.39 seconds
Started Jun 11 12:49:14 PM PDT 24
Finished Jun 11 12:49:19 PM PDT 24
Peak memory 218176 kb
Host smart-162e1e0f-fe51-41ae-97c4-6807a60bd764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360607942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2360607942
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2548947744
Short name T673
Test name
Test status
Simulation time 139276778 ps
CPU time 2.58 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:22 PM PDT 24
Peak memory 208012 kb
Host smart-9eec32e8-4ed5-4325-899e-9441e39e7cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548947744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2548947744
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2473609219
Short name T487
Test name
Test status
Simulation time 1604880466 ps
CPU time 4.18 seconds
Started Jun 11 12:49:16 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 208880 kb
Host smart-4b5cc1d4-a0d9-465e-aab6-23a880304144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473609219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2473609219
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.4119130952
Short name T516
Test name
Test status
Simulation time 933999063 ps
CPU time 13.49 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 211068 kb
Host smart-acd203f1-73f3-4fc6-80cd-9befb6f03ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119130952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4119130952
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.63031601
Short name T486
Test name
Test status
Simulation time 27173142 ps
CPU time 0.84 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 206000 kb
Host smart-66a7a692-d651-478a-80e7-73a6d476105b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63031601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.63031601
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.5541139
Short name T422
Test name
Test status
Simulation time 58812019 ps
CPU time 3.93 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 215248 kb
Host smart-a9a57045-cf5d-4eac-9546-05cd5fe8c807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5541139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.5541139
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2222298117
Short name T818
Test name
Test status
Simulation time 190416258 ps
CPU time 2.13 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 209696 kb
Host smart-9251fbd1-8923-4ffc-a587-74eecf67102b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222298117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2222298117
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.274033003
Short name T722
Test name
Test status
Simulation time 85463894 ps
CPU time 3.21 seconds
Started Jun 11 12:49:32 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 208160 kb
Host smart-8261badd-ad97-4c1b-bbaa-93d21495009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274033003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.274033003
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2698710909
Short name T865
Test name
Test status
Simulation time 36667881 ps
CPU time 2.52 seconds
Started Jun 11 12:49:12 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 214368 kb
Host smart-8f4ea450-a10d-4231-b6ca-b91628cddbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698710909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2698710909
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_random.774420049
Short name T320
Test name
Test status
Simulation time 2595897041 ps
CPU time 18.03 seconds
Started Jun 11 12:49:27 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 208768 kb
Host smart-5eb9f40d-9c51-48a5-a8a1-72ee8afc988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774420049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.774420049
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2906841262
Short name T657
Test name
Test status
Simulation time 167077481 ps
CPU time 5.65 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 207888 kb
Host smart-a76c4504-4bc4-41f2-a12c-ddfb2c07dee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906841262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2906841262
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.271511676
Short name T515
Test name
Test status
Simulation time 25594288 ps
CPU time 1.94 seconds
Started Jun 11 12:49:29 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 208592 kb
Host smart-9b20e00b-bf19-4a17-acd9-aafa9e4ad0b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271511676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.271511676
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3028555202
Short name T739
Test name
Test status
Simulation time 102712820 ps
CPU time 3.92 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 208548 kb
Host smart-bc7bead2-3128-4557-ad03-a3ae2a185569
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028555202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3028555202
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2325557924
Short name T3
Test name
Test status
Simulation time 91996917 ps
CPU time 2.82 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 207088 kb
Host smart-51379fe5-8de6-48de-ab00-9cdbf3561690
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325557924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2325557924
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3691668813
Short name T593
Test name
Test status
Simulation time 2046053030 ps
CPU time 19.79 seconds
Started Jun 11 12:49:32 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 218284 kb
Host smart-cf787e9a-1142-4296-8b30-2d1ebcfb6f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691668813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3691668813
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2055981703
Short name T453
Test name
Test status
Simulation time 159710046 ps
CPU time 2.2 seconds
Started Jun 11 12:49:30 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 206680 kb
Host smart-7f97ef63-57f3-4545-b06a-735e583f5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055981703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2055981703
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3162341094
Short name T110
Test name
Test status
Simulation time 360263859 ps
CPU time 7.36 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 222672 kb
Host smart-fded58e0-2422-41ef-9431-8833d6cd3dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162341094 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3162341094
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2947443279
Short name T136
Test name
Test status
Simulation time 141407834 ps
CPU time 5.76 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 207360 kb
Host smart-8ce361b1-415f-4158-afa1-c3f0c8cdac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947443279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2947443279
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1781860463
Short name T634
Test name
Test status
Simulation time 131007999 ps
CPU time 3.47 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 210572 kb
Host smart-4d89c5eb-9048-4ddc-ac5f-cbec6d74e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781860463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1781860463
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1262610269
Short name T457
Test name
Test status
Simulation time 22342015 ps
CPU time 0.71 seconds
Started Jun 11 12:49:44 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 205968 kb
Host smart-4229ef55-0a27-40f9-93a4-9217f38afdd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262610269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1262610269
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1390628375
Short name T363
Test name
Test status
Simulation time 93241319 ps
CPU time 3.95 seconds
Started Jun 11 12:49:29 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 218388 kb
Host smart-f000a720-1a68-4242-b06d-c67e0cb94adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390628375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1390628375
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2930577564
Short name T341
Test name
Test status
Simulation time 54925216 ps
CPU time 1.95 seconds
Started Jun 11 12:49:36 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 214376 kb
Host smart-b5fc8a65-2b22-45ef-9ce7-3f29b005dede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930577564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2930577564
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3671336793
Short name T731
Test name
Test status
Simulation time 42274171 ps
CPU time 2.26 seconds
Started Jun 11 12:49:36 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 214356 kb
Host smart-17bbd8b8-3656-4fa2-8d37-4fcee45060c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671336793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3671336793
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1668939064
Short name T681
Test name
Test status
Simulation time 134044669 ps
CPU time 1.51 seconds
Started Jun 11 12:49:35 PM PDT 24
Finished Jun 11 12:49:38 PM PDT 24
Peak memory 206164 kb
Host smart-1e42a537-d446-49c5-8321-b03efa534988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668939064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1668939064
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2869905614
Short name T591
Test name
Test status
Simulation time 313847573 ps
CPU time 5.92 seconds
Started Jun 11 12:49:27 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 218476 kb
Host smart-b0b7122e-f584-4295-b209-40287f8acecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869905614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2869905614
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.678733595
Short name T779
Test name
Test status
Simulation time 326176751 ps
CPU time 3.33 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 209060 kb
Host smart-74c3a408-fb06-483e-b5c2-f7fbe3ace3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678733595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.678733595
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3244901677
Short name T907
Test name
Test status
Simulation time 105652680 ps
CPU time 3.35 seconds
Started Jun 11 12:49:32 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 208612 kb
Host smart-0a7040f2-deca-4d0a-a934-fc363a0dc1fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244901677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3244901677
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.841357019
Short name T868
Test name
Test status
Simulation time 395906847 ps
CPU time 3.66 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 208824 kb
Host smart-61cf0d2e-3cec-4398-a46b-945eab106c61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841357019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.841357019
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.481885728
Short name T720
Test name
Test status
Simulation time 428080133 ps
CPU time 5.73 seconds
Started Jun 11 12:49:13 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 208800 kb
Host smart-062483b9-5c93-4566-b1eb-3d2962c3887b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481885728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.481885728
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3600303444
Short name T509
Test name
Test status
Simulation time 275410716 ps
CPU time 3.58 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 210196 kb
Host smart-aa861d40-f602-42b2-81dd-8eeb62d49109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600303444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3600303444
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.406371084
Short name T459
Test name
Test status
Simulation time 86215072 ps
CPU time 2.7 seconds
Started Jun 11 12:49:17 PM PDT 24
Finished Jun 11 12:49:23 PM PDT 24
Peak memory 207116 kb
Host smart-729fb97f-b61a-432d-b15a-fc3f2aef3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406371084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.406371084
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3091169647
Short name T343
Test name
Test status
Simulation time 629279106 ps
CPU time 16.94 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:50:12 PM PDT 24
Peak memory 216868 kb
Host smart-0bdbb1e0-6fa8-481f-9c97-d2cfe929bee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091169647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3091169647
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1392381582
Short name T294
Test name
Test status
Simulation time 154740452 ps
CPU time 3.8 seconds
Started Jun 11 12:49:20 PM PDT 24
Finished Jun 11 12:49:26 PM PDT 24
Peak memory 210096 kb
Host smart-80599ace-04a0-4556-a459-607c06c23541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392381582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1392381582
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3944602784
Short name T614
Test name
Test status
Simulation time 15400395 ps
CPU time 0.75 seconds
Started Jun 11 12:49:52 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 206008 kb
Host smart-31e81f84-4695-4011-aea4-f98ecb586c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944602784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3944602784
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.624855521
Short name T231
Test name
Test status
Simulation time 337280822 ps
CPU time 4.59 seconds
Started Jun 11 12:49:47 PM PDT 24
Finished Jun 11 12:49:53 PM PDT 24
Peak memory 209748 kb
Host smart-d96c812b-ed46-461b-b884-32d00dad6832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624855521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.624855521
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3734715588
Short name T660
Test name
Test status
Simulation time 473786956 ps
CPU time 3.37 seconds
Started Jun 11 12:49:36 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 207508 kb
Host smart-26d5d035-769a-4f2c-ba0a-497ec4fac381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734715588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3734715588
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.259330070
Short name T304
Test name
Test status
Simulation time 106548538 ps
CPU time 1.83 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:40 PM PDT 24
Peak memory 215980 kb
Host smart-896611b8-d753-4685-9af3-ae88835bb7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259330070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.259330070
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.899044639
Short name T394
Test name
Test status
Simulation time 84253762 ps
CPU time 1.92 seconds
Started Jun 11 12:49:35 PM PDT 24
Finished Jun 11 12:49:38 PM PDT 24
Peak memory 214188 kb
Host smart-474444a0-e614-4f0a-8f77-0d6911e83161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899044639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.899044639
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3850791821
Short name T535
Test name
Test status
Simulation time 822665258 ps
CPU time 4.26 seconds
Started Jun 11 12:49:52 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 214648 kb
Host smart-b204a01b-be0e-43a3-8364-eacbb5db085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850791821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3850791821
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2250847563
Short name T859
Test name
Test status
Simulation time 419655973 ps
CPU time 10.1 seconds
Started Jun 11 12:49:38 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 209608 kb
Host smart-a3c3ed10-5c57-4f09-b428-aae5c6cd7b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250847563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2250847563
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3826270219
Short name T507
Test name
Test status
Simulation time 85073701 ps
CPU time 1.82 seconds
Started Jun 11 12:49:41 PM PDT 24
Finished Jun 11 12:49:44 PM PDT 24
Peak memory 208604 kb
Host smart-62dbf484-d181-4361-b39f-1ee1fa3394f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826270219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3826270219
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1531329656
Short name T549
Test name
Test status
Simulation time 1515384344 ps
CPU time 26.68 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 209220 kb
Host smart-c1cb5264-f2ee-4d13-86a7-3a2f8bbd4212
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531329656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1531329656
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3875736807
Short name T512
Test name
Test status
Simulation time 187566246 ps
CPU time 2.72 seconds
Started Jun 11 12:49:37 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 207100 kb
Host smart-7fab91e4-a342-43cb-ace7-e93f405c0fe0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875736807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3875736807
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2158630524
Short name T406
Test name
Test status
Simulation time 556072083 ps
CPU time 7.01 seconds
Started Jun 11 12:49:36 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 208548 kb
Host smart-3d6d0eb2-948a-4d33-9cd0-6418f1cc26cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158630524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2158630524
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1266219197
Short name T216
Test name
Test status
Simulation time 118873144 ps
CPU time 2.47 seconds
Started Jun 11 12:49:51 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 214432 kb
Host smart-3d6a3d79-5853-4d6f-8b3e-073cee7528e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266219197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1266219197
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.902874176
Short name T769
Test name
Test status
Simulation time 542030105 ps
CPU time 3.47 seconds
Started Jun 11 12:49:45 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 208536 kb
Host smart-04ef6c03-1803-40c8-b6bc-46abe41b9487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902874176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.902874176
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1420172071
Short name T279
Test name
Test status
Simulation time 329074686 ps
CPU time 3.47 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:44 PM PDT 24
Peak memory 214304 kb
Host smart-91d89b3b-56c2-4759-84d1-6126929ab327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420172071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1420172071
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.648028571
Short name T817
Test name
Test status
Simulation time 40128855 ps
CPU time 0.73 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 206024 kb
Host smart-4cfb1564-16bd-4214-976a-07fa13511210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648028571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.648028571
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2243279914
Short name T43
Test name
Test status
Simulation time 52723880 ps
CPU time 2.65 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 207528 kb
Host smart-581fefef-317d-41a8-850d-2b6b6a9271f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243279914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2243279914
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.910158353
Short name T621
Test name
Test status
Simulation time 132109333 ps
CPU time 5.16 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 220556 kb
Host smart-b08dd82c-5028-4393-9c1a-f76297cb5a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910158353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.910158353
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2466788936
Short name T891
Test name
Test status
Simulation time 120716539 ps
CPU time 3.51 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 214180 kb
Host smart-83c72b1e-e7ca-4bfd-802f-701acfa5ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466788936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2466788936
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3896627513
Short name T754
Test name
Test status
Simulation time 324463128 ps
CPU time 3.52 seconds
Started Jun 11 12:49:36 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 209052 kb
Host smart-b87e980c-5fa0-4de3-b7db-4957c83b4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896627513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3896627513
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.4137082969
Short name T638
Test name
Test status
Simulation time 97273867 ps
CPU time 4.27 seconds
Started Jun 11 12:50:07 PM PDT 24
Finished Jun 11 12:50:13 PM PDT 24
Peak memory 209776 kb
Host smart-608055d4-87fa-43d7-aa1c-0530c1d97465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137082969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4137082969
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3387043147
Short name T357
Test name
Test status
Simulation time 860578488 ps
CPU time 21.91 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 208060 kb
Host smart-ae0c816b-5c6a-447a-af98-98aa16f6c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387043147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3387043147
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.330108012
Short name T254
Test name
Test status
Simulation time 869146936 ps
CPU time 9.18 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 208700 kb
Host smart-ef280482-bef1-4926-8b45-3b75ecd09c16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330108012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.330108012
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2467827356
Short name T220
Test name
Test status
Simulation time 4158879079 ps
CPU time 30.02 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:50:26 PM PDT 24
Peak memory 208356 kb
Host smart-3a26b25c-bd99-49cb-a399-6168595fc4eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467827356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2467827356
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1835277260
Short name T562
Test name
Test status
Simulation time 209317926 ps
CPU time 5.52 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 208700 kb
Host smart-17001fd4-f07f-4257-82a0-80f56f3ea2b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835277260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1835277260
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2179412233
Short name T603
Test name
Test status
Simulation time 104433132 ps
CPU time 2.11 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 214448 kb
Host smart-cad2e63e-9817-4efe-a655-17ebc09bc003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179412233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2179412233
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.747673126
Short name T450
Test name
Test status
Simulation time 138678453 ps
CPU time 1.71 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 206184 kb
Host smart-4de74eb4-d716-45e2-a44c-330d2ecf60dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747673126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.747673126
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.206517095
Short name T513
Test name
Test status
Simulation time 222136075 ps
CPU time 11.97 seconds
Started Jun 11 12:49:29 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 216280 kb
Host smart-0802b241-f1c3-4420-abc4-6487733dfd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206517095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.206517095
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.604984376
Short name T841
Test name
Test status
Simulation time 308562402 ps
CPU time 6.57 seconds
Started Jun 11 12:49:30 PM PDT 24
Finished Jun 11 12:49:38 PM PDT 24
Peak memory 208012 kb
Host smart-a84adf13-c4a7-4c31-ae1d-365efcde967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604984376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.604984376
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.378986418
Short name T745
Test name
Test status
Simulation time 47916047 ps
CPU time 2.39 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 209756 kb
Host smart-9049105d-7189-4781-8cff-3150f5159966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378986418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.378986418
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3617359191
Short name T452
Test name
Test status
Simulation time 12343219 ps
CPU time 0.81 seconds
Started Jun 11 12:48:06 PM PDT 24
Finished Jun 11 12:48:09 PM PDT 24
Peak memory 205996 kb
Host smart-8af2eb9c-a1a9-49fb-95f0-83b5c46927b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617359191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3617359191
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1290914931
Short name T421
Test name
Test status
Simulation time 129504547 ps
CPU time 2.54 seconds
Started Jun 11 12:48:18 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 215464 kb
Host smart-4ca3411b-b044-403e-a407-867e3bd3264f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290914931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1290914931
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3903801906
Short name T652
Test name
Test status
Simulation time 51621055 ps
CPU time 3.34 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:18 PM PDT 24
Peak memory 218892 kb
Host smart-944df9d2-2f00-4c06-84aa-bb0219f3fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903801906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3903801906
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3878137485
Short name T608
Test name
Test status
Simulation time 208125333 ps
CPU time 2.61 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:18 PM PDT 24
Peak memory 208404 kb
Host smart-3d25c229-75b6-445e-a8ad-2426e9bfbcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878137485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3878137485
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1224150225
Short name T771
Test name
Test status
Simulation time 371482732 ps
CPU time 3.92 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 214856 kb
Host smart-2e2ccbd6-514e-4eb7-8ee7-707111dea2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224150225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1224150225
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3557436314
Short name T896
Test name
Test status
Simulation time 317217925 ps
CPU time 2.63 seconds
Started Jun 11 12:48:10 PM PDT 24
Finished Jun 11 12:48:15 PM PDT 24
Peak memory 214352 kb
Host smart-144eb85e-67ec-49c3-a636-801a5f795b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557436314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3557436314
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2363387265
Short name T777
Test name
Test status
Simulation time 91722403 ps
CPU time 4.17 seconds
Started Jun 11 12:48:17 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 219708 kb
Host smart-7b6f67f4-005d-4ee2-8a67-26bba24ece51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363387265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2363387265
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3362189668
Short name T314
Test name
Test status
Simulation time 127924652 ps
CPU time 5.95 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 218684 kb
Host smart-5db04e16-8204-4096-b2ec-f4e0cbb70d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362189668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3362189668
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3536174136
Short name T38
Test name
Test status
Simulation time 751116599 ps
CPU time 13.63 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 239896 kb
Host smart-7a293c3d-b69f-42ea-b55b-8d9ace80d477
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536174136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3536174136
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1690411194
Short name T347
Test name
Test status
Simulation time 205714823 ps
CPU time 6.91 seconds
Started Jun 11 12:48:10 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 206808 kb
Host smart-b36fe0c5-808c-42d5-a652-0d3f8da5ec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690411194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1690411194
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.696343865
Short name T866
Test name
Test status
Simulation time 506130280 ps
CPU time 3.57 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 208644 kb
Host smart-14b9d95d-592e-4836-b2d7-83bc220ee7e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696343865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.696343865
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4207589216
Short name T822
Test name
Test status
Simulation time 297028061 ps
CPU time 5.77 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:33 PM PDT 24
Peak memory 208320 kb
Host smart-c67c901b-c0d2-4263-b25a-bf4c89df0d5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207589216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4207589216
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3798075812
Short name T329
Test name
Test status
Simulation time 51511830 ps
CPU time 2.89 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 207040 kb
Host smart-86e50bb9-698d-4b22-8528-5478d52a7d25
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798075812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3798075812
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3949801999
Short name T654
Test name
Test status
Simulation time 22385545 ps
CPU time 1.49 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 207844 kb
Host smart-d064f40f-ae65-4e51-8a65-6f72693a33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949801999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3949801999
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4077723965
Short name T768
Test name
Test status
Simulation time 142506141 ps
CPU time 3.51 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 207180 kb
Host smart-f82918a2-fdf7-4ef2-a4f6-55fc546180fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077723965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4077723965
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.772192415
Short name T383
Test name
Test status
Simulation time 438520672 ps
CPU time 18.47 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 215728 kb
Host smart-dcb55d05-2f94-4b60-8e42-2025aef8d559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772192415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.772192415
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4038486891
Short name T196
Test name
Test status
Simulation time 208517787 ps
CPU time 7.12 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 219300 kb
Host smart-32e73215-22e9-499f-9d3e-303cb8cbe6b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038486891 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4038486891
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2853649943
Short name T669
Test name
Test status
Simulation time 129714933 ps
CPU time 5.46 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:11 PM PDT 24
Peak memory 209756 kb
Host smart-cb438dd3-50e0-4c08-a569-a44b962d23bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853649943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2853649943
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1729134716
Short name T33
Test name
Test status
Simulation time 234725376 ps
CPU time 2.02 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:12 PM PDT 24
Peak memory 209892 kb
Host smart-9c5df6e5-5c35-406a-a481-268098da1acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729134716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1729134716
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.380885546
Short name T759
Test name
Test status
Simulation time 17447551 ps
CPU time 0.88 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 206092 kb
Host smart-b96b2328-7af1-432a-92c4-f2b680aff278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380885546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.380885546
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.279765369
Short name T297
Test name
Test status
Simulation time 195181166 ps
CPU time 4.3 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:49 PM PDT 24
Peak memory 215128 kb
Host smart-a99381fe-c497-4266-a7be-a0692e8e2c0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279765369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.279765369
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.219116507
Short name T662
Test name
Test status
Simulation time 138474918 ps
CPU time 4.6 seconds
Started Jun 11 12:49:41 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 214388 kb
Host smart-2bb16de4-471f-40d1-ac19-7a687bef5e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219116507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.219116507
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4070067339
Short name T897
Test name
Test status
Simulation time 156279929 ps
CPU time 2.24 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 207520 kb
Host smart-f5560991-0662-4db2-8853-684061617c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070067339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4070067339
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1065776229
Short name T772
Test name
Test status
Simulation time 19906598 ps
CPU time 1.5 seconds
Started Jun 11 12:49:28 PM PDT 24
Finished Jun 11 12:49:31 PM PDT 24
Peak memory 214472 kb
Host smart-bce8e5d8-d7e3-41ae-b249-34cc8d5c05e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065776229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1065776229
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3693714601
Short name T342
Test name
Test status
Simulation time 716413850 ps
CPU time 4.41 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 214332 kb
Host smart-084aca82-18eb-4af7-98a7-46a63da5347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693714601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3693714601
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3647476573
Short name T368
Test name
Test status
Simulation time 237107421 ps
CPU time 3.44 seconds
Started Jun 11 12:49:51 PM PDT 24
Finished Jun 11 12:49:55 PM PDT 24
Peak memory 214424 kb
Host smart-9a2a711c-770c-4e5e-9419-4ed8c1fbab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647476573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3647476573
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1811315258
Short name T253
Test name
Test status
Simulation time 46464861 ps
CPU time 3.01 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:53 PM PDT 24
Peak memory 207024 kb
Host smart-24c90f07-9b5c-41fe-b9cc-21495a2bbbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811315258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1811315258
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3882602652
Short name T542
Test name
Test status
Simulation time 316485668 ps
CPU time 3.5 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 208808 kb
Host smart-a7fccac0-1173-4e7d-8a2c-a23147b0f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882602652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3882602652
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2156327826
Short name T300
Test name
Test status
Simulation time 856781325 ps
CPU time 20.41 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 208588 kb
Host smart-41528885-b45f-4b13-b188-6ac95e63caf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156327826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2156327826
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.954928643
Short name T842
Test name
Test status
Simulation time 415749779 ps
CPU time 3.15 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 208632 kb
Host smart-59009cc4-8b48-4dde-934f-6d3ee8e258aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954928643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.954928643
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4036815650
Short name T860
Test name
Test status
Simulation time 37660532 ps
CPU time 2.19 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 207088 kb
Host smart-ca5b21bb-5569-4609-9e6a-150b4240f79c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036815650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4036815650
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3940926916
Short name T738
Test name
Test status
Simulation time 1574940518 ps
CPU time 3.16 seconds
Started Jun 11 12:49:40 PM PDT 24
Finished Jun 11 12:49:44 PM PDT 24
Peak memory 207700 kb
Host smart-14e7afe4-f727-407a-8652-127b54860373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940926916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3940926916
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2949580654
Short name T723
Test name
Test status
Simulation time 1647082518 ps
CPU time 3.48 seconds
Started Jun 11 12:49:52 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 208656 kb
Host smart-870f941e-b772-444f-9cda-e8dfbf301e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949580654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2949580654
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1066640025
Short name T80
Test name
Test status
Simulation time 1193331699 ps
CPU time 32.26 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:50:17 PM PDT 24
Peak memory 215256 kb
Host smart-7524959e-639c-4755-a894-7362dac8a7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066640025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1066640025
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1131945801
Short name T193
Test name
Test status
Simulation time 2213551953 ps
CPU time 18.71 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:20 PM PDT 24
Peak memory 222780 kb
Host smart-e1fadfc5-148e-4a38-9290-e4ab497cdcb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131945801 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1131945801
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1585371418
Short name T328
Test name
Test status
Simulation time 699005894 ps
CPU time 6.29 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 209628 kb
Host smart-d7f1d5dd-2899-45c6-b143-bab350698cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585371418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1585371418
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3836826654
Short name T403
Test name
Test status
Simulation time 164307531 ps
CPU time 2.16 seconds
Started Jun 11 12:49:32 PM PDT 24
Finished Jun 11 12:49:36 PM PDT 24
Peak memory 210296 kb
Host smart-5093af2e-3819-4900-bd95-19b0216386a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836826654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3836826654
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2480015246
Short name T577
Test name
Test status
Simulation time 47810189 ps
CPU time 0.91 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 206188 kb
Host smart-c35ae204-ecb3-4fcb-858e-2d637adf9d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480015246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2480015246
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2041503021
Short name T432
Test name
Test status
Simulation time 66468067 ps
CPU time 4.43 seconds
Started Jun 11 12:49:45 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 222496 kb
Host smart-6935a606-60e1-4c8d-b58a-ec8da44bf88a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041503021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2041503021
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1333666833
Short name T679
Test name
Test status
Simulation time 50315405 ps
CPU time 1.4 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:02 PM PDT 24
Peak memory 214632 kb
Host smart-cf8565f3-f23f-41df-a8a5-e06cd07eaa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333666833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1333666833
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2385748141
Short name T49
Test name
Test status
Simulation time 167657620 ps
CPU time 2.45 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 210448 kb
Host smart-dec76d51-27cc-4ca6-89c5-fc5ac605f8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385748141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2385748141
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2722496316
Short name T96
Test name
Test status
Simulation time 227289759 ps
CPU time 8.32 seconds
Started Jun 11 12:49:56 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 214400 kb
Host smart-4e7d9a99-2ff1-4ce6-aad0-ba7e2d4f0d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722496316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2722496316
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2597795565
Short name T834
Test name
Test status
Simulation time 75929119 ps
CPU time 3.85 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:49:48 PM PDT 24
Peak memory 214292 kb
Host smart-2929e08f-567f-48d6-90a6-3f97fc38b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597795565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2597795565
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_random.77024158
Short name T353
Test name
Test status
Simulation time 680991344 ps
CPU time 6.98 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 208704 kb
Host smart-719295eb-5f19-43f6-9f06-610d1e923c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77024158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.77024158
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2254510889
Short name T833
Test name
Test status
Simulation time 180717106 ps
CPU time 3.15 seconds
Started Jun 11 12:49:44 PM PDT 24
Finished Jun 11 12:49:49 PM PDT 24
Peak memory 208600 kb
Host smart-ca614c41-ebd8-4659-a06a-72b424ff1ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254510889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2254510889
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2107172617
Short name T877
Test name
Test status
Simulation time 2001585343 ps
CPU time 14.44 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:50:02 PM PDT 24
Peak memory 208328 kb
Host smart-e335a5f0-badb-4b92-b8c2-3c37fb165f72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107172617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2107172617
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1797828702
Short name T612
Test name
Test status
Simulation time 301920485 ps
CPU time 3.32 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 208708 kb
Host smart-79194954-457d-43e8-9f64-81188d12597a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797828702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1797828702
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1106626143
Short name T778
Test name
Test status
Simulation time 52798684 ps
CPU time 2.9 seconds
Started Jun 11 12:49:56 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 207160 kb
Host smart-9a6998cc-be9d-43ba-a38f-330f6e82c506
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106626143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1106626143
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1619444324
Short name T736
Test name
Test status
Simulation time 416917568 ps
CPU time 4.56 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 209828 kb
Host smart-8d3475e1-8c34-4bbf-9e2f-cbfe6f0c4beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619444324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1619444324
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.725346225
Short name T120
Test name
Test status
Simulation time 1438603025 ps
CPU time 9.19 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 207840 kb
Host smart-5da8e4e2-ac49-46d3-b392-feca3377288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725346225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.725346225
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3891454905
Short name T280
Test name
Test status
Simulation time 1455558452 ps
CPU time 14.22 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 215788 kb
Host smart-e671ec50-7be7-42ed-a2e7-d6899326ccd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891454905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3891454905
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1424777183
Short name T134
Test name
Test status
Simulation time 2425003684 ps
CPU time 16.01 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 221360 kb
Host smart-752ddff5-5c1c-4955-b7d2-ba971ce43993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424777183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1424777183
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2543237234
Short name T322
Test name
Test status
Simulation time 101091104 ps
CPU time 3.28 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 208356 kb
Host smart-6aef81fe-d156-43d5-a4c3-c6cdf6ab8fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543237234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2543237234
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.357593623
Short name T853
Test name
Test status
Simulation time 122622880 ps
CPU time 2.25 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:49:49 PM PDT 24
Peak memory 210076 kb
Host smart-90df04e5-f9a9-450e-a060-fdafc6fa20aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357593623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.357593623
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2481530066
Short name T463
Test name
Test status
Simulation time 11355656 ps
CPU time 0.86 seconds
Started Jun 11 12:49:51 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 205976 kb
Host smart-2475daff-890c-4a65-8414-c3e273881fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481530066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2481530066
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2920068555
Short name T902
Test name
Test status
Simulation time 7134360183 ps
CPU time 47.21 seconds
Started Jun 11 12:49:50 PM PDT 24
Finished Jun 11 12:50:38 PM PDT 24
Peak memory 214396 kb
Host smart-05e8b8d4-0d7f-4bd0-829f-885975bfefb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920068555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2920068555
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.13935147
Short name T890
Test name
Test status
Simulation time 35127646 ps
CPU time 2.27 seconds
Started Jun 11 12:50:08 PM PDT 24
Finished Jun 11 12:50:13 PM PDT 24
Peak memory 214416 kb
Host smart-885364f0-f434-4abc-889b-f9631b14ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13935147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.13935147
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.864417589
Short name T290
Test name
Test status
Simulation time 373163419 ps
CPU time 3.5 seconds
Started Jun 11 12:49:52 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 214260 kb
Host smart-0c641a6f-f363-4e31-801e-ba9f57411743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864417589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.864417589
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4068873551
Short name T380
Test name
Test status
Simulation time 370641532 ps
CPU time 5.38 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 214208 kb
Host smart-d4b467ab-5f5e-4942-9f1b-8283590e6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068873551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4068873551
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3059716106
Short name T918
Test name
Test status
Simulation time 165201412 ps
CPU time 3.62 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 215556 kb
Host smart-9ea7d6fa-8e16-4fc4-9085-e905166b2ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059716106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3059716106
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.174945327
Short name T869
Test name
Test status
Simulation time 333868511 ps
CPU time 5.35 seconds
Started Jun 11 12:49:50 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 210420 kb
Host smart-66a3ca60-f152-4535-a095-e2af243bafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174945327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.174945327
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2297071922
Short name T218
Test name
Test status
Simulation time 3167005301 ps
CPU time 56.91 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:50:51 PM PDT 24
Peak memory 208708 kb
Host smart-d0b8531e-23c4-488f-87be-dcc3ea47a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297071922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2297071922
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.728895599
Short name T514
Test name
Test status
Simulation time 398072882 ps
CPU time 2.74 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:06 PM PDT 24
Peak memory 208824 kb
Host smart-b3e0e496-d53f-4497-a4a6-f61e8846ec1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728895599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.728895599
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2439636402
Short name T746
Test name
Test status
Simulation time 144591485 ps
CPU time 5.47 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 208152 kb
Host smart-ee302e10-a788-413a-a77d-3ba4bd3e5e1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439636402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2439636402
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4824024
Short name T114
Test name
Test status
Simulation time 565387739 ps
CPU time 6.69 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 208260 kb
Host smart-fa9e803f-01bb-4bbe-9538-74ebd5370fd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4824024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4824024
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2747076414
Short name T702
Test name
Test status
Simulation time 93227085 ps
CPU time 2.39 seconds
Started Jun 11 12:50:04 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 214300 kb
Host smart-1b33625e-56e8-44a1-82d8-0483faa4b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747076414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2747076414
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3624436017
Short name T462
Test name
Test status
Simulation time 1610327816 ps
CPU time 22.72 seconds
Started Jun 11 12:50:09 PM PDT 24
Finished Jun 11 12:50:37 PM PDT 24
Peak memory 208064 kb
Host smart-5e888bdc-feb8-43fa-8368-42e18c7bb2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624436017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3624436017
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3681605003
Short name T713
Test name
Test status
Simulation time 747306954 ps
CPU time 8.98 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:49 PM PDT 24
Peak memory 218936 kb
Host smart-c2689190-9d6d-43e7-b045-4f640bb8916f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681605003 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3681605003
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1984427886
Short name T832
Test name
Test status
Simulation time 227902370 ps
CPU time 5.88 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 207760 kb
Host smart-25dc9be5-c312-48f0-8a73-35f54751aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984427886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1984427886
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3529974854
Short name T53
Test name
Test status
Simulation time 427243622 ps
CPU time 2.41 seconds
Started Jun 11 12:49:57 PM PDT 24
Finished Jun 11 12:50:01 PM PDT 24
Peak memory 210424 kb
Host smart-395af1dc-518e-495c-8642-2c7ebd602b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529974854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3529974854
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3860203158
Short name T451
Test name
Test status
Simulation time 47691537 ps
CPU time 0.67 seconds
Started Jun 11 12:50:07 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 205996 kb
Host smart-098d8524-76ed-421e-90d7-779c05b2dc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860203158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3860203158
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1917557962
Short name T423
Test name
Test status
Simulation time 829057529 ps
CPU time 12.53 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 214300 kb
Host smart-df5ed85b-17b8-43d8-a2cb-73b0e8dd9ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917557962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1917557962
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2853920763
Short name T526
Test name
Test status
Simulation time 118747469 ps
CPU time 2.26 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:49:46 PM PDT 24
Peak memory 222668 kb
Host smart-16168ccc-3367-445c-8fff-ecb8ae7d5f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853920763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2853920763
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.368650228
Short name T70
Test name
Test status
Simulation time 18873555 ps
CPU time 1.37 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 206844 kb
Host smart-c64b8cda-23b9-46b3-a3b5-5fd6e7d649b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368650228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.368650228
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2582930249
Short name T286
Test name
Test status
Simulation time 120328379 ps
CPU time 1.86 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 214368 kb
Host smart-0619df5b-d8a1-4913-a363-a2659b86d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582930249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2582930249
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2063328980
Short name T260
Test name
Test status
Simulation time 91670400 ps
CPU time 3.03 seconds
Started Jun 11 12:49:43 PM PDT 24
Finished Jun 11 12:49:47 PM PDT 24
Peak memory 220916 kb
Host smart-8206c96e-a73c-42f3-8b8b-673212cf68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063328980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2063328980
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_random.3547891226
Short name T82
Test name
Test status
Simulation time 948489288 ps
CPU time 7.11 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:50:01 PM PDT 24
Peak memory 208692 kb
Host smart-d5a29f33-4972-4c9a-ad3a-7537532e7558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547891226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3547891226
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1490733012
Short name T701
Test name
Test status
Simulation time 408045560 ps
CPU time 4.27 seconds
Started Jun 11 12:49:45 PM PDT 24
Finished Jun 11 12:49:51 PM PDT 24
Peak memory 208792 kb
Host smart-0fda4251-d36c-46f1-8771-0ced302c7c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490733012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1490733012
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3126153205
Short name T622
Test name
Test status
Simulation time 2698977889 ps
CPU time 12.02 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 208724 kb
Host smart-26f7731a-5e4f-42b8-86a9-3031df8ba0f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126153205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3126153205
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.425063912
Short name T482
Test name
Test status
Simulation time 85643154 ps
CPU time 1.88 seconds
Started Jun 11 12:50:07 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 207284 kb
Host smart-c4e1eabb-12ed-4300-abc7-c350ef2b2f52
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425063912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.425063912
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.818647886
Short name T143
Test name
Test status
Simulation time 51454788 ps
CPU time 2.76 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 207100 kb
Host smart-7652afe2-2eb0-4084-bada-b493a3f9e617
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818647886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.818647886
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2483825466
Short name T724
Test name
Test status
Simulation time 1782069977 ps
CPU time 3.35 seconds
Started Jun 11 12:49:50 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 209332 kb
Host smart-a170a9e9-5205-464c-88e3-ede5bae38f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483825466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2483825466
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3034579444
Short name T798
Test name
Test status
Simulation time 49041554 ps
CPU time 2.58 seconds
Started Jun 11 12:49:39 PM PDT 24
Finished Jun 11 12:49:43 PM PDT 24
Peak memory 208416 kb
Host smart-c8f87de1-538e-4cff-b12d-c07522602b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034579444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3034579444
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4198595070
Short name T228
Test name
Test status
Simulation time 649319155 ps
CPU time 8.79 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:22 PM PDT 24
Peak memory 215204 kb
Host smart-69f69d22-bb9c-4aa4-8729-80d821458c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198595070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4198595070
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3979616120
Short name T207
Test name
Test status
Simulation time 51147089 ps
CPU time 3.33 seconds
Started Jun 11 12:49:58 PM PDT 24
Finished Jun 11 12:50:03 PM PDT 24
Peak memory 210292 kb
Host smart-52460ca9-8134-408e-b7d1-f184e7c5e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979616120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3979616120
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1857536392
Short name T1
Test name
Test status
Simulation time 206139720 ps
CPU time 2.87 seconds
Started Jun 11 12:49:46 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 210416 kb
Host smart-3198390c-69ca-451a-ac88-ad9e4c4a0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857536392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1857536392
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.766163189
Short name T86
Test name
Test status
Simulation time 22035835 ps
CPU time 0.89 seconds
Started Jun 11 12:49:42 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 205892 kb
Host smart-98de3052-287e-463e-9734-2a64ac197c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766163189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.766163189
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1396726916
Short name T429
Test name
Test status
Simulation time 148006928 ps
CPU time 3.04 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 215316 kb
Host smart-dc4307f0-1355-4a95-9d70-1c392a530eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396726916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1396726916
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2905259543
Short name T750
Test name
Test status
Simulation time 122560133 ps
CPU time 1.74 seconds
Started Jun 11 12:50:04 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 208028 kb
Host smart-26998afc-c653-4ffe-bdb2-40057861b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905259543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2905259543
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1356737922
Short name T224
Test name
Test status
Simulation time 83448582 ps
CPU time 4.11 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:12 PM PDT 24
Peak memory 214376 kb
Host smart-aa34e2bb-5c1e-43b5-9ca7-d9e8a4ab4d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356737922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1356737922
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.552993672
Short name T780
Test name
Test status
Simulation time 74393972 ps
CPU time 3.48 seconds
Started Jun 11 12:49:57 PM PDT 24
Finished Jun 11 12:50:02 PM PDT 24
Peak memory 214324 kb
Host smart-ec04cc7c-55a7-44ea-a029-ff3d0eda7263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552993672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.552993672
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.275899650
Short name T560
Test name
Test status
Simulation time 231318407 ps
CPU time 2.81 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 214356 kb
Host smart-aee68738-e4c2-41b9-8660-402e9cad0373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275899650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.275899650
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2663446128
Short name T272
Test name
Test status
Simulation time 284417043 ps
CPU time 3.94 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:53 PM PDT 24
Peak memory 207824 kb
Host smart-559753e2-9b58-4201-922c-6e177b70f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663446128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2663446128
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.877853630
Short name T214
Test name
Test status
Simulation time 325107214 ps
CPU time 2.65 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 208412 kb
Host smart-f249aff2-5695-49af-9648-82b64b51fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877853630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.877853630
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3189228326
Short name T585
Test name
Test status
Simulation time 233751947 ps
CPU time 4.89 seconds
Started Jun 11 12:49:47 PM PDT 24
Finished Jun 11 12:49:53 PM PDT 24
Peak memory 208428 kb
Host smart-f758bf93-348a-4f8e-9d96-6e87e4d2e631
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189228326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3189228326
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3083647325
Short name T714
Test name
Test status
Simulation time 116486121 ps
CPU time 3.37 seconds
Started Jun 11 12:49:45 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 208912 kb
Host smart-3d8330a2-3362-4927-ad0f-31ab3b1b80c4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083647325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3083647325
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2847354506
Short name T704
Test name
Test status
Simulation time 220031588 ps
CPU time 4.73 seconds
Started Jun 11 12:49:58 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 208768 kb
Host smart-828ff39a-1a38-4050-8609-025db820593c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847354506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2847354506
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.95157984
Short name T728
Test name
Test status
Simulation time 86358749 ps
CPU time 2.84 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:49:53 PM PDT 24
Peak memory 218476 kb
Host smart-39858126-f262-436a-bedf-73f4aa04b363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95157984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.95157984
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3025739643
Short name T781
Test name
Test status
Simulation time 182263116 ps
CPU time 2.23 seconds
Started Jun 11 12:50:09 PM PDT 24
Finished Jun 11 12:50:16 PM PDT 24
Peak memory 208496 kb
Host smart-c5e4f217-9eeb-4457-ba6c-f7dcc10791a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025739643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3025739643
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3782268498
Short name T629
Test name
Test status
Simulation time 812724062 ps
CPU time 6.47 seconds
Started Jun 11 12:49:52 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 209912 kb
Host smart-841e6605-5413-4935-b500-bb5042fa919c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782268498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3782268498
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4008917642
Short name T135
Test name
Test status
Simulation time 2147122594 ps
CPU time 16.96 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:18 PM PDT 24
Peak memory 222644 kb
Host smart-415abe73-902f-406b-a2b8-e3f61f5da76a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008917642 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4008917642
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3368423124
Short name T206
Test name
Test status
Simulation time 2117251771 ps
CPU time 15.77 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:50:06 PM PDT 24
Peak memory 208176 kb
Host smart-056f9028-d9e0-4127-908c-e50367766637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368423124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3368423124
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.498574161
Short name T189
Test name
Test status
Simulation time 28820145 ps
CPU time 1.62 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 209860 kb
Host smart-74e7518c-8f5b-4cdf-877f-3f201ef242d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498574161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.498574161
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3314876813
Short name T490
Test name
Test status
Simulation time 32477360 ps
CPU time 0.78 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 206004 kb
Host smart-0ed05c4c-810d-4a07-9c0f-96d363cae92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314876813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3314876813
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3310622817
Short name T438
Test name
Test status
Simulation time 59319549 ps
CPU time 3.96 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 214340 kb
Host smart-e43834ad-4714-4edb-a8e0-fa278cfc41f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310622817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3310622817
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1544385595
Short name T710
Test name
Test status
Simulation time 371421224 ps
CPU time 2.92 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:49:57 PM PDT 24
Peak memory 214336 kb
Host smart-b77507d0-877b-40f3-9007-20325a4835f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544385595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1544385595
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.123130838
Short name T430
Test name
Test status
Simulation time 60816564 ps
CPU time 1.4 seconds
Started Jun 11 12:50:04 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 207436 kb
Host smart-c1466dbc-2d6a-462e-a1f8-1acbaf6a2877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123130838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.123130838
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.903478804
Short name T594
Test name
Test status
Simulation time 175172672 ps
CPU time 4.91 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:02 PM PDT 24
Peak memory 214344 kb
Host smart-c25bdc11-85f3-437f-a1cd-3a16a995ae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903478804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.903478804
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2806041186
Short name T306
Test name
Test status
Simulation time 174031263 ps
CPU time 2.39 seconds
Started Jun 11 12:49:56 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 221768 kb
Host smart-0c3820bf-6005-4d4c-a412-55c5674a53a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806041186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2806041186
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.722241690
Short name T875
Test name
Test status
Simulation time 360230675 ps
CPU time 5.64 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 222508 kb
Host smart-63cc6b99-8bbf-4a02-ba9b-19007ca3f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722241690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.722241690
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3664522233
Short name T625
Test name
Test status
Simulation time 2016429011 ps
CPU time 6.29 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:03 PM PDT 24
Peak memory 208708 kb
Host smart-3aa2221a-90c0-46de-83ee-99fcdafe2f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664522233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3664522233
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3390720274
Short name T500
Test name
Test status
Simulation time 354759379 ps
CPU time 4.22 seconds
Started Jun 11 12:49:51 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 208744 kb
Host smart-8f712f9c-a611-4ff2-abb4-e6cded499c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390720274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3390720274
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.126569474
Short name T488
Test name
Test status
Simulation time 98305858 ps
CPU time 2.62 seconds
Started Jun 11 12:49:44 PM PDT 24
Finished Jun 11 12:49:48 PM PDT 24
Peak memory 207092 kb
Host smart-be958b1d-c5aa-455a-b3c7-57a73b8cb1dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126569474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.126569474
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2832471890
Short name T870
Test name
Test status
Simulation time 407834130 ps
CPU time 3.16 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 208836 kb
Host smart-93493a0b-4fe0-4786-9823-8bad65863750
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832471890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2832471890
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2416339924
Short name T651
Test name
Test status
Simulation time 74282405 ps
CPU time 2.26 seconds
Started Jun 11 12:49:56 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 207032 kb
Host smart-f5693479-26a6-4382-90a3-970e5fd30c9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416339924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2416339924
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.452480662
Short name T820
Test name
Test status
Simulation time 310763153 ps
CPU time 3.62 seconds
Started Jun 11 12:49:48 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 208872 kb
Host smart-330d380f-1d3d-44a5-be86-2ddb401e2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452480662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.452480662
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3106439454
Short name T530
Test name
Test status
Simulation time 324644396 ps
CPU time 3.47 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:49:54 PM PDT 24
Peak memory 206916 kb
Host smart-643d5439-4d0e-46b4-92be-1b0668c4de24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106439454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3106439454
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3514726965
Short name T76
Test name
Test status
Simulation time 792254035 ps
CPU time 27.5 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:50:22 PM PDT 24
Peak memory 215156 kb
Host smart-352df375-f57e-45cc-8aa5-c7e2ce222e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514726965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3514726965
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2930253697
Short name T547
Test name
Test status
Simulation time 943077630 ps
CPU time 9.84 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 222556 kb
Host smart-b34dba12-5c46-439a-9edc-57a022b30477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930253697 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2930253697
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1168188700
Short name T782
Test name
Test status
Simulation time 63579170 ps
CPU time 4.05 seconds
Started Jun 11 12:50:05 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 207460 kb
Host smart-cb009419-81bd-4c7d-908c-ebbc3321a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168188700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1168188700
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.360834160
Short name T52
Test name
Test status
Simulation time 1976195018 ps
CPU time 19.71 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 210952 kb
Host smart-39a3bad0-82e8-4ea7-a2c7-ed5ef29e877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360834160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.360834160
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.245957866
Short name T108
Test name
Test status
Simulation time 43581651 ps
CPU time 0.86 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 205948 kb
Host smart-bf6a6c73-0d6c-46df-af44-39bef323d198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245957866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.245957866
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1823621856
Short name T592
Test name
Test status
Simulation time 156899324 ps
CPU time 4.18 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:01 PM PDT 24
Peak memory 209096 kb
Host smart-a226d162-6e1c-48f3-aeea-2392ce4ebc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823621856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1823621856
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2869607380
Short name T858
Test name
Test status
Simulation time 134398926 ps
CPU time 1.86 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 209000 kb
Host smart-f5328617-71f1-46de-b9f1-6b415111630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869607380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2869607380
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.193780910
Short name T24
Test name
Test status
Simulation time 196704841 ps
CPU time 5.13 seconds
Started Jun 11 12:49:57 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 214952 kb
Host smart-604caec7-4bb9-4037-b40b-dcc88e598aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193780910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.193780910
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1426402398
Short name T656
Test name
Test status
Simulation time 174754547 ps
CPU time 2.99 seconds
Started Jun 11 12:49:49 PM PDT 24
Finished Jun 11 12:49:53 PM PDT 24
Peak memory 214304 kb
Host smart-1709f887-d4ec-478b-ab45-eb8bc821033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426402398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1426402398
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2099446725
Short name T233
Test name
Test status
Simulation time 125534337 ps
CPU time 3.06 seconds
Started Jun 11 12:49:41 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 222444 kb
Host smart-7e76dfdb-2746-4706-b8e7-3794ae833730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099446725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2099446725
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.287507473
Short name T479
Test name
Test status
Simulation time 9429915365 ps
CPU time 39.29 seconds
Started Jun 11 12:49:51 PM PDT 24
Finished Jun 11 12:50:31 PM PDT 24
Peak memory 210704 kb
Host smart-32954328-82ec-46e2-983c-5886037dc709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287507473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.287507473
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.716036466
Short name T361
Test name
Test status
Simulation time 87755074 ps
CPU time 3.85 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 208888 kb
Host smart-05307d8b-0203-45fc-b2e9-ae2f00259393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716036466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.716036466
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2029761254
Short name T644
Test name
Test status
Simulation time 606095612 ps
CPU time 4.86 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:50:00 PM PDT 24
Peak memory 207900 kb
Host smart-9e102116-4766-4709-8869-ba00996f9042
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029761254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2029761254
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2519116458
Short name T493
Test name
Test status
Simulation time 261894575 ps
CPU time 3.54 seconds
Started Jun 11 12:49:53 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 208736 kb
Host smart-24110d30-d0e9-410f-8895-e9c37d32e02b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519116458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2519116458
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2699008943
Short name T416
Test name
Test status
Simulation time 232049189 ps
CPU time 5.41 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 209004 kb
Host smart-50a9725e-e676-4cef-8484-1211a65fac0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699008943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2699008943
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3010118986
Short name T468
Test name
Test status
Simulation time 968447316 ps
CPU time 7.89 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:16 PM PDT 24
Peak memory 208576 kb
Host smart-106a63fd-6fc7-417b-9410-d58da94aaef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010118986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3010118986
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.318559904
Short name T888
Test name
Test status
Simulation time 1530685620 ps
CPU time 3.99 seconds
Started Jun 11 12:49:45 PM PDT 24
Finished Jun 11 12:49:50 PM PDT 24
Peak memory 208896 kb
Host smart-41da51b1-71cf-400f-9f69-8f53d128b344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318559904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.318559904
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1232636391
Short name T172
Test name
Test status
Simulation time 244689886 ps
CPU time 15.32 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:17 PM PDT 24
Peak memory 222568 kb
Host smart-a7abde67-1261-44ea-8ccb-a45dda39ca53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232636391 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1232636391
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2896347003
Short name T425
Test name
Test status
Simulation time 851816682 ps
CPU time 7.41 seconds
Started Jun 11 12:49:50 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 209020 kb
Host smart-33f536f4-32ca-461a-b301-5e10df39ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896347003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2896347003
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3092694948
Short name T502
Test name
Test status
Simulation time 189618811 ps
CPU time 2.42 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 210112 kb
Host smart-1d2b234b-09e9-442c-91d9-9a2aa887d2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092694948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3092694948
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2736567322
Short name T107
Test name
Test status
Simulation time 25884640 ps
CPU time 0.95 seconds
Started Jun 11 12:50:09 PM PDT 24
Finished Jun 11 12:50:13 PM PDT 24
Peak memory 206172 kb
Host smart-232129a1-77f9-4b77-853f-035528af068d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736567322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2736567322
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.445683238
Short name T573
Test name
Test status
Simulation time 88202082 ps
CPU time 3.84 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 209560 kb
Host smart-e0b2606f-55cb-42e8-9418-d205cefecb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445683238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.445683238
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3854392148
Short name T775
Test name
Test status
Simulation time 96198806 ps
CPU time 2.39 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 214300 kb
Host smart-79b7bf03-235e-497d-bc0f-d2653f0bf99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854392148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3854392148
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1073705379
Short name T696
Test name
Test status
Simulation time 174802348 ps
CPU time 5.83 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 214432 kb
Host smart-84455702-befc-49c8-bc26-58b7e65ce5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073705379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1073705379
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3300102228
Short name T471
Test name
Test status
Simulation time 115290269 ps
CPU time 1.52 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 206212 kb
Host smart-7819cbc1-958d-413f-baa6-1f61872ca89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300102228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3300102228
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2021871268
Short name T39
Test name
Test status
Simulation time 266183231 ps
CPU time 3.46 seconds
Started Jun 11 12:50:05 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 208684 kb
Host smart-50ea99c9-21b1-446e-a74d-84a33e4e35ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021871268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2021871268
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.253376818
Short name T672
Test name
Test status
Simulation time 164269540 ps
CPU time 4.13 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 208372 kb
Host smart-d1456fc2-0723-49cc-acdf-923c256608d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253376818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.253376818
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4006609026
Short name T917
Test name
Test status
Simulation time 76763618 ps
CPU time 3.25 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 208520 kb
Host smart-6384f188-36f0-4673-958b-ba40c85f55a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006609026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4006609026
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1399770349
Short name T219
Test name
Test status
Simulation time 608607388 ps
CPU time 21.22 seconds
Started Jun 11 12:49:57 PM PDT 24
Finished Jun 11 12:50:20 PM PDT 24
Peak memory 208816 kb
Host smart-cc845611-47e6-4ddb-9c72-20cfc0cf8229
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399770349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1399770349
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3795169909
Short name T903
Test name
Test status
Simulation time 167651016 ps
CPU time 1.92 seconds
Started Jun 11 12:50:04 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 208732 kb
Host smart-c1e80ad7-139d-4532-a989-ae437b396d11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795169909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3795169909
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2291610988
Short name T643
Test name
Test status
Simulation time 86658620 ps
CPU time 3.21 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 209928 kb
Host smart-aaf5ccf7-e795-4386-8592-e4b1446d82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291610988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2291610988
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2140441294
Short name T504
Test name
Test status
Simulation time 6447458093 ps
CPU time 49.51 seconds
Started Jun 11 12:49:56 PM PDT 24
Finished Jun 11 12:50:48 PM PDT 24
Peak memory 208380 kb
Host smart-cc87ff9f-7792-4beb-adde-c594baa9e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140441294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2140441294
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.549243066
Short name T390
Test name
Test status
Simulation time 4650434840 ps
CPU time 30.49 seconds
Started Jun 11 12:50:07 PM PDT 24
Finished Jun 11 12:50:40 PM PDT 24
Peak memory 216612 kb
Host smart-63004b77-e675-4744-add3-79f5df6b7d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549243066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.549243066
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2929209129
Short name T116
Test name
Test status
Simulation time 88656856 ps
CPU time 3.77 seconds
Started Jun 11 12:49:56 PM PDT 24
Finished Jun 11 12:50:02 PM PDT 24
Peak memory 209816 kb
Host smart-1b11e705-e935-49c2-9568-bf3a45b4f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929209129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2929209129
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2059051287
Short name T63
Test name
Test status
Simulation time 720366786 ps
CPU time 3.71 seconds
Started Jun 11 12:50:10 PM PDT 24
Finished Jun 11 12:50:17 PM PDT 24
Peak memory 210172 kb
Host smart-f9cb9c33-5297-4eaa-8784-17c5cadad783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059051287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2059051287
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2729167612
Short name T444
Test name
Test status
Simulation time 19730464 ps
CPU time 0.98 seconds
Started Jun 11 12:50:04 PM PDT 24
Finished Jun 11 12:50:06 PM PDT 24
Peak memory 206168 kb
Host smart-fe3e336d-c83e-42af-9b74-d1e305704547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729167612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2729167612
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3513004842
Short name T18
Test name
Test status
Simulation time 48669891 ps
CPU time 2.31 seconds
Started Jun 11 12:50:27 PM PDT 24
Finished Jun 11 12:50:31 PM PDT 24
Peak memory 209164 kb
Host smart-52bee363-f495-4fe9-88f8-38077aa300a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513004842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3513004842
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3573183677
Short name T319
Test name
Test status
Simulation time 360964758 ps
CPU time 7.9 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 214356 kb
Host smart-da33648e-01ab-4799-9aa2-63d78a16613b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573183677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3573183677
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.319646922
Short name T104
Test name
Test status
Simulation time 121196971 ps
CPU time 5.24 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 214444 kb
Host smart-beb82b41-be7c-485e-9565-a591e433e961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319646922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.319646922
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3044467279
Short name T45
Test name
Test status
Simulation time 98056699 ps
CPU time 1.82 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:06 PM PDT 24
Peak memory 214328 kb
Host smart-9f9df2fb-6f93-40d6-a7bd-b0f3a12c69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044467279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3044467279
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1938130678
Short name T843
Test name
Test status
Simulation time 44291242 ps
CPU time 3.11 seconds
Started Jun 11 12:50:26 PM PDT 24
Finished Jun 11 12:50:31 PM PDT 24
Peak memory 210480 kb
Host smart-a7116c88-e796-44a4-bc37-fd1c8c6d0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938130678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1938130678
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.716858860
Short name T707
Test name
Test status
Simulation time 265600067 ps
CPU time 6.85 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 218572 kb
Host smart-3098be08-7eb1-47c0-bf77-3b6d60f7bf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716858860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.716858860
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3547191389
Short name T348
Test name
Test status
Simulation time 250042481 ps
CPU time 3.23 seconds
Started Jun 11 12:50:09 PM PDT 24
Finished Jun 11 12:50:16 PM PDT 24
Peak memory 208896 kb
Host smart-477146e5-a77c-4cb4-b29c-ac89b4bafd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547191389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3547191389
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1477819769
Short name T855
Test name
Test status
Simulation time 59514939 ps
CPU time 2.3 seconds
Started Jun 11 12:50:09 PM PDT 24
Finished Jun 11 12:50:14 PM PDT 24
Peak memory 208988 kb
Host smart-06937d5b-cb33-4249-b552-140f2df97a6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477819769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1477819769
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.675141208
Short name T699
Test name
Test status
Simulation time 959443866 ps
CPU time 7.71 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 208692 kb
Host smart-78b679e8-1e0b-4282-8476-dcff22bbb47d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675141208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.675141208
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3006287046
Short name T845
Test name
Test status
Simulation time 18942160 ps
CPU time 1.66 seconds
Started Jun 11 12:50:00 PM PDT 24
Finished Jun 11 12:50:03 PM PDT 24
Peak memory 206996 kb
Host smart-8bef707d-9239-4e4a-8b7a-fa2cd840a4db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006287046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3006287046
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1881926246
Short name T884
Test name
Test status
Simulation time 122585693 ps
CPU time 2.47 seconds
Started Jun 11 12:49:54 PM PDT 24
Finished Jun 11 12:49:58 PM PDT 24
Peak memory 215856 kb
Host smart-38b73240-8567-4d85-8cbd-b032de7c5c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881926246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1881926246
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2746238922
Short name T572
Test name
Test status
Simulation time 1426017900 ps
CPU time 26.67 seconds
Started Jun 11 12:50:14 PM PDT 24
Finished Jun 11 12:50:43 PM PDT 24
Peak memory 207936 kb
Host smart-55b193fe-fe21-4efa-b7d4-a6021e478256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746238922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2746238922
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3783284590
Short name T248
Test name
Test status
Simulation time 3029612498 ps
CPU time 29.64 seconds
Started Jun 11 12:50:07 PM PDT 24
Finished Jun 11 12:50:39 PM PDT 24
Peak memory 222460 kb
Host smart-1016f333-c7ca-4894-b2ba-97b14256d8f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783284590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3783284590
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3892516481
Short name T266
Test name
Test status
Simulation time 122411040 ps
CPU time 5.29 seconds
Started Jun 11 12:49:58 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 218408 kb
Host smart-0a7aa338-be7b-4f45-bab6-f2100ee43137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892516481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3892516481
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3557610987
Short name T809
Test name
Test status
Simulation time 143738241 ps
CPU time 3.85 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:13 PM PDT 24
Peak memory 210772 kb
Host smart-f99cd60f-9a85-403d-ad47-8c01c2478be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557610987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3557610987
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3791710860
Short name T752
Test name
Test status
Simulation time 10410472 ps
CPU time 0.85 seconds
Started Jun 11 12:50:05 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 205920 kb
Host smart-53d85372-6b25-45a9-9ecf-c82908216278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791710860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3791710860
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.580319372
Short name T251
Test name
Test status
Simulation time 97883879 ps
CPU time 5.56 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:02 PM PDT 24
Peak memory 214316 kb
Host smart-76755832-d795-47e6-8460-9bfe9ce3d6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580319372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.580319372
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2565247466
Short name T28
Test name
Test status
Simulation time 82357033 ps
CPU time 3.44 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:12 PM PDT 24
Peak memory 222776 kb
Host smart-13ef0b02-5a0e-4b5b-84c8-519bb24945f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565247466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2565247466
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3751059860
Short name T861
Test name
Test status
Simulation time 50920287 ps
CPU time 2.6 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 209308 kb
Host smart-d48e7a45-388a-42a6-a43e-7c11008ca97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751059860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3751059860
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4251238467
Short name T105
Test name
Test status
Simulation time 1068863523 ps
CPU time 10.91 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:14 PM PDT 24
Peak memory 220708 kb
Host smart-d37dac50-2b42-4869-848e-659384eec632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251238467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4251238467
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1896712097
Short name T338
Test name
Test status
Simulation time 107993977 ps
CPU time 2.37 seconds
Started Jun 11 12:50:07 PM PDT 24
Finished Jun 11 12:50:12 PM PDT 24
Peak memory 214256 kb
Host smart-d08b8c67-46cd-4061-b21c-c33f48e1d77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896712097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1896712097
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3100102632
Short name T237
Test name
Test status
Simulation time 370670048 ps
CPU time 3.46 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:06 PM PDT 24
Peak memory 215868 kb
Host smart-c1c9f18d-2a6a-486e-abb7-07fade60ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100102632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3100102632
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3101678803
Short name T427
Test name
Test status
Simulation time 1097366135 ps
CPU time 6.57 seconds
Started Jun 11 12:50:06 PM PDT 24
Finished Jun 11 12:50:15 PM PDT 24
Peak memory 210452 kb
Host smart-85d1d402-d28d-4324-928e-4715855e1b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101678803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3101678803
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2448211521
Short name T508
Test name
Test status
Simulation time 205036361 ps
CPU time 2.89 seconds
Started Jun 11 12:49:59 PM PDT 24
Finished Jun 11 12:50:04 PM PDT 24
Peak memory 206760 kb
Host smart-1c54abfd-21cc-40a8-b604-a3a0eee83332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448211521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2448211521
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4222585928
Short name T413
Test name
Test status
Simulation time 92241518 ps
CPU time 2.56 seconds
Started Jun 11 12:50:05 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 206900 kb
Host smart-88bad588-79f6-4a35-8076-fd904b39b634
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222585928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4222585928
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1441220654
Short name T518
Test name
Test status
Simulation time 335885339 ps
CPU time 5.25 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 209016 kb
Host smart-164dd99a-7d3c-493f-a016-327a27cb9f25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441220654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1441220654
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4000937423
Short name T800
Test name
Test status
Simulation time 209923747 ps
CPU time 3.52 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 206916 kb
Host smart-ad1aa9aa-8b51-4cba-9e24-b45a56df95f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000937423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4000937423
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1775689340
Short name T109
Test name
Test status
Simulation time 5643317736 ps
CPU time 33.14 seconds
Started Jun 11 12:50:05 PM PDT 24
Finished Jun 11 12:50:40 PM PDT 24
Peak memory 209496 kb
Host smart-fb93f993-15c6-4378-9e61-f19f72e5dfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775689340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1775689340
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1128417145
Short name T112
Test name
Test status
Simulation time 260025166 ps
CPU time 4.02 seconds
Started Jun 11 12:50:01 PM PDT 24
Finished Jun 11 12:50:07 PM PDT 24
Peak memory 206768 kb
Host smart-f5d231ee-f8bc-4b85-b337-6580767f1965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128417145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1128417145
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1130288314
Short name T239
Test name
Test status
Simulation time 785088495 ps
CPU time 22.42 seconds
Started Jun 11 12:50:02 PM PDT 24
Finished Jun 11 12:50:26 PM PDT 24
Peak memory 216124 kb
Host smart-428753df-4c40-4c97-a830-f755d1867528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130288314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1130288314
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.882144117
Short name T141
Test name
Test status
Simulation time 380227005 ps
CPU time 14.65 seconds
Started Jun 11 12:49:55 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 221008 kb
Host smart-14f21814-8b86-4764-b5a5-b6333043c647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882144117 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.882144117
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3560727586
Short name T873
Test name
Test status
Simulation time 65181997 ps
CPU time 3.34 seconds
Started Jun 11 12:50:19 PM PDT 24
Finished Jun 11 12:50:23 PM PDT 24
Peak memory 209564 kb
Host smart-f57e1e1e-53b1-484b-bc62-4df6884ae77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560727586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3560727586
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.591147199
Short name T698
Test name
Test status
Simulation time 20346694 ps
CPU time 1.4 seconds
Started Jun 11 12:50:03 PM PDT 24
Finished Jun 11 12:50:06 PM PDT 24
Peak memory 208768 kb
Host smart-8d6f1754-7d11-4a3c-90e0-8ef7e6a46e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591147199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.591147199
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3262620361
Short name T844
Test name
Test status
Simulation time 19238008 ps
CPU time 0.82 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 205984 kb
Host smart-267ee328-3f75-4eb9-b1b9-c4df58922942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262620361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3262620361
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2299555375
Short name T21
Test name
Test status
Simulation time 113014017 ps
CPU time 2.15 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 215448 kb
Host smart-5efccf87-4298-4ab1-ba16-4851e9e504b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299555375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2299555375
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2206807418
Short name T72
Test name
Test status
Simulation time 1706274152 ps
CPU time 14.15 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 209228 kb
Host smart-5eb5bc2a-7e08-4761-b28c-9e2885705481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206807418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2206807418
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.473519316
Short name T567
Test name
Test status
Simulation time 671258281 ps
CPU time 2.63 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 214416 kb
Host smart-9f31da67-5f1d-4bca-bb95-0025badef302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473519316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.473519316
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2713152149
Short name T284
Test name
Test status
Simulation time 198038793 ps
CPU time 3.06 seconds
Started Jun 11 12:48:08 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 214580 kb
Host smart-39fcd383-a596-4167-b3ba-5005debed902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713152149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2713152149
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3468792711
Short name T808
Test name
Test status
Simulation time 202843348 ps
CPU time 5.21 seconds
Started Jun 11 12:48:05 PM PDT 24
Finished Jun 11 12:48:12 PM PDT 24
Peak memory 220712 kb
Host smart-e4cbc25d-fb77-4066-b92c-0a82dbee375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468792711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3468792711
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3082568942
Short name T908
Test name
Test status
Simulation time 293142922 ps
CPU time 4.54 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 208972 kb
Host smart-b793b0b0-0b54-491f-8ab7-9fdd0677c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082568942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3082568942
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3348284061
Short name T812
Test name
Test status
Simulation time 89949044 ps
CPU time 2.86 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:35 PM PDT 24
Peak memory 208936 kb
Host smart-a26bc1aa-051f-4fd0-8a1e-37914b2f5f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348284061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3348284061
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1508603163
Short name T674
Test name
Test status
Simulation time 292276872 ps
CPU time 5.29 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 208116 kb
Host smart-230b8c2b-bb09-44dc-afd2-e549ba33add6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508603163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1508603163
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2183771761
Short name T668
Test name
Test status
Simulation time 66168141 ps
CPU time 3.25 seconds
Started Jun 11 12:48:19 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 208884 kb
Host smart-52a978d9-5ce0-4024-b35a-be6cd6e26b57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183771761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2183771761
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.306459010
Short name T697
Test name
Test status
Simulation time 99825828 ps
CPU time 4.08 seconds
Started Jun 11 12:48:18 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 208092 kb
Host smart-1e18bfb0-1df4-4be9-9b71-e9228361a8f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306459010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.306459010
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3898592830
Short name T528
Test name
Test status
Simulation time 278138545 ps
CPU time 5.22 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:11 PM PDT 24
Peak memory 208416 kb
Host smart-63f65ba2-6f63-43ba-85ac-73a362986db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898592830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3898592830
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2008933709
Short name T458
Test name
Test status
Simulation time 46777276 ps
CPU time 2.4 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 208316 kb
Host smart-6eba505d-2b05-4445-8d15-0d633ee5b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008933709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2008933709
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.74023684
Short name T170
Test name
Test status
Simulation time 102287439 ps
CPU time 0.79 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 205940 kb
Host smart-c91ef1a3-51b8-4468-bca5-1529a916c6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74023684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.74023684
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1939471113
Short name T889
Test name
Test status
Simulation time 216518926 ps
CPU time 7.44 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 220176 kb
Host smart-1a31ac44-e77d-4c8f-b244-0727ad78d992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939471113 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1939471113
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3822670020
Short name T461
Test name
Test status
Simulation time 121659890 ps
CPU time 5.38 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 210080 kb
Host smart-d4d7584c-7081-4a15-beaa-edb89209ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822670020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3822670020
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3107781819
Short name T561
Test name
Test status
Simulation time 90778415 ps
CPU time 3.21 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:21 PM PDT 24
Peak memory 210316 kb
Host smart-7f85a8fc-fb17-4337-b71e-44a20551268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107781819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3107781819
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1258334874
Short name T678
Test name
Test status
Simulation time 16053995 ps
CPU time 0.77 seconds
Started Jun 11 12:48:43 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 205876 kb
Host smart-f1653b54-4d8c-43f6-9f23-a307c37d7498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258334874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1258334874
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3627767816
Short name T381
Test name
Test status
Simulation time 1113477803 ps
CPU time 9.1 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 215256 kb
Host smart-aeeba8e8-5684-434b-b549-6718fdcd61d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627767816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3627767816
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2249484809
Short name T784
Test name
Test status
Simulation time 864147529 ps
CPU time 5.33 seconds
Started Jun 11 12:48:06 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 214716 kb
Host smart-a9755f11-4673-4cff-b1f9-486684150db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249484809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2249484809
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1805274425
Short name T898
Test name
Test status
Simulation time 36816457 ps
CPU time 1.88 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 218356 kb
Host smart-d4f77e9f-d833-457f-ac4c-f1dee2c4260b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805274425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1805274425
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.739502155
Short name T95
Test name
Test status
Simulation time 264884925 ps
CPU time 6.41 seconds
Started Jun 11 12:47:59 PM PDT 24
Finished Jun 11 12:48:08 PM PDT 24
Peak memory 214380 kb
Host smart-27af51f7-58cb-43cf-9b94-14a5e4f950a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739502155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.739502155
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2263969732
Short name T631
Test name
Test status
Simulation time 174743450 ps
CPU time 2.38 seconds
Started Jun 11 12:48:11 PM PDT 24
Finished Jun 11 12:48:16 PM PDT 24
Peak memory 214380 kb
Host smart-5382d67a-cf6a-44b8-b4f0-c8dd1d559c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263969732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2263969732
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1777458311
Short name T317
Test name
Test status
Simulation time 353678929 ps
CPU time 5.89 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 207984 kb
Host smart-38616284-2bdb-4041-933b-9be97bb40f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777458311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1777458311
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.858675340
Short name T743
Test name
Test status
Simulation time 224067339 ps
CPU time 2.86 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:17 PM PDT 24
Peak memory 207024 kb
Host smart-0f812c39-7a5a-4b35-84f0-39ecb568e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858675340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.858675340
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3878767800
Short name T485
Test name
Test status
Simulation time 161233032 ps
CPU time 2.94 seconds
Started Jun 11 12:48:01 PM PDT 24
Finished Jun 11 12:48:06 PM PDT 24
Peak memory 208688 kb
Host smart-3709f178-2c49-45e1-9a14-e8eb950f858c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878767800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3878767800
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3787819426
Short name T221
Test name
Test status
Simulation time 83566482 ps
CPU time 2.55 seconds
Started Jun 11 12:48:10 PM PDT 24
Finished Jun 11 12:48:15 PM PDT 24
Peak memory 206992 kb
Host smart-6cc8629c-c611-441d-910d-cd65476b97f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787819426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3787819426
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.922356638
Short name T16
Test name
Test status
Simulation time 1562784230 ps
CPU time 27.8 seconds
Started Jun 11 12:48:06 PM PDT 24
Finished Jun 11 12:48:35 PM PDT 24
Peak memory 209188 kb
Host smart-b8e8a8c0-b31d-487d-a9dc-5f4351341cad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922356638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.922356638
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3408410629
Short name T12
Test name
Test status
Simulation time 100706920 ps
CPU time 2.07 seconds
Started Jun 11 12:48:04 PM PDT 24
Finished Jun 11 12:48:08 PM PDT 24
Peak memory 216444 kb
Host smart-59390243-4b56-4453-a942-b24a7135e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408410629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3408410629
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2664326172
Short name T653
Test name
Test status
Simulation time 91093833 ps
CPU time 1.99 seconds
Started Jun 11 12:48:12 PM PDT 24
Finished Jun 11 12:48:17 PM PDT 24
Peak memory 208292 kb
Host smart-1728e343-471f-4d42-8bbd-133234f83cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664326172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2664326172
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.22460181
Short name T203
Test name
Test status
Simulation time 1487560767 ps
CPU time 14.14 seconds
Started Jun 11 12:48:17 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 221236 kb
Host smart-ec5cff53-708a-4a6e-a744-57683927d6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22460181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.22460181
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3713270474
Short name T299
Test name
Test status
Simulation time 577780653 ps
CPU time 7.35 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:24 PM PDT 24
Peak memory 208892 kb
Host smart-5b217d31-573a-46d2-8292-b2678f196a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713270474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3713270474
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1346058511
Short name T177
Test name
Test status
Simulation time 52606002 ps
CPU time 2.1 seconds
Started Jun 11 12:48:01 PM PDT 24
Finished Jun 11 12:48:05 PM PDT 24
Peak memory 210124 kb
Host smart-9c48baed-5054-4854-9f5a-de6a0b515066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346058511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1346058511
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1395742288
Short name T460
Test name
Test status
Simulation time 103305845 ps
CPU time 0.69 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 206200 kb
Host smart-8264619a-7008-43c2-a78a-ff86b1a16184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395742288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1395742288
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1436920191
Short name T250
Test name
Test status
Simulation time 538777084 ps
CPU time 7.19 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 214516 kb
Host smart-6ebeaf89-07c4-4296-879f-2ef29123f72d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436920191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1436920191
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3610765152
Short name T582
Test name
Test status
Simulation time 359362345 ps
CPU time 4.21 seconds
Started Jun 11 12:48:40 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 209468 kb
Host smart-02a9e0f1-1444-4d53-9554-e03af3fe1ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610765152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3610765152
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4076609697
Short name T618
Test name
Test status
Simulation time 1268490386 ps
CPU time 23.12 seconds
Started Jun 11 12:48:22 PM PDT 24
Finished Jun 11 12:48:48 PM PDT 24
Peak memory 214252 kb
Host smart-0469cd75-9a2a-4c1d-b8ee-7bf7c8672e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076609697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4076609697
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2682014370
Short name T97
Test name
Test status
Simulation time 182238811 ps
CPU time 2.16 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 214304 kb
Host smart-b3acd6d7-392e-4a26-9678-4de01e720317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682014370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2682014370
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1529686099
Short name T236
Test name
Test status
Simulation time 850086488 ps
CPU time 5.89 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 209460 kb
Host smart-4f054060-25f1-4cba-98f8-2eec7e0bf01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529686099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1529686099
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2618454130
Short name T211
Test name
Test status
Simulation time 103367401 ps
CPU time 4.71 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:28 PM PDT 24
Peak memory 208772 kb
Host smart-401ceb5b-37fb-44ef-9bdd-3f12ead84015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618454130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2618454130
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4144607312
Short name T864
Test name
Test status
Simulation time 32387393 ps
CPU time 2.16 seconds
Started Jun 11 12:48:06 PM PDT 24
Finished Jun 11 12:48:10 PM PDT 24
Peak memory 206868 kb
Host smart-e76fd4ec-2876-439f-b67c-9b0815df20ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144607312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4144607312
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1770328804
Short name T310
Test name
Test status
Simulation time 264108728 ps
CPU time 2.92 seconds
Started Jun 11 12:48:19 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 208820 kb
Host smart-734cec01-127a-4a49-8065-8f1f08e5fa9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770328804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1770328804
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.811851284
Short name T367
Test name
Test status
Simulation time 89284338 ps
CPU time 3.15 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 207052 kb
Host smart-c69d519d-1907-418e-8f8e-7815e418a0f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811851284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.811851284
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.908408728
Short name T900
Test name
Test status
Simulation time 1888677612 ps
CPU time 48.92 seconds
Started Jun 11 12:48:09 PM PDT 24
Finished Jun 11 12:49:01 PM PDT 24
Peak memory 208292 kb
Host smart-944fea1e-ce85-4665-aa39-35d5aeb89f7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908408728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.908408728
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2865671764
Short name T700
Test name
Test status
Simulation time 309929994 ps
CPU time 4.66 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 210152 kb
Host smart-0643a380-ddce-4d7e-aa0e-fb03c4ec4d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865671764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2865671764
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3385062546
Short name T659
Test name
Test status
Simulation time 43088987 ps
CPU time 1.58 seconds
Started Jun 11 12:48:41 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 207008 kb
Host smart-dd3c328c-6f73-4408-b889-d38c23cfa601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385062546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3385062546
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2910295780
Short name T201
Test name
Test status
Simulation time 3177850448 ps
CPU time 11.86 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 216696 kb
Host smart-8f0bab34-ea21-430f-9fd1-a54b3f9a68ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910295780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2910295780
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3988118296
Short name T278
Test name
Test status
Simulation time 194096416 ps
CPU time 11.25 seconds
Started Jun 11 12:48:25 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 219684 kb
Host smart-dfb83854-5216-48e1-8866-a587903dad30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988118296 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3988118296
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3740295987
Short name T913
Test name
Test status
Simulation time 962394255 ps
CPU time 11.42 seconds
Started Jun 11 12:48:25 PM PDT 24
Finished Jun 11 12:48:39 PM PDT 24
Peak memory 209196 kb
Host smart-298fb95e-ee2b-43c1-b915-7ccc6a63b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740295987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3740295987
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3938810982
Short name T854
Test name
Test status
Simulation time 102588013 ps
CPU time 1.68 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:28 PM PDT 24
Peak memory 209864 kb
Host smart-b315f5aa-bd9f-449d-ae86-bd39cdc1551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938810982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3938810982
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2486496119
Short name T595
Test name
Test status
Simulation time 11230874 ps
CPU time 0.86 seconds
Started Jun 11 12:48:27 PM PDT 24
Finished Jun 11 12:48:31 PM PDT 24
Peak memory 205988 kb
Host smart-859f96b0-5ebc-49c7-a28e-958f1bda5a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486496119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2486496119
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4264291903
Short name T147
Test name
Test status
Simulation time 58680700 ps
CPU time 4.13 seconds
Started Jun 11 12:48:13 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 222592 kb
Host smart-3aa9ed5f-0551-4765-800d-63a0a5780075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264291903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4264291903
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1560506789
Short name T565
Test name
Test status
Simulation time 193286241 ps
CPU time 4.44 seconds
Started Jun 11 12:48:19 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 214688 kb
Host smart-1b4808ab-a656-4b07-96f2-bf33c2b87b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560506789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1560506789
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.120516728
Short name T77
Test name
Test status
Simulation time 174002519 ps
CPU time 2.64 seconds
Started Jun 11 12:48:18 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 207396 kb
Host smart-12773e95-c7f1-4c94-8092-a0c9a8ff7612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120516728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.120516728
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1616636222
Short name T225
Test name
Test status
Simulation time 280630248 ps
CPU time 7.77 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:34 PM PDT 24
Peak memory 214376 kb
Host smart-cfb9ffa1-e9ae-4ca2-ab7c-62193079ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616636222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1616636222
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1054535307
Short name T258
Test name
Test status
Simulation time 147118997 ps
CPU time 3.26 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 214352 kb
Host smart-dc9794bc-b4ad-49de-a137-3123e91a452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054535307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1054535307
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3687046899
Short name T55
Test name
Test status
Simulation time 473908073 ps
CPU time 2.83 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:30 PM PDT 24
Peak memory 219916 kb
Host smart-34c3ef2b-3f60-4f8e-8930-700a2c2b4bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687046899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3687046899
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_sideload.274226297
Short name T880
Test name
Test status
Simulation time 2040012338 ps
CPU time 8.26 seconds
Started Jun 11 12:48:45 PM PDT 24
Finished Jun 11 12:48:57 PM PDT 24
Peak memory 208312 kb
Host smart-6ab6f258-4ba6-417a-bebf-81efbd05478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274226297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.274226297
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1467102981
Short name T732
Test name
Test status
Simulation time 205547140 ps
CPU time 2.63 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 207384 kb
Host smart-422a465b-0aed-43a3-af85-c583c1d1e31a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467102981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1467102981
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.786930249
Short name T689
Test name
Test status
Simulation time 272027635 ps
CPU time 4.24 seconds
Started Jun 11 12:48:19 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 209100 kb
Host smart-1720143e-3ae5-48ba-8f29-73e15c3f200f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786930249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.786930249
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1528923459
Short name T840
Test name
Test status
Simulation time 19687276 ps
CPU time 1.74 seconds
Started Jun 11 12:48:26 PM PDT 24
Finished Jun 11 12:48:31 PM PDT 24
Peak memory 207232 kb
Host smart-46a2a4ab-18e2-4643-b564-88e8670ec64d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528923459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1528923459
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.156077402
Short name T828
Test name
Test status
Simulation time 1113454773 ps
CPU time 5 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 218164 kb
Host smart-d9b989a5-cbb6-4f83-a112-2b778d96caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156077402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.156077402
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2376393293
Short name T640
Test name
Test status
Simulation time 249130480 ps
CPU time 3.55 seconds
Started Jun 11 12:48:17 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 206828 kb
Host smart-1625c882-1d1e-4525-90d6-a40ea604a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376393293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2376393293
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3041306143
Short name T84
Test name
Test status
Simulation time 2798291958 ps
CPU time 28.1 seconds
Started Jun 11 12:48:27 PM PDT 24
Finished Jun 11 12:48:58 PM PDT 24
Peak memory 220268 kb
Host smart-4d32e8e8-14dd-41f6-8bff-614d16f21602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041306143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3041306143
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.484066754
Short name T756
Test name
Test status
Simulation time 669746304 ps
CPU time 16.73 seconds
Started Jun 11 12:48:24 PM PDT 24
Finished Jun 11 12:48:43 PM PDT 24
Peak memory 222588 kb
Host smart-c6fbb574-7b47-4fb3-8df3-48ec43b72ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484066754 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.484066754
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.717314736
Short name T140
Test name
Test status
Simulation time 155137253 ps
CPU time 4.58 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 209136 kb
Host smart-d1bd4ccd-c9c8-41d3-b65b-bf154b800ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717314736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.717314736
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1114425412
Short name T204
Test name
Test status
Simulation time 96646412 ps
CPU time 3.18 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 210184 kb
Host smart-01121fb0-6d80-49ae-9bcc-ea38dde7ce6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114425412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1114425412
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2977228714
Short name T602
Test name
Test status
Simulation time 15317997 ps
CPU time 0.71 seconds
Started Jun 11 12:48:25 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 205960 kb
Host smart-9544171f-46f9-4ce5-9136-1c65667e3d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977228714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2977228714
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1260385765
Short name T428
Test name
Test status
Simulation time 54342664 ps
CPU time 2.37 seconds
Started Jun 11 12:48:18 PM PDT 24
Finished Jun 11 12:48:23 PM PDT 24
Peak memory 214372 kb
Host smart-7da7a1f6-2415-4e90-83f8-49c9febcda91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260385765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1260385765
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3031042218
Short name T605
Test name
Test status
Simulation time 294855863 ps
CPU time 7.36 seconds
Started Jun 11 12:48:21 PM PDT 24
Finished Jun 11 12:48:32 PM PDT 24
Peak memory 214616 kb
Host smart-e200dd34-2d75-46fa-83e8-f53133cedfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031042218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3031042218
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.233254319
Short name T426
Test name
Test status
Simulation time 66013578 ps
CPU time 1.87 seconds
Started Jun 11 12:48:07 PM PDT 24
Finished Jun 11 12:48:11 PM PDT 24
Peak memory 222460 kb
Host smart-e54e463d-71ef-4a15-9097-5a30664214b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233254319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.233254319
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2679467916
Short name T894
Test name
Test status
Simulation time 184885695 ps
CPU time 2.24 seconds
Started Jun 11 12:48:16 PM PDT 24
Finished Jun 11 12:48:20 PM PDT 24
Peak memory 214300 kb
Host smart-1d2347d9-fdbb-4ff1-a051-d0c21f2796e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679467916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2679467916
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.475175777
Short name T726
Test name
Test status
Simulation time 59146974 ps
CPU time 3.01 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 214412 kb
Host smart-e0e51411-7196-4935-ada5-848220502af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475175777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.475175777
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1779294820
Short name T41
Test name
Test status
Simulation time 251074065 ps
CPU time 3.75 seconds
Started Jun 11 12:48:19 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 214396 kb
Host smart-007740f7-e507-46ad-8000-1b4dc2076bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779294820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1779294820
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2438098261
Short name T910
Test name
Test status
Simulation time 148557835 ps
CPU time 6.6 seconds
Started Jun 11 12:48:14 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 210432 kb
Host smart-dde75b78-1d95-4cae-a435-c28b46843abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438098261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2438098261
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3902463588
Short name T370
Test name
Test status
Simulation time 74059295 ps
CPU time 3.1 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:29 PM PDT 24
Peak memory 208652 kb
Host smart-7d5fa8a8-86ca-4746-abb1-6b423e2c4a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902463588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3902463588
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2305839556
Short name T677
Test name
Test status
Simulation time 177187034 ps
CPU time 3.79 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:21 PM PDT 24
Peak memory 208440 kb
Host smart-2bd3d78b-26c6-44fc-a4ef-935b5c25d736
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305839556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2305839556
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.806457354
Short name T760
Test name
Test status
Simulation time 146299356 ps
CPU time 2.94 seconds
Started Jun 11 12:48:05 PM PDT 24
Finished Jun 11 12:48:09 PM PDT 24
Peak memory 207732 kb
Host smart-951bbd6e-fb32-417b-b50f-6b773d915763
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806457354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.806457354
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3978146043
Short name T882
Test name
Test status
Simulation time 347998357 ps
CPU time 5.23 seconds
Started Jun 11 12:48:23 PM PDT 24
Finished Jun 11 12:48:31 PM PDT 24
Peak memory 207776 kb
Host smart-8d1e7d8a-1232-4fe3-94f4-bfe2bde42a90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978146043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3978146043
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.580700403
Short name T4
Test name
Test status
Simulation time 116266627 ps
CPU time 1.93 seconds
Started Jun 11 12:48:22 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 208444 kb
Host smart-2db18d24-8b76-4fa0-9faf-2207787b07e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580700403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.580700403
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2621825662
Short name T511
Test name
Test status
Simulation time 477727995 ps
CPU time 3.3 seconds
Started Jun 11 12:48:08 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 208436 kb
Host smart-57aeab26-3d3a-4e3e-a29b-9dac6390df8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621825662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2621825662
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1908972751
Short name T169
Test name
Test status
Simulation time 78775980 ps
CPU time 0.79 seconds
Started Jun 11 12:48:33 PM PDT 24
Finished Jun 11 12:48:35 PM PDT 24
Peak memory 205892 kb
Host smart-84427811-617f-4b4d-8564-4802d6b26428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908972751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1908972751
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3326709519
Short name T142
Test name
Test status
Simulation time 177398950 ps
CPU time 5.88 seconds
Started Jun 11 12:48:39 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 218524 kb
Host smart-af880e43-905f-4e63-ba94-eb4a3575633a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326709519 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3326709519
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2985947744
Short name T119
Test name
Test status
Simulation time 582875306 ps
CPU time 5.14 seconds
Started Jun 11 12:48:17 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 218348 kb
Host smart-975c5397-5431-46d4-893f-fc450d75dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985947744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2985947744
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.345237885
Short name T587
Test name
Test status
Simulation time 62893153 ps
CPU time 2.83 seconds
Started Jun 11 12:48:20 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 210116 kb
Host smart-8e523b35-21ff-46d5-a294-56e176210580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345237885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.345237885
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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