Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T4	1		T29	1		T52	1
auto[OpGenId]	14	1			T62	1		T72	1		T77	1
auto[OpGenSwOut]	24	1			T63	1		T156	1		T8	1
auto[OpGenHwOut]	17	1			T5	1		T6	1		T30	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1704	1			T114	1		T29	1		T5	2
auto[StInit]	91	1			T4	1		T43	1		T29	1
auto[StCreatorRootKey]	59	1			T62	1		T63	1		T49	1
auto[StOwnerIntKey]	44	1			T29	1		T67	2		T68	1
auto[StOwnerKey]	38	1			T42	1		T6	1		T48	1
auto[StDisabled]	489	1			T33	1		T29	2		T67	3
auto[StInvalid]	50	1			T2	1		T47	1		T57	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3457

1

T1

1

T2

2

T3

1

auto[1]

105

1

T4

1

T62

1

T63

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1699	1			T114	1		T29	1		T5	2
auto[StReset]	auto[1]	5	1			T8	1		T58	1		T236	1
auto[StInit]	auto[0]	46	1			T43	1		T29	1		T60	1
auto[StInit]	auto[1]	45	1			T4	1		T52	1		T53	1
auto[StCreatorRootKey]	auto[0]	36	1			T49	1		T93	1		T137	1
auto[StCreatorRootKey]	auto[1]	23	1			T62	1		T63	1		T35	1
auto[StOwnerIntKey]	auto[0]	36	1			T67	2		T68	1		T69	1
auto[StOwnerIntKey]	auto[1]	8	1			T29	1		T237	1		T83	1
auto[StOwnerKey]	auto[0]	27	1			T42	1		T6	1		T48	1
auto[StOwnerKey]	auto[1]	11	1			T73	1		T238	1		T140	1
auto[StDisabled]	auto[0]	476	1			T33	1		T29	2		T67	3
auto[StDisabled]	auto[1]	13	1			T72	1		T77	1		T206	1
auto[StInvalid]	auto[0]	50	1			T2	1		T47	1		T57	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T58	1		T236	1		T197	1
auto[StReset]	auto[OpGenSwOut]	1	1			T8	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	18	1			T4	1		T52	1		T53	1
auto[StInit]	auto[OpGenId]	3	1			T239	1		T240	1		T78	1
auto[StInit]	auto[OpGenSwOut]	13	1			T156	1		T138	1		T158	1
auto[StInit]	auto[OpGenHwOut]	11	1			T5	1		T6	1		T30	1
auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T35	1		T64	1		T241	1
auto[StCreatorRootKey]	auto[OpGenId]	5	1			T62	1		T242	1		T194	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T63	1		T243	1		T244	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T245	1		T79	1		T246	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T29	1		T247	1		T248	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T83	1		T249	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T237	1		T250	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	9	1			T73	1		T238	1		T140	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T251	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T252	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T243	1		T87	1		T253	1
auto[StDisabled]	auto[OpGenId]	4	1			T72	1		T77	1		T254	1
auto[StDisabled]	auto[OpGenSwOut]	2	1			T207	1		T255	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T206	1		T256	1		-	-