Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4898

1

T2

1

T3

1

T14

4

auto[1]

595

1

T1

3

T15

1

T33

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4898

1

T2

1

T3

1

T14

4

auto[1]

595

1

T1

3

T15

1

T33

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4968

1

T2

1

T14

4

T15

3

auto[1]

525

1

T1

3

T3

1

T15

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4968

1

T2

1

T14

4

T15

3

auto[1]

525

1

T1

3

T3

1

T15

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	483	1			T1	2		T50	4		T41	3
auto[OpGenId]	1156	1			T2	1		T16	2		T33	1
auto[OpGenSwOut]	1151	1			T3	1		T14	2		T15	3
auto[OpGenHwOut]	2622	1			T1	1		T14	2		T15	1
auto[OpDisable]	81	1			T55	1		T56	1		T5	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	483	1			T1	2		T50	4		T41	3
auto[OpGenId]	1156	1			T2	1		T16	2		T33	1
auto[OpGenSwOut]	1151	1			T3	1		T14	2		T15	3
auto[OpGenHwOut]	2622	1			T1	1		T14	2		T15	1
auto[OpDisable]	81	1			T55	1		T56	1		T5	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4899

1

T1

3

T2

1

T3

1

auto[1]

594

1

T17

6

T38

6

T97

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4899

1

T1

3

T2

1

T3

1

auto[1]

594

1

T17

6

T38

6

T97

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5244

1

T1

3

T2

1

T3

1

auto[1]

249

1

T97

2

T50

11

T130

10

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1899	1			T1	1		T2	1		T3	1
auto[1]	745	1			T14	1		T16	1		T17	2
auto[2]	766	1			T17	2		T38	1		T97	2
auto[3]	675	1			T1	2		T14	1		T15	1
auto[4]	369	1			T14	1		T16	2		T19	2
auto[5]	348	1			T15	1		T154	2		T51	1
auto[6]	335	1			T15	1		T17	1		T19	3
auto[7]	356	1			T19	1		T38	1		T154	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1408	1			T14	1		T15	2		T16	2
clear_one[1]	745	1			T14	1		T16	1		T17	2
clear_one[2]	766	1			T17	2		T38	1		T97	2
clear_one[3]	675	1			T1	2		T14	1		T15	1
clear_none	1899	1			T1	1		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1007	1			T19	5		T50	3		T51	1
auto[StInit]	647	1			T16	1		T17	1		T19	1
auto[StCreatorRootKey]	584	1			T17	1		T19	1		T38	1
auto[StOwnerIntKey]	540	1			T17	1		T19	1		T38	1
auto[StOwnerKey]	476	1			T1	1		T3	1		T16	1
auto[StDisabled]	1940	1			T1	2		T15	4		T16	2
auto[StInvalid]	299	1			T2	1		T14	4		T41	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1007	1			T19	5		T50	3		T51	1
auto[StInit]	647	1			T16	1		T17	1		T19	1
auto[StCreatorRootKey]	584	1			T17	1		T19	1		T38	1
auto[StOwnerIntKey]	540	1			T17	1		T19	1		T38	1
auto[StOwnerKey]	476	1			T1	1		T3	1		T16	1
auto[StDisabled]	1940	1			T1	2		T15	4		T16	2
auto[StInvalid]	299	1			T2	1		T14	4		T41	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[1] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[1] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T257	1		T258	1		T259	1
auto[0]	auto[StReset]	auto[OpGenId]	153	1			T50	1		T41	2		T54	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	168	1			T222	1		T130	1		T29	3
auto[0]	auto[StReset]	auto[OpGenHwOut]	268	1			T19	1		T50	2		T51	1
auto[0]	auto[StInit]	auto[OpAdvance]	46	1			T142	2		T67	1		T53	1
auto[0]	auto[StInit]	auto[OpGenId]	100	1			T16	1		T97	1		T54	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	86	1			T97	1		T67	1		T52	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	183	1			T17	1		T38	1		T154	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T260	1		T139	1		T261	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	51	1			T143	1		T61	1		T5	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	54	1			T5	1		T213	1		T262	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	91	1			T17	1		T38	1		T97	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T263	1		T264	1		T256	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	40	1			T222	1		T142	1		T5	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T67	1		T6	1		T156	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T19	1		T33	1		T234	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	16	1			T5	1		T265	1		T156	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	31	1			T5	1		T6	1		T266	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T3	1		T5	1		T156	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	56	1			T1	1		T38	1		T234	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T80	1		T156	1		T64	1
auto[0]	auto[StDisabled]	auto[OpGenId]	67	1			T222	1		T130	3		T142	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T15	1		T80	2		T93	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T17	1		T19	1		T38	2
auto[0]	auto[StDisabled]	auto[OpDisable]	28	1			T5	1		T80	2		T6	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	14	1			T41	1		T267	1		T268	1
auto[0]	auto[StInvalid]	auto[OpGenId]	25	1			T2	1		T41	1		T267	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T14	1		T269	1		T270	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T219	1		T267	1		T271	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T152	1		T80	1		T103	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	20	1			T130	1		T6	1		T272	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T19	2		T273	2		T145	1
auto[1]	auto[StInit]	auto[OpAdvance]	5	1			T58	1		T79	1		T31	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T6	2		T274	1		T275	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	11	1			T223	1		T63	1		T137	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	23	1			T234	1		T149	1		T92	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T80	1		T24	1		T276	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T93	1		T137	1		T218	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T148	1		T94	1		T277	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T273	1		T56	1		T224	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T80	1		T158	1		T257	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T278	1		T198	1		T279	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T141	1		T266	1		T201	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T148	1		T150	1		T5	2
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T280	1		T281	1		T282	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T80	1		T64	1		T118	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T141	1		T6	1		T156	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T16	1		T17	1		T155	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T64	1		T118	1		T158	2
auto[1]	auto[StDisabled]	auto[OpGenId]	59	1			T5	1		T226	1		T165	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T148	2		T67	1		T5	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T17	1		T38	1		T222	1
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T76	1		T58	1		T243	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	12	1			T41	2		T102	1		T283	1
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T47	1		T284	1		T285	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T116	1		T267	1		T271	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T14	1		T57	1		T286	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T54	1		T287	1		T288	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T156	1		T289	2		T64	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	47	1			T234	1		T145	1		T230	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T290	1		T291	1		T292	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T293	1		T157	1		T25	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T156	1		T294	1		T295	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	25	1			T212	1		T296	1		T158	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T80	1		T73	1		T201	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T278	1		T65	1		T158	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T130	2		T65	1		T158	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	51	1			T51	1		T233	1		T151	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T29	1		T157	1		T201	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T226	1		T72	1		T24	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T262	1		T111	1		T65	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T17	1		T38	1		T156	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T25	1		T201	1		T297	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T137	1		T298	1		T99	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T222	1		T80	1		T93	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T273	1		T230	1		T80	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	40	1			T50	4		T222	1		T130	1
auto[2]	auto[StDisabled]	auto[OpGenId]	58	1			T142	2		T149	1		T165	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T97	1		T130	3		T80	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	170	1			T17	1		T97	1		T50	1
auto[2]	auto[StDisabled]	auto[OpDisable]	16	1			T56	1		T156	1		T72	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	11	1			T47	2		T289	2		T286	2
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T103	1		T98	1		T299	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T57	1		T300	1		T283	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T267	1		T300	1		T283	1
auto[3]	auto[StReset]	auto[OpGenId]	15	1			T278	1		T276	1		T245	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	21	1			T6	1		T156	1		T93	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	42	1			T29	1		T8	1		T96	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T269	1		T117	1		T26	1
auto[3]	auto[StInit]	auto[OpGenId]	9	1			T35	1		T301	1		T110	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	9	1			T302	1		T303	1		T304	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	22	1			T151	1		T230	1		T80	2
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T6	1		T303	2		T305	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T165	1		T201	1		T140	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T229	1		T64	1		T204	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T154	1		T155	1		T232	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T165	1		T306	1		T140	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T80	1		T208	1		T65	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T228	1		T6	1		T307	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T155	1		T233	1		T80	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T156	1		T306	1		T64	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	16	1			T148	1		T156	1		T260	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T6	1		T308	1		T274	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T19	1		T51	1		T151	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T1	2		T265	1		T58	1
auto[3]	auto[StDisabled]	auto[OpGenId]	67	1			T56	1		T5	2		T80	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	48	1			T15	1		T80	1		T293	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T19	1		T51	1		T155	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T309	1		T206	1		T241	2
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T269	1		T310	1		T268	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T101	1		T311	1		T98	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T270	1		T300	1		T283	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T14	1		T103	1		T269	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T64	1		T312	1		T299	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T238	1		T313	1		T243	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T234	1		T314	1		T296	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T110	1		T107	1		T315	1
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T50	1		T299	1		T316	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	2	1			T47	1		T64	1		-	-
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T50	1		T51	1		T145	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T241	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T149	1		T243	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T50	1		T312	2		T318	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T19	1		T50	2		T319	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T252	1		T320	1		T321	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T322	1		T323	1		T324	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T156	1		T325	1		T317	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T151	1		T326	1		T137	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T142	2		T80	1		T327	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T278	1		T76	1		T137	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T328	1		T77	1		T329	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T50	1		T235	1		T67	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	22	1			T29	1		T280	3		T64	1
auto[4]	auto[StDisabled]	auto[OpGenId]	35	1			T16	1		T50	1		T226	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T50	2		T130	1		T144	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T16	1		T19	1		T50	1
auto[4]	auto[StDisabled]	auto[OpDisable]	3	1			T158	1		T85	1		T89	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	7	1			T47	2		T310	1		T116	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T101	1		T330	1		T331	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T14	1		T57	1		T332	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T286	1		T333	1		T334	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T29	1		T6	1		T103	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T41	1		T57	1		T65	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	27	1			T54	1		T273	1		T151	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T29	1		T335	1		T336	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T328	1		T118	1		T337	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T222	1		T338	1		T26	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T322	1		T193	1		T256	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T22	1		T339	1		T340	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T237	1		T341	1		T207	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T326	1		T96	1		T342	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T343	1		T58	1		T274	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T344	1		T85	1		T345	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T77	1		T158	1		T346	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T230	1		T347	1		T348	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T77	1		T257	1		T349	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	2	1			T5	1		T323	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T58	1		T257	1		T83	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T154	1		T150	1		T92	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T67	1		T228	1		T64	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T5	1		T64	1		T335	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T152	1		T229	1		T156	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T15	1		T154	1		T51	1
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T158	1		T350	1		T205	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T219	1		T299	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T351	1		T352	1		T353	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T41	1		T116	1		T102	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T354	1		T332	1		T284	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T355	1		T298	1		T356	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T118	1		T357	1		T358	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	17	1			T19	2		T234	1		T359	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T241	1		T360	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T201	1		T109	1		T107	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T65	1		T206	1		T59	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	4	1			T19	1		T319	1		T361	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T362	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T64	1		T158	1		T345	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T288	1		T363	1		T364	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T234	1		T231	1		T365	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T366	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T77	1		T140	1		T206	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T156	1		T65	1		T21	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	25	1			T97	1		T235	1		T145	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T65	1		T261	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	8	1			T33	1		T204	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T224	1		T73	1		T58	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T97	1		T231	1		T296	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	13	1			T77	1		T158	1		T323	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T29	1		T67	1		T5	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T15	1		T143	1		T5	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T17	1		T155	1		T234	2
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T201	1		T84	1		T193	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T332	1		T368	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T310	1		T271	1		T98	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T219	1		T270	1		T271	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T267	1		T286	1		T300	1
auto[7]	auto[StReset]	auto[OpGenId]	15	1			T41	1		T223	1		T152	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T141	1		T93	1		T272	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	17	1			T64	1		T308	1		T355	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T93	1		T244	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T64	1		T288	1		T205	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T369	1		T85	1		T107	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T141	1		T220	1		T158	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T365	1		T370	1		T246	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T29	1		T371	1		T372	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T104	1		T373	1		T252	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T235	1		T5	1		T65	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T130	2		T73	1		T137	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T260	1		T58	1		T139	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T337	1		T374	1		T375	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T154	1		T51	1		T273	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T67	1		T376	1		T377	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T378	1		T379	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T130	3		T65	1		T201	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	10	1			T348	1		T218	1		T111	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	11	1			T156	1		T365	1		T64	1
auto[7]	auto[StDisabled]	auto[OpGenId]	32	1			T6	1		T277	1		T137	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T141	1		T67	1		T80	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T19	1		T38	1		T234	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T55	1		T158	1		T85	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T380	1		T341	1		T381	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T103	1		T219	1		T271	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T289	1		T98	1		T382	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T57	1		T289	1		T269	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1408

1

T14

1

T15

2

T16

2

clear_one[1]

auto[0]

auto[0]

auto[0]

448

1

T14

1

T16

1

T19

2

clear_one[1]

auto[0]

auto[0]

auto[1]

145

1

T17

2

T38

1

T235

1

clear_one[1]

auto[0]

auto[1]

auto[0]

118

1

T222

1

T232

2

T148

3

clear_one[1]

auto[0]

auto[1]

auto[1]

34

1

T148

1

T5

1

T80

1

clear_one[2]

auto[0]

auto[0]

auto[0]

445

1

T50

5

T154

1

T51

3

clear_one[2]

auto[0]

auto[0]

auto[1]

130

1

T17

2

T38

1

T97

1

clear_one[2]

auto[1]

auto[0]

auto[0]

137

1

T234

1

T222

2

T145

1

clear_one[2]

auto[1]

auto[0]

auto[1]

54

1

T97

1

T130

3

T142

1

clear_one[3]

auto[0]

auto[0]

auto[0]

398

1

T14

1

T15

1

T233

1

clear_one[3]

auto[0]

auto[1]

auto[0]

103

1

T19

2

T154

1

T51

2

clear_one[3]

auto[1]

auto[0]

auto[0]

129

1

T155

3

T145

1

T150

2

clear_one[3]

auto[1]

auto[1]

auto[0]

45

1

T1

2

T148

1

T80

1

clear_none

auto[0]

auto[0]

auto[0]

1367

1

T2

1

T14

1

T16

1

clear_none

auto[0]

auto[0]

auto[1]

131

1

T17

2

T38

4

T233

1

clear_none

auto[0]

auto[1]

auto[0]

145

1

T3

1

T19

2

T154

1

clear_none

auto[0]

auto[1]

auto[1]

26

1

T29

1

T156

1

T65

1

clear_none

auto[1]

auto[0]

auto[0]

128

1

T97

1

T155

2

T234

2

clear_none

auto[1]

auto[0]

auto[1]

48

1

T63

1

T80

2

T6

1

clear_none

auto[1]

auto[1]

auto[0]

28

1

T1

1

T15

1

T33

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T72

2

T306

1

T64

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1323	1			T14	1		T15	2		T16	2
clear_all	auto[1]	85	1			T50	7		T130	4		T142	2
clear_one[1]	auto[0]	722	1			T14	1		T16	1		T17	2
clear_one[1]	auto[1]	23	1			T165	2		T280	1		T290	5
clear_one[2]	auto[0]	720	1			T17	2		T38	1		T97	1
clear_one[2]	auto[1]	46	1			T97	1		T50	4		T130	4
clear_one[3]	auto[0]	653	1			T1	2		T14	1		T15	1
clear_one[3]	auto[1]	22	1			T165	2		T265	2		T306	1
clear_none	auto[0]	1826	1			T1	1		T2	1		T3	1
clear_none	auto[1]	73	1			T97	1		T130	2		T142	3