Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11596

1

T1

10

T3

6

T4

1

auto[Attestation]

7846

1

T1

9

T3

9

T4

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2880	1			T1	2		T4	1		T15	2
auto[Aes]	3499	1			T1	3		T3	2		T15	3
auto[Kmac]	3530	1			T1	4		T3	5		T15	4
auto[Otbn]	3466	1			T1	5		T3	2		T15	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7847	1			T1	8		T2	2		T3	4
auto[OpGenId]	6067	1			T1	5		T3	6		T4	1
auto[OpGenSwOut]	6182	1			T1	6		T3	3		T15	5
auto[OpGenHwOut]	7193	1			T1	8		T3	6		T4	1
auto[OpDisable]	154	1			T54	1		T55	1		T56	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11033

1

T1

14

T2

1

T3

18

auto[OpDoneFail]

16410

1

T1

13

T2

1

T3

1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6474	1			T1	1		T2	1		T3	1
auto[StInit]	3956	1			T1	2		T2	1		T3	2
auto[StCreatorRootKey]	3396	1			T1	4		T3	2		T15	2
auto[StOwnerIntKey]	2880	1			T1	6		T3	6		T15	2
auto[StOwnerKey]	2522	1			T1	4		T3	8		T15	2
auto[StDisabled]	8215	1			T1	10		T15	7		T16	11

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	333	1			T15	1		T122	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T222	1		T62	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	93	1			T142	2		T67	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T1	1		T130	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T29	1		T80	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	235	1			T15	1		T97	1		T149	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	337	1			T15	1		T97	1		T122	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T224	1		T69	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T39	1		T97	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T67	1		T152	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T222	1		T130	1		T225	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	221	1			T1	1		T97	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	326	1			T97	1		T122	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	89	1			T67	1		T47	1		T226	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T54	1		T130	1		T142	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T1	1		T42	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	78	1			T3	2		T16	1		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	225	1			T15	1		T39	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	363	1			T39	2		T97	2		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	113	1			T97	1		T55	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T222	1		T130	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T1	1		T227	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T39	1		T42	1		T142	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	243	1			T97	2		T50	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T80	3		T6	2		T156	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T39	1		T143	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	91	1			T50	1		T42	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T16	1		T222	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T50	1		T130	1		T148	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	234	1			T50	1		T142	1		T148	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T80	3		T138	1		T65	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T50	1		T223	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T222	1		T130	1		T148	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	63	1			T3	1		T143	1		T224	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T42	1		T222	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	216	1			T33	1		T97	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T5	1		T80	6		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T16	1		T122	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T62	1		T29	2		T148	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T67	1		T228	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	73	1			T97	1		T130	1		T228	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	232	1			T1	1		T15	1		T39	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T5	2		T80	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T222	1		T130	1		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T1	1		T67	2		T224	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T29	1		T67	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T224	1		T5	1		T229	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	204	1			T148	1		T227	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	275	1			T50	2		T41	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T148	1		T152	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T223	1		T29	1		T156	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	81	1			T142	1		T148	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T50	1		T142	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T16	1		T130	2		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T15	1		T97	1		T50	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T29	1		T151	1		T230	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	133	1			T15	1		T16	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T155	1		T230	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T3	1		T155	1		T150	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	285	1			T1	1		T16	1		T155	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	512	1			T19	18		T50	1		T51	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	135	1			T19	1		T50	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	116	1			T50	1		T154	1		T232	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	113	1			T97	2		T154	1		T232	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T1	1		T51	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	282	1			T19	4		T33	1		T50	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	411	1			T15	1		T97	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	159	1			T1	1		T17	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T17	1		T38	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	117	1			T17	1		T38	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	81	1			T17	1		T233	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	311	1			T15	1		T16	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	74	1			T80	2		T156	1		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	94	1			T4	1		T33	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T222	1		T224	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T1	1		T16	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T33	1		T29	1		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	175	1			T16	1		T222	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T80	2		T156	3		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	119	1			T155	1		T234	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	128	1			T54	1		T222	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	107	1			T16	1		T33	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	89	1			T1	1		T33	3		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	274	1			T97	1		T155	1		T234	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T156	3		T93	2		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	134	1			T97	1		T154	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T19	1		T33	2		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T1	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	94	1			T3	2		T15	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	265	1			T97	1		T154	4		T51	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	50	1			T5	1		T80	1		T156	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T42	1		T56	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T235	1		T56	1		T228	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T235	1		T223	2		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	78	1			T1	1		T3	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	280	1			T1	1		T17	2		T38	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T1	1		T130	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	694	1			T15	2		T97	1		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	203	1			T39	1		T97	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	683	1			T1	1		T15	1		T97	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	228	1			T1	1		T3	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	656	1			T15	1		T39	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	221	1			T1	1		T39	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	738	1			T39	2		T97	5		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	208	1			T50	2		T42	1		T222	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	442	1			T16	1		T39	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	228	1			T3	1		T42	1		T222	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	423	1			T33	1		T97	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	210	1			T97	1		T62	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	438	1			T1	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	203	1			T67	3		T224	2		T228	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	400	1			T1	1		T222	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	200	1			T50	1		T223	1		T142	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	587	1			T16	1		T50	2		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	294	1			T3	1		T15	1		T97	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	894	1			T1	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	292	1			T1	1		T97	2		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	946	1			T19	23		T33	1		T50	6
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T17	3		T38	2		T233	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	903	1			T1	1		T15	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	177	1			T1	1		T16	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	365	1			T4	1		T16	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	310	1			T1	1		T33	4		T234	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	464	1			T16	1		T97	1		T155	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	283	1			T1	1		T3	3		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T97	2		T154	5		T51	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T3	2		T38	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	455	1			T1	2		T16	1		T17	2