Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33631

1

T1

32

T2

26

T3

21

auto[1]

291

1

T97

13

T50

10

T130

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33641	1			T1	32		T2	26		T3	21
auto[134217728:268435455]	5	1			T130	1		T406	1		T291	1
auto[268435456:402653183]	5	1			T97	1		T312	1		T259	1
auto[402653184:536870911]	10	1			T406	1		T312	1		T259	1
auto[536870912:671088639]	9	1			T50	1		T130	1		T291	2
auto[671088640:805306367]	9	1			T97	2		T50	1		T157	1
auto[805306368:939524095]	7	1			T50	1		T265	1		T365	1
auto[939524096:1073741823]	9	1			T97	1		T50	1		T165	1
auto[1073741824:1207959551]	8	1			T406	2		T290	1		T291	1
auto[1207959552:1342177279]	7	1			T142	1		T165	1		T406	1
auto[1342177280:1476395007]	8	1			T290	1		T291	1		T312	1
auto[1476395008:1610612735]	8	1			T130	2		T257	1		T312	1
auto[1610612736:1744830463]	8	1			T97	1		T280	1		T303	1
auto[1744830464:1879048191]	7	1			T265	1		T280	1		T389	1
auto[1879048192:2013265919]	11	1			T97	2		T50	1		T142	1
auto[2013265920:2147483647]	15	1			T130	1		T265	3		T297	1
auto[2147483648:2281701375]	12	1			T50	1		T290	1		T258	1
auto[2281701376:2415919103]	10	1			T130	1		T290	1		T257	1
auto[2415919104:2550136831]	4	1			T389	1		T391	1		T407	1
auto[2550136832:2684354559]	9	1			T50	2		T265	1		T408	1
auto[2684354560:2818572287]	14	1			T265	1		T280	1		T406	2
auto[2818572288:2952790015]	11	1			T265	2		T306	1		T257	1
auto[2952790016:3087007743]	9	1			T97	2		T130	1		T406	2
auto[3087007744:3221225471]	7	1			T130	1		T142	1		T290	1
auto[3221225472:3355443199]	8	1			T50	1		T265	2		T406	1
auto[3355443200:3489660927]	10	1			T97	1		T130	1		T265	2
auto[3489660928:3623878655]	8	1			T97	1		T165	1		T365	1
auto[3623878656:3758096383]	13	1			T50	1		T130	1		T265	2
auto[3758096384:3892314111]	11	1			T307	1		T291	2		T409	1
auto[3892314112:4026531839]	12	1			T97	1		T165	1		T157	1
auto[4026531840:4160749567]	11	1			T410	2		T411	1		T407	1
auto[4160749568:4294967295]	6	1			T406	1		T290	1		T412	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33631	1			T1	32		T2	26		T3	21
auto[0:134217727]	auto[1]	10	1			T97	1		T280	2		T307	1
auto[134217728:268435455]	auto[1]	5	1			T130	1		T406	1		T291	1
auto[268435456:402653183]	auto[1]	5	1			T97	1		T312	1		T259	1
auto[402653184:536870911]	auto[1]	10	1			T406	1		T312	1		T259	1
auto[536870912:671088639]	auto[1]	9	1			T50	1		T130	1		T291	2
auto[671088640:805306367]	auto[1]	9	1			T97	2		T50	1		T157	1
auto[805306368:939524095]	auto[1]	7	1			T50	1		T265	1		T365	1
auto[939524096:1073741823]	auto[1]	9	1			T97	1		T50	1		T165	1
auto[1073741824:1207959551]	auto[1]	8	1			T406	2		T290	1		T291	1
auto[1207959552:1342177279]	auto[1]	7	1			T142	1		T165	1		T406	1
auto[1342177280:1476395007]	auto[1]	8	1			T290	1		T291	1		T312	1
auto[1476395008:1610612735]	auto[1]	8	1			T130	2		T257	1		T312	1
auto[1610612736:1744830463]	auto[1]	8	1			T97	1		T280	1		T303	1
auto[1744830464:1879048191]	auto[1]	7	1			T265	1		T280	1		T389	1
auto[1879048192:2013265919]	auto[1]	11	1			T97	2		T50	1		T142	1
auto[2013265920:2147483647]	auto[1]	15	1			T130	1		T265	3		T297	1
auto[2147483648:2281701375]	auto[1]	12	1			T50	1		T290	1		T258	1
auto[2281701376:2415919103]	auto[1]	10	1			T130	1		T290	1		T257	1
auto[2415919104:2550136831]	auto[1]	4	1			T389	1		T391	1		T407	1
auto[2550136832:2684354559]	auto[1]	9	1			T50	2		T265	1		T408	1
auto[2684354560:2818572287]	auto[1]	14	1			T265	1		T280	1		T406	2
auto[2818572288:2952790015]	auto[1]	11	1			T265	2		T306	1		T257	1
auto[2952790016:3087007743]	auto[1]	9	1			T97	2		T130	1		T406	2
auto[3087007744:3221225471]	auto[1]	7	1			T130	1		T142	1		T290	1
auto[3221225472:3355443199]	auto[1]	8	1			T50	1		T265	2		T406	1
auto[3355443200:3489660927]	auto[1]	10	1			T97	1		T130	1		T265	2
auto[3489660928:3623878655]	auto[1]	8	1			T97	1		T165	1		T365	1
auto[3623878656:3758096383]	auto[1]	13	1			T50	1		T130	1		T265	2
auto[3758096384:3892314111]	auto[1]	11	1			T307	1		T291	2		T409	1
auto[3892314112:4026531839]	auto[1]	12	1			T97	1		T165	1		T157	1
auto[4026531840:4160749567]	auto[1]	11	1			T410	2		T411	1		T407	1
auto[4160749568:4294967295]	auto[1]	6	1			T406	1		T290	1		T412	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3098

1

T1

5

T2

1

T3

3

auto[1]

263

1

T97

5

T50

11

T130

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T97	2		T142	1		T152	1
auto[134217728:268435455]	112	1			T4	1		T16	1		T97	1
auto[268435456:402653183]	98	1			T1	1		T16	1		T29	1
auto[402653184:536870911]	110	1			T50	1		T222	1		T142	2
auto[536870912:671088639]	82	1			T130	2		T142	1		T29	1
auto[671088640:805306367]	93	1			T50	1		T223	1		T72	1
auto[805306368:939524095]	127	1			T16	1		T50	1		T41	1
auto[939524096:1073741823]	116	1			T33	1		T130	1		T142	1
auto[1073741824:1207959551]	120	1			T41	1		T54	1		T130	2
auto[1207959552:1342177279]	107	1			T1	1		T50	1		T29	1
auto[1342177280:1476395007]	91	1			T50	1		T142	1		T29	1
auto[1476395008:1610612735]	100	1			T41	1		T222	2		T55	1
auto[1610612736:1744830463]	107	1			T3	1		T50	1		T5	1
auto[1744830464:1879048191]	100	1			T97	1		T54	1		T222	1
auto[1879048192:2013265919]	103	1			T41	1		T142	1		T63	1
auto[2013265920:2147483647]	90	1			T97	2		T223	2		T142	1
auto[2147483648:2281701375]	113	1			T3	1		T14	1		T97	1
auto[2281701376:2415919103]	126	1			T2	1		T130	1		T142	1
auto[2415919104:2550136831]	87	1			T97	1		T50	1		T142	1
auto[2550136832:2684354559]	126	1			T14	1		T33	1		T97	1
auto[2684354560:2818572287]	101	1			T1	1		T50	1		T130	1
auto[2818572288:2952790015]	102	1			T16	1		T50	2		T148	1
auto[2952790016:3087007743]	115	1			T33	1		T130	1		T80	1
auto[3087007744:3221225471]	99	1			T50	1		T222	1		T130	1
auto[3221225472:3355443199]	103	1			T3	1		T50	1		T222	1
auto[3355443200:3489660927]	94	1			T50	1		T63	1		T5	1
auto[3489660928:3623878655]	122	1			T50	1		T56	1		T142	3
auto[3623878656:3758096383]	107	1			T50	1		T142	1		T5	1
auto[3758096384:3892314111]	105	1			T29	2		T47	1		T80	1
auto[3892314112:4026531839]	90	1			T1	1		T97	1		T55	1
auto[4026531840:4160749567]	97	1			T1	1		T50	1		T54	1
auto[4160749568:4294967295]	104	1			T97	1		T41	3		T142	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[3892314112:4026531839]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	108	1			T97	1		T152	1		T47	1
auto[0:134217727]	auto[1]	6	1			T97	1		T142	1		T290	1
auto[134217728:268435455]	auto[0]	102	1			T4	1		T16	1		T60	1
auto[134217728:268435455]	auto[1]	10	1			T97	1		T157	1		T290	1
auto[268435456:402653183]	auto[0]	89	1			T1	1		T16	1		T29	1
auto[268435456:402653183]	auto[1]	9	1			T280	1		T413	1		T259	2
auto[402653184:536870911]	auto[0]	98	1			T222	1		T67	1		T152	1
auto[402653184:536870911]	auto[1]	12	1			T50	1		T142	2		T291	1
auto[536870912:671088639]	auto[0]	70	1			T29	1		T67	1		T229	1
auto[536870912:671088639]	auto[1]	12	1			T130	2		T142	1		T280	1
auto[671088640:805306367]	auto[0]	84	1			T223	1		T72	1		T93	1
auto[671088640:805306367]	auto[1]	9	1			T50	1		T365	1		T306	1
auto[805306368:939524095]	auto[0]	117	1			T16	1		T41	1		T29	2
auto[805306368:939524095]	auto[1]	10	1			T50	1		T265	1		T406	1
auto[939524096:1073741823]	auto[0]	109	1			T33	1		T5	1		T80	1
auto[939524096:1073741823]	auto[1]	7	1			T130	1		T142	1		T290	2
auto[1073741824:1207959551]	auto[0]	114	1			T41	1		T54	1		T130	1
auto[1073741824:1207959551]	auto[1]	6	1			T130	1		T280	1		T406	1
auto[1207959552:1342177279]	auto[0]	100	1			T1	1		T50	1		T29	1
auto[1207959552:1342177279]	auto[1]	7	1			T157	1		T280	1		T406	1
auto[1342177280:1476395007]	auto[0]	83	1			T50	1		T29	1		T228	1
auto[1342177280:1476395007]	auto[1]	8	1			T142	1		T297	1		T257	1
auto[1476395008:1610612735]	auto[0]	94	1			T41	1		T222	2		T55	1
auto[1476395008:1610612735]	auto[1]	6	1			T142	2		T257	1		T291	1
auto[1610612736:1744830463]	auto[0]	99	1			T3	1		T5	1		T262	1
auto[1610612736:1744830463]	auto[1]	8	1			T50	1		T265	1		T406	1
auto[1744830464:1879048191]	auto[0]	90	1			T97	1		T54	1		T222	1
auto[1744830464:1879048191]	auto[1]	10	1			T130	1		T265	2		T306	1
auto[1879048192:2013265919]	auto[0]	96	1			T41	1		T63	1		T148	1
auto[1879048192:2013265919]	auto[1]	7	1			T142	1		T280	1		T406	1
auto[2013265920:2147483647]	auto[0]	83	1			T97	1		T223	2		T67	1
auto[2013265920:2147483647]	auto[1]	7	1			T97	1		T142	1		T290	2
auto[2147483648:2281701375]	auto[0]	104	1			T3	1		T14	1		T97	1
auto[2147483648:2281701375]	auto[1]	9	1			T165	1		T265	1		T290	1
auto[2281701376:2415919103]	auto[0]	112	1			T2	1		T29	1		T60	1
auto[2281701376:2415919103]	auto[1]	14	1			T130	1		T142	1		T165	1
auto[2415919104:2550136831]	auto[0]	81	1			T97	1		T142	1		T293	1
auto[2415919104:2550136831]	auto[1]	6	1			T50	1		T265	1		T409	2
auto[2550136832:2684354559]	auto[0]	121	1			T14	1		T33	1		T62	1
auto[2550136832:2684354559]	auto[1]	5	1			T97	1		T291	1		T410	2
auto[2684354560:2818572287]	auto[0]	92	1			T1	1		T223	1		T63	1
auto[2684354560:2818572287]	auto[1]	9	1			T50	1		T130	1		T165	1
auto[2818572288:2952790015]	auto[0]	91	1			T16	1		T148	1		T224	1
auto[2818572288:2952790015]	auto[1]	11	1			T50	2		T265	1		T406	1
auto[2952790016:3087007743]	auto[0]	105	1			T33	1		T130	1		T80	1
auto[2952790016:3087007743]	auto[1]	10	1			T265	1		T258	1		T413	1
auto[3087007744:3221225471]	auto[0]	95	1			T50	1		T222	1		T130	1
auto[3087007744:3221225471]	auto[1]	4	1			T142	1		T165	1		T410	2
auto[3221225472:3355443199]	auto[0]	97	1			T3	1		T50	1		T222	1
auto[3221225472:3355443199]	auto[1]	6	1			T280	1		T291	1		T392	1
auto[3355443200:3489660927]	auto[0]	89	1			T63	1		T5	1		T229	1
auto[3355443200:3489660927]	auto[1]	5	1			T50	1		T392	1		T414	1
auto[3489660928:3623878655]	auto[0]	112	1			T50	1		T56	1		T142	1
auto[3489660928:3623878655]	auto[1]	10	1			T142	2		T165	1		T291	1
auto[3623878656:3758096383]	auto[0]	98	1			T142	1		T5	1		T80	1
auto[3623878656:3758096383]	auto[1]	9	1			T50	1		T365	1		T280	1
auto[3758096384:3892314111]	auto[0]	99	1			T29	2		T47	1		T80	1
auto[3758096384:3892314111]	auto[1]	6	1			T165	1		T365	1		T406	1
auto[3892314112:4026531839]	auto[0]	90	1			T1	1		T97	1		T55	1
auto[4026531840:4160749567]	auto[0]	83	1			T1	1		T54	1		T29	1
auto[4026531840:4160749567]	auto[1]	14	1			T50	1		T130	1		T142	1
auto[4160749568:4294967295]	auto[0]	93	1			T41	3		T67	1		T53	1
auto[4160749568:4294967295]	auto[1]	11	1			T97	1		T142	1		T165	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1625

1

T1

3

T3

1

T16

2

auto[1]

1895

1

T1

2

T2

1

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	132	1			T55	1		T29	2		T148	1
auto[134217728:268435455]	126	1			T16	1		T29	1		T67	1
auto[268435456:402653183]	123	1			T1	1		T29	2		T60	1
auto[402653184:536870911]	107	1			T223	1		T29	1		T53	1
auto[536870912:671088639]	115	1			T33	1		T47	2		T5	1
auto[671088640:805306367]	113	1			T16	1		T97	1		T54	1
auto[805306368:939524095]	98	1			T60	1		T52	1		T152	1
auto[939524096:1073741823]	103	1			T152	1		T68	1		T80	1
auto[1073741824:1207959551]	106	1			T50	1		T114	1		T63	1
auto[1207959552:1342177279]	110	1			T14	1		T63	2		T29	1
auto[1342177280:1476395007]	96	1			T1	1		T222	1		T57	1
auto[1476395008:1610612735]	110	1			T50	1		T114	1		T55	1
auto[1610612736:1744830463]	113	1			T3	1		T223	1		T29	1
auto[1744830464:1879048191]	121	1			T97	1		T222	1		T60	1
auto[1879048192:2013265919]	101	1			T33	1		T41	1		T130	1
auto[2013265920:2147483647]	103	1			T1	1		T3	1		T14	1
auto[2147483648:2281701375]	101	1			T16	1		T222	1		T223	1
auto[2281701376:2415919103]	120	1			T1	1		T41	1		T114	1
auto[2415919104:2550136831]	107	1			T54	1		T60	1		T67	1
auto[2550136832:2684354559]	117	1			T222	1		T62	1		T67	2
auto[2684354560:2818572287]	85	1			T33	1		T41	1		T114	1
auto[2818572288:2952790015]	125	1			T4	2		T33	1		T67	2
auto[2952790016:3087007743]	77	1			T16	1		T97	1		T67	1
auto[3087007744:3221225471]	101	1			T97	1		T50	2		T29	1
auto[3221225472:3355443199]	104	1			T2	1		T222	1		T148	1
auto[3355443200:3489660927]	137	1			T47	1		T5	2		T80	2
auto[3489660928:3623878655]	128	1			T3	1		T97	1		T142	1
auto[3623878656:3758096383]	103	1			T97	1		T41	2		T52	1
auto[3758096384:3892314111]	107	1			T67	1		T47	1		T5	1
auto[3892314112:4026531839]	111	1			T1	1		T50	1		T41	1
auto[4026531840:4160749567]	105	1			T222	1		T62	1		T142	2
auto[4160749568:4294967295]	115	1			T41	1		T223	1		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T29	1		T148	1		T228	1
auto[0:134217727]	auto[1]	72	1			T55	1		T29	1		T80	1
auto[134217728:268435455]	auto[0]	53	1			T16	1		T29	1		T67	1
auto[134217728:268435455]	auto[1]	73	1			T229	1		T293	1		T156	2
auto[268435456:402653183]	auto[0]	55	1			T1	1		T29	1		T6	2
auto[268435456:402653183]	auto[1]	68	1			T29	1		T60	1		T228	1
auto[402653184:536870911]	auto[0]	46	1			T53	1		T80	1		T354	1
auto[402653184:536870911]	auto[1]	61	1			T223	1		T29	1		T68	1
auto[536870912:671088639]	auto[0]	48	1			T47	1		T5	1		T6	2
auto[536870912:671088639]	auto[1]	67	1			T33	1		T47	1		T293	1
auto[671088640:805306367]	auto[0]	48	1			T16	1		T54	1		T60	1
auto[671088640:805306367]	auto[1]	65	1			T97	1		T29	1		T148	1
auto[805306368:939524095]	auto[0]	48	1			T60	1		T52	1		T152	1
auto[805306368:939524095]	auto[1]	50	1			T228	1		T6	1		T103	1
auto[939524096:1073741823]	auto[0]	43	1			T152	1		T80	1		T265	1
auto[939524096:1073741823]	auto[1]	60	1			T68	1		T30	1		T213	1
auto[1073741824:1207959551]	auto[0]	55	1			T114	1		T63	1		T29	1
auto[1073741824:1207959551]	auto[1]	51	1			T50	1		T29	2		T68	1
auto[1207959552:1342177279]	auto[0]	49	1			T29	1		T80	1		T6	3
auto[1207959552:1342177279]	auto[1]	61	1			T14	1		T63	2		T148	1
auto[1342177280:1476395007]	auto[0]	39	1			T1	1		T57	1		T5	1
auto[1342177280:1476395007]	auto[1]	57	1			T222	1		T80	1		T6	2
auto[1476395008:1610612735]	auto[0]	46	1			T50	1		T114	1		T30	1
auto[1476395008:1610612735]	auto[1]	64	1			T55	1		T29	2		T68	1
auto[1610612736:1744830463]	auto[0]	63	1			T3	1		T152	1		T6	1
auto[1610612736:1744830463]	auto[1]	50	1			T223	1		T29	1		T67	1
auto[1744830464:1879048191]	auto[0]	43	1			T60	1		T228	1		T6	1
auto[1744830464:1879048191]	auto[1]	78	1			T97	1		T222	1		T5	1
auto[1879048192:2013265919]	auto[0]	50	1			T41	1		T5	1		T156	1
auto[1879048192:2013265919]	auto[1]	51	1			T33	1		T130	1		T63	1
auto[2013265920:2147483647]	auto[0]	47	1			T1	1		T114	1		T67	1
auto[2013265920:2147483647]	auto[1]	56	1			T3	1		T14	1		T55	1
auto[2147483648:2281701375]	auto[0]	39	1			T222	1		T223	1		T5	1
auto[2147483648:2281701375]	auto[1]	62	1			T16	1		T6	1		T72	1
auto[2281701376:2415919103]	auto[0]	58	1			T41	1		T114	1		T130	1
auto[2281701376:2415919103]	auto[1]	62	1			T1	1		T56	1		T142	1
auto[2415919104:2550136831]	auto[0]	51	1			T54	1		T60	1		T67	1
auto[2415919104:2550136831]	auto[1]	56	1			T152	1		T218	1		T201	1
auto[2550136832:2684354559]	auto[0]	54	1			T222	1		T67	1		T5	1
auto[2550136832:2684354559]	auto[1]	63	1			T62	1		T67	1		T5	2
auto[2684354560:2818572287]	auto[0]	38	1			T41	1		T6	1		T266	1
auto[2684354560:2818572287]	auto[1]	47	1			T33	1		T114	1		T156	2
auto[2818572288:2952790015]	auto[0]	61	1			T67	1		T293	1		T6	2
auto[2818572288:2952790015]	auto[1]	64	1			T4	2		T33	1		T67	1
auto[2952790016:3087007743]	auto[0]	31	1			T97	1		T67	1		T5	1
auto[2952790016:3087007743]	auto[1]	46	1			T16	1		T152	1		T5	1
auto[3087007744:3221225471]	auto[0]	52	1			T50	1		T29	1		T152	1
auto[3087007744:3221225471]	auto[1]	49	1			T97	1		T50	1		T5	1
auto[3221225472:3355443199]	auto[0]	49	1			T53	1		T307	1		T77	1
auto[3221225472:3355443199]	auto[1]	55	1			T2	1		T222	1		T148	1
auto[3355443200:3489660927]	auto[0]	68	1			T47	1		T5	1		T6	2
auto[3355443200:3489660927]	auto[1]	69	1			T5	1		T80	2		T156	1
auto[3489660928:3623878655]	auto[0]	64	1			T97	1		T57	1		T80	1
auto[3489660928:3623878655]	auto[1]	64	1			T3	1		T142	1		T80	1
auto[3623878656:3758096383]	auto[0]	66	1			T41	2		T52	1		T5	2
auto[3623878656:3758096383]	auto[1]	37	1			T97	1		T80	2		T229	1
auto[3758096384:3892314111]	auto[0]	58	1			T47	1		T156	1		T72	1
auto[3758096384:3892314111]	auto[1]	49	1			T67	1		T5	1		T213	1
auto[3892314112:4026531839]	auto[0]	44	1			T50	1		T41	1		T54	1
auto[3892314112:4026531839]	auto[1]	67	1			T1	1		T130	1		T60	1
auto[4026531840:4160749567]	auto[0]	45	1			T222	1		T62	1		T142	2
auto[4026531840:4160749567]	auto[1]	60	1			T68	1		T57	1		T5	1
auto[4160749568:4294967295]	auto[0]	54	1			T41	1		T80	1		T6	3
auto[4160749568:4294967295]	auto[1]	61	1			T223	1		T29	1		T224	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1613

1

T1

2

T3

1

T16

2

auto[1]

1906

1

T1

3

T2

1

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T1	1		T16	1		T41	1
auto[134217728:268435455]	114	1			T97	1		T41	1		T29	2
auto[268435456:402653183]	101	1			T1	1		T63	1		T148	1
auto[402653184:536870911]	97	1			T57	1		T5	1		T156	2
auto[536870912:671088639]	89	1			T1	1		T3	1		T222	1
auto[671088640:805306367]	99	1			T142	1		T29	1		T67	1
auto[805306368:939524095]	93	1			T62	1		T29	1		T152	1
auto[939524096:1073741823]	116	1			T114	1		T5	2		T229	1
auto[1073741824:1207959551]	110	1			T97	1		T142	1		T152	1
auto[1207959552:1342177279]	105	1			T2	1		T97	1		T222	1
auto[1342177280:1476395007]	123	1			T33	1		T54	1		T29	1
auto[1476395008:1610612735]	92	1			T97	1		T223	1		T29	2
auto[1610612736:1744830463]	104	1			T3	1		T14	1		T67	1
auto[1744830464:1879048191]	98	1			T41	2		T222	1		T130	1
auto[1879048192:2013265919]	116	1			T1	1		T4	1		T50	1
auto[2013265920:2147483647]	106	1			T50	1		T5	1		T80	1
auto[2147483648:2281701375]	92	1			T16	1		T29	1		T60	1
auto[2281701376:2415919103]	112	1			T41	1		T61	1		T224	1
auto[2415919104:2550136831]	122	1			T33	1		T54	1		T130	1
auto[2550136832:2684354559]	94	1			T222	1		T148	1		T80	1
auto[2684354560:2818572287]	119	1			T114	2		T130	1		T29	1
auto[2818572288:2952790015]	106	1			T1	1		T4	1		T56	1
auto[2952790016:3087007743]	129	1			T3	1		T33	1		T60	1
auto[3087007744:3221225471]	133	1			T97	1		T63	1		T29	1
auto[3221225472:3355443199]	108	1			T114	1		T54	1		T223	1
auto[3355443200:3489660927]	113	1			T29	1		T60	1		T152	1
auto[3489660928:3623878655]	121	1			T50	2		T29	1		T52	1
auto[3623878656:3758096383]	131	1			T16	1		T50	1		T41	1
auto[3758096384:3892314111]	108	1			T14	1		T16	1		T222	1
auto[3892314112:4026531839]	136	1			T97	1		T114	1		T222	1
auto[4026531840:4160749567]	98	1			T33	1		T55	1		T67	1
auto[4160749568:4294967295]	115	1			T55	1		T67	3		T68	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T16	1		T41	1		T142	1
auto[0:134217727]	auto[1]	61	1			T1	1		T55	1		T63	1
auto[134217728:268435455]	auto[0]	44	1			T41	1		T269	1		T120	2
auto[134217728:268435455]	auto[1]	70	1			T97	1		T29	2		T67	2
auto[268435456:402653183]	auto[0]	44	1			T6	1		T265	2		T156	1
auto[268435456:402653183]	auto[1]	57	1			T1	1		T63	1		T148	1
auto[402653184:536870911]	auto[0]	45	1			T57	1		T156	1		T117	1
auto[402653184:536870911]	auto[1]	52	1			T5	1		T156	1		T314	1
auto[536870912:671088639]	auto[0]	40	1			T1	1		T3	1		T222	1
auto[536870912:671088639]	auto[1]	49	1			T6	1		T156	1		T72	1
auto[671088640:805306367]	auto[0]	39	1			T29	1		T67	1		T93	1
auto[671088640:805306367]	auto[1]	60	1			T142	1		T93	1		T310	1
auto[805306368:939524095]	auto[0]	40	1			T62	1		T29	1		T152	1
auto[805306368:939524095]	auto[1]	53	1			T314	1		T118	1		T158	2
auto[939524096:1073741823]	auto[0]	52	1			T114	1		T265	1		T415	1
auto[939524096:1073741823]	auto[1]	64	1			T5	2		T229	1		T6	2
auto[1073741824:1207959551]	auto[0]	47	1			T97	1		T152	1		T57	1
auto[1073741824:1207959551]	auto[1]	63	1			T142	1		T68	1		T5	1
auto[1207959552:1342177279]	auto[0]	47	1			T5	1		T80	1		T354	1
auto[1207959552:1342177279]	auto[1]	58	1			T2	1		T97	1		T222	1
auto[1342177280:1476395007]	auto[0]	54	1			T54	1		T29	1		T68	1
auto[1342177280:1476395007]	auto[1]	69	1			T33	1		T5	1		T6	1
auto[1476395008:1610612735]	auto[0]	42	1			T223	1		T29	2		T6	1
auto[1476395008:1610612735]	auto[1]	50	1			T97	1		T148	1		T67	1
auto[1610612736:1744830463]	auto[0]	51	1			T67	1		T80	1		T6	2
auto[1610612736:1744830463]	auto[1]	53	1			T3	1		T14	1		T68	1
auto[1744830464:1879048191]	auto[0]	37	1			T41	2		T222	1		T67	1
auto[1744830464:1879048191]	auto[1]	61	1			T130	1		T223	1		T80	1
auto[1879048192:2013265919]	auto[0]	49	1			T41	1		T29	1		T5	1
auto[1879048192:2013265919]	auto[1]	67	1			T1	1		T4	1		T50	1
auto[2013265920:2147483647]	auto[0]	45	1			T50	1		T5	1		T213	1
auto[2013265920:2147483647]	auto[1]	61	1			T80	1		T229	1		T157	2
auto[2147483648:2281701375]	auto[0]	48	1			T60	1		T156	2		T314	1
auto[2147483648:2281701375]	auto[1]	44	1			T16	1		T29	1		T5	2
auto[2281701376:2415919103]	auto[0]	56	1			T41	1		T5	1		T229	1
auto[2281701376:2415919103]	auto[1]	56	1			T61	1		T224	1		T156	2
auto[2415919104:2550136831]	auto[0]	58	1			T54	1		T63	1		T60	1
auto[2415919104:2550136831]	auto[1]	64	1			T33	1		T130	1		T223	1
auto[2550136832:2684354559]	auto[0]	52	1			T148	1		T80	1		T6	1
auto[2550136832:2684354559]	auto[1]	42	1			T222	1		T293	1		T93	1
auto[2684354560:2818572287]	auto[0]	64	1			T114	2		T130	1		T6	1
auto[2684354560:2818572287]	auto[1]	55	1			T29	1		T60	1		T224	1
auto[2818572288:2952790015]	auto[0]	48	1			T1	1		T72	1		T93	1
auto[2818572288:2952790015]	auto[1]	58	1			T4	1		T56	1		T29	1
auto[2952790016:3087007743]	auto[0]	71	1			T60	1		T5	1		T80	2
auto[2952790016:3087007743]	auto[1]	58	1			T3	1		T33	1		T5	1
auto[3087007744:3221225471]	auto[0]	55	1			T47	1		T93	1		T219	1
auto[3087007744:3221225471]	auto[1]	78	1			T97	1		T63	1		T29	1
auto[3221225472:3355443199]	auto[0]	52	1			T114	1		T54	1		T29	1
auto[3221225472:3355443199]	auto[1]	56	1			T223	1		T67	1		T80	1
auto[3355443200:3489660927]	auto[0]	52	1			T29	1		T60	1		T152	1
auto[3355443200:3489660927]	auto[1]	61	1			T213	1		T262	2		T156	2
auto[3489660928:3623878655]	auto[0]	52	1			T50	1		T52	1		T6	2
auto[3489660928:3623878655]	auto[1]	69	1			T50	1		T29	1		T47	1
auto[3623878656:3758096383]	auto[0]	54	1			T50	1		T41	1		T142	1
auto[3623878656:3758096383]	auto[1]	77	1			T16	1		T224	1		T68	1
auto[3758096384:3892314111]	auto[0]	50	1			T16	1		T222	1		T6	1
auto[3758096384:3892314111]	auto[1]	58	1			T14	1		T67	1		T5	1
auto[3892314112:4026531839]	auto[0]	73	1			T97	1		T114	1		T52	1
auto[3892314112:4026531839]	auto[1]	63	1			T222	1		T62	1		T165	1
auto[4026531840:4160749567]	auto[0]	45	1			T47	1		T6	1		T265	1
auto[4026531840:4160749567]	auto[1]	53	1			T33	1		T55	1		T67	1
auto[4160749568:4294967295]	auto[0]	49	1			T67	1		T68	1		T57	1
auto[4160749568:4294967295]	auto[1]	66	1			T55	1		T67	2		T68	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T1

3

T3

1

T16

2

auto[1]

1917

1

T1

2

T2

1

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T14	1		T97	1		T29	1
auto[134217728:268435455]	100	1			T1	1		T55	1		T223	1
auto[268435456:402653183]	106	1			T29	1		T52	1		T5	1
auto[402653184:536870911]	115	1			T14	1		T47	1		T80	1
auto[536870912:671088639]	112	1			T54	1		T29	1		T53	1
auto[671088640:805306367]	104	1			T50	1		T41	1		T224	1
auto[805306368:939524095]	104	1			T63	1		T293	1		T72	1
auto[939524096:1073741823]	92	1			T41	1		T60	1		T5	1
auto[1073741824:1207959551]	118	1			T33	1		T97	2		T114	1
auto[1207959552:1342177279]	129	1			T114	1		T67	1		T68	1
auto[1342177280:1476395007]	113	1			T1	1		T152	1		T5	1
auto[1476395008:1610612735]	126	1			T222	1		T142	1		T29	2
auto[1610612736:1744830463]	107	1			T29	1		T148	1		T68	1
auto[1744830464:1879048191]	101	1			T33	1		T142	1		T63	1
auto[1879048192:2013265919]	97	1			T50	1		T63	1		T67	1
auto[2013265920:2147483647]	113	1			T97	1		T114	1		T67	1
auto[2147483648:2281701375]	103	1			T3	1		T33	1		T41	1
auto[2281701376:2415919103]	113	1			T16	1		T41	1		T55	1
auto[2415919104:2550136831]	116	1			T1	1		T33	1		T97	1
auto[2550136832:2684354559]	116	1			T41	1		T130	1		T80	3
auto[2684354560:2818572287]	99	1			T54	1		T222	1		T152	1
auto[2818572288:2952790015]	90	1			T97	1		T54	1		T29	1
auto[2952790016:3087007743]	104	1			T67	2		T52	1		T6	1
auto[3087007744:3221225471]	119	1			T16	1		T67	1		T61	1
auto[3221225472:3355443199]	119	1			T3	1		T16	1		T130	1
auto[3355443200:3489660927]	106	1			T222	1		T62	1		T29	1
auto[3489660928:3623878655]	106	1			T4	1		T16	1		T114	1
auto[3623878656:3758096383]	124	1			T1	1		T222	1		T29	2
auto[3758096384:3892314111]	117	1			T3	1		T50	2		T41	1
auto[3892314112:4026531839]	114	1			T1	1		T4	1		T50	1
auto[4026531840:4160749567]	114	1			T2	1		T29	1		T152	1
auto[4160749568:4294967295]	109	1			T114	1		T222	1		T29	1