Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3099

1

T1

5

T2

1

T3

3

auto[1]

267

1

T97

9

T50

13

T130

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T3	1		T50	1		T63	1
auto[134217728:268435455]	97	1			T97	1		T114	1		T29	1
auto[268435456:402653183]	108	1			T50	1		T55	1		T68	1
auto[402653184:536870911]	100	1			T1	1		T50	1		T41	1
auto[536870912:671088639]	93	1			T50	1		T130	1		T29	1
auto[671088640:805306367]	111	1			T97	1		T50	1		T67	1
auto[805306368:939524095]	99	1			T222	1		T55	1		T67	1
auto[939524096:1073741823]	98	1			T50	1		T142	1		T224	1
auto[1073741824:1207959551]	105	1			T3	1		T97	2		T222	1
auto[1207959552:1342177279]	108	1			T50	2		T222	1		T130	1
auto[1342177280:1476395007]	112	1			T16	1		T97	1		T148	1
auto[1476395008:1610612735]	118	1			T33	1		T97	2		T142	1
auto[1610612736:1744830463]	101	1			T50	1		T63	1		T67	1
auto[1744830464:1879048191]	97	1			T50	1		T41	1		T29	1
auto[1879048192:2013265919]	111	1			T97	1		T63	1		T29	2
auto[2013265920:2147483647]	110	1			T50	1		T222	1		T62	1
auto[2147483648:2281701375]	92	1			T97	1		T54	1		T130	1
auto[2281701376:2415919103]	113	1			T1	1		T33	1		T41	1
auto[2415919104:2550136831]	116	1			T1	2		T41	1		T223	1
auto[2550136832:2684354559]	89	1			T41	1		T29	1		T67	1
auto[2684354560:2818572287]	111	1			T1	1		T97	1		T223	1
auto[2818572288:2952790015]	123	1			T4	1		T97	1		T130	1
auto[2952790016:3087007743]	95	1			T50	1		T41	1		T29	1
auto[3087007744:3221225471]	117	1			T2	1		T16	1		T33	1
auto[3221225472:3355443199]	98	1			T50	1		T54	1		T56	1
auto[3355443200:3489660927]	107	1			T97	1		T142	1		T29	1
auto[3489660928:3623878655]	94	1			T16	1		T50	2		T57	2
auto[3623878656:3758096383]	107	1			T14	2		T97	1		T142	2
auto[3758096384:3892314111]	98	1			T3	1		T50	1		T222	1
auto[3892314112:4026531839]	106	1			T16	1		T41	1		T54	1
auto[4026531840:4160749567]	114	1			T50	1		T130	2		T29	1
auto[4160749568:4294967295]	106	1			T97	1		T222	1		T223	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	106	1			T3	1		T50	1		T63	1
auto[0:134217727]	auto[1]	6	1			T265	1		T259	1		T389	1
auto[134217728:268435455]	auto[0]	90	1			T114	1		T29	1		T6	1
auto[134217728:268435455]	auto[1]	7	1			T97	1		T165	1		T265	1
auto[268435456:402653183]	auto[0]	101	1			T50	1		T55	1		T68	1
auto[268435456:402653183]	auto[1]	7	1			T265	1		T280	1		T291	1
auto[402653184:536870911]	auto[0]	94	1			T1	1		T41	1		T29	1
auto[402653184:536870911]	auto[1]	6	1			T50	1		T165	1		T389	1
auto[536870912:671088639]	auto[0]	83	1			T50	1		T29	1		T6	3
auto[536870912:671088639]	auto[1]	10	1			T130	1		T280	2		T306	1
auto[671088640:805306367]	auto[0]	96	1			T67	1		T293	1		T6	1
auto[671088640:805306367]	auto[1]	15	1			T97	1		T50	1		T280	1
auto[805306368:939524095]	auto[0]	90	1			T222	1		T55	1		T67	1
auto[805306368:939524095]	auto[1]	9	1			T165	1		T257	1		T312	1
auto[939524096:1073741823]	auto[0]	89	1			T224	1		T228	1		T5	1
auto[939524096:1073741823]	auto[1]	9	1			T50	1		T142	1		T165	1
auto[1073741824:1207959551]	auto[0]	94	1			T3	1		T97	1		T222	1
auto[1073741824:1207959551]	auto[1]	11	1			T97	1		T406	1		T337	1
auto[1207959552:1342177279]	auto[0]	98	1			T222	1		T130	1		T29	2
auto[1207959552:1342177279]	auto[1]	10	1			T50	2		T142	1		T406	1
auto[1342177280:1476395007]	auto[0]	103	1			T16	1		T97	1		T148	1
auto[1342177280:1476395007]	auto[1]	9	1			T265	1		T389	2		T410	1
auto[1476395008:1610612735]	auto[0]	111	1			T33	1		T60	1		T228	1
auto[1476395008:1610612735]	auto[1]	7	1			T97	2		T142	1		T406	1
auto[1610612736:1744830463]	auto[0]	94	1			T50	1		T63	1		T67	1
auto[1610612736:1744830463]	auto[1]	7	1			T290	1		T291	1		T312	1
auto[1744830464:1879048191]	auto[0]	89	1			T41	1		T29	1		T80	2
auto[1744830464:1879048191]	auto[1]	8	1			T50	1		T165	1		T406	1
auto[1879048192:2013265919]	auto[0]	104	1			T97	1		T63	1		T29	2
auto[1879048192:2013265919]	auto[1]	7	1			T257	2		T291	1		T409	1
auto[2013265920:2147483647]	auto[0]	98	1			T222	1		T62	1		T223	1
auto[2013265920:2147483647]	auto[1]	12	1			T50	1		T142	1		T265	1
auto[2147483648:2281701375]	auto[0]	86	1			T97	1		T54	1		T67	1
auto[2147483648:2281701375]	auto[1]	6	1			T130	1		T142	1		T165	1
auto[2281701376:2415919103]	auto[0]	105	1			T1	1		T33	1		T41	1
auto[2281701376:2415919103]	auto[1]	8	1			T303	1		T411	1		T391	1
auto[2415919104:2550136831]	auto[0]	109	1			T1	2		T41	1		T223	1
auto[2415919104:2550136831]	auto[1]	7	1			T406	1		T408	1		T389	1
auto[2550136832:2684354559]	auto[0]	84	1			T41	1		T29	1		T67	1
auto[2550136832:2684354559]	auto[1]	5	1			T258	1		T259	1		T411	1
auto[2684354560:2818572287]	auto[0]	101	1			T1	1		T223	1		T5	1
auto[2684354560:2818572287]	auto[1]	10	1			T97	1		T165	1		T291	1
auto[2818572288:2952790015]	auto[0]	109	1			T4	1		T55	1		T29	1
auto[2818572288:2952790015]	auto[1]	14	1			T97	1		T130	1		T265	2
auto[2952790016:3087007743]	auto[0]	89	1			T41	1		T29	1		T60	1
auto[2952790016:3087007743]	auto[1]	6	1			T50	1		T290	1		T421	1
auto[3087007744:3221225471]	auto[0]	112	1			T2	1		T16	1		T33	1
auto[3087007744:3221225471]	auto[1]	5	1			T50	1		T312	1		T320	1
auto[3221225472:3355443199]	auto[0]	90	1			T54	1		T56	1		T142	1
auto[3221225472:3355443199]	auto[1]	8	1			T50	1		T265	1		T312	1
auto[3355443200:3489660927]	auto[0]	99	1			T97	1		T142	1		T29	1
auto[3355443200:3489660927]	auto[1]	8	1			T280	1		T290	1		T409	1
auto[3489660928:3623878655]	auto[0]	86	1			T16	1		T50	1		T57	2
auto[3489660928:3623878655]	auto[1]	8	1			T50	1		T265	1		T414	1
auto[3623878656:3758096383]	auto[0]	101	1			T14	2		T142	2		T80	1
auto[3623878656:3758096383]	auto[1]	6	1			T97	1		T280	1		T306	1
auto[3758096384:3892314111]	auto[0]	87	1			T3	1		T222	1		T80	1
auto[3758096384:3892314111]	auto[1]	11	1			T50	1		T130	1		T165	1
auto[3892314112:4026531839]	auto[0]	101	1			T16	1		T41	1		T54	1
auto[3892314112:4026531839]	auto[1]	5	1			T142	2		T320	1		T422	1
auto[4026531840:4160749567]	auto[0]	103	1			T130	1		T29	1		T53	1
auto[4026531840:4160749567]	auto[1]	11	1			T50	1		T130	1		T290	1
auto[4160749568:4294967295]	auto[0]	97	1			T222	1		T223	1		T80	2
auto[4160749568:4294967295]	auto[1]	9	1			T97	1		T157	1		T413	1