Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7287

1

T1

10

T2

6

T3

5

auto[1]

282

1

T97

5

T50

10

T130

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3012	1			T1	5		T2	3		T3	2
auto[134217728:268435455]	169	1			T3	1		T142	1		T61	1
auto[268435456:402653183]	144	1			T130	1		T142	1		T63	1
auto[402653184:536870911]	162	1			T16	1		T33	2		T41	1
auto[536870912:671088639]	146	1			T223	1		T63	1		T67	1
auto[671088640:805306367]	154	1			T16	1		T97	1		T142	1
auto[805306368:939524095]	152	1			T14	1		T50	1		T41	1
auto[939524096:1073741823]	143	1			T1	1		T3	1		T41	1
auto[1073741824:1207959551]	155	1			T222	1		T130	1		T148	1
auto[1207959552:1342177279]	144	1			T130	1		T142	1		T29	1
auto[1342177280:1476395007]	157	1			T16	1		T50	3		T54	1
auto[1476395008:1610612735]	152	1			T50	3		T54	1		T67	1
auto[1610612736:1744830463]	151	1			T97	2		T54	1		T222	1
auto[1744830464:1879048191]	161	1			T3	1		T14	1		T97	1
auto[1879048192:2013265919]	157	1			T16	4		T130	1		T55	1
auto[2013265920:2147483647]	122	1			T50	1		T41	1		T114	1
auto[2147483648:2281701375]	149	1			T1	1		T16	1		T130	1
auto[2281701376:2415919103]	131	1			T14	1		T16	1		T50	1
auto[2415919104:2550136831]	146	1			T2	1		T33	1		T41	3
auto[2550136832:2684354559]	126	1			T63	1		T29	1		T148	1
auto[2684354560:2818572287]	139	1			T16	1		T142	1		T29	1
auto[2818572288:2952790015]	134	1			T2	1		T14	1		T97	1
auto[2952790016:3087007743]	139	1			T97	2		T62	1		T223	1
auto[3087007744:3221225471]	156	1			T2	1		T4	1		T41	2
auto[3221225472:3355443199]	140	1			T1	1		T33	1		T97	1
auto[3355443200:3489660927]	146	1			T97	1		T50	1		T29	1
auto[3489660928:3623878655]	129	1			T1	1		T148	1		T152	2
auto[3623878656:3758096383]	133	1			T14	1		T97	1		T50	1
auto[3758096384:3892314111]	134	1			T1	1		T50	1		T130	1
auto[3892314112:4026531839]	174	1			T16	1		T41	1		T130	1
auto[4026531840:4160749567]	133	1			T50	1		T41	1		T223	1
auto[4160749568:4294967295]	179	1			T97	1		T130	2		T142	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3002	1			T1	5		T2	3		T3	2
auto[0:134217727]	auto[1]	10	1			T406	1		T258	1		T408	1
auto[134217728:268435455]	auto[0]	162	1			T3	1		T61	1		T47	1
auto[134217728:268435455]	auto[1]	7	1			T142	1		T280	1		T257	1
auto[268435456:402653183]	auto[0]	136	1			T63	1		T67	1		T152	2
auto[268435456:402653183]	auto[1]	8	1			T130	1		T142	1		T265	1
auto[402653184:536870911]	auto[0]	153	1			T16	1		T33	2		T41	1
auto[402653184:536870911]	auto[1]	9	1			T265	1		T291	2		T389	1
auto[536870912:671088639]	auto[0]	140	1			T223	1		T63	1		T67	1
auto[536870912:671088639]	auto[1]	6	1			T406	2		T414	1		T410	1
auto[671088640:805306367]	auto[0]	146	1			T16	1		T97	1		T29	3
auto[671088640:805306367]	auto[1]	8	1			T142	1		T165	1		T291	1
auto[805306368:939524095]	auto[0]	146	1			T14	1		T50	1		T41	1
auto[805306368:939524095]	auto[1]	6	1			T130	1		T297	1		T389	1
auto[939524096:1073741823]	auto[0]	133	1			T1	1		T3	1		T41	1
auto[939524096:1073741823]	auto[1]	10	1			T280	1		T306	1		T290	1
auto[1073741824:1207959551]	auto[0]	148	1			T222	1		T148	1		T5	1
auto[1073741824:1207959551]	auto[1]	7	1			T130	1		T337	1		T312	1
auto[1207959552:1342177279]	auto[0]	135	1			T130	1		T29	1		T152	1
auto[1207959552:1342177279]	auto[1]	9	1			T142	1		T265	1		T413	1
auto[1342177280:1476395007]	auto[0]	143	1			T16	1		T54	1		T29	1
auto[1342177280:1476395007]	auto[1]	14	1			T50	3		T142	1		T165	1
auto[1476395008:1610612735]	auto[0]	143	1			T50	2		T54	1		T67	1
auto[1476395008:1610612735]	auto[1]	9	1			T50	1		T389	1		T409	1
auto[1610612736:1744830463]	auto[0]	145	1			T97	1		T54	1		T222	1
auto[1610612736:1744830463]	auto[1]	6	1			T97	1		T165	1		T265	1
auto[1744830464:1879048191]	auto[0]	155	1			T3	1		T14	1		T97	1
auto[1744830464:1879048191]	auto[1]	6	1			T50	1		T142	2		T416	1
auto[1879048192:2013265919]	auto[0]	153	1			T16	4		T130	1		T55	1
auto[1879048192:2013265919]	auto[1]	4	1			T291	1		T312	1		T410	1
auto[2013265920:2147483647]	auto[0]	113	1			T41	1		T114	1		T55	1
auto[2013265920:2147483647]	auto[1]	9	1			T50	1		T130	1		T290	2
auto[2147483648:2281701375]	auto[0]	139	1			T1	1		T16	1		T29	3
auto[2147483648:2281701375]	auto[1]	10	1			T130	1		T307	1		T297	1
auto[2281701376:2415919103]	auto[0]	117	1			T14	1		T16	1		T67	1
auto[2281701376:2415919103]	auto[1]	14	1			T50	1		T165	1		T265	1
auto[2415919104:2550136831]	auto[0]	127	1			T2	1		T33	1		T41	3
auto[2415919104:2550136831]	auto[1]	19	1			T130	3		T142	1		T337	1
auto[2550136832:2684354559]	auto[0]	123	1			T63	1		T29	1		T148	1
auto[2550136832:2684354559]	auto[1]	3	1			T165	1		T412	1		T417	1
auto[2684354560:2818572287]	auto[0]	129	1			T16	1		T142	1		T29	1
auto[2684354560:2818572287]	auto[1]	10	1			T265	1		T365	1		T406	1
auto[2818572288:2952790015]	auto[0]	126	1			T2	1		T14	1		T97	1
auto[2818572288:2952790015]	auto[1]	8	1			T50	1		T265	1		T257	1
auto[2952790016:3087007743]	auto[0]	131	1			T97	1		T62	1		T223	1
auto[2952790016:3087007743]	auto[1]	8	1			T97	1		T157	1		T290	1
auto[3087007744:3221225471]	auto[0]	148	1			T2	1		T4	1		T41	2
auto[3087007744:3221225471]	auto[1]	8	1			T142	1		T265	2		T412	1
auto[3221225472:3355443199]	auto[0]	131	1			T1	1		T33	1		T97	1
auto[3221225472:3355443199]	auto[1]	9	1			T165	1		T280	1		T312	1
auto[3355443200:3489660927]	auto[0]	137	1			T29	1		T57	1		T80	1
auto[3355443200:3489660927]	auto[1]	9	1			T97	1		T50	1		T413	1
auto[3489660928:3623878655]	auto[0]	124	1			T1	1		T148	1		T152	2
auto[3489660928:3623878655]	auto[1]	5	1			T406	1		T312	1		T390	1
auto[3623878656:3758096383]	auto[0]	121	1			T14	1		T142	1		T5	2
auto[3623878656:3758096383]	auto[1]	12	1			T97	1		T50	1		T142	1
auto[3758096384:3892314111]	auto[0]	130	1			T1	1		T50	1		T29	2
auto[3758096384:3892314111]	auto[1]	4	1			T130	1		T142	1		T417	1
auto[3892314112:4026531839]	auto[0]	159	1			T16	1		T41	1		T223	1
auto[3892314112:4026531839]	auto[1]	15	1			T130	1		T142	1		T265	2
auto[4026531840:4160749567]	auto[0]	126	1			T50	1		T41	1		T223	1
auto[4026531840:4160749567]	auto[1]	7	1			T165	1		T406	1		T290	1
auto[4160749568:4294967295]	auto[0]	166	1			T130	1		T142	1		T29	1
auto[4160749568:4294967295]	auto[1]	13	1			T97	1		T130	1		T157	1