Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4696

1

T1

10

T2

2

T3

4

auto[1]

2344

1

T3

2

T14

2

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	206	1			T33	2		T222	2		T29	4
auto[134217728:268435455]	202	1			T97	2		T60	4		T67	2
auto[268435456:402653183]	228	1			T97	2		T50	2		T54	2
auto[402653184:536870911]	218	1			T1	2		T29	2		T148	2
auto[536870912:671088639]	262	1			T14	2		T63	2		T67	2
auto[671088640:805306367]	216	1			T33	2		T29	4		T68	4
auto[805306368:939524095]	194	1			T33	2		T54	2		T142	2
auto[939524096:1073741823]	204	1			T97	2		T41	2		T60	2
auto[1073741824:1207959551]	216	1			T41	2		T54	2		T130	2
auto[1207959552:1342177279]	222	1			T2	2		T16	4		T148	2
auto[1342177280:1476395007]	196	1			T29	2		T152	2		T5	2
auto[1476395008:1610612735]	260	1			T97	2		T41	2		T114	2
auto[1610612736:1744830463]	238	1			T114	2		T55	4		T56	2
auto[1744830464:1879048191]	192	1			T4	2		T152	4		T6	4
auto[1879048192:2013265919]	212	1			T3	2		T16	2		T223	2
auto[2013265920:2147483647]	244	1			T33	2		T97	2		T55	2
auto[2147483648:2281701375]	222	1			T41	4		T223	2		T29	4
auto[2281701376:2415919103]	236	1			T114	2		T142	2		T29	4
auto[2415919104:2550136831]	228	1			T29	2		T52	4		T61	2
auto[2550136832:2684354559]	228	1			T1	2		T16	2		T97	2
auto[2684354560:2818572287]	232	1			T41	2		T62	2		T228	2
auto[2818572288:2952790015]	196	1			T50	2		T63	4		T67	2
auto[2952790016:3087007743]	228	1			T41	2		T114	2		T47	2
auto[3087007744:3221225471]	222	1			T67	2		T152	2		T5	2
auto[3221225472:3355443199]	250	1			T222	2		T29	4		T5	4
auto[3355443200:3489660927]	230	1			T4	2		T53	2		T80	2
auto[3489660928:3623878655]	222	1			T142	2		T29	4		T148	2
auto[3623878656:3758096383]	218	1			T3	2		T222	2		T142	2
auto[3758096384:3892314111]	206	1			T1	2		T50	2		T148	2
auto[3892314112:4026531839]	206	1			T1	2		T50	2		T130	2
auto[4026531840:4160749567]	220	1			T14	2		T50	2		T114	2
auto[4160749568:4294967295]	186	1			T1	2		T3	2		T223	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	136	1			T33	2		T222	2		T29	2
auto[0:134217727]	auto[1]	70	1			T29	2		T156	2		T20	2
auto[134217728:268435455]	auto[0]	134	1			T60	2		T67	2		T6	2
auto[134217728:268435455]	auto[1]	68	1			T97	2		T60	2		T5	2
auto[268435456:402653183]	auto[0]	152	1			T97	2		T50	2		T54	2
auto[268435456:402653183]	auto[1]	76	1			T52	2		T47	2		T156	2
auto[402653184:536870911]	auto[0]	158	1			T1	2		T29	2		T148	2
auto[402653184:536870911]	auto[1]	60	1			T80	2		T6	2		T156	2
auto[536870912:671088639]	auto[0]	176	1			T14	2		T63	2		T6	2
auto[536870912:671088639]	auto[1]	86	1			T67	2		T152	2		T269	2
auto[671088640:805306367]	auto[0]	146	1			T33	2		T29	4		T68	4
auto[671088640:805306367]	auto[1]	70	1			T80	2		T103	2		T280	2
auto[805306368:939524095]	auto[0]	122	1			T33	2		T54	2		T57	2
auto[805306368:939524095]	auto[1]	72	1			T142	2		T47	2		T5	2
auto[939524096:1073741823]	auto[0]	140	1			T97	2		T60	2		T6	2
auto[939524096:1073741823]	auto[1]	64	1			T41	2		T152	2		T73	2
auto[1073741824:1207959551]	auto[0]	138	1			T54	2		T130	2		T63	2
auto[1073741824:1207959551]	auto[1]	78	1			T41	2		T5	4		T80	4
auto[1207959552:1342177279]	auto[0]	156	1			T2	2		T16	2		T148	2
auto[1207959552:1342177279]	auto[1]	66	1			T16	2		T34	2		T138	4
auto[1342177280:1476395007]	auto[0]	130	1			T5	2		T80	2		T293	2
auto[1342177280:1476395007]	auto[1]	66	1			T29	2		T152	2		T72	2
auto[1476395008:1610612735]	auto[0]	158	1			T97	2		T41	2		T222	4
auto[1476395008:1610612735]	auto[1]	102	1			T114	2		T62	2		T6	2
auto[1610612736:1744830463]	auto[0]	164	1			T114	2		T55	2		T60	2
auto[1610612736:1744830463]	auto[1]	74	1			T55	2		T56	2		T156	2
auto[1744830464:1879048191]	auto[0]	150	1			T6	4		T94	2		T73	2
auto[1744830464:1879048191]	auto[1]	42	1			T4	2		T152	4		T310	2
auto[1879048192:2013265919]	auto[0]	144	1			T223	2		T67	2		T5	2
auto[1879048192:2013265919]	auto[1]	68	1			T3	2		T16	2		T73	2
auto[2013265920:2147483647]	auto[0]	174	1			T33	2		T97	2		T29	2
auto[2013265920:2147483647]	auto[1]	70	1			T55	2		T6	2		T156	2
auto[2147483648:2281701375]	auto[0]	146	1			T41	2		T223	2		T29	2
auto[2147483648:2281701375]	auto[1]	76	1			T41	2		T29	2		T354	2
auto[2281701376:2415919103]	auto[0]	170	1			T142	2		T29	2		T5	2
auto[2281701376:2415919103]	auto[1]	66	1			T114	2		T29	2		T224	2
auto[2415919104:2550136831]	auto[0]	140	1			T6	2		T354	2		T64	2
auto[2415919104:2550136831]	auto[1]	88	1			T29	2		T52	4		T61	2
auto[2550136832:2684354559]	auto[0]	144	1			T1	2		T97	2		T228	2
auto[2550136832:2684354559]	auto[1]	84	1			T16	2		T29	2		T67	2
auto[2684354560:2818572287]	auto[0]	164	1			T41	2		T62	2		T228	2
auto[2684354560:2818572287]	auto[1]	68	1			T80	2		T262	2		T156	2
auto[2818572288:2952790015]	auto[0]	130	1			T50	2		T63	4		T68	2
auto[2818572288:2952790015]	auto[1]	66	1			T67	2		T224	2		T80	2
auto[2952790016:3087007743]	auto[0]	134	1			T41	2		T47	2		T229	2
auto[2952790016:3087007743]	auto[1]	94	1			T114	2		T5	2		T156	4
auto[3087007744:3221225471]	auto[0]	136	1			T80	2		T229	2		T6	2
auto[3087007744:3221225471]	auto[1]	86	1			T67	2		T152	2		T5	2
auto[3221225472:3355443199]	auto[0]	164	1			T5	2		T80	2		T293	2
auto[3221225472:3355443199]	auto[1]	86	1			T222	2		T29	4		T5	2
auto[3355443200:3489660927]	auto[0]	150	1			T6	4		T156	4		T277	2
auto[3355443200:3489660927]	auto[1]	80	1			T4	2		T53	2		T80	2
auto[3489660928:3623878655]	auto[0]	140	1			T142	2		T148	2		T224	2
auto[3489660928:3623878655]	auto[1]	82	1			T29	4		T30	2		T343	2
auto[3623878656:3758096383]	auto[0]	138	1			T3	2		T222	2		T142	2
auto[3623878656:3758096383]	auto[1]	80	1			T67	2		T52	2		T156	2
auto[3758096384:3892314111]	auto[0]	148	1			T1	2		T148	2		T228	2
auto[3758096384:3892314111]	auto[1]	58	1			T50	2		T265	2		T156	4
auto[3892314112:4026531839]	auto[0]	138	1			T1	2		T50	2		T130	2
auto[3892314112:4026531839]	auto[1]	68	1			T152	2		T277	2		T137	2
auto[4026531840:4160749567]	auto[0]	146	1			T114	2		T67	2		T47	2
auto[4026531840:4160749567]	auto[1]	74	1			T14	2		T50	2		T5	2
auto[4160749568:4294967295]	auto[0]	130	1			T1	2		T3	2		T223	2
auto[4160749568:4294967295]	auto[1]	56	1			T223	2		T68	2		T47	2