Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.04 98.07 98.25 100.00 99.02 98.41 91.14


Total test records in report: 1087
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T1009 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.556961826 Jun 13 12:59:58 PM PDT 24 Jun 13 01:00:03 PM PDT 24 215841898 ps
T1010 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1972816509 Jun 13 01:00:09 PM PDT 24 Jun 13 01:00:11 PM PDT 24 272089486 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.595497738 Jun 13 01:00:17 PM PDT 24 Jun 13 01:00:20 PM PDT 24 94310797 ps
T1012 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1856104510 Jun 13 01:00:12 PM PDT 24 Jun 13 01:00:15 PM PDT 24 26453333 ps
T180 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1608603485 Jun 13 01:00:15 PM PDT 24 Jun 13 01:00:18 PM PDT 24 52603366 ps
T1013 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2639819442 Jun 13 12:59:58 PM PDT 24 Jun 13 01:00:00 PM PDT 24 29871166 ps
T1014 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2935010430 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:14 PM PDT 24 11244478 ps
T1015 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3417927332 Jun 13 01:00:01 PM PDT 24 Jun 13 01:00:04 PM PDT 24 28710833 ps
T1016 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.962916958 Jun 13 01:00:21 PM PDT 24 Jun 13 01:00:27 PM PDT 24 2091669464 ps
T1017 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2027190102 Jun 13 01:00:20 PM PDT 24 Jun 13 01:00:21 PM PDT 24 12832457 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.16389911 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:06 PM PDT 24 31995894 ps
T1019 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3376272627 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:10 PM PDT 24 217562465 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.946023273 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:06 PM PDT 24 25543721 ps
T177 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3893212415 Jun 13 01:00:00 PM PDT 24 Jun 13 01:00:06 PM PDT 24 179001558 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2886669186 Jun 13 01:00:02 PM PDT 24 Jun 13 01:00:04 PM PDT 24 15829069 ps
T1022 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.9174186 Jun 13 01:00:15 PM PDT 24 Jun 13 01:00:17 PM PDT 24 28194108 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1386979181 Jun 13 01:00:05 PM PDT 24 Jun 13 01:00:09 PM PDT 24 87378003 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2730310255 Jun 13 01:00:10 PM PDT 24 Jun 13 01:00:17 PM PDT 24 541376593 ps
T1025 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2925776110 Jun 13 01:00:20 PM PDT 24 Jun 13 01:00:24 PM PDT 24 312149778 ps
T1026 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3209706716 Jun 13 01:00:12 PM PDT 24 Jun 13 01:00:14 PM PDT 24 67122518 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2185150861 Jun 13 01:00:10 PM PDT 24 Jun 13 01:00:14 PM PDT 24 23149109 ps
T1028 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2257162971 Jun 13 01:00:13 PM PDT 24 Jun 13 01:00:16 PM PDT 24 26671058 ps
T1029 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1852000690 Jun 13 01:00:27 PM PDT 24 Jun 13 01:00:29 PM PDT 24 39385162 ps
T1030 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1066978920 Jun 13 01:00:17 PM PDT 24 Jun 13 01:00:29 PM PDT 24 886042802 ps
T1031 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.370666571 Jun 13 01:00:22 PM PDT 24 Jun 13 01:00:23 PM PDT 24 41419684 ps
T1032 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.589092861 Jun 13 01:00:25 PM PDT 24 Jun 13 01:00:26 PM PDT 24 12622770 ps
T1033 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3238133890 Jun 13 01:00:18 PM PDT 24 Jun 13 01:00:19 PM PDT 24 45790765 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3896937525 Jun 13 01:00:04 PM PDT 24 Jun 13 01:00:07 PM PDT 24 195609758 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3983680722 Jun 13 12:59:59 PM PDT 24 Jun 13 01:00:05 PM PDT 24 857114926 ps
T1036 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3165942866 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:07 PM PDT 24 61600499 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3047499389 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:14 PM PDT 24 23678185 ps
T1038 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3737881251 Jun 13 01:00:27 PM PDT 24 Jun 13 01:00:29 PM PDT 24 42394547 ps
T1039 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3474439280 Jun 13 01:00:24 PM PDT 24 Jun 13 01:00:26 PM PDT 24 11719568 ps
T1040 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3402854209 Jun 13 01:00:21 PM PDT 24 Jun 13 01:00:23 PM PDT 24 27200019 ps
T1041 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2135777056 Jun 13 01:00:20 PM PDT 24 Jun 13 01:00:21 PM PDT 24 82193767 ps
T1042 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.290390747 Jun 13 01:00:27 PM PDT 24 Jun 13 01:00:28 PM PDT 24 42489882 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3468867190 Jun 13 01:00:14 PM PDT 24 Jun 13 01:00:16 PM PDT 24 168282216 ps
T1044 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.668516797 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:15 PM PDT 24 1643881625 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3187821476 Jun 13 01:00:17 PM PDT 24 Jun 13 01:00:19 PM PDT 24 23227681 ps
T1046 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3732318580 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:14 PM PDT 24 46219473 ps
T185 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4269072869 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:17 PM PDT 24 223228314 ps
T1047 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.809349330 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:14 PM PDT 24 29307202 ps
T1048 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4251996217 Jun 13 01:00:08 PM PDT 24 Jun 13 01:00:11 PM PDT 24 157127010 ps
T1049 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1647394990 Jun 13 01:00:29 PM PDT 24 Jun 13 01:00:31 PM PDT 24 77044873 ps
T1050 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.568612196 Jun 13 01:00:06 PM PDT 24 Jun 13 01:00:09 PM PDT 24 185123364 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3441458286 Jun 13 01:00:10 PM PDT 24 Jun 13 01:00:13 PM PDT 24 39583612 ps
T172 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1014892638 Jun 13 01:00:10 PM PDT 24 Jun 13 01:00:22 PM PDT 24 1024719403 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.738669502 Jun 13 12:59:59 PM PDT 24 Jun 13 01:00:03 PM PDT 24 1485385930 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1333948781 Jun 13 12:59:59 PM PDT 24 Jun 13 01:00:01 PM PDT 24 42556385 ps
T1054 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3558572042 Jun 13 01:00:22 PM PDT 24 Jun 13 01:00:23 PM PDT 24 30198812 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4089624758 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:10 PM PDT 24 873138175 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.780985383 Jun 13 01:00:10 PM PDT 24 Jun 13 01:00:13 PM PDT 24 165356962 ps
T170 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1597347038 Jun 13 01:00:22 PM PDT 24 Jun 13 01:00:26 PM PDT 24 81020748 ps
T183 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.610288595 Jun 13 01:00:14 PM PDT 24 Jun 13 01:00:19 PM PDT 24 419021583 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3360988421 Jun 13 01:00:00 PM PDT 24 Jun 13 01:00:03 PM PDT 24 257457353 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4082822880 Jun 13 12:59:58 PM PDT 24 Jun 13 01:00:02 PM PDT 24 60448841 ps
T1059 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2552405656 Jun 13 01:00:04 PM PDT 24 Jun 13 01:00:07 PM PDT 24 98782466 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3357648047 Jun 13 01:00:19 PM PDT 24 Jun 13 01:00:21 PM PDT 24 27376562 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1093392423 Jun 13 01:00:12 PM PDT 24 Jun 13 01:00:15 PM PDT 24 52431550 ps
T1062 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3542865262 Jun 13 01:00:15 PM PDT 24 Jun 13 01:00:17 PM PDT 24 43763040 ps
T1063 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2621935973 Jun 13 01:00:02 PM PDT 24 Jun 13 01:00:04 PM PDT 24 111697069 ps
T1064 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3266718088 Jun 13 01:00:16 PM PDT 24 Jun 13 01:00:19 PM PDT 24 202964317 ps
T1065 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2084139871 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:14 PM PDT 24 9112386 ps
T1066 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3706914576 Jun 13 12:59:59 PM PDT 24 Jun 13 01:00:08 PM PDT 24 379196246 ps
T1067 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1810576473 Jun 13 01:00:12 PM PDT 24 Jun 13 01:00:14 PM PDT 24 18503845 ps
T1068 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1000054468 Jun 13 01:00:19 PM PDT 24 Jun 13 01:00:31 PM PDT 24 655022727 ps
T1069 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.685952143 Jun 13 01:00:05 PM PDT 24 Jun 13 01:00:08 PM PDT 24 62901593 ps
T1070 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.494021642 Jun 13 01:00:40 PM PDT 24 Jun 13 01:00:41 PM PDT 24 11746625 ps
T1071 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2117368187 Jun 13 01:00:12 PM PDT 24 Jun 13 01:00:15 PM PDT 24 41507055 ps
T1072 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1905354917 Jun 13 01:00:18 PM PDT 24 Jun 13 01:00:20 PM PDT 24 10266315 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.637052446 Jun 13 01:00:17 PM PDT 24 Jun 13 01:00:19 PM PDT 24 68888715 ps
T187 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2978987357 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:10 PM PDT 24 137576505 ps
T1074 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4140764698 Jun 13 01:00:16 PM PDT 24 Jun 13 01:00:18 PM PDT 24 31259731 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.310339354 Jun 13 01:00:03 PM PDT 24 Jun 13 01:00:11 PM PDT 24 262411113 ps
T189 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2032436850 Jun 13 01:00:18 PM PDT 24 Jun 13 01:00:28 PM PDT 24 872784021 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2451625411 Jun 13 01:00:00 PM PDT 24 Jun 13 01:00:02 PM PDT 24 25780640 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3366571311 Jun 13 01:00:11 PM PDT 24 Jun 13 01:00:13 PM PDT 24 50296262 ps
T1078 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.214978833 Jun 13 01:00:23 PM PDT 24 Jun 13 01:00:25 PM PDT 24 62331709 ps
T1079 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.912761923 Jun 13 01:00:21 PM PDT 24 Jun 13 01:00:23 PM PDT 24 23427272 ps
T1080 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2070023538 Jun 13 01:00:04 PM PDT 24 Jun 13 01:00:07 PM PDT 24 210373663 ps
T1081 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2855472742 Jun 13 12:59:58 PM PDT 24 Jun 13 01:00:09 PM PDT 24 591283179 ps
T1082 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3496135267 Jun 13 01:00:22 PM PDT 24 Jun 13 01:00:23 PM PDT 24 126574662 ps
T1083 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4166849906 Jun 13 01:00:23 PM PDT 24 Jun 13 01:00:26 PM PDT 24 37289308 ps
T1084 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.240595142 Jun 13 01:00:26 PM PDT 24 Jun 13 01:00:28 PM PDT 24 272251664 ps
T1085 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2086113762 Jun 13 01:00:02 PM PDT 24 Jun 13 01:00:07 PM PDT 24 169478586 ps
T1086 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.898870393 Jun 13 01:00:00 PM PDT 24 Jun 13 01:00:02 PM PDT 24 13539823 ps
T1087 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.347138920 Jun 13 01:00:37 PM PDT 24 Jun 13 01:00:39 PM PDT 24 49117836 ps

Test location /workspace/coverage/default/12.keymgr_custom_cm.4219546383
Short name T4
Test name
Test status
Simulation time 913283254 ps
CPU time 6.1 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:56 PM PDT 24
Peak memory 209372 kb
Host smart-aac762d5-543d-43c1-8722-08390d69e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219546383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4219546383
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4116311002
Short name T6
Test name
Test status
Simulation time 2329786827 ps
CPU time 41.57 seconds
Started Jun 13 01:07:33 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 215788 kb
Host smart-b412f3bc-450e-4517-b81c-c913698aecf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116311002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4116311002
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3501110724
Short name T156
Test name
Test status
Simulation time 9604146166 ps
CPU time 72.92 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:09:15 PM PDT 24
Peak memory 222780 kb
Host smart-f9e10733-f71e-43b9-a353-e7a4ad8869a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501110724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3501110724
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.764712847
Short name T140
Test name
Test status
Simulation time 4088709497 ps
CPU time 28.78 seconds
Started Jun 13 01:34:29 PM PDT 24
Finished Jun 13 01:34:58 PM PDT 24
Peak memory 222356 kb
Host smart-f5f1bba9-30e9-4ec3-81c7-b4f1133843ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764712847 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.764712847
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3720512240
Short name T11
Test name
Test status
Simulation time 721483588 ps
CPU time 5.31 seconds
Started Jun 13 01:06:50 PM PDT 24
Finished Jun 13 01:06:58 PM PDT 24
Peak memory 237192 kb
Host smart-fbe5df9f-7675-492c-b44c-26a0d92972ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720512240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3720512240
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2984368003
Short name T50
Test name
Test status
Simulation time 662201377 ps
CPU time 9.43 seconds
Started Jun 13 02:06:25 PM PDT 24
Finished Jun 13 02:06:36 PM PDT 24
Peak memory 222440 kb
Host smart-ec8b506b-4a29-4638-bcbc-d6f075f9c47b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984368003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2984368003
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3876170275
Short name T80
Test name
Test status
Simulation time 1054752447 ps
CPU time 27.33 seconds
Started Jun 13 01:08:36 PM PDT 24
Finished Jun 13 01:09:05 PM PDT 24
Peak memory 215676 kb
Host smart-7c29a73d-79fa-4149-9eee-40de0793f6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876170275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3876170275
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2628130566
Short name T8
Test name
Test status
Simulation time 222148532 ps
CPU time 4.07 seconds
Started Jun 13 01:09:03 PM PDT 24
Finished Jun 13 01:09:09 PM PDT 24
Peak memory 222604 kb
Host smart-56b6b5ff-b019-4ed0-96b5-3d2b7d554a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628130566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2628130566
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3927941531
Short name T41
Test name
Test status
Simulation time 39227103 ps
CPU time 2.19 seconds
Started Jun 13 02:31:13 PM PDT 24
Finished Jun 13 02:31:20 PM PDT 24
Peak memory 216292 kb
Host smart-01c16ec7-3c3c-444b-91e8-46a1392ae49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927941531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3927941531
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3024091116
Short name T97
Test name
Test status
Simulation time 135612736 ps
CPU time 5.03 seconds
Started Jun 13 01:08:43 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 215320 kb
Host smart-42584561-7ec9-414d-a0a8-8aea9f1436f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024091116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3024091116
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2497208333
Short name T128
Test name
Test status
Simulation time 556401875 ps
CPU time 6.71 seconds
Started Jun 13 01:00:16 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 214448 kb
Host smart-00dace1e-3945-44bb-8f85-147b3e4b04c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497208333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2497208333
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2648570311
Short name T93
Test name
Test status
Simulation time 656926518 ps
CPU time 15.49 seconds
Started Jun 13 01:35:52 PM PDT 24
Finished Jun 13 01:36:09 PM PDT 24
Peak memory 222528 kb
Host smart-5f64cc72-b52d-43e9-8bbf-3410e6ecd5bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648570311 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2648570311
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2564962575
Short name T65
Test name
Test status
Simulation time 6204432122 ps
CPU time 46.7 seconds
Started Jun 13 01:08:06 PM PDT 24
Finished Jun 13 01:08:53 PM PDT 24
Peak memory 215760 kb
Host smart-2b837da0-a5f0-4fcd-a59d-754b6121fee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564962575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2564962575
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.936429369
Short name T406
Test name
Test status
Simulation time 2322645069 ps
CPU time 7.15 seconds
Started Jun 13 01:20:11 PM PDT 24
Finished Jun 13 01:20:18 PM PDT 24
Peak memory 214416 kb
Host smart-702a5fba-f493-4bab-af0f-94785ddfb3dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936429369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.936429369
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2022823454
Short name T130
Test name
Test status
Simulation time 170386284 ps
CPU time 9.53 seconds
Started Jun 13 01:09:01 PM PDT 24
Finished Jun 13 01:09:12 PM PDT 24
Peak memory 215520 kb
Host smart-a1cd0e7e-cdce-4402-bebc-859425d6570c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022823454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2022823454
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3005779398
Short name T24
Test name
Test status
Simulation time 158240640 ps
CPU time 4.06 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:05 PM PDT 24
Peak memory 222460 kb
Host smart-240f2549-271a-4d59-95f0-7e4904a36547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005779398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3005779398
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.621695998
Short name T265
Test name
Test status
Simulation time 173709018 ps
CPU time 9.05 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:37 PM PDT 24
Peak memory 214292 kb
Host smart-5742085f-ff42-4e7e-8842-767cd1160bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621695998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.621695998
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1855835740
Short name T33
Test name
Test status
Simulation time 105166848 ps
CPU time 4.52 seconds
Started Jun 13 01:07:47 PM PDT 24
Finished Jun 13 01:07:52 PM PDT 24
Peak memory 214144 kb
Host smart-42e42368-de89-437a-9a0a-154ec9123425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855835740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1855835740
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.4221717513
Short name T158
Test name
Test status
Simulation time 2212193686 ps
CPU time 30.87 seconds
Started Jun 13 01:08:42 PM PDT 24
Finished Jun 13 01:09:13 PM PDT 24
Peak memory 217068 kb
Host smart-f16d3d86-125f-49ae-8b96-b51cc32345af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221717513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.4221717513
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3138995864
Short name T166
Test name
Test status
Simulation time 95880427 ps
CPU time 4.26 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 214152 kb
Host smart-8a654e99-93d1-40d1-9651-97555d5e8b08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138995864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3138995864
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.575638204
Short name T291
Test name
Test status
Simulation time 268746128 ps
CPU time 15.08 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:29 PM PDT 24
Peak memory 215328 kb
Host smart-7a4564e8-b87d-443d-9392-bd5728a53b47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575638204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.575638204
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.198032354
Short name T47
Test name
Test status
Simulation time 121780039 ps
CPU time 2.4 seconds
Started Jun 13 02:01:05 PM PDT 24
Finished Jun 13 02:01:08 PM PDT 24
Peak memory 222524 kb
Host smart-b2c90194-f74e-46e0-afca-d80492b6cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198032354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.198032354
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3431887161
Short name T58
Test name
Test status
Simulation time 1695821714 ps
CPU time 23.34 seconds
Started Jun 13 01:08:32 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 216120 kb
Host smart-14e4dbdd-0ee3-4c84-828d-90c8324a9e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431887161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3431887161
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.147566474
Short name T23
Test name
Test status
Simulation time 108052594 ps
CPU time 2.76 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:07:59 PM PDT 24
Peak memory 209588 kb
Host smart-f92665ee-cd55-4047-a8bf-af3366aee8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147566474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.147566474
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.465304070
Short name T411
Test name
Test status
Simulation time 163190654 ps
CPU time 8.92 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 214292 kb
Host smart-15dea0bc-a986-48bc-bd9c-70b7df9ffe60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465304070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.465304070
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2363618146
Short name T63
Test name
Test status
Simulation time 161368645 ps
CPU time 4.95 seconds
Started Jun 13 01:07:36 PM PDT 24
Finished Jun 13 01:07:41 PM PDT 24
Peak memory 222484 kb
Host smart-ec243aff-e874-4639-8515-dd6fff8c72f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363618146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2363618146
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3582893733
Short name T72
Test name
Test status
Simulation time 272564510 ps
CPU time 13.71 seconds
Started Jun 13 01:08:03 PM PDT 24
Finished Jun 13 01:08:18 PM PDT 24
Peak memory 215960 kb
Host smart-192d8060-c73c-440c-be86-c3595b0272fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582893733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3582893733
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.133130528
Short name T44
Test name
Test status
Simulation time 126105163 ps
CPU time 1.59 seconds
Started Jun 13 01:08:12 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 209760 kb
Host smart-af8cf440-8469-4d0c-9dc5-68324c94a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133130528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.133130528
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.266988139
Short name T949
Test name
Test status
Simulation time 182852622 ps
CPU time 8.57 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:22 PM PDT 24
Peak memory 214432 kb
Host smart-ef3f6c0e-d472-4cba-a809-4b3947706b95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266988139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.266988139
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.471785007
Short name T108
Test name
Test status
Simulation time 120165449 ps
CPU time 4.94 seconds
Started Jun 13 01:08:07 PM PDT 24
Finished Jun 13 01:08:12 PM PDT 24
Peak memory 214276 kb
Host smart-bfeff559-29e0-4fee-baf9-103f41e63695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471785007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.471785007
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2404182991
Short name T106
Test name
Test status
Simulation time 62208488 ps
CPU time 3.14 seconds
Started Jun 13 01:08:28 PM PDT 24
Finished Jun 13 01:08:32 PM PDT 24
Peak memory 208876 kb
Host smart-3087f12e-197a-4a9d-9fad-859370c8fe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404182991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2404182991
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.787569907
Short name T112
Test name
Test status
Simulation time 17904198 ps
CPU time 0.79 seconds
Started Jun 13 01:08:49 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 205912 kb
Host smart-d3c8d007-1d21-4e54-b49d-bd679efdaf69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787569907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.787569907
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3966226861
Short name T42
Test name
Test status
Simulation time 518239620 ps
CPU time 13.34 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:56 PM PDT 24
Peak memory 210484 kb
Host smart-9151e8e9-df60-4305-b7bc-d866d1f1b13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966226861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3966226861
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3862618239
Short name T64
Test name
Test status
Simulation time 1560339130 ps
CPU time 36.19 seconds
Started Jun 13 01:07:16 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 220760 kb
Host smart-4ee5a445-6ac4-4d2e-9ee0-3800b839a287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862618239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3862618239
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2385098239
Short name T389
Test name
Test status
Simulation time 235656770 ps
CPU time 3.77 seconds
Started Jun 13 01:07:44 PM PDT 24
Finished Jun 13 01:07:48 PM PDT 24
Peak memory 214272 kb
Host smart-e1ba3aab-49bf-41e8-82e9-033f2921b39e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385098239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2385098239
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.253833828
Short name T320
Test name
Test status
Simulation time 180766277 ps
CPU time 10.04 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:10 PM PDT 24
Peak memory 214292 kb
Host smart-fa88265d-b863-4232-901c-7febfaffd8c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253833828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.253833828
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3130791127
Short name T29
Test name
Test status
Simulation time 551311359 ps
CPU time 13.6 seconds
Started Jun 13 01:37:06 PM PDT 24
Finished Jun 13 01:37:20 PM PDT 24
Peak memory 222676 kb
Host smart-f14d7995-d410-4474-af87-78bdc4711524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130791127 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3130791127
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.180517279
Short name T19
Test name
Test status
Simulation time 692810514 ps
CPU time 3.8 seconds
Started Jun 13 01:07:12 PM PDT 24
Finished Jun 13 01:07:16 PM PDT 24
Peak memory 208924 kb
Host smart-ffed294d-668e-4dd9-95eb-3ccb9014ae3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180517279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.180517279
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3150108782
Short name T85
Test name
Test status
Simulation time 1969806007 ps
CPU time 63.43 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:09:51 PM PDT 24
Peak memory 222228 kb
Host smart-345e1330-1909-45b3-b355-def04e39eadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150108782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3150108782
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1067233144
Short name T165
Test name
Test status
Simulation time 1151310501 ps
CPU time 13.93 seconds
Started Jun 13 03:03:35 PM PDT 24
Finished Jun 13 03:03:50 PM PDT 24
Peak memory 214868 kb
Host smart-eef022ec-10ac-41e1-80d0-1b61dd539049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067233144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1067233144
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2421837653
Short name T269
Test name
Test status
Simulation time 51791188 ps
CPU time 3.62 seconds
Started Jun 13 01:06:56 PM PDT 24
Finished Jun 13 01:07:01 PM PDT 24
Peak memory 222392 kb
Host smart-b85114f7-09d5-463b-8ba0-1aa346330e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421837653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2421837653
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.759861796
Short name T205
Test name
Test status
Simulation time 2384967240 ps
CPU time 42.47 seconds
Started Jun 13 01:07:02 PM PDT 24
Finished Jun 13 01:07:46 PM PDT 24
Peak memory 222452 kb
Host smart-86413d6e-d8c0-4e0b-b961-d4eab2da4240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759861796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.759861796
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.672724355
Short name T123
Test name
Test status
Simulation time 57643928 ps
CPU time 2.2 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:26 PM PDT 24
Peak memory 217492 kb
Host smart-e3d7b6f2-62b7-408e-800e-172723cd4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672724355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.672724355
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1773521560
Short name T5
Test name
Test status
Simulation time 4599406938 ps
CPU time 129.84 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:10:40 PM PDT 24
Peak memory 217376 kb
Host smart-e6aa3033-e469-49bc-9c75-3d852b8929d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773521560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1773521560
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.466391179
Short name T303
Test name
Test status
Simulation time 107770220 ps
CPU time 3.94 seconds
Started Jun 13 01:06:40 PM PDT 24
Finished Jun 13 01:06:45 PM PDT 24
Peak memory 214376 kb
Host smart-3d962ea1-7d6e-447b-bda5-40d69ecbaf54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466391179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.466391179
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2391230912
Short name T271
Test name
Test status
Simulation time 282668411 ps
CPU time 2.67 seconds
Started Jun 13 01:08:03 PM PDT 24
Finished Jun 13 01:08:06 PM PDT 24
Peak memory 214244 kb
Host smart-e4539b1f-1df7-4fc7-a457-263aaf460b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391230912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2391230912
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3783536312
Short name T186
Test name
Test status
Simulation time 102746069 ps
CPU time 4.12 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 213932 kb
Host smart-9de8619a-0d59-40ba-a430-42063dcf2e08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783536312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3783536312
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1014892638
Short name T172
Test name
Test status
Simulation time 1024719403 ps
CPU time 10.63 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:22 PM PDT 24
Peak memory 213984 kb
Host smart-0e23169d-f3b2-4746-940a-c9bdf83122cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014892638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1014892638
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2834074068
Short name T181
Test name
Test status
Simulation time 115237784 ps
CPU time 4.48 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 214052 kb
Host smart-a69bdd6e-2350-44a3-beaf-7d32405ccf6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834074068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2834074068
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.546018575
Short name T252
Test name
Test status
Simulation time 2201577060 ps
CPU time 25.17 seconds
Started Jun 13 01:06:50 PM PDT 24
Finished Jun 13 01:07:17 PM PDT 24
Peak memory 215124 kb
Host smart-79396da6-c946-4e0c-8218-b28a06598d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546018575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.546018575
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3897192220
Short name T241
Test name
Test status
Simulation time 3549481018 ps
CPU time 111.95 seconds
Started Jun 13 01:07:41 PM PDT 24
Finished Jun 13 01:09:34 PM PDT 24
Peak memory 222552 kb
Host smart-69589928-0c84-4e3d-9157-dada72458b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897192220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3897192220
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2545548006
Short name T627
Test name
Test status
Simulation time 39364132 ps
CPU time 2.56 seconds
Started Jun 13 01:07:56 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 214388 kb
Host smart-27f0ba37-a743-4ad4-8387-d78d31cbd681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545548006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2545548006
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.4216584034
Short name T154
Test name
Test status
Simulation time 384067410 ps
CPU time 2.25 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 206996 kb
Host smart-dcbceca3-54ea-4f02-ac7d-2f3d51a20065
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216584034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4216584034
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3024545379
Short name T246
Test name
Test status
Simulation time 3773275962 ps
CPU time 70.43 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:08:37 PM PDT 24
Peak memory 222520 kb
Host smart-b1fd9f91-c528-4f80-823b-6cd204e88f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024545379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3024545379
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2469808443
Short name T71
Test name
Test status
Simulation time 77898851 ps
CPU time 1.61 seconds
Started Jun 13 02:10:49 PM PDT 24
Finished Jun 13 02:10:52 PM PDT 24
Peak memory 210256 kb
Host smart-f12efab4-e531-4af1-84db-2a17d67d7a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469808443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2469808443
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2612044067
Short name T131
Test name
Test status
Simulation time 158764339 ps
CPU time 7.02 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:25 PM PDT 24
Peak memory 214556 kb
Host smart-50298943-6074-4b23-9194-d00ca45a44a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612044067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2612044067
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2978987357
Short name T187
Test name
Test status
Simulation time 137576505 ps
CPU time 4.82 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:10 PM PDT 24
Peak memory 206260 kb
Host smart-388666ca-2196-4876-8544-04e99a6bc07d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978987357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2978987357
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4269072869
Short name T185
Test name
Test status
Simulation time 223228314 ps
CPU time 4.62 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 205936 kb
Host smart-1b39bfa3-e4bc-4aaf-b3e1-7fbf937dcd81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269072869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4269072869
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3080784081
Short name T40
Test name
Test status
Simulation time 1445520849 ps
CPU time 9.99 seconds
Started Jun 13 01:07:07 PM PDT 24
Finished Jun 13 01:07:18 PM PDT 24
Peak memory 238164 kb
Host smart-2203e598-ad63-4a1c-a317-1ae6eeb2f3f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080784081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3080784081
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3397025304
Short name T27
Test name
Test status
Simulation time 44291209 ps
CPU time 2.51 seconds
Started Jun 13 01:07:27 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 221520 kb
Host smart-717c7f57-b57d-40fd-899a-3e691075fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397025304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3397025304
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2461463701
Short name T125
Test name
Test status
Simulation time 53461367 ps
CPU time 2.4 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:09 PM PDT 24
Peak memory 216936 kb
Host smart-01b5cc3b-7e7b-4bb6-a524-a83a497135ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461463701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2461463701
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.4254802087
Short name T194
Test name
Test status
Simulation time 263810672 ps
CPU time 11.09 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 222640 kb
Host smart-1ec26309-ec0c-46fe-b779-090530c6bdbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254802087 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.4254802087
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3304090409
Short name T57
Test name
Test status
Simulation time 708169284 ps
CPU time 2.98 seconds
Started Jun 13 01:08:12 PM PDT 24
Finished Jun 13 01:08:17 PM PDT 24
Peak memory 206924 kb
Host smart-549e3b1e-3174-47ff-bf63-a6797075ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304090409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3304090409
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.467525237
Short name T895
Test name
Test status
Simulation time 814725018 ps
CPU time 41.87 seconds
Started Jun 13 01:08:42 PM PDT 24
Finished Jun 13 01:09:24 PM PDT 24
Peak memory 214320 kb
Host smart-ea104979-3873-4df3-a5cf-ccbba08d11fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467525237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.467525237
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.895400818
Short name T207
Test name
Test status
Simulation time 898706939 ps
CPU time 32.61 seconds
Started Jun 13 01:55:05 PM PDT 24
Finished Jun 13 01:55:39 PM PDT 24
Peak memory 222488 kb
Host smart-7fb86e43-c902-4b68-a7f6-126de6745973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895400818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.895400818
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4146866497
Short name T98
Test name
Test status
Simulation time 86017827 ps
CPU time 1.73 seconds
Started Jun 13 01:07:17 PM PDT 24
Finished Jun 13 01:07:20 PM PDT 24
Peak memory 215540 kb
Host smart-cf2d0d37-a045-49a8-b1f7-92a12da8a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146866497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4146866497
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1503816786
Short name T124
Test name
Test status
Simulation time 39621324 ps
CPU time 2.62 seconds
Started Jun 13 01:49:19 PM PDT 24
Finished Jun 13 01:49:23 PM PDT 24
Peak memory 218084 kb
Host smart-2b1d276a-74fb-43cd-8655-76b6a8ef669b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503816786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1503816786
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.884878547
Short name T126
Test name
Test status
Simulation time 84257188 ps
CPU time 2.15 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:35 PM PDT 24
Peak memory 217892 kb
Host smart-3e942bdc-322b-4312-82ae-04117e97e420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884878547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.884878547
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.523535337
Short name T290
Test name
Test status
Simulation time 1377635673 ps
CPU time 10.69 seconds
Started Jun 13 01:06:48 PM PDT 24
Finished Jun 13 01:06:59 PM PDT 24
Peak memory 215032 kb
Host smart-c425d506-31fc-4ff6-bf60-d56d25825fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523535337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.523535337
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3652594269
Short name T256
Test name
Test status
Simulation time 760267418 ps
CPU time 16.16 seconds
Started Jun 13 01:06:55 PM PDT 24
Finished Jun 13 01:07:13 PM PDT 24
Peak memory 222520 kb
Host smart-cd75cdba-7c98-4322-8bef-b8d75a16c7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652594269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3652594269
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1547268960
Short name T903
Test name
Test status
Simulation time 146044073 ps
CPU time 3.39 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:46 PM PDT 24
Peak memory 215736 kb
Host smart-c50aae3e-b7a4-4d1a-afc2-cad92c99f6a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547268960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1547268960
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4219960952
Short name T896
Test name
Test status
Simulation time 2379424548 ps
CPU time 6.1 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:08:01 PM PDT 24
Peak memory 214296 kb
Host smart-35b8f555-8ec4-43d5-a473-668f6f0f935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219960952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4219960952
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4022567497
Short name T109
Test name
Test status
Simulation time 4861049504 ps
CPU time 25.19 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:09:05 PM PDT 24
Peak memory 214416 kb
Host smart-04254b0b-61f8-4eb0-9b74-60459c16bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022567497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4022567497
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3149749963
Short name T390
Test name
Test status
Simulation time 486084124 ps
CPU time 3.46 seconds
Started Jun 13 02:02:02 PM PDT 24
Finished Jun 13 02:02:06 PM PDT 24
Peak memory 214416 kb
Host smart-a9d110a8-0405-4237-a6f8-873419617b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149749963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3149749963
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3713383359
Short name T179
Test name
Test status
Simulation time 102202795 ps
CPU time 5.41 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 214112 kb
Host smart-6030aab5-fd6e-48f3-90cd-ce1a0b689b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713383359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3713383359
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2032436850
Short name T189
Test name
Test status
Simulation time 872784021 ps
CPU time 8.58 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:28 PM PDT 24
Peak memory 214168 kb
Host smart-5847af97-5358-4a5e-a86c-4ea9e5e532ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032436850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2032436850
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1597347038
Short name T170
Test name
Test status
Simulation time 81020748 ps
CPU time 2.6 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 206080 kb
Host smart-236e77e2-1539-4861-9a7d-b74ca1f1882b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597347038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1597347038
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1042635405
Short name T670
Test name
Test status
Simulation time 90813183 ps
CPU time 3.81 seconds
Started Jun 13 01:06:46 PM PDT 24
Finished Jun 13 01:06:51 PM PDT 24
Peak memory 214292 kb
Host smart-6936941b-7081-4898-9362-8425913902be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042635405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1042635405
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2523233892
Short name T147
Test name
Test status
Simulation time 74125423 ps
CPU time 1.46 seconds
Started Jun 13 01:06:58 PM PDT 24
Finished Jun 13 01:07:02 PM PDT 24
Peak memory 209980 kb
Host smart-6d548121-2507-4b42-86f4-176b9b9afe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523233892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2523233892
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.339213318
Short name T385
Test name
Test status
Simulation time 467545489 ps
CPU time 19.28 seconds
Started Jun 13 01:07:41 PM PDT 24
Finished Jun 13 01:08:01 PM PDT 24
Peak memory 222592 kb
Host smart-3d4d99a4-e3ba-4ca7-8184-6c2bcf04f2cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339213318 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.339213318
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1198435889
Short name T381
Test name
Test status
Simulation time 123325927 ps
CPU time 2.79 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:43 PM PDT 24
Peak memory 214360 kb
Host smart-06ccee56-80b0-4cfd-97c6-0fff6e97ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198435889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1198435889
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2356784080
Short name T353
Test name
Test status
Simulation time 341147798 ps
CPU time 5.34 seconds
Started Jun 13 01:07:52 PM PDT 24
Finished Jun 13 01:07:58 PM PDT 24
Peak memory 222408 kb
Host smart-2117e596-d4d3-4cde-98b4-fae5da1799aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356784080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2356784080
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2416433665
Short name T219
Test name
Test status
Simulation time 182913998 ps
CPU time 4.72 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:01 PM PDT 24
Peak memory 214480 kb
Host smart-89b2be33-9920-459f-9f37-db2d29533f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416433665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2416433665
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4137429836
Short name T249
Test name
Test status
Simulation time 1358682682 ps
CPU time 21.71 seconds
Started Jun 13 01:07:56 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 222600 kb
Host smart-66f5caab-3c26-4079-9fe0-bb6d62e96db0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137429836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4137429836
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2224092112
Short name T674
Test name
Test status
Simulation time 118333114 ps
CPU time 3.09 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 208360 kb
Host smart-e29001d4-a9fe-4dbf-a6c5-0f4ccb250a75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224092112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2224092112
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2988826809
Short name T251
Test name
Test status
Simulation time 125067376 ps
CPU time 4.5 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:13 PM PDT 24
Peak memory 210272 kb
Host smart-9245ec16-1681-4667-bacd-2217c45a8a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988826809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2988826809
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3452315958
Short name T915
Test name
Test status
Simulation time 3612583462 ps
CPU time 40.93 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 216536 kb
Host smart-5460124e-82c4-442d-90c4-2100a4e28121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452315958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3452315958
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.594326537
Short name T368
Test name
Test status
Simulation time 37448842 ps
CPU time 1.6 seconds
Started Jun 13 01:08:11 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 214324 kb
Host smart-209d37aa-7058-4da4-875c-72795a994fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594326537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.594326537
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1881426537
Short name T330
Test name
Test status
Simulation time 62556608 ps
CPU time 3.59 seconds
Started Jun 13 01:07:02 PM PDT 24
Finished Jun 13 01:07:07 PM PDT 24
Peak memory 207184 kb
Host smart-63d80292-0c4a-4a3e-bad4-25ceace4e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881426537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1881426537
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3795813118
Short name T379
Test name
Test status
Simulation time 139532351 ps
CPU time 2.98 seconds
Started Jun 13 01:06:56 PM PDT 24
Finished Jun 13 01:07:00 PM PDT 24
Peak memory 206868 kb
Host smart-f5730e1a-8557-4e35-a3e3-e703c54f34b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795813118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3795813118
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1342003297
Short name T84
Test name
Test status
Simulation time 564580042 ps
CPU time 13.9 seconds
Started Jun 13 01:08:13 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 208168 kb
Host smart-061516e9-1477-4ebd-baa6-2f68e7c66966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342003297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1342003297
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.596082167
Short name T326
Test name
Test status
Simulation time 30313600 ps
CPU time 2.43 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:20 PM PDT 24
Peak memory 206872 kb
Host smart-fc43f5b1-dede-49aa-a8b0-fc62bb705075
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596082167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.596082167
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1694010817
Short name T316
Test name
Test status
Simulation time 2933004576 ps
CPU time 51.17 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:09:13 PM PDT 24
Peak memory 222476 kb
Host smart-aee4c622-f73f-450d-89bf-6e5305f374f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694010817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1694010817
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1970277615
Short name T239
Test name
Test status
Simulation time 523730988 ps
CPU time 2.17 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:35 PM PDT 24
Peak memory 209680 kb
Host smart-c278e701-e120-4bfb-b0ee-5a0215d48d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970277615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1970277615
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1894101316
Short name T237
Test name
Test status
Simulation time 867995561 ps
CPU time 13.26 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 220416 kb
Host smart-4c694b36-56a9-47b3-9f71-cbebaec4672d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894101316 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1894101316
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1660224337
Short name T340
Test name
Test status
Simulation time 56898244 ps
CPU time 2.98 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:35 PM PDT 24
Peak memory 207976 kb
Host smart-64a6cfe9-909c-4113-b080-6ff3804ef528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660224337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1660224337
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1402245648
Short name T366
Test name
Test status
Simulation time 76039823 ps
CPU time 2.98 seconds
Started Jun 13 02:00:51 PM PDT 24
Finished Jun 13 02:00:55 PM PDT 24
Peak memory 214300 kb
Host smart-1805438f-519f-4f4b-bded-46110c059ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402245648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1402245648
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_random.41190663
Short name T362
Test name
Test status
Simulation time 186796812 ps
CPU time 4.38 seconds
Started Jun 13 01:41:33 PM PDT 24
Finished Jun 13 01:41:38 PM PDT 24
Peak memory 209056 kb
Host smart-106da8c6-4617-4774-954c-cae0dded6e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41190663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.41190663
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.172544523
Short name T253
Test name
Test status
Simulation time 469759625 ps
CPU time 20.11 seconds
Started Jun 13 01:38:49 PM PDT 24
Finished Jun 13 01:39:10 PM PDT 24
Peak memory 222500 kb
Host smart-97a15d3d-1596-43ee-8464-e8d0dd3d23a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172544523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.172544523
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3731243818
Short name T416
Test name
Test status
Simulation time 226725332 ps
CPU time 4.16 seconds
Started Jun 13 01:29:37 PM PDT 24
Finished Jun 13 01:29:42 PM PDT 24
Peak memory 215320 kb
Host smart-ca4cb726-6427-4175-995c-2114cb1385c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731243818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3731243818
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.41303064
Short name T62
Test name
Test status
Simulation time 611863777 ps
CPU time 3.55 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:46 PM PDT 24
Peak memory 218168 kb
Host smart-4895c243-dffd-48b4-a0c0-83da55729010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41303064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.41303064
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.575372951
Short name T971
Test name
Test status
Simulation time 184057228 ps
CPU time 6.76 seconds
Started Jun 13 12:59:59 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 205808 kb
Host smart-98e77eb9-6d80-437b-b272-67d0230e2d80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575372951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.575372951
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2456023711
Short name T950
Test name
Test status
Simulation time 6085903479 ps
CPU time 17.79 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 206036 kb
Host smart-772e6116-ba32-4694-94bc-8bb37c632ad4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456023711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
456023711
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2258362710
Short name T972
Test name
Test status
Simulation time 40433014 ps
CPU time 0.93 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:00 PM PDT 24
Peak memory 205684 kb
Host smart-9310d7a8-daf2-4775-9f47-23c825a08232
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258362710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
258362710
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2886669186
Short name T1021
Test name
Test status
Simulation time 15829069 ps
CPU time 1.27 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 214064 kb
Host smart-0565f19a-77be-4460-bafc-86c3c691e4b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886669186 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2886669186
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2451625411
Short name T1076
Test name
Test status
Simulation time 25780640 ps
CPU time 1.12 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:02 PM PDT 24
Peak memory 205808 kb
Host smart-055be1fb-bde1-4fad-b93a-e352bafd01a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451625411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2451625411
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2639819442
Short name T1013
Test name
Test status
Simulation time 29871166 ps
CPU time 0.74 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:00 PM PDT 24
Peak memory 205548 kb
Host smart-a7c5118c-2277-4484-8ef4-b7478773661d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639819442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2639819442
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4082822880
Short name T1058
Test name
Test status
Simulation time 60448841 ps
CPU time 2.44 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:02 PM PDT 24
Peak memory 205828 kb
Host smart-ec104d9d-2e48-4d94-ae3f-3de32bebc98f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082822880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4082822880
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3360988421
Short name T1057
Test name
Test status
Simulation time 257457353 ps
CPU time 2.04 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:03 PM PDT 24
Peak memory 214452 kb
Host smart-c81a2304-d627-4036-9f7f-2fbf187159c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360988421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3360988421
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3098660719
Short name T134
Test name
Test status
Simulation time 144028733 ps
CPU time 6.53 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 214552 kb
Host smart-8f123883-2cbd-4d22-b906-154ae4b99c3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098660719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3098660719
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1136826040
Short name T947
Test name
Test status
Simulation time 1704825987 ps
CPU time 3.09 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 214116 kb
Host smart-b5fc2177-d603-4393-a4e4-5ec9b5fbc837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136826040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1136826040
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2847795323
Short name T171
Test name
Test status
Simulation time 160521688 ps
CPU time 3.36 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:03 PM PDT 24
Peak memory 214200 kb
Host smart-7e9fd550-240a-4ca5-9ced-fd1e42003307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847795323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2847795323
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1943529551
Short name T159
Test name
Test status
Simulation time 126846371 ps
CPU time 7.22 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:10 PM PDT 24
Peak memory 205956 kb
Host smart-f3e803db-2a0d-45d4-a3a4-afa822fddd3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943529551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
943529551
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3445939683
Short name T965
Test name
Test status
Simulation time 655027846 ps
CPU time 16.94 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 205932 kb
Host smart-45c22a3c-b788-4c2d-a65a-f2167ce74cd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445939683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
445939683
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2621935973
Short name T1063
Test name
Test status
Simulation time 111697069 ps
CPU time 1.46 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 205728 kb
Host smart-358a5c7b-9afa-4647-915d-306e079e8dec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621935973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
621935973
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3896937525
Short name T1034
Test name
Test status
Simulation time 195609758 ps
CPU time 1.64 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 214236 kb
Host smart-6aa915e9-7ad7-44ed-9591-1b986a70711e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896937525 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3896937525
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2871886206
Short name T944
Test name
Test status
Simulation time 55912064 ps
CPU time 0.97 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:02 PM PDT 24
Peak memory 205716 kb
Host smart-c0e0b967-8bc9-4eec-9158-18a3c2e83322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871886206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2871886206
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2327546939
Short name T921
Test name
Test status
Simulation time 43371662 ps
CPU time 0.87 seconds
Started Jun 13 01:00:01 PM PDT 24
Finished Jun 13 01:00:03 PM PDT 24
Peak memory 205680 kb
Host smart-cbd6eae0-e7d5-4623-a3bb-2a01d113928c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327546939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2327546939
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.738669502
Short name T1052
Test name
Test status
Simulation time 1485385930 ps
CPU time 2.54 seconds
Started Jun 13 12:59:59 PM PDT 24
Finished Jun 13 01:00:03 PM PDT 24
Peak memory 205932 kb
Host smart-599cfc6f-7c1e-40b1-8276-aedd63ad4f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738669502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.738669502
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.225678529
Short name T136
Test name
Test status
Simulation time 151871337 ps
CPU time 1.55 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:05 PM PDT 24
Peak memory 214568 kb
Host smart-f2c55080-6c14-4db0-b3ef-16a724c271c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225678529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.225678529
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.644054745
Short name T986
Test name
Test status
Simulation time 113266146 ps
CPU time 4.17 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 220592 kb
Host smart-f9b8674f-910d-4d5f-b4c5-4d99a67d9f4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644054745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.644054745
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3417927332
Short name T1015
Test name
Test status
Simulation time 28710833 ps
CPU time 1.82 seconds
Started Jun 13 01:00:01 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 214152 kb
Host smart-e639c368-02f3-4aaa-8a32-6055c2b354dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417927332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3417927332
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.909869527
Short name T969
Test name
Test status
Simulation time 37528971 ps
CPU time 1.87 seconds
Started Jun 13 01:00:09 PM PDT 24
Finished Jun 13 01:00:12 PM PDT 24
Peak memory 214136 kb
Host smart-5cad51ec-2fdb-4530-beb0-c8abfe3c6482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909869527 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.909869527
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2257162971
Short name T1028
Test name
Test status
Simulation time 26671058 ps
CPU time 1.65 seconds
Started Jun 13 01:00:13 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 205964 kb
Host smart-6bb8fa5a-e0e1-44f7-8252-f2d62af82791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257162971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2257162971
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.402005741
Short name T941
Test name
Test status
Simulation time 10520667 ps
CPU time 0.8 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:12 PM PDT 24
Peak memory 205660 kb
Host smart-2365ff3c-e902-4746-a4db-5d6cb89bf3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402005741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.402005741
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2857122002
Short name T987
Test name
Test status
Simulation time 125466015 ps
CPU time 1.74 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 205888 kb
Host smart-e7dbf80b-b87e-4076-82be-d192979fe7c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857122002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2857122002
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3209706716
Short name T1026
Test name
Test status
Simulation time 67122518 ps
CPU time 1.45 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 214472 kb
Host smart-44363174-0e93-46ae-b82a-c29cb9e5a2b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209706716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3209706716
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2185150861
Short name T1027
Test name
Test status
Simulation time 23149109 ps
CPU time 1.71 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 214080 kb
Host smart-42e77e1e-9be4-4c9b-86fe-31ce51e4a286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185150861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2185150861
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2534859022
Short name T190
Test name
Test status
Simulation time 115629548 ps
CPU time 5 seconds
Started Jun 13 01:00:16 PM PDT 24
Finished Jun 13 01:00:21 PM PDT 24
Peak memory 214084 kb
Host smart-2584cb3f-4179-4bc2-b2ff-37d7882db3bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534859022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2534859022
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.524574834
Short name T932
Test name
Test status
Simulation time 97143496 ps
CPU time 1.56 seconds
Started Jun 13 01:00:14 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 214048 kb
Host smart-89b50ac1-5cc3-4d06-b73b-f16aa177aadc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524574834 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.524574834
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3187821476
Short name T1045
Test name
Test status
Simulation time 23227681 ps
CPU time 1.14 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 205980 kb
Host smart-42548254-8caa-43c7-9a0a-5d9d9e8979a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187821476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3187821476
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2935010430
Short name T1014
Test name
Test status
Simulation time 11244478 ps
CPU time 0.79 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205588 kb
Host smart-09dc0fc7-7ff0-42cf-94d9-689b1d766ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935010430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2935010430
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.831369570
Short name T937
Test name
Test status
Simulation time 483211594 ps
CPU time 3.03 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 205964 kb
Host smart-041fd5ef-bf76-49f2-9712-e77726e31eeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831369570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.831369570
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3035922308
Short name T981
Test name
Test status
Simulation time 283417904 ps
CPU time 1.8 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 214452 kb
Host smart-7dad8b96-cb2d-4873-8d62-d74539c77813
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035922308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3035922308
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2730310255
Short name T1024
Test name
Test status
Simulation time 541376593 ps
CPU time 4.83 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 214440 kb
Host smart-c1491d73-6813-467d-ae58-4e4afe7a4bad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730310255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2730310255
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3511015308
Short name T1001
Test name
Test status
Simulation time 530701650 ps
CPU time 4.84 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 214120 kb
Host smart-11683592-6f5d-4baf-9149-2f0502f9ba65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511015308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3511015308
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.610288595
Short name T183
Test name
Test status
Simulation time 419021583 ps
CPU time 3.44 seconds
Started Jun 13 01:00:14 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 214212 kb
Host smart-7478f806-80fc-4dec-8dd6-e34b4b5acc69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610288595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.610288595
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.286465200
Short name T966
Test name
Test status
Simulation time 350023368 ps
CPU time 1.61 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 214200 kb
Host smart-0aa06a47-ed53-4b1d-9324-7b16efcf5f8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286465200 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.286465200
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3468867190
Short name T1043
Test name
Test status
Simulation time 168282216 ps
CPU time 1.52 seconds
Started Jun 13 01:00:14 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 205744 kb
Host smart-229565c0-2874-406f-a27d-91ac003d9d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468867190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3468867190
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1810576473
Short name T1067
Test name
Test status
Simulation time 18503845 ps
CPU time 0.83 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205660 kb
Host smart-f4d37799-4a70-4691-8ca8-1000284ae1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810576473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1810576473
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.99300700
Short name T991
Test name
Test status
Simulation time 49195870 ps
CPU time 1.79 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 206036 kb
Host smart-b93cf128-d000-4413-89af-8109c88ec481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99300700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sam
e_csr_outstanding.99300700
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.668516797
Short name T1044
Test name
Test status
Simulation time 1643881625 ps
CPU time 2.7 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 214452 kb
Host smart-631bfed5-bd7d-4a6a-adaf-6c15a0516f2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668516797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.668516797
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.780985383
Short name T1056
Test name
Test status
Simulation time 165356962 ps
CPU time 2.1 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 214160 kb
Host smart-77618ae2-77df-4550-a4f1-d6611139f94b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780985383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.780985383
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3441922630
Short name T167
Test name
Test status
Simulation time 817706701 ps
CPU time 5.88 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 214148 kb
Host smart-68f3ae4d-a816-4d57-a239-86ad63a9a1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441922630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3441922630
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1856104510
Short name T1012
Test name
Test status
Simulation time 26453333 ps
CPU time 1.81 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 214236 kb
Host smart-fba20750-6e51-4cde-abcf-8666b68caa79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856104510 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1856104510
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.809349330
Short name T1047
Test name
Test status
Simulation time 29307202 ps
CPU time 1.54 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205964 kb
Host smart-284e18b8-f019-442a-b706-e8e7a92e0553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809349330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.809349330
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3732318580
Short name T1046
Test name
Test status
Simulation time 46219473 ps
CPU time 0.83 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205676 kb
Host smart-dba56a59-658b-4deb-9dec-12a99eb20c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732318580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3732318580
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3366571311
Short name T1077
Test name
Test status
Simulation time 50296262 ps
CPU time 1.68 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 205948 kb
Host smart-fcf99c70-28bc-4e0a-b220-60d21c62096c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366571311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3366571311
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4251996217
Short name T1048
Test name
Test status
Simulation time 157127010 ps
CPU time 2.11 seconds
Started Jun 13 01:00:08 PM PDT 24
Finished Jun 13 01:00:11 PM PDT 24
Peak memory 214468 kb
Host smart-d7c8004a-fed6-4ee5-8243-e02cec1c3663
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251996217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4251996217
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3044014813
Short name T984
Test name
Test status
Simulation time 926853123 ps
CPU time 12.8 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 222508 kb
Host smart-c4054b63-d68d-450e-88ff-448077cde75a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044014813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3044014813
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1399792326
Short name T964
Test name
Test status
Simulation time 62564890 ps
CPU time 1.99 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 216236 kb
Host smart-50df7c40-b3bb-42e8-a4b8-b359762eb3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399792326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1399792326
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4140764698
Short name T1074
Test name
Test status
Simulation time 31259731 ps
CPU time 1.2 seconds
Started Jun 13 01:00:16 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 214020 kb
Host smart-397acafb-c46b-4fc2-a556-906fab6c9f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140764698 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4140764698
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1879605928
Short name T1008
Test name
Test status
Simulation time 9965053 ps
CPU time 0.99 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:22 PM PDT 24
Peak memory 205468 kb
Host smart-535e8854-3559-4c12-87f5-5762ad113cb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879605928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1879605928
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2084139871
Short name T1065
Test name
Test status
Simulation time 9112386 ps
CPU time 0.85 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205564 kb
Host smart-696758fe-c108-457d-ac7f-ec639884f612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084139871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2084139871
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3266718088
Short name T1064
Test name
Test status
Simulation time 202964317 ps
CPU time 1.78 seconds
Started Jun 13 01:00:16 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 206036 kb
Host smart-92735ef6-24bd-4562-a3e6-265d8ebdc908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266718088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3266718088
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1049435649
Short name T959
Test name
Test status
Simulation time 254245214 ps
CPU time 2.11 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 214480 kb
Host smart-55ede57e-b976-4587-b619-db91156207b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049435649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1049435649
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.266699268
Short name T135
Test name
Test status
Simulation time 327027505 ps
CPU time 9.38 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:20 PM PDT 24
Peak memory 214580 kb
Host smart-78f611c2-7e3f-4502-b3c5-03e437a52685
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266699268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.266699268
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1972816509
Short name T1010
Test name
Test status
Simulation time 272089486 ps
CPU time 1.73 seconds
Started Jun 13 01:00:09 PM PDT 24
Finished Jun 13 01:00:11 PM PDT 24
Peak memory 205760 kb
Host smart-9f60011d-e5d2-49c3-ba45-fab5e1bb9ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972816509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1972816509
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4045218479
Short name T961
Test name
Test status
Simulation time 34185341 ps
CPU time 1.63 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:20 PM PDT 24
Peak memory 217280 kb
Host smart-6edd5afb-f7ae-4823-9a69-861330d4853a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045218479 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4045218479
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2027190102
Short name T1017
Test name
Test status
Simulation time 12832457 ps
CPU time 0.84 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:21 PM PDT 24
Peak memory 205512 kb
Host smart-0987ddee-7658-480a-bfd0-5b8fa4427e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027190102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2027190102
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.800704266
Short name T976
Test name
Test status
Simulation time 9293798 ps
CPU time 0.8 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 205668 kb
Host smart-7256b375-e57b-441f-9b61-be56ba3038c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800704266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.800704266
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.595497738
Short name T1011
Test name
Test status
Simulation time 94310797 ps
CPU time 2.21 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:20 PM PDT 24
Peak memory 205972 kb
Host smart-a8e1b4ac-6f3c-496a-bcfd-6022f2623663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595497738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.595497738
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3727874230
Short name T975
Test name
Test status
Simulation time 252496195 ps
CPU time 1.8 seconds
Started Jun 13 01:00:14 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 214452 kb
Host smart-bf016b42-7738-41c5-80d7-202d413fb236
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727874230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3727874230
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.75913476
Short name T982
Test name
Test status
Simulation time 266159434 ps
CPU time 5.4 seconds
Started Jun 13 01:00:14 PM PDT 24
Finished Jun 13 01:00:20 PM PDT 24
Peak memory 214464 kb
Host smart-e63a42a3-b250-4a34-aeac-ec285830d014
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75913476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.k
eymgr_shadow_reg_errors_with_csr_rw.75913476
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3542865262
Short name T1062
Test name
Test status
Simulation time 43763040 ps
CPU time 2.07 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 214092 kb
Host smart-8aca5109-cee1-484c-b720-606202efefae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542865262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3542865262
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1608603485
Short name T180
Test name
Test status
Simulation time 52603366 ps
CPU time 2.95 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 214052 kb
Host smart-48420b73-0211-4f86-967c-4bb8895eb414
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608603485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1608603485
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.9174186
Short name T1022
Test name
Test status
Simulation time 28194108 ps
CPU time 1.86 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 214296 kb
Host smart-167bf708-81a5-40fd-b548-21a91559eac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9174186 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.9174186
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3841157045
Short name T929
Test name
Test status
Simulation time 168128908 ps
CPU time 1.12 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:20 PM PDT 24
Peak memory 205964 kb
Host smart-a661c420-d6bc-4515-8620-a40cfc532e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841157045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3841157045
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3357648047
Short name T1060
Test name
Test status
Simulation time 27376562 ps
CPU time 0.69 seconds
Started Jun 13 01:00:19 PM PDT 24
Finished Jun 13 01:00:21 PM PDT 24
Peak memory 205664 kb
Host smart-6a4e58f0-62e9-4645-b42d-6dcfdd949123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357648047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3357648047
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1427805459
Short name T978
Test name
Test status
Simulation time 81653581 ps
CPU time 1.45 seconds
Started Jun 13 01:00:19 PM PDT 24
Finished Jun 13 01:00:22 PM PDT 24
Peak memory 205908 kb
Host smart-2cdcab45-46c8-4907-aa0d-c1cf580038b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427805459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1427805459
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.765339701
Short name T127
Test name
Test status
Simulation time 178468435 ps
CPU time 1.77 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:21 PM PDT 24
Peak memory 214412 kb
Host smart-3ffdd1e6-0560-4481-8910-a822bb6ddd73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765339701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.765339701
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1066978920
Short name T1030
Test name
Test status
Simulation time 886042802 ps
CPU time 10.77 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:29 PM PDT 24
Peak memory 214520 kb
Host smart-45a826cb-8c84-49c9-b5a8-6b80c987087f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066978920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1066978920
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2356207838
Short name T933
Test name
Test status
Simulation time 91892546 ps
CPU time 2.94 seconds
Started Jun 13 01:00:19 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 214136 kb
Host smart-6db7846c-b246-4d48-b0ca-c3bf363a3ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356207838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2356207838
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2795014534
Short name T182
Test name
Test status
Simulation time 2467454352 ps
CPU time 7.01 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:27 PM PDT 24
Peak memory 214196 kb
Host smart-0878ac82-6372-4d4a-9746-227fc4a973ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795014534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2795014534
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3367115576
Short name T967
Test name
Test status
Simulation time 23726218 ps
CPU time 1.15 seconds
Started Jun 13 01:00:14 PM PDT 24
Finished Jun 13 01:00:16 PM PDT 24
Peak memory 205944 kb
Host smart-1e264d84-227e-4e7e-94d3-4e99e98f7ec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367115576 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3367115576
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.119995673
Short name T997
Test name
Test status
Simulation time 15360767 ps
CPU time 1.26 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 205900 kb
Host smart-cea65839-8417-4626-92b2-4ed70e116cbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119995673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.119995673
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1905354917
Short name T1072
Test name
Test status
Simulation time 10266315 ps
CPU time 0.79 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:20 PM PDT 24
Peak memory 205616 kb
Host smart-d9372a4a-f24a-413a-a23a-90c1a715dfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905354917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1905354917
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1967623671
Short name T995
Test name
Test status
Simulation time 90149152 ps
CPU time 3.43 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 205708 kb
Host smart-04d94bf0-5210-47cd-8aa4-a176b3ae71cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967623671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1967623671
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.962916958
Short name T1016
Test name
Test status
Simulation time 2091669464 ps
CPU time 5.66 seconds
Started Jun 13 01:00:21 PM PDT 24
Finished Jun 13 01:00:27 PM PDT 24
Peak memory 214460 kb
Host smart-59f921e1-77c3-4469-9159-eeba76c23341
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962916958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.962916958
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2915539743
Short name T999
Test name
Test status
Simulation time 521784342 ps
CPU time 3.55 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 214112 kb
Host smart-2e3d7f09-4fb9-476f-b7a9-efcab1e9b272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915539743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2915539743
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.127290689
Short name T173
Test name
Test status
Simulation time 206504795 ps
CPU time 1.91 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 214244 kb
Host smart-39f84454-0e92-4e9a-a735-fff9b1b1c073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127290689 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.127290689
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.637052446
Short name T1073
Test name
Test status
Simulation time 68888715 ps
CPU time 1 seconds
Started Jun 13 01:00:17 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 205768 kb
Host smart-8641b5f3-47ff-4f4c-ba33-b6aa0cedcfe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637052446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.637052446
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3238133890
Short name T1033
Test name
Test status
Simulation time 45790765 ps
CPU time 0.69 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 205616 kb
Host smart-8fea0bc4-c1ef-481f-8c6f-f957167f3a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238133890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3238133890
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.432765461
Short name T161
Test name
Test status
Simulation time 692977191 ps
CPU time 1.51 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 205876 kb
Host smart-83daa915-71e9-4673-9fa2-f4955f53d44a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432765461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.432765461
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1006491994
Short name T132
Test name
Test status
Simulation time 74184117 ps
CPU time 1.83 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 214372 kb
Host smart-23b7f07a-214f-44aa-8065-a23a5ef53c04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006491994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1006491994
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2177945109
Short name T954
Test name
Test status
Simulation time 361498692 ps
CPU time 5.11 seconds
Started Jun 13 01:00:18 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 220028 kb
Host smart-dea984dc-5d50-4fcb-995d-cca6088a114d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177945109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2177945109
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1980183623
Short name T973
Test name
Test status
Simulation time 87221356 ps
CPU time 2.46 seconds
Started Jun 13 01:00:15 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 214160 kb
Host smart-fb9dba57-2386-4014-9c56-bfe7e98a7907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980183623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1980183623
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2178127486
Short name T188
Test name
Test status
Simulation time 346469748 ps
CPU time 4.05 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:25 PM PDT 24
Peak memory 214000 kb
Host smart-fa40db45-4e9d-444f-a48c-d71270689cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178127486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2178127486
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4166849906
Short name T1083
Test name
Test status
Simulation time 37289308 ps
CPU time 2.13 seconds
Started Jun 13 01:00:23 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 214160 kb
Host smart-a21d48d2-4f87-4230-934d-d1d8c5bcb3cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166849906 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.4166849906
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2135777056
Short name T1041
Test name
Test status
Simulation time 82193767 ps
CPU time 0.83 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:21 PM PDT 24
Peak memory 205768 kb
Host smart-52c56776-854c-4d17-aec5-623f254a98e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135777056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2135777056
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.976379101
Short name T977
Test name
Test status
Simulation time 37364421 ps
CPU time 0.78 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 205644 kb
Host smart-5bf83eb4-eedb-4066-b497-969efa4e497d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976379101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.976379101
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.240595142
Short name T1084
Test name
Test status
Simulation time 272251664 ps
CPU time 2.22 seconds
Started Jun 13 01:00:26 PM PDT 24
Finished Jun 13 01:00:28 PM PDT 24
Peak memory 205856 kb
Host smart-1eb8e38a-49aa-4080-8747-6e238e7abee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240595142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.240595142
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2925776110
Short name T1025
Test name
Test status
Simulation time 312149778 ps
CPU time 3.02 seconds
Started Jun 13 01:00:20 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 214392 kb
Host smart-0c6342f9-0028-404b-b8f5-f9cdffe0845c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925776110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2925776110
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1000054468
Short name T1068
Test name
Test status
Simulation time 655022727 ps
CPU time 10.64 seconds
Started Jun 13 01:00:19 PM PDT 24
Finished Jun 13 01:00:31 PM PDT 24
Peak memory 214468 kb
Host smart-a154547c-9804-44e5-b8b0-3e6e01a8f478
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000054468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1000054468
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2706072441
Short name T926
Test name
Test status
Simulation time 95519713 ps
CPU time 3.71 seconds
Started Jun 13 01:00:24 PM PDT 24
Finished Jun 13 01:00:28 PM PDT 24
Peak memory 214124 kb
Host smart-719659e5-0cc3-402d-a0d0-3615ec0d3011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706072441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2706072441
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.510092785
Short name T980
Test name
Test status
Simulation time 232542440 ps
CPU time 8.69 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 205952 kb
Host smart-f939dd62-97f2-4b99-99ce-216efed14817
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510092785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.510092785
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2981364796
Short name T1004
Test name
Test status
Simulation time 532000569 ps
CPU time 7.7 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 206032 kb
Host smart-60d760fa-7b12-48f2-9d77-47c3130e728d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981364796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
981364796
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.613564576
Short name T958
Test name
Test status
Simulation time 53919939 ps
CPU time 1.75 seconds
Started Jun 13 12:59:56 PM PDT 24
Finished Jun 13 12:59:58 PM PDT 24
Peak memory 205888 kb
Host smart-80fe2974-58ae-40c7-bad4-eb5518579702
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613564576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.613564576
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1401598278
Short name T938
Test name
Test status
Simulation time 32165095 ps
CPU time 2.12 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:05 PM PDT 24
Peak memory 214188 kb
Host smart-e8d9b705-1c69-44af-bfeb-2eb967cd069e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401598278 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1401598278
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1333948781
Short name T1053
Test name
Test status
Simulation time 42556385 ps
CPU time 1.22 seconds
Started Jun 13 12:59:59 PM PDT 24
Finished Jun 13 01:00:01 PM PDT 24
Peak memory 206036 kb
Host smart-665a94e9-949d-4865-8b68-a55e010733f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333948781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1333948781
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4195233250
Short name T989
Test name
Test status
Simulation time 21515793 ps
CPU time 0.69 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 205720 kb
Host smart-3782b478-7b17-400b-82d1-b8a9e6b653c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195233250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4195233250
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.439813669
Short name T988
Test name
Test status
Simulation time 66886023 ps
CPU time 2.05 seconds
Started Jun 13 12:59:59 PM PDT 24
Finished Jun 13 01:00:03 PM PDT 24
Peak memory 205972 kb
Host smart-c10723f3-0ba5-412b-9a94-92ffb4114192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439813669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.439813669
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4042785073
Short name T968
Test name
Test status
Simulation time 768825512 ps
CPU time 3.03 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 214312 kb
Host smart-de4897a2-2d7f-427a-bfc4-bc067d243140
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042785073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4042785073
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3425148020
Short name T164
Test name
Test status
Simulation time 313835153 ps
CPU time 6.22 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 214456 kb
Host smart-de76fcc3-aa26-4fe6-a7ed-e31804597a99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425148020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3425148020
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.753387663
Short name T931
Test name
Test status
Simulation time 186304053 ps
CPU time 3.19 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 214160 kb
Host smart-e0573513-3881-43f6-8fff-8128a707558d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753387663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.753387663
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.556961826
Short name T1009
Test name
Test status
Simulation time 215841898 ps
CPU time 3.46 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:03 PM PDT 24
Peak memory 205848 kb
Host smart-0a2bfc6b-e12a-49dc-9b87-707551af8709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556961826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
556961826
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.883613379
Short name T974
Test name
Test status
Simulation time 13280182 ps
CPU time 0.71 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 205660 kb
Host smart-7619cbbe-2c32-4f08-8196-c9fd02452756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883613379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.883613379
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.912761923
Short name T1079
Test name
Test status
Simulation time 23427272 ps
CPU time 0.95 seconds
Started Jun 13 01:00:21 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 205880 kb
Host smart-ee49eb84-ca8e-4ee8-a9f5-3bccecf83fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912761923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.912761923
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.630583457
Short name T935
Test name
Test status
Simulation time 109934743 ps
CPU time 0.73 seconds
Started Jun 13 01:00:24 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 205644 kb
Host smart-478b81c9-ee05-4d13-9e2f-b2a6e1d0e4a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630583457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.630583457
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3474439280
Short name T1039
Test name
Test status
Simulation time 11719568 ps
CPU time 0.84 seconds
Started Jun 13 01:00:24 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 205640 kb
Host smart-2bdbf49c-f9c9-4ece-85b3-986aa7f7eada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474439280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3474439280
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.214978833
Short name T1078
Test name
Test status
Simulation time 62331709 ps
CPU time 0.72 seconds
Started Jun 13 01:00:23 PM PDT 24
Finished Jun 13 01:00:25 PM PDT 24
Peak memory 205524 kb
Host smart-91d2a1a2-2394-4240-9a17-2b49499a62ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214978833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.214978833
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2786757677
Short name T923
Test name
Test status
Simulation time 101015598 ps
CPU time 0.74 seconds
Started Jun 13 01:00:24 PM PDT 24
Finished Jun 13 01:00:25 PM PDT 24
Peak memory 205676 kb
Host smart-7125a3a0-9d9d-4ab3-8f56-417ca64f23e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786757677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2786757677
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.589092861
Short name T1032
Test name
Test status
Simulation time 12622770 ps
CPU time 0.73 seconds
Started Jun 13 01:00:25 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 205568 kb
Host smart-244a45c3-ac58-488b-a5e5-787be5ae83b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589092861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.589092861
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.922331583
Short name T940
Test name
Test status
Simulation time 19699073 ps
CPU time 0.82 seconds
Started Jun 13 01:00:23 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 205680 kb
Host smart-1f82aea6-9f6c-4cd0-a549-76e895dfca2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922331583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.922331583
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1827412382
Short name T928
Test name
Test status
Simulation time 15538437 ps
CPU time 0.82 seconds
Started Jun 13 01:00:21 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 205564 kb
Host smart-e28afa6a-4838-4ba3-b34e-daf7c242c8d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827412382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1827412382
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.704585630
Short name T924
Test name
Test status
Simulation time 11619546 ps
CPU time 0.85 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:24 PM PDT 24
Peak memory 205572 kb
Host smart-37ca433b-1ca0-4838-94b8-ec5b926b57af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704585630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.704585630
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3706914576
Short name T1066
Test name
Test status
Simulation time 379196246 ps
CPU time 7.93 seconds
Started Jun 13 12:59:59 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 205948 kb
Host smart-c7a7b74c-2b8a-4559-83d3-d4956d0b8217
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706914576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
706914576
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3321202983
Short name T934
Test name
Test status
Simulation time 1289289603 ps
CPU time 17.02 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 205940 kb
Host smart-0b6e8ecc-7f82-47a9-8a49-badc9903840d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321202983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
321202983
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3977841204
Short name T948
Test name
Test status
Simulation time 163779862 ps
CPU time 1.16 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:00 PM PDT 24
Peak memory 205952 kb
Host smart-e57a15c3-bacd-445d-a10b-11aae2a62223
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977841204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
977841204
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.849660286
Short name T919
Test name
Test status
Simulation time 24723905 ps
CPU time 1.38 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:01 PM PDT 24
Peak memory 214120 kb
Host smart-c858634e-1856-43cd-8b1a-9afec49a9a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849660286 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.849660286
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.147638406
Short name T996
Test name
Test status
Simulation time 29642173 ps
CPU time 1.54 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 205748 kb
Host smart-ed3f39a1-7950-4b06-af99-f034ceb1fa0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147638406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.147638406
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1242074892
Short name T942
Test name
Test status
Simulation time 7939287 ps
CPU time 0.83 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:02 PM PDT 24
Peak memory 205680 kb
Host smart-732e598d-ddfa-473c-812c-e7dabbe61a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242074892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1242074892
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4012579944
Short name T1005
Test name
Test status
Simulation time 37823758 ps
CPU time 2.12 seconds
Started Jun 13 01:00:01 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 205992 kb
Host smart-0f726146-95d6-4820-8896-ab112b541202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012579944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4012579944
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1286867082
Short name T1007
Test name
Test status
Simulation time 80891589 ps
CPU time 1.3 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:01 PM PDT 24
Peak memory 214420 kb
Host smart-23f8cdcf-6bb4-422c-85d8-1b67151ec4f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286867082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1286867082
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2086113762
Short name T1085
Test name
Test status
Simulation time 169478586 ps
CPU time 4.55 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 222432 kb
Host smart-bc1b5437-b6df-46fa-908c-d2c542763ae9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086113762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2086113762
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3983680722
Short name T1035
Test name
Test status
Simulation time 857114926 ps
CPU time 5.05 seconds
Started Jun 13 12:59:59 PM PDT 24
Finished Jun 13 01:00:05 PM PDT 24
Peak memory 214096 kb
Host smart-3f6a8f84-bc9d-4610-a33d-b72194f6f5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983680722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3983680722
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1574426601
Short name T993
Test name
Test status
Simulation time 20914275 ps
CPU time 0.75 seconds
Started Jun 13 01:00:24 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 205592 kb
Host smart-dc357c7f-fbe0-475c-8cd6-b0eb4a4d7d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574426601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1574426601
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3496135267
Short name T1082
Test name
Test status
Simulation time 126574662 ps
CPU time 0.85 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 205596 kb
Host smart-67d3ffbf-fe57-419a-8e76-5ed9835522cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496135267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3496135267
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.370666571
Short name T1031
Test name
Test status
Simulation time 41419684 ps
CPU time 0.73 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 205672 kb
Host smart-e986f554-d894-4334-a7e5-9f8c2c89b6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370666571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.370666571
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2294693812
Short name T925
Test name
Test status
Simulation time 63831561 ps
CPU time 0.79 seconds
Started Jun 13 01:00:25 PM PDT 24
Finished Jun 13 01:00:27 PM PDT 24
Peak memory 205644 kb
Host smart-c35873e0-ddc6-4b93-b0c3-365fc521eb9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294693812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2294693812
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3402854209
Short name T1040
Test name
Test status
Simulation time 27200019 ps
CPU time 0.72 seconds
Started Jun 13 01:00:21 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 205664 kb
Host smart-47ce7e1e-2fb9-4e51-a75f-2bc193653fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402854209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3402854209
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3558572042
Short name T1054
Test name
Test status
Simulation time 30198812 ps
CPU time 0.75 seconds
Started Jun 13 01:00:22 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 205652 kb
Host smart-1537e66d-ad0a-400d-9815-1aec2829b7f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558572042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3558572042
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1458701173
Short name T930
Test name
Test status
Simulation time 38254603 ps
CPU time 0.85 seconds
Started Jun 13 01:00:25 PM PDT 24
Finished Jun 13 01:00:27 PM PDT 24
Peak memory 205612 kb
Host smart-bc2f28cf-cdc5-49f4-a06c-c3ae6b6f2cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458701173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1458701173
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2560997554
Short name T943
Test name
Test status
Simulation time 39092645 ps
CPU time 0.8 seconds
Started Jun 13 01:00:24 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 205544 kb
Host smart-2be9083d-64a8-4c65-aa1e-38421073c5e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560997554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2560997554
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3737881251
Short name T1038
Test name
Test status
Simulation time 42394547 ps
CPU time 0.73 seconds
Started Jun 13 01:00:27 PM PDT 24
Finished Jun 13 01:00:29 PM PDT 24
Peak memory 205588 kb
Host smart-dd41ec9c-202e-4476-a76a-ab19452981d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737881251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3737881251
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1852000690
Short name T1029
Test name
Test status
Simulation time 39385162 ps
CPU time 0.77 seconds
Started Jun 13 01:00:27 PM PDT 24
Finished Jun 13 01:00:29 PM PDT 24
Peak memory 205568 kb
Host smart-1e0754b2-a8ea-4bb1-ae8d-06db657bbef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852000690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1852000690
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.310339354
Short name T1075
Test name
Test status
Simulation time 262411113 ps
CPU time 5.76 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:11 PM PDT 24
Peak memory 205968 kb
Host smart-791eb00e-52bc-4dd4-b08b-a0fe622977e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310339354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.310339354
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3412092582
Short name T920
Test name
Test status
Simulation time 131807542 ps
CPU time 8.08 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 206044 kb
Host smart-7a0dd2e4-2b7f-4075-8b32-aa3576f25536
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412092582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
412092582
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.845411408
Short name T994
Test name
Test status
Simulation time 64192153 ps
CPU time 1.11 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 205976 kb
Host smart-eaa270bd-5a6d-40e0-a76d-ceb768b0b284
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845411408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.845411408
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.16389911
Short name T1018
Test name
Test status
Simulation time 31995894 ps
CPU time 1.24 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 214252 kb
Host smart-854dbac3-b299-4afd-b1ba-5f72e2d2a026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389911 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.16389911
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.388571405
Short name T214
Test name
Test status
Simulation time 61575478 ps
CPU time 0.97 seconds
Started Jun 13 01:00:06 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 205792 kb
Host smart-13cc74a3-4795-4cd3-aaa0-4eba925502ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388571405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.388571405
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.898870393
Short name T1086
Test name
Test status
Simulation time 13539823 ps
CPU time 0.74 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:02 PM PDT 24
Peak memory 205672 kb
Host smart-520af555-cbaf-417b-abf5-95a63d95d6a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898870393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.898870393
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3598777365
Short name T162
Test name
Test status
Simulation time 207586966 ps
CPU time 2.77 seconds
Started Jun 13 01:00:05 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 205944 kb
Host smart-c9e14a75-7839-47e8-a731-cf74ba77f880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598777365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3598777365
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2882038816
Short name T133
Test name
Test status
Simulation time 123195121 ps
CPU time 2.99 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 214588 kb
Host smart-9d239bba-3bf3-40b6-8d07-b04ad5a3d53c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882038816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2882038816
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2855472742
Short name T1081
Test name
Test status
Simulation time 591283179 ps
CPU time 10.04 seconds
Started Jun 13 12:59:58 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 214364 kb
Host smart-f309c734-bb70-4d0f-90ce-24ca201a66a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855472742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2855472742
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2999483372
Short name T946
Test name
Test status
Simulation time 814801762 ps
CPU time 3.1 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:01 PM PDT 24
Peak memory 216632 kb
Host smart-8dc5f347-7865-4929-bc63-a52e25e04438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999483372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2999483372
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3893212415
Short name T177
Test name
Test status
Simulation time 179001558 ps
CPU time 5.07 seconds
Started Jun 13 01:00:00 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 206084 kb
Host smart-91a463c8-c727-4ab9-b5e5-c383c987e920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893212415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3893212415
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4102229640
Short name T970
Test name
Test status
Simulation time 13084578 ps
CPU time 0.94 seconds
Started Jun 13 01:00:29 PM PDT 24
Finished Jun 13 01:00:30 PM PDT 24
Peak memory 205760 kb
Host smart-0a6894f1-e906-46ca-97d7-aff969178d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102229640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4102229640
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.347138920
Short name T1087
Test name
Test status
Simulation time 49117836 ps
CPU time 0.88 seconds
Started Jun 13 01:00:37 PM PDT 24
Finished Jun 13 01:00:39 PM PDT 24
Peak memory 205680 kb
Host smart-9822da4e-ccfa-483f-b3b9-e854ee596e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347138920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.347138920
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1647394990
Short name T1049
Test name
Test status
Simulation time 77044873 ps
CPU time 0.72 seconds
Started Jun 13 01:00:29 PM PDT 24
Finished Jun 13 01:00:31 PM PDT 24
Peak memory 205584 kb
Host smart-fc7cfa8b-32c4-4ab3-9fab-b9fddfa1aeec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647394990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1647394990
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2878744809
Short name T927
Test name
Test status
Simulation time 12312853 ps
CPU time 0.91 seconds
Started Jun 13 01:00:28 PM PDT 24
Finished Jun 13 01:00:30 PM PDT 24
Peak memory 205596 kb
Host smart-0eb252b4-d7ec-4e39-a14c-4b005734c667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878744809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2878744809
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.654780031
Short name T1002
Test name
Test status
Simulation time 93956192 ps
CPU time 0.79 seconds
Started Jun 13 01:00:26 PM PDT 24
Finished Jun 13 01:00:27 PM PDT 24
Peak memory 205580 kb
Host smart-f54259f7-3a96-4cbd-97dc-c2f26d913f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654780031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.654780031
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.804871855
Short name T939
Test name
Test status
Simulation time 16720501 ps
CPU time 0.74 seconds
Started Jun 13 01:00:30 PM PDT 24
Finished Jun 13 01:00:31 PM PDT 24
Peak memory 205592 kb
Host smart-c7777ac4-119b-48d4-b784-f605a6dd372b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804871855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.804871855
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.494021642
Short name T1070
Test name
Test status
Simulation time 11746625 ps
CPU time 0.75 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:00:41 PM PDT 24
Peak memory 205596 kb
Host smart-aca96033-ac72-4ffc-8320-d91bba036437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494021642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.494021642
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.290390747
Short name T1042
Test name
Test status
Simulation time 42489882 ps
CPU time 0.7 seconds
Started Jun 13 01:00:27 PM PDT 24
Finished Jun 13 01:00:28 PM PDT 24
Peak memory 205548 kb
Host smart-6dcf059a-9fd3-4f5c-ab90-d5744cf44109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290390747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.290390747
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1799644922
Short name T979
Test name
Test status
Simulation time 43283627 ps
CPU time 0.83 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:00:42 PM PDT 24
Peak memory 205668 kb
Host smart-7e91e705-4a7d-412b-a17b-c9be24e44b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799644922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1799644922
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.237895992
Short name T936
Test name
Test status
Simulation time 9517316 ps
CPU time 0.84 seconds
Started Jun 13 01:00:27 PM PDT 24
Finished Jun 13 01:00:29 PM PDT 24
Peak memory 205584 kb
Host smart-fd717e58-517f-41d3-bf59-8d03baeb64f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237895992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.237895992
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.685952143
Short name T1069
Test name
Test status
Simulation time 62901593 ps
CPU time 2.12 seconds
Started Jun 13 01:00:05 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 214252 kb
Host smart-69ad0520-cd60-4469-a68e-a19c61812004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685952143 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.685952143
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2552405656
Short name T1059
Test name
Test status
Simulation time 98782466 ps
CPU time 1.22 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 205980 kb
Host smart-39f4d445-d647-4616-ba39-98b3addc6155
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552405656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2552405656
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3878680537
Short name T951
Test name
Test status
Simulation time 84237227 ps
CPU time 0.86 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 205552 kb
Host smart-c768d5b3-7c2c-4b54-b064-6b7b63094f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878680537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3878680537
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3963086310
Short name T983
Test name
Test status
Simulation time 734925243 ps
CPU time 2.34 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 205952 kb
Host smart-60de60b9-041f-4335-a5ad-b64faa910b59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963086310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3963086310
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3037299894
Short name T990
Test name
Test status
Simulation time 174412265 ps
CPU time 1.54 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:05 PM PDT 24
Peak memory 214480 kb
Host smart-a8dad994-893c-4285-8817-57700e114f5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037299894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3037299894
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.760957048
Short name T960
Test name
Test status
Simulation time 731590657 ps
CPU time 4.82 seconds
Started Jun 13 01:00:06 PM PDT 24
Finished Jun 13 01:00:12 PM PDT 24
Peak memory 214444 kb
Host smart-cfcc9705-e2a0-409f-aa36-c2092087f3be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760957048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.760957048
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3165942866
Short name T1036
Test name
Test status
Simulation time 61600499 ps
CPU time 2.53 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 214084 kb
Host smart-3e8125a4-8c25-4482-b1b7-c59f942be762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165942866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3165942866
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2690874124
Short name T174
Test name
Test status
Simulation time 278653850 ps
CPU time 2.07 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 214136 kb
Host smart-30118668-a327-46c1-8a4d-91364fdb0a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690874124 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2690874124
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1529833515
Short name T160
Test name
Test status
Simulation time 64885515 ps
CPU time 1.03 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 205888 kb
Host smart-9fa06abd-7735-483b-b63c-341c0c60ed75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529833515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1529833515
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2278860737
Short name T957
Test name
Test status
Simulation time 16897555 ps
CPU time 0.67 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 205508 kb
Host smart-ddac364c-95d9-445a-b6fc-0146a1e5cda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278860737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2278860737
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4237554941
Short name T163
Test name
Test status
Simulation time 359949751 ps
CPU time 1.97 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 206000 kb
Host smart-a4fa705a-68d0-42bf-9b14-a19f683c3bb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237554941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4237554941
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.568612196
Short name T1050
Test name
Test status
Simulation time 185123364 ps
CPU time 1.74 seconds
Started Jun 13 01:00:06 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 214512 kb
Host smart-18658ba9-8bd5-48f8-adc6-cf9a3067c0a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568612196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.568612196
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4089624758
Short name T1055
Test name
Test status
Simulation time 873138175 ps
CPU time 5.12 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:10 PM PDT 24
Peak memory 220376 kb
Host smart-5575185b-2d99-4c7d-81f0-e03361bce5b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089624758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4089624758
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.350711445
Short name T953
Test name
Test status
Simulation time 534065406 ps
CPU time 4.03 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 214112 kb
Host smart-f584f331-1628-4150-b349-808b4a8ed5fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350711445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.350711445
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1386979181
Short name T1023
Test name
Test status
Simulation time 87378003 ps
CPU time 3.14 seconds
Started Jun 13 01:00:05 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 214208 kb
Host smart-a0a1d48e-0e71-41b1-9655-b782d225cb84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386979181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1386979181
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2591381930
Short name T922
Test name
Test status
Simulation time 92851841 ps
CPU time 1.19 seconds
Started Jun 13 01:00:08 PM PDT 24
Finished Jun 13 01:00:10 PM PDT 24
Peak memory 206060 kb
Host smart-faebaf0d-ce04-4e0a-9d8e-d11bdb262a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591381930 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2591381930
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2329714993
Short name T1000
Test name
Test status
Simulation time 22529192 ps
CPU time 1.08 seconds
Started Jun 13 01:00:06 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 205944 kb
Host smart-dd816620-0154-4759-9bfb-090694f23ab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329714993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2329714993
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.637094242
Short name T992
Test name
Test status
Simulation time 13322694 ps
CPU time 0.81 seconds
Started Jun 13 01:00:06 PM PDT 24
Finished Jun 13 01:00:08 PM PDT 24
Peak memory 205600 kb
Host smart-421e5aca-71d7-46f5-93ad-2cf96bdfc0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637094242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.637094242
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3663042920
Short name T952
Test name
Test status
Simulation time 95392072 ps
CPU time 4.02 seconds
Started Jun 13 01:00:05 PM PDT 24
Finished Jun 13 01:00:10 PM PDT 24
Peak memory 205952 kb
Host smart-578aa6ab-84a3-488d-bace-7483cf365c50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663042920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3663042920
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1248687701
Short name T129
Test name
Test status
Simulation time 37421277 ps
CPU time 1.85 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 214460 kb
Host smart-58a46f44-e2d7-4337-9519-f90108453e17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248687701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1248687701
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3376272627
Short name T1019
Test name
Test status
Simulation time 217562465 ps
CPU time 4.96 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:10 PM PDT 24
Peak memory 220120 kb
Host smart-eaada14e-cce8-45b7-8a00-ceae7e6b181f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376272627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3376272627
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2070023538
Short name T1080
Test name
Test status
Simulation time 210373663 ps
CPU time 1.33 seconds
Started Jun 13 01:00:04 PM PDT 24
Finished Jun 13 01:00:07 PM PDT 24
Peak memory 214004 kb
Host smart-496200ef-0769-46da-8851-eaf457359ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070023538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2070023538
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1007965648
Short name T176
Test name
Test status
Simulation time 488614377 ps
CPU time 10.11 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205960 kb
Host smart-20bc8f1b-ecee-4c5b-9866-a767ea1c0c77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007965648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1007965648
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1806580392
Short name T945
Test name
Test status
Simulation time 31893025 ps
CPU time 2.44 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 214200 kb
Host smart-4c350017-1ea6-480c-a518-9adc8aa3198d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806580392 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1806580392
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2280057949
Short name T998
Test name
Test status
Simulation time 44709385 ps
CPU time 1.09 seconds
Started Jun 13 01:00:16 PM PDT 24
Finished Jun 13 01:00:17 PM PDT 24
Peak memory 205792 kb
Host smart-726f2130-a231-4be1-89f9-96921a041b35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280057949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2280057949
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3047499389
Short name T1037
Test name
Test status
Simulation time 23678185 ps
CPU time 0.74 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 205872 kb
Host smart-7f121f34-f25a-47bc-93da-7160e63decee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047499389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3047499389
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3253008029
Short name T956
Test name
Test status
Simulation time 52234762 ps
CPU time 2.51 seconds
Started Jun 13 01:00:09 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 206056 kb
Host smart-996ccc66-30eb-4e11-8ac9-a65fc63966c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253008029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3253008029
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.946023273
Short name T1020
Test name
Test status
Simulation time 25543721 ps
CPU time 1.39 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:06 PM PDT 24
Peak memory 214460 kb
Host smart-880cdff6-83e6-4832-bff5-8bdf17216c3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946023273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.946023273
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.518096102
Short name T955
Test name
Test status
Simulation time 317601777 ps
CPU time 7.92 seconds
Started Jun 13 01:00:03 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 220452 kb
Host smart-cf44ccff-16f5-4dee-bcff-7b02aecb2839
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518096102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.518096102
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1555858054
Short name T985
Test name
Test status
Simulation time 79514159 ps
CPU time 3.19 seconds
Started Jun 13 01:00:05 PM PDT 24
Finished Jun 13 01:00:09 PM PDT 24
Peak memory 217168 kb
Host smart-4d66bbda-0793-4402-b0f8-6efd0cb4bc61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555858054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1555858054
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2117368187
Short name T1071
Test name
Test status
Simulation time 41507055 ps
CPU time 2 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 214224 kb
Host smart-c75ec4aa-aad3-4024-9094-8a4fd0b72399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117368187 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2117368187
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3441458286
Short name T1051
Test name
Test status
Simulation time 39583612 ps
CPU time 1.07 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 205932 kb
Host smart-f2ea9aaa-c89b-47d2-b291-bd29c710f993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441458286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3441458286
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2389220358
Short name T1003
Test name
Test status
Simulation time 47472125 ps
CPU time 0.73 seconds
Started Jun 13 01:00:11 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 205644 kb
Host smart-73101c07-e54c-4ff0-ad2e-432d5279780c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389220358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2389220358
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1703377251
Short name T963
Test name
Test status
Simulation time 21950482 ps
CPU time 1.73 seconds
Started Jun 13 01:00:09 PM PDT 24
Finished Jun 13 01:00:11 PM PDT 24
Peak memory 206008 kb
Host smart-0cb0f561-d6fc-46ae-88a4-121d3c63f612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703377251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1703377251
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1093392423
Short name T1061
Test name
Test status
Simulation time 52431550 ps
CPU time 1.55 seconds
Started Jun 13 01:00:12 PM PDT 24
Finished Jun 13 01:00:15 PM PDT 24
Peak memory 214480 kb
Host smart-9cb2622d-1da4-4638-b199-f462ea210504
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093392423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1093392423
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.127646084
Short name T962
Test name
Test status
Simulation time 367638608 ps
CPU time 13.58 seconds
Started Jun 13 01:00:09 PM PDT 24
Finished Jun 13 01:00:23 PM PDT 24
Peak memory 214396 kb
Host smart-30c11234-1f8c-4f78-a04d-cadd69d6f53a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127646084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.127646084
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2073013067
Short name T1006
Test name
Test status
Simulation time 270575767 ps
CPU time 2.9 seconds
Started Jun 13 01:00:10 PM PDT 24
Finished Jun 13 01:00:14 PM PDT 24
Peak memory 214092 kb
Host smart-0110de4d-59ce-46af-b452-cc591b4274d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073013067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2073013067
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2822517412
Short name T860
Test name
Test status
Simulation time 8120862 ps
CPU time 0.82 seconds
Started Jun 13 01:06:49 PM PDT 24
Finished Jun 13 01:06:51 PM PDT 24
Peak memory 205892 kb
Host smart-963665ef-de4f-40a5-ad67-f481840a809e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822517412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2822517412
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2779995942
Short name T34
Test name
Test status
Simulation time 982886988 ps
CPU time 3.08 seconds
Started Jun 13 01:06:46 PM PDT 24
Finished Jun 13 01:06:50 PM PDT 24
Peak memory 217976 kb
Host smart-6cb426c2-c774-4f0a-a58c-0b0e6d8b827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779995942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2779995942
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3250732619
Short name T309
Test name
Test status
Simulation time 343652179 ps
CPU time 3.78 seconds
Started Jun 13 01:06:40 PM PDT 24
Finished Jun 13 01:06:45 PM PDT 24
Peak memory 208096 kb
Host smart-7abf6d3e-a5b2-46cf-b0c7-1480b0b0d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250732619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3250732619
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1105071900
Short name T310
Test name
Test status
Simulation time 77921747 ps
CPU time 3.62 seconds
Started Jun 13 01:06:47 PM PDT 24
Finished Jun 13 01:06:51 PM PDT 24
Peak memory 211696 kb
Host smart-c896bccb-447c-4962-9e79-f1803df6ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105071900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1105071900
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.24096707
Short name T883
Test name
Test status
Simulation time 33438608 ps
CPU time 2.01 seconds
Started Jun 13 01:06:52 PM PDT 24
Finished Jun 13 01:06:56 PM PDT 24
Peak memory 218316 kb
Host smart-6a222042-bbc5-4a94-b8b1-65b727fd9500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24096707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.24096707
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2556054988
Short name T760
Test name
Test status
Simulation time 174825788 ps
CPU time 7.15 seconds
Started Jun 13 01:06:43 PM PDT 24
Finished Jun 13 01:06:51 PM PDT 24
Peak memory 214316 kb
Host smart-d7eb71bc-cbd6-4995-be05-8e5be48d39b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556054988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2556054988
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3178095591
Short name T692
Test name
Test status
Simulation time 180396235 ps
CPU time 4.77 seconds
Started Jun 13 01:06:40 PM PDT 24
Finished Jun 13 01:06:45 PM PDT 24
Peak memory 207996 kb
Host smart-5aed7c72-f6dd-4965-9971-6cf5cbbefc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178095591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3178095591
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.736597334
Short name T821
Test name
Test status
Simulation time 478852212 ps
CPU time 2.83 seconds
Started Jun 13 01:06:42 PM PDT 24
Finished Jun 13 01:06:45 PM PDT 24
Peak memory 206960 kb
Host smart-05ab35a8-ee57-4b39-acc8-0f0023191efd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736597334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.736597334
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2418022493
Short name T737
Test name
Test status
Simulation time 105450006 ps
CPU time 2.44 seconds
Started Jun 13 01:06:44 PM PDT 24
Finished Jun 13 01:06:47 PM PDT 24
Peak memory 206888 kb
Host smart-50afa1d9-f268-4087-9a0d-25e952f291a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418022493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2418022493
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3623196187
Short name T483
Test name
Test status
Simulation time 70168561 ps
CPU time 3.36 seconds
Started Jun 13 01:06:40 PM PDT 24
Finished Jun 13 01:06:44 PM PDT 24
Peak memory 208204 kb
Host smart-59be3db0-52a1-4258-a867-e8f5555c96da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623196187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3623196187
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.84730403
Short name T221
Test name
Test status
Simulation time 300751911 ps
CPU time 2.4 seconds
Started Jun 13 01:06:51 PM PDT 24
Finished Jun 13 01:06:56 PM PDT 24
Peak memory 209144 kb
Host smart-0c1b973d-710a-4e22-a7ad-3e6179b676d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84730403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.84730403
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1612208215
Short name T810
Test name
Test status
Simulation time 215604926 ps
CPU time 4.6 seconds
Started Jun 13 01:06:43 PM PDT 24
Finished Jun 13 01:06:48 PM PDT 24
Peak memory 208360 kb
Host smart-94b9393c-1ea4-4118-80a6-ba57e5d92260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612208215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1612208215
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2547690554
Short name T720
Test name
Test status
Simulation time 4148528353 ps
CPU time 30.06 seconds
Started Jun 13 01:06:50 PM PDT 24
Finished Jun 13 01:07:22 PM PDT 24
Peak memory 208856 kb
Host smart-1d998de7-91ab-40c6-987a-1e120d81b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547690554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2547690554
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3720113248
Short name T495
Test name
Test status
Simulation time 362571610 ps
CPU time 6.35 seconds
Started Jun 13 01:06:51 PM PDT 24
Finished Jun 13 01:07:00 PM PDT 24
Peak memory 210944 kb
Host smart-663dbd21-1e50-417a-af52-22a0a1ac8ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720113248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3720113248
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4046636645
Short name T696
Test name
Test status
Simulation time 38749842 ps
CPU time 0.91 seconds
Started Jun 13 01:07:00 PM PDT 24
Finished Jun 13 01:07:02 PM PDT 24
Peak memory 205912 kb
Host smart-ddc8624d-361a-4eec-b57d-f412a18ee653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046636645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4046636645
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2134692085
Short name T805
Test name
Test status
Simulation time 9359210298 ps
CPU time 25.64 seconds
Started Jun 13 01:06:57 PM PDT 24
Finished Jun 13 01:07:26 PM PDT 24
Peak memory 214352 kb
Host smart-3c3491a9-d144-492a-a45b-cf99cd048fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134692085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2134692085
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.25394023
Short name T82
Test name
Test status
Simulation time 710639240 ps
CPU time 8.21 seconds
Started Jun 13 01:06:52 PM PDT 24
Finished Jun 13 01:07:02 PM PDT 24
Peak memory 209508 kb
Host smart-51d3267b-4933-4b36-a8fa-104c892b2013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25394023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.25394023
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3423343999
Short name T917
Test name
Test status
Simulation time 356214519 ps
CPU time 6.05 seconds
Started Jun 13 01:06:50 PM PDT 24
Finished Jun 13 01:06:59 PM PDT 24
Peak memory 214392 kb
Host smart-93201dd9-c182-4aee-9ee2-1db836b56a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423343999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3423343999
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2301536302
Short name T807
Test name
Test status
Simulation time 36004108 ps
CPU time 1.92 seconds
Started Jun 13 01:06:49 PM PDT 24
Finished Jun 13 01:06:52 PM PDT 24
Peak memory 208304 kb
Host smart-c269bb91-0c66-48bc-becd-b77d6c1b3287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301536302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2301536302
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3572112945
Short name T356
Test name
Test status
Simulation time 259550097 ps
CPU time 6.23 seconds
Started Jun 13 01:06:49 PM PDT 24
Finished Jun 13 01:06:57 PM PDT 24
Peak memory 214284 kb
Host smart-c24bd78d-6353-4ad5-87c6-d0aaf3ce71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572112945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3572112945
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.5149814
Short name T12
Test name
Test status
Simulation time 1467213630 ps
CPU time 9.02 seconds
Started Jun 13 01:06:59 PM PDT 24
Finished Jun 13 01:07:10 PM PDT 24
Peak memory 238132 kb
Host smart-1be6dcb6-9e6e-4e06-9b2d-d58feda911aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5149814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.5149814
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4204069799
Short name T638
Test name
Test status
Simulation time 130482370 ps
CPU time 4.14 seconds
Started Jun 13 01:06:50 PM PDT 24
Finished Jun 13 01:06:56 PM PDT 24
Peak memory 208432 kb
Host smart-1ce1e948-8f02-415d-9649-9848a9899a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204069799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4204069799
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3550095298
Short name T91
Test name
Test status
Simulation time 506169471 ps
CPU time 3.11 seconds
Started Jun 13 01:06:49 PM PDT 24
Finished Jun 13 01:06:54 PM PDT 24
Peak memory 206884 kb
Host smart-17a17649-adc4-4abf-90e9-d0d17ccf2c12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550095298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3550095298
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3954539618
Short name T784
Test name
Test status
Simulation time 376571301 ps
CPU time 6.69 seconds
Started Jun 13 01:06:50 PM PDT 24
Finished Jun 13 01:06:58 PM PDT 24
Peak memory 206884 kb
Host smart-4b23332b-f3db-41ac-9098-e9b5eae6f0ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954539618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3954539618
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.802626795
Short name T462
Test name
Test status
Simulation time 177854178 ps
CPU time 2.37 seconds
Started Jun 13 01:06:46 PM PDT 24
Finished Jun 13 01:06:49 PM PDT 24
Peak memory 208868 kb
Host smart-a553c090-9309-4867-a029-9036f5fb25ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802626795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.802626795
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3487287543
Short name T518
Test name
Test status
Simulation time 205644664 ps
CPU time 3.61 seconds
Started Jun 13 01:06:56 PM PDT 24
Finished Jun 13 01:07:03 PM PDT 24
Peak memory 214324 kb
Host smart-cda5480d-30fa-48be-b30e-947dbca21fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487287543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3487287543
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3734342525
Short name T227
Test name
Test status
Simulation time 79859419 ps
CPU time 2.61 seconds
Started Jun 13 01:06:51 PM PDT 24
Finished Jun 13 01:06:56 PM PDT 24
Peak memory 206692 kb
Host smart-0687a944-4e8c-4df0-b0b0-d2a6f6fe324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734342525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3734342525
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3403219691
Short name T752
Test name
Test status
Simulation time 3789832405 ps
CPU time 9.12 seconds
Started Jun 13 01:06:47 PM PDT 24
Finished Jun 13 01:06:57 PM PDT 24
Peak memory 208200 kb
Host smart-87200851-0922-4ccd-a349-6ec2a72c678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403219691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3403219691
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1417762559
Short name T865
Test name
Test status
Simulation time 62531986 ps
CPU time 0.96 seconds
Started Jun 13 01:07:41 PM PDT 24
Finished Jun 13 01:07:43 PM PDT 24
Peak memory 206072 kb
Host smart-22b0b416-ec01-4cff-93b0-31c43dc94eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417762559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1417762559
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1016995012
Short name T259
Test name
Test status
Simulation time 57976785 ps
CPU time 4.11 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:47 PM PDT 24
Peak memory 214300 kb
Host smart-bd100f4b-b024-4974-a1dd-9286952b8ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016995012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1016995012
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.915236938
Short name T686
Test name
Test status
Simulation time 6110051867 ps
CPU time 24.87 seconds
Started Jun 13 01:07:41 PM PDT 24
Finished Jun 13 01:08:06 PM PDT 24
Peak memory 208724 kb
Host smart-861fb093-aa09-4585-8f3f-f02daac17a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915236938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.915236938
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4268850885
Short name T286
Test name
Test status
Simulation time 460651413 ps
CPU time 2.24 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:46 PM PDT 24
Peak memory 214312 kb
Host smart-944e1459-be87-4ec1-81b5-e9c01bfb0192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268850885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4268850885
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1511154159
Short name T910
Test name
Test status
Simulation time 353958778 ps
CPU time 3.84 seconds
Started Jun 13 01:07:47 PM PDT 24
Finished Jun 13 01:07:51 PM PDT 24
Peak memory 214376 kb
Host smart-a74e728e-c709-4dec-977d-b3e3f0bdde43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511154159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1511154159
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1115833564
Short name T375
Test name
Test status
Simulation time 265731161 ps
CPU time 5.31 seconds
Started Jun 13 01:07:47 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 210552 kb
Host smart-d044fb09-5cd7-4cdb-8136-e71b33133743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115833564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1115833564
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1315497103
Short name T578
Test name
Test status
Simulation time 1342700852 ps
CPU time 8.66 seconds
Started Jun 13 01:07:43 PM PDT 24
Finished Jun 13 01:07:52 PM PDT 24
Peak memory 208756 kb
Host smart-d740662f-1bda-44bd-8196-0d755574006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315497103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1315497103
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2948441074
Short name T294
Test name
Test status
Simulation time 1210822410 ps
CPU time 3.87 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:36 PM PDT 24
Peak memory 208704 kb
Host smart-50afd828-fb24-4a52-aea0-112f2388f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948441074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2948441074
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2304362518
Short name T722
Test name
Test status
Simulation time 124141369 ps
CPU time 4.27 seconds
Started Jun 13 01:07:44 PM PDT 24
Finished Jun 13 01:07:49 PM PDT 24
Peak memory 208552 kb
Host smart-7d7f40ea-a817-49e4-ae77-efaad3c4e3ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304362518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2304362518
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3253460854
Short name T700
Test name
Test status
Simulation time 474678301 ps
CPU time 3.98 seconds
Started Jun 13 01:07:33 PM PDT 24
Finished Jun 13 01:07:38 PM PDT 24
Peak memory 206932 kb
Host smart-86fe8af7-e822-49fd-9810-7783e9a662fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253460854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3253460854
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2075264906
Short name T439
Test name
Test status
Simulation time 237713636 ps
CPU time 6.87 seconds
Started Jun 13 01:07:46 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 208120 kb
Host smart-06f7df57-0acf-4e13-9a02-3dc1d95314e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075264906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2075264906
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2238540165
Short name T833
Test name
Test status
Simulation time 167975851 ps
CPU time 4.55 seconds
Started Jun 13 01:07:39 PM PDT 24
Finished Jun 13 01:07:44 PM PDT 24
Peak memory 208852 kb
Host smart-fd0c7100-4533-4580-8cf1-0460524c11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238540165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2238540165
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3650891931
Short name T676
Test name
Test status
Simulation time 232138215 ps
CPU time 2.8 seconds
Started Jun 13 01:07:36 PM PDT 24
Finished Jun 13 01:07:39 PM PDT 24
Peak memory 208356 kb
Host smart-3375cd33-d768-40ee-babc-ac4a365a88fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650891931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3650891931
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3064366937
Short name T94
Test name
Test status
Simulation time 3408754626 ps
CPU time 8.42 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:49 PM PDT 24
Peak memory 208100 kb
Host smart-1901bd7f-eaeb-4a58-87e5-901760fc3db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064366937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3064366937
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.871073385
Short name T715
Test name
Test status
Simulation time 15659372 ps
CPU time 0.77 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:43 PM PDT 24
Peak memory 205896 kb
Host smart-cee889f8-2768-42af-a9f6-368821b61dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871073385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.871073385
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3642846497
Short name T806
Test name
Test status
Simulation time 2619223893 ps
CPU time 31.48 seconds
Started Jun 13 01:07:46 PM PDT 24
Finished Jun 13 01:08:18 PM PDT 24
Peak memory 209564 kb
Host smart-79ec727d-a75b-4e3e-8f11-ca5330323ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642846497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3642846497
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3248193046
Short name T609
Test name
Test status
Simulation time 92242172 ps
CPU time 3.89 seconds
Started Jun 13 01:07:47 PM PDT 24
Finished Jun 13 01:07:51 PM PDT 24
Peak memory 214204 kb
Host smart-91c6d512-899e-47b7-928f-2761ee0543bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248193046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3248193046
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1756259744
Short name T582
Test name
Test status
Simulation time 414547292 ps
CPU time 4.7 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:46 PM PDT 24
Peak memory 207748 kb
Host smart-a40cceca-fa8b-4a7b-bedf-70345309923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756259744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1756259744
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.260094155
Short name T607
Test name
Test status
Simulation time 5148957024 ps
CPU time 45.39 seconds
Started Jun 13 01:07:39 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 208572 kb
Host smart-c9bb9a3d-646f-4f87-9467-247fda00a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260094155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.260094155
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2279296074
Short name T511
Test name
Test status
Simulation time 1305249865 ps
CPU time 9.67 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:51 PM PDT 24
Peak memory 207008 kb
Host smart-c242c53a-3c34-4a8b-9c11-113b743f18a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279296074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2279296074
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2389509028
Short name T559
Test name
Test status
Simulation time 1200882445 ps
CPU time 30.11 seconds
Started Jun 13 01:07:41 PM PDT 24
Finished Jun 13 01:08:12 PM PDT 24
Peak memory 208184 kb
Host smart-32f41ba8-e64e-49de-b509-04d04cfd8e8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389509028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2389509028
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1202200504
Short name T733
Test name
Test status
Simulation time 1109747960 ps
CPU time 6.33 seconds
Started Jun 13 01:07:43 PM PDT 24
Finished Jun 13 01:07:50 PM PDT 24
Peak memory 208720 kb
Host smart-83d69815-129b-4486-8dd6-1e20f51cd01e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202200504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1202200504
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3296706359
Short name T548
Test name
Test status
Simulation time 874907283 ps
CPU time 9.39 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:50 PM PDT 24
Peak memory 208348 kb
Host smart-780512ab-f96b-4afb-9570-723e551989c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296706359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3296706359
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3879923356
Short name T640
Test name
Test status
Simulation time 56478432 ps
CPU time 2.26 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:45 PM PDT 24
Peak memory 214220 kb
Host smart-b8a31ab4-c4bc-40b1-8f74-d81e2c4f3658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879923356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3879923356
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.998424077
Short name T783
Test name
Test status
Simulation time 9287348412 ps
CPU time 12.51 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 208192 kb
Host smart-ec4b51ca-5efe-4a0b-80ba-96dd294b2ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998424077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.998424077
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4179491521
Short name T629
Test name
Test status
Simulation time 484829828 ps
CPU time 8.81 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:49 PM PDT 24
Peak memory 220776 kb
Host smart-f1c207d9-d1ed-4358-93d2-e9d8f675925d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179491521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4179491521
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.356444766
Short name T153
Test name
Test status
Simulation time 72405196 ps
CPU time 5.34 seconds
Started Jun 13 01:07:42 PM PDT 24
Finished Jun 13 01:07:48 PM PDT 24
Peak memory 222636 kb
Host smart-113584ca-517c-4727-9a74-74f2af6aafaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356444766 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.356444766
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1571714043
Short name T704
Test name
Test status
Simulation time 973271194 ps
CPU time 8.32 seconds
Started Jun 13 01:07:41 PM PDT 24
Finished Jun 13 01:07:50 PM PDT 24
Peak memory 210112 kb
Host smart-aa3e8824-ef8e-453c-aaf9-123551ecd51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571714043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1571714043
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.4037920
Short name T537
Test name
Test status
Simulation time 59206732 ps
CPU time 1.05 seconds
Started Jun 13 01:07:38 PM PDT 24
Finished Jun 13 01:07:40 PM PDT 24
Peak memory 208476 kb
Host smart-abcf159d-81d2-40a6-998b-4e0a4c804b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.4037920
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.725906580
Short name T652
Test name
Test status
Simulation time 16442317 ps
CPU time 0.95 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:52 PM PDT 24
Peak memory 206100 kb
Host smart-b95ac28f-a72f-4f80-83a9-2df3679e94a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725906580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.725906580
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2774096879
Short name T202
Test name
Test status
Simulation time 82159069 ps
CPU time 2.09 seconds
Started Jun 13 01:07:43 PM PDT 24
Finished Jun 13 01:07:45 PM PDT 24
Peak memory 208792 kb
Host smart-5d6f5d60-6200-4014-b16e-58badfc7eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774096879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2774096879
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.354567217
Short name T728
Test name
Test status
Simulation time 108998925 ps
CPU time 2.25 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 214572 kb
Host smart-a9025c70-e945-4ff9-bd2d-0b74a1365bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354567217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.354567217
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3926351268
Short name T506
Test name
Test status
Simulation time 467291271 ps
CPU time 3.71 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:59 PM PDT 24
Peak memory 222356 kb
Host smart-cc55f767-56cc-46e5-a7fd-12723740c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926351268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3926351268
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.104057498
Short name T489
Test name
Test status
Simulation time 2357692826 ps
CPU time 22.07 seconds
Started Jun 13 01:07:44 PM PDT 24
Finished Jun 13 01:08:07 PM PDT 24
Peak memory 214416 kb
Host smart-052dacf4-c0b7-4059-89bf-53b361fb6c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104057498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.104057498
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1696702658
Short name T398
Test name
Test status
Simulation time 109477501 ps
CPU time 3.06 seconds
Started Jun 13 01:07:39 PM PDT 24
Finished Jun 13 01:07:43 PM PDT 24
Peak memory 208516 kb
Host smart-feaebc48-8389-4168-a71c-b3733fa30d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696702658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1696702658
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1442542811
Short name T668
Test name
Test status
Simulation time 158360288 ps
CPU time 4.56 seconds
Started Jun 13 01:07:47 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 208444 kb
Host smart-48373467-44e3-4196-957d-bbe547183a0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442542811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1442542811
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3734351893
Short name T359
Test name
Test status
Simulation time 87385183 ps
CPU time 2.72 seconds
Started Jun 13 01:07:40 PM PDT 24
Finished Jun 13 01:07:44 PM PDT 24
Peak memory 208616 kb
Host smart-b65d5b82-d993-443e-860e-703fbf35d247
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734351893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3734351893
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1131237510
Short name T17
Test name
Test status
Simulation time 383054172 ps
CPU time 4.7 seconds
Started Jun 13 01:07:43 PM PDT 24
Finished Jun 13 01:07:48 PM PDT 24
Peak memory 207148 kb
Host smart-a85cde57-09cb-43e0-81c9-41fd3879b182
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131237510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1131237510
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1163204433
Short name T325
Test name
Test status
Simulation time 18023843 ps
CPU time 1.6 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:52 PM PDT 24
Peak memory 206972 kb
Host smart-0bb6bed4-fd44-482c-91f3-7b4ae8d4fd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163204433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1163204433
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.135734530
Short name T429
Test name
Test status
Simulation time 228189394 ps
CPU time 2.86 seconds
Started Jun 13 01:07:44 PM PDT 24
Finished Jun 13 01:07:47 PM PDT 24
Peak memory 206920 kb
Host smart-56257602-6526-48f8-aac6-93943ee5f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135734530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.135734530
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.381809747
Short name T617
Test name
Test status
Simulation time 193083806 ps
CPU time 1.91 seconds
Started Jun 13 01:07:52 PM PDT 24
Finished Jun 13 01:07:54 PM PDT 24
Peak memory 209368 kb
Host smart-7b63c555-0e94-45a1-a443-b6fac62fc9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381809747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.381809747
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1541742720
Short name T612
Test name
Test status
Simulation time 43935779 ps
CPU time 2.79 seconds
Started Jun 13 01:07:51 PM PDT 24
Finished Jun 13 01:07:54 PM PDT 24
Peak memory 207624 kb
Host smart-69ab44dc-0527-42de-9187-46c7909e9e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541742720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1541742720
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3108261537
Short name T387
Test name
Test status
Simulation time 147318777 ps
CPU time 2.28 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:57 PM PDT 24
Peak memory 210188 kb
Host smart-6fdc4545-79b8-423f-a8a2-82db6302df01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108261537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3108261537
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4269882443
Short name T880
Test name
Test status
Simulation time 32293564 ps
CPU time 0.98 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:07:57 PM PDT 24
Peak memory 206068 kb
Host smart-dec46c47-aaa7-497e-a7b2-c3e2c4be659d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269882443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4269882443
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.253057979
Short name T392
Test name
Test status
Simulation time 102641797 ps
CPU time 2.33 seconds
Started Jun 13 01:07:52 PM PDT 24
Finished Jun 13 01:07:55 PM PDT 24
Peak memory 214320 kb
Host smart-40faea7e-a4ed-42b8-b0fc-15d51003f158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253057979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.253057979
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.187646412
Short name T849
Test name
Test status
Simulation time 223069394 ps
CPU time 3.24 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:58 PM PDT 24
Peak memory 207212 kb
Host smart-b740bcfb-58bf-4b9c-a13f-8bde45355db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187646412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.187646412
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2084982423
Short name T795
Test name
Test status
Simulation time 310339225 ps
CPU time 2.77 seconds
Started Jun 13 01:07:52 PM PDT 24
Finished Jun 13 01:07:56 PM PDT 24
Peak memory 214312 kb
Host smart-d5d36f16-6669-4921-8a7c-f7966a59d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084982423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2084982423
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.749383074
Short name T341
Test name
Test status
Simulation time 381851171 ps
CPU time 12.64 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:08 PM PDT 24
Peak memory 222376 kb
Host smart-0a0b3bb0-f5c5-485b-80a6-242c6b1fee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749383074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.749383074
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.92520951
Short name T396
Test name
Test status
Simulation time 63491909 ps
CPU time 3.82 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:01 PM PDT 24
Peak memory 222400 kb
Host smart-55b1162e-18c2-475a-82b8-e09955f6f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92520951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.92520951
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3148846816
Short name T653
Test name
Test status
Simulation time 899525114 ps
CPU time 25.64 seconds
Started Jun 13 01:07:51 PM PDT 24
Finished Jun 13 01:08:17 PM PDT 24
Peak memory 208488 kb
Host smart-518dbfb1-6c71-4be9-8b87-6a4ec5faa40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148846816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3148846816
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1671430810
Short name T141
Test name
Test status
Simulation time 91972608 ps
CPU time 4.6 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:56 PM PDT 24
Peak memory 208380 kb
Host smart-02540262-fe4c-44d7-a073-614003fe4984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671430810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1671430810
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1887315041
Short name T769
Test name
Test status
Simulation time 29004697 ps
CPU time 2.16 seconds
Started Jun 13 01:07:49 PM PDT 24
Finished Jun 13 01:07:52 PM PDT 24
Peak memory 206784 kb
Host smart-601c74d9-efb3-4cb2-b292-ce2d7fd53032
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887315041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1887315041
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2993132202
Short name T361
Test name
Test status
Simulation time 54686551 ps
CPU time 2.27 seconds
Started Jun 13 01:07:50 PM PDT 24
Finished Jun 13 01:07:53 PM PDT 24
Peak memory 208988 kb
Host smart-98ab936c-3877-4e84-b5e4-44fad97618c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993132202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2993132202
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2590265361
Short name T870
Test name
Test status
Simulation time 180790787 ps
CPU time 6.21 seconds
Started Jun 13 01:07:53 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 208144 kb
Host smart-63a4cbcd-81cd-44c1-b7c0-fd317ac6e99b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590265361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2590265361
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2882177287
Short name T614
Test name
Test status
Simulation time 119144431 ps
CPU time 2.63 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:57 PM PDT 24
Peak memory 207684 kb
Host smart-ae41a6c1-f7aa-413e-a4b4-79b98ef52347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882177287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2882177287
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.436181535
Short name T122
Test name
Test status
Simulation time 938309872 ps
CPU time 7.06 seconds
Started Jun 13 01:07:53 PM PDT 24
Finished Jun 13 01:08:01 PM PDT 24
Peak memory 208164 kb
Host smart-ba05b8ce-cfb6-4294-a00e-6a11be7ee07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436181535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.436181535
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4165905142
Short name T224
Test name
Test status
Simulation time 158795374 ps
CPU time 4.63 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:59 PM PDT 24
Peak memory 207812 kb
Host smart-6cce07ee-481b-4127-9a39-fa9134324623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165905142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4165905142
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.512835003
Short name T139
Test name
Test status
Simulation time 1216517708 ps
CPU time 12.29 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:08:07 PM PDT 24
Peak memory 222616 kb
Host smart-1fa380c8-866f-4ad2-9e0f-f96bc21db142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512835003 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.512835003
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3805329783
Short name T675
Test name
Test status
Simulation time 386249397 ps
CPU time 2.95 seconds
Started Jun 13 01:07:51 PM PDT 24
Finished Jun 13 01:07:55 PM PDT 24
Peak memory 210608 kb
Host smart-07ad2496-8806-4dc9-8c98-443195883838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805329783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3805329783
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.316234317
Short name T564
Test name
Test status
Simulation time 20517281 ps
CPU time 0.85 seconds
Started Jun 13 01:08:04 PM PDT 24
Finished Jun 13 01:08:05 PM PDT 24
Peak memory 205912 kb
Host smart-38746092-5a15-437d-820c-2cb768b59dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316234317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.316234317
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1137471957
Short name T287
Test name
Test status
Simulation time 90234266 ps
CPU time 2.96 seconds
Started Jun 13 01:07:53 PM PDT 24
Finished Jun 13 01:07:57 PM PDT 24
Peak memory 215484 kb
Host smart-dd1efb3f-b17a-4404-a15a-056b6c4ef06b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137471957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1137471957
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.215195776
Short name T496
Test name
Test status
Simulation time 52804561 ps
CPU time 2.38 seconds
Started Jun 13 01:07:56 PM PDT 24
Finished Jun 13 01:07:59 PM PDT 24
Peak memory 214216 kb
Host smart-6810d76b-0a52-4fcb-a2d1-070ad70ec6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215195776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.215195776
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4226716274
Short name T363
Test name
Test status
Simulation time 110190397 ps
CPU time 2.97 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:58 PM PDT 24
Peak memory 209600 kb
Host smart-fbb9fd9d-7d94-4144-bf2f-17ddf12e76b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226716274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4226716274
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3936593161
Short name T751
Test name
Test status
Simulation time 438558583 ps
CPU time 4.43 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 220348 kb
Host smart-55533dfc-e6e3-442e-ab95-7d6b2b0231ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936593161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3936593161
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3626309575
Short name T763
Test name
Test status
Simulation time 571857578 ps
CPU time 7.42 seconds
Started Jun 13 01:07:56 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 214296 kb
Host smart-1320814b-3431-4c6c-b92a-02bcc8d6d5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626309575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3626309575
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1263302724
Short name T400
Test name
Test status
Simulation time 91802045 ps
CPU time 3.52 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 208472 kb
Host smart-7f3a1b3d-993e-4abe-aa81-8e8f19ff73cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263302724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1263302724
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2797086081
Short name T664
Test name
Test status
Simulation time 110676864 ps
CPU time 3.87 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:01 PM PDT 24
Peak memory 206808 kb
Host smart-b98f6890-3b24-4f03-ab0d-f01f49a8db5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797086081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2797086081
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2659440574
Short name T775
Test name
Test status
Simulation time 2680543833 ps
CPU time 29.38 seconds
Started Jun 13 01:07:56 PM PDT 24
Finished Jun 13 01:08:26 PM PDT 24
Peak memory 208572 kb
Host smart-dfffcfec-a36a-4095-9b5e-087443aa287f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659440574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2659440574
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1457637782
Short name T444
Test name
Test status
Simulation time 20173411 ps
CPU time 1.74 seconds
Started Jun 13 01:07:57 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 207316 kb
Host smart-f2fc98e2-71ef-4b62-bab9-1041ffb75315
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457637782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1457637782
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2631894607
Short name T3
Test name
Test status
Simulation time 131233886 ps
CPU time 3.39 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 208708 kb
Host smart-c9be3561-a2cd-40f3-a82d-2bf11aa785e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631894607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2631894607
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.668244681
Short name T768
Test name
Test status
Simulation time 692074042 ps
CPU time 3.42 seconds
Started Jun 13 01:07:55 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 206832 kb
Host smart-c975d4de-e882-48b7-be69-a1f914fb501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668244681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.668244681
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4124648521
Short name T875
Test name
Test status
Simulation time 1058961384 ps
CPU time 30.76 seconds
Started Jun 13 01:07:56 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 209280 kb
Host smart-c2d63887-1834-4c80-b4cb-bdb1afda2ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124648521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4124648521
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1169521251
Short name T1
Test name
Test status
Simulation time 998017061 ps
CPU time 21.01 seconds
Started Jun 13 01:07:53 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 208552 kb
Host smart-a44e46fe-7011-41e2-8087-10255467b87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169521251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1169521251
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.701988320
Short name T738
Test name
Test status
Simulation time 227158997 ps
CPU time 2.68 seconds
Started Jun 13 01:07:54 PM PDT 24
Finished Jun 13 01:07:58 PM PDT 24
Peak memory 210168 kb
Host smart-0d6ffa46-eb58-4161-9958-4208f35af48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701988320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.701988320
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1616811735
Short name T426
Test name
Test status
Simulation time 74296873 ps
CPU time 1 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:02 PM PDT 24
Peak memory 206104 kb
Host smart-2c215844-a7fe-418b-907f-cb52f0094ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616811735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1616811735
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4018160310
Short name T409
Test name
Test status
Simulation time 658852056 ps
CPU time 9.14 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:10 PM PDT 24
Peak memory 215280 kb
Host smart-ca67cbbc-c28b-425b-b117-ccbad20a8b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4018160310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4018160310
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1110773511
Short name T20
Test name
Test status
Simulation time 131038940 ps
CPU time 2.27 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 214556 kb
Host smart-c39c1991-4dbf-4a8f-9c22-31260a64342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110773511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1110773511
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2504870448
Short name T782
Test name
Test status
Simulation time 87349685 ps
CPU time 2.16 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 209500 kb
Host smart-133d6433-e2e2-4ca2-9329-f8eb338e8943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504870448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2504870448
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1811075509
Short name T103
Test name
Test status
Simulation time 251595994 ps
CPU time 4.53 seconds
Started Jun 13 01:07:58 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 221704 kb
Host smart-e73d18d0-0acd-4269-ad0c-5d267ee2e072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811075509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1811075509
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4285598808
Short name T192
Test name
Test status
Simulation time 73281011 ps
CPU time 2.49 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:02 PM PDT 24
Peak memory 220108 kb
Host smart-e69469a7-4aac-4827-b3aa-99abef44ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285598808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4285598808
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1327860848
Short name T295
Test name
Test status
Simulation time 306030592 ps
CPU time 3.98 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:08:06 PM PDT 24
Peak memory 209364 kb
Host smart-67329786-46fe-494f-a727-7484cb91264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327860848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1327860848
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3912518212
Short name T819
Test name
Test status
Simulation time 905051721 ps
CPU time 3.28 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 206908 kb
Host smart-d5d2904c-0391-44a6-8501-2466ac3cbfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912518212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3912518212
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1613962250
Short name T897
Test name
Test status
Simulation time 145244576 ps
CPU time 2.97 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 208808 kb
Host smart-a908beb8-0e51-4fe2-8ac4-e7d7638228de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613962250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1613962250
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.962004070
Short name T427
Test name
Test status
Simulation time 48210303 ps
CPU time 2.71 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 206856 kb
Host smart-176e9667-0501-49a2-8128-ba85c55e8b47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962004070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.962004070
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.727807997
Short name T313
Test name
Test status
Simulation time 251466093 ps
CPU time 5.38 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:06 PM PDT 24
Peak memory 209740 kb
Host smart-baa00bc8-a3ae-4600-8328-393d0ae84ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727807997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.727807997
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.759647029
Short name T394
Test name
Test status
Simulation time 73359111 ps
CPU time 2.5 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 207392 kb
Host smart-ea2c098c-ede2-4c52-9218-8605812f2fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759647029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.759647029
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.603542793
Short name T260
Test name
Test status
Simulation time 718925859 ps
CPU time 4.92 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:08:07 PM PDT 24
Peak memory 207752 kb
Host smart-9d2b0356-e0de-4e0c-9b63-c01e444035a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603542793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.603542793
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1141256445
Short name T579
Test name
Test status
Simulation time 52452415 ps
CPU time 2.55 seconds
Started Jun 13 01:08:02 PM PDT 24
Finished Jun 13 01:08:05 PM PDT 24
Peak memory 210048 kb
Host smart-e9f65e71-6421-42c2-b137-9ad68757bcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141256445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1141256445
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4063037834
Short name T428
Test name
Test status
Simulation time 16614256 ps
CPU time 1.01 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 206056 kb
Host smart-dd93961a-f7fd-4b4a-9ab5-32694c2ebcd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063037834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4063037834
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4283840138
Short name T35
Test name
Test status
Simulation time 299985274 ps
CPU time 2.79 seconds
Started Jun 13 01:08:02 PM PDT 24
Finished Jun 13 01:08:05 PM PDT 24
Peak memory 220312 kb
Host smart-e1c79300-824a-4008-89b6-ec2db2fb69f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283840138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4283840138
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2655057744
Short name T523
Test name
Test status
Simulation time 177643308 ps
CPU time 2.04 seconds
Started Jun 13 01:07:58 PM PDT 24
Finished Jun 13 01:08:00 PM PDT 24
Peak memory 208688 kb
Host smart-d196c351-33ce-4758-b9fd-3a0a7fe82152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655057744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2655057744
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2897907945
Short name T382
Test name
Test status
Simulation time 394912046 ps
CPU time 3.44 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 214248 kb
Host smart-8434ea7c-1702-4d7a-8386-961ebffbba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897907945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2897907945
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3554913757
Short name T66
Test name
Test status
Simulation time 90443700 ps
CPU time 2.9 seconds
Started Jun 13 01:08:01 PM PDT 24
Finished Jun 13 01:08:05 PM PDT 24
Peak memory 216168 kb
Host smart-194600fa-3523-4669-afad-f69d8d9eb306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554913757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3554913757
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2283550132
Short name T262
Test name
Test status
Simulation time 1153148246 ps
CPU time 12.49 seconds
Started Jun 13 01:08:03 PM PDT 24
Finished Jun 13 01:08:16 PM PDT 24
Peak memory 209520 kb
Host smart-111aaabe-c350-4656-b7bd-6fd561683ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283550132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2283550132
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3856702070
Short name T372
Test name
Test status
Simulation time 120572563 ps
CPU time 3.08 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 207368 kb
Host smart-71a9a43d-a9ae-46d1-b387-1cbebbc9d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856702070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3856702070
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3805423836
Short name T626
Test name
Test status
Simulation time 100994769 ps
CPU time 2.79 seconds
Started Jun 13 01:08:05 PM PDT 24
Finished Jun 13 01:08:09 PM PDT 24
Peak memory 206932 kb
Host smart-7168d432-ae16-4096-b922-b8322f462bac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805423836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3805423836
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.200198222
Short name T688
Test name
Test status
Simulation time 121077663 ps
CPU time 4.77 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:06 PM PDT 24
Peak memory 208992 kb
Host smart-99646a20-351d-47bd-96e9-7d806a76941d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200198222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.200198222
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1455344863
Short name T714
Test name
Test status
Simulation time 41808714 ps
CPU time 1.92 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 206924 kb
Host smart-c671d324-a091-4eb1-a99a-37058603b6e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455344863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1455344863
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.938273860
Short name T695
Test name
Test status
Simulation time 839832682 ps
CPU time 6.55 seconds
Started Jun 13 01:07:57 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 214280 kb
Host smart-f7c19fbb-e10c-49e8-9abb-1d2149dd7791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938273860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.938273860
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1569898066
Short name T702
Test name
Test status
Simulation time 190927934 ps
CPU time 6.28 seconds
Started Jun 13 01:08:03 PM PDT 24
Finished Jun 13 01:08:10 PM PDT 24
Peak memory 208204 kb
Host smart-f675fd21-52f6-4d9a-8460-9a01bb173153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569898066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1569898066
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1095543496
Short name T441
Test name
Test status
Simulation time 653989895 ps
CPU time 6.02 seconds
Started Jun 13 01:07:59 PM PDT 24
Finished Jun 13 01:08:06 PM PDT 24
Peak memory 208300 kb
Host smart-3d702dd2-fd25-4b0d-8767-5f4485171ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095543496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1095543496
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2599744090
Short name T168
Test name
Test status
Simulation time 79277654 ps
CPU time 2.07 seconds
Started Jun 13 01:08:00 PM PDT 24
Finished Jun 13 01:08:03 PM PDT 24
Peak memory 210248 kb
Host smart-fab6e1ec-4f9e-4cb4-9703-7c1a6fb583fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599744090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2599744090
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1862380812
Short name T730
Test name
Test status
Simulation time 15796782 ps
CPU time 0.72 seconds
Started Jun 13 01:08:13 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 205912 kb
Host smart-f648d858-edca-4c05-8dcf-4a2fc1537fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862380812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1862380812
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2287401776
Short name T879
Test name
Test status
Simulation time 200397900 ps
CPU time 3.56 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 215756 kb
Host smart-880649c1-a849-4da9-8778-0181575e1de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2287401776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2287401776
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1471313901
Short name T884
Test name
Test status
Simulation time 24642353 ps
CPU time 1.96 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:12 PM PDT 24
Peak memory 208228 kb
Host smart-25518bc7-e962-4649-a8c8-ec5559835af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471313901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1471313901
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4068099582
Short name T14
Test name
Test status
Simulation time 64251790 ps
CPU time 2.19 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:13 PM PDT 24
Peak memory 214296 kb
Host smart-83794ff6-623f-489f-8317-900d38b9bdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068099582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4068099582
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3286019504
Short name T102
Test name
Test status
Simulation time 500486978 ps
CPU time 4.3 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 214212 kb
Host smart-976b38bc-1825-4fde-badc-bcccf92bbcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286019504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3286019504
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.2638070534
Short name T364
Test name
Test status
Simulation time 295153327 ps
CPU time 4.8 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 210128 kb
Host smart-cad86393-a894-4bc9-8860-2aece1991c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638070534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2638070534
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.316267373
Short name T590
Test name
Test status
Simulation time 430274338 ps
CPU time 4.07 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 208552 kb
Host smart-72d13f7b-1415-4b3d-90d4-aeff59dd0c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316267373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.316267373
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1105219627
Short name T497
Test name
Test status
Simulation time 127228609 ps
CPU time 4.06 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 208068 kb
Host smart-61a3601f-c931-4656-a4a3-9eaa58a756c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105219627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1105219627
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1419399588
Short name T432
Test name
Test status
Simulation time 230607178 ps
CPU time 3.96 seconds
Started Jun 13 01:08:07 PM PDT 24
Finished Jun 13 01:08:12 PM PDT 24
Peak memory 208656 kb
Host smart-4581eb79-923a-41c6-ad62-4870b9ca67dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419399588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1419399588
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3115639354
Short name T456
Test name
Test status
Simulation time 292624164 ps
CPU time 3.28 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 208708 kb
Host smart-56f49253-f08d-4595-ad06-26bd31182039
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115639354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3115639354
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.988520203
Short name T261
Test name
Test status
Simulation time 80698105 ps
CPU time 2.62 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 216136 kb
Host smart-222835ed-7a73-4baa-91b9-a494567d8a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988520203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.988520203
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2648265012
Short name T820
Test name
Test status
Simulation time 66308939 ps
CPU time 2.47 seconds
Started Jun 13 01:08:04 PM PDT 24
Finished Jun 13 01:08:07 PM PDT 24
Peak memory 208352 kb
Host smart-4756ce9f-1763-4390-9e72-5a639ac2b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648265012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2648265012
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3621143285
Short name T317
Test name
Test status
Simulation time 1200177379 ps
CPU time 19.94 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:31 PM PDT 24
Peak memory 222628 kb
Host smart-3c608ba9-f53f-4c4c-b067-447c3526131e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621143285 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3621143285
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1369040569
Short name T118
Test name
Test status
Simulation time 1474130644 ps
CPU time 20.62 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 214276 kb
Host smart-cbfd55c7-5da3-42bd-830c-ecff7164a30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369040569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1369040569
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1528661441
Short name T449
Test name
Test status
Simulation time 87792024 ps
CPU time 1.71 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:10 PM PDT 24
Peak memory 210268 kb
Host smart-3e6f5822-849f-44d9-82d0-1276331d0a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528661441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1528661441
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3379279848
Short name T558
Test name
Test status
Simulation time 27773994 ps
CPU time 0.78 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:11 PM PDT 24
Peak memory 205864 kb
Host smart-066544ee-5e4e-44a3-9001-9997f9c2897e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379279848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3379279848
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2734514185
Short name T413
Test name
Test status
Simulation time 38073124 ps
CPU time 3.06 seconds
Started Jun 13 01:08:12 PM PDT 24
Finished Jun 13 01:08:17 PM PDT 24
Peak memory 214304 kb
Host smart-9ef5b5ce-8ff5-4e10-ba15-79390d4ff557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734514185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2734514185
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.913029569
Short name T443
Test name
Test status
Simulation time 95042960 ps
CPU time 4.52 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 209420 kb
Host smart-b9d5e50b-aebb-4009-afb3-bf2cbef01eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913029569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.913029569
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4049094302
Short name T475
Test name
Test status
Simulation time 130860734 ps
CPU time 1.83 seconds
Started Jun 13 01:08:07 PM PDT 24
Finished Jun 13 01:08:10 PM PDT 24
Peak memory 208876 kb
Host smart-372b207a-9749-41b9-bac3-db0c73769556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049094302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4049094302
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.37187730
Short name T809
Test name
Test status
Simulation time 70920195 ps
CPU time 1.87 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:12 PM PDT 24
Peak memory 214276 kb
Host smart-936013d6-b0fe-44df-9ff0-3ea31df49e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37187730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.37187730
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1759419223
Short name T238
Test name
Test status
Simulation time 1015538836 ps
CPU time 3.43 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:12 PM PDT 24
Peak memory 214312 kb
Host smart-2c6dbba3-c044-4831-badf-20b7d431d589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759419223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1759419223
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2269805543
Short name T499
Test name
Test status
Simulation time 287334308 ps
CPU time 6.53 seconds
Started Jun 13 01:08:11 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 207832 kb
Host smart-a35951d2-6463-48b6-be2a-1c1ceddb7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269805543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2269805543
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.149956878
Short name T357
Test name
Test status
Simulation time 103955467 ps
CPU time 4.44 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 208556 kb
Host smart-01b8d409-ed02-471e-9eb2-ba6ccdf36cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149956878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.149956878
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1668111651
Short name T753
Test name
Test status
Simulation time 915456708 ps
CPU time 4.72 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 208292 kb
Host smart-730bce18-caed-421b-a38e-f55a2669c495
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668111651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1668111651
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1832219762
Short name T553
Test name
Test status
Simulation time 32435871 ps
CPU time 2.34 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:18 PM PDT 24
Peak memory 207328 kb
Host smart-53578a97-4de6-454e-a890-1146085379fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832219762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1832219762
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2675542261
Short name T643
Test name
Test status
Simulation time 124990098 ps
CPU time 3.88 seconds
Started Jun 13 01:08:12 PM PDT 24
Finished Jun 13 01:08:17 PM PDT 24
Peak memory 206876 kb
Host smart-be4b34a7-6819-4590-9968-19a4789f7e7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675542261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2675542261
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3681341266
Short name T369
Test name
Test status
Simulation time 303622312 ps
CPU time 8.47 seconds
Started Jun 13 01:08:11 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 214356 kb
Host smart-7fd69df4-bb08-416b-9939-7efa9bf6317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681341266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3681341266
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4262768081
Short name T655
Test name
Test status
Simulation time 45920957 ps
CPU time 2.33 seconds
Started Jun 13 01:08:06 PM PDT 24
Finished Jun 13 01:08:09 PM PDT 24
Peak memory 208428 kb
Host smart-c3bd657b-a0d1-4873-a5df-9e12d77ac07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262768081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4262768081
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1499893863
Short name T528
Test name
Test status
Simulation time 115677538 ps
CPU time 5.71 seconds
Started Jun 13 01:08:11 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 218436 kb
Host smart-083678c5-a0e7-4c0c-a2f3-31fb7281003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499893863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1499893863
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3623049248
Short name T479
Test name
Test status
Simulation time 62877375 ps
CPU time 2.73 seconds
Started Jun 13 01:08:09 PM PDT 24
Finished Jun 13 01:08:13 PM PDT 24
Peak memory 210172 kb
Host smart-fad66b96-5800-49dd-9131-dde3bc1d2394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623049248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3623049248
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3353134957
Short name T538
Test name
Test status
Simulation time 10852110 ps
CPU time 0.85 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 205896 kb
Host smart-0a259feb-1a5a-4b13-95fd-3f142b3f0779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353134957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3353134957
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1853894885
Short name T142
Test name
Test status
Simulation time 88830850 ps
CPU time 4.97 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 214320 kb
Host smart-2463f08c-86e4-4d9a-ba14-c5761fb6a185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853894885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1853894885
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2525620013
Short name T30
Test name
Test status
Simulation time 47455438 ps
CPU time 2.71 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 221272 kb
Host smart-794b69f5-297f-42f7-afa9-eafa491113b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525620013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2525620013
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2806213096
Short name T592
Test name
Test status
Simulation time 226071487 ps
CPU time 5.58 seconds
Started Jun 13 01:08:12 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 214304 kb
Host smart-4dc9f124-487a-4e71-a67d-6877fc961ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806213096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2806213096
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3764779868
Short name T245
Test name
Test status
Simulation time 67887249 ps
CPU time 2.43 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:11 PM PDT 24
Peak memory 221800 kb
Host smart-33de7264-a359-4c23-9e25-d13cf8e2ed59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764779868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3764779868
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2194507618
Short name T346
Test name
Test status
Simulation time 224504956 ps
CPU time 4.16 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:20 PM PDT 24
Peak memory 207500 kb
Host smart-3588b0cc-11ad-4f39-b0aa-67b67baab05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194507618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2194507618
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1041112101
Short name T15
Test name
Test status
Simulation time 1353489227 ps
CPU time 27.13 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 208220 kb
Host smart-1cd1f772-053a-400e-bc0a-cd3ac0e121fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041112101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1041112101
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.768417659
Short name T234
Test name
Test status
Simulation time 4467377279 ps
CPU time 30.33 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:46 PM PDT 24
Peak memory 209184 kb
Host smart-e30107fe-f030-403e-93f9-fbbd41b8bd1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768417659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.768417659
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3925721706
Short name T569
Test name
Test status
Simulation time 1509533530 ps
CPU time 21.69 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:37 PM PDT 24
Peak memory 208264 kb
Host smart-7225b263-bc38-42b2-8162-16eaf3aec7a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925721706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3925721706
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3070087971
Short name T595
Test name
Test status
Simulation time 97044489 ps
CPU time 2.88 seconds
Started Jun 13 01:08:06 PM PDT 24
Finished Jun 13 01:08:10 PM PDT 24
Peak memory 206800 kb
Host smart-dd13176d-1311-4c65-b97e-bf0ccd3fe962
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070087971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3070087971
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.508953512
Short name T301
Test name
Test status
Simulation time 71408842 ps
CPU time 3.08 seconds
Started Jun 13 01:08:13 PM PDT 24
Finished Jun 13 01:08:17 PM PDT 24
Peak memory 218260 kb
Host smart-dde6f798-f9cb-45eb-9b46-74eb9be4a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508953512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.508953512
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.530484593
Short name T767
Test name
Test status
Simulation time 107353133 ps
CPU time 3.99 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:20 PM PDT 24
Peak memory 208700 kb
Host smart-4d58fddd-6bb7-48d1-ac61-cb8f424a3585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530484593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.530484593
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.694486883
Short name T892
Test name
Test status
Simulation time 817798733 ps
CPU time 17.61 seconds
Started Jun 13 01:08:10 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 216500 kb
Host smart-b322462e-afd8-43c4-8b82-838bc6b10e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694486883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.694486883
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3501368704
Short name T120
Test name
Test status
Simulation time 1216496272 ps
CPU time 16.75 seconds
Started Jun 13 01:08:13 PM PDT 24
Finished Jun 13 01:08:32 PM PDT 24
Peak memory 220164 kb
Host smart-45140010-7b9c-4535-b195-ffdbc95fcb13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501368704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3501368704
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1165106764
Short name T16
Test name
Test status
Simulation time 328917939 ps
CPU time 4.39 seconds
Started Jun 13 01:08:08 PM PDT 24
Finished Jun 13 01:08:14 PM PDT 24
Peak memory 207748 kb
Host smart-61a136b0-51ce-4509-aee4-2f1fdea3e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165106764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1165106764
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.251244406
Short name T178
Test name
Test status
Simulation time 53259932 ps
CPU time 2.88 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 209948 kb
Host smart-92ab36e6-48bc-47b8-8e8c-4ef3e7a9d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251244406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.251244406
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.878919241
Short name T604
Test name
Test status
Simulation time 15830878 ps
CPU time 0.91 seconds
Started Jun 13 01:07:04 PM PDT 24
Finished Jun 13 01:07:06 PM PDT 24
Peak memory 206068 kb
Host smart-9d298ced-bf74-4442-b527-1aa7ac21c1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878919241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.878919241
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1412032061
Short name T414
Test name
Test status
Simulation time 134814023 ps
CPU time 4.24 seconds
Started Jun 13 01:06:59 PM PDT 24
Finished Jun 13 01:07:06 PM PDT 24
Peak memory 214216 kb
Host smart-4416b4e3-b491-42b2-8d61-6e6b9a5ba5ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412032061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1412032061
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1664949307
Short name T32
Test name
Test status
Simulation time 97268860 ps
CPU time 4.1 seconds
Started Jun 13 01:07:01 PM PDT 24
Finished Jun 13 01:07:06 PM PDT 24
Peak memory 209232 kb
Host smart-dca6729a-acc4-4ef3-913d-b9b16fb6fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664949307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1664949307
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3645293583
Short name T554
Test name
Test status
Simulation time 18350409 ps
CPU time 1.53 seconds
Started Jun 13 01:06:54 PM PDT 24
Finished Jun 13 01:06:57 PM PDT 24
Peak memory 214272 kb
Host smart-3314b227-0526-4013-801d-5093a6a1d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645293583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3645293583
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4256925976
Short name T530
Test name
Test status
Simulation time 75133700 ps
CPU time 4.17 seconds
Started Jun 13 01:06:58 PM PDT 24
Finished Jun 13 01:07:05 PM PDT 24
Peak memory 214196 kb
Host smart-26575091-0e1c-47a2-aabd-d5bac3ebfe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256925976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4256925976
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3687708338
Short name T808
Test name
Test status
Simulation time 109095289 ps
CPU time 3.37 seconds
Started Jun 13 01:06:57 PM PDT 24
Finished Jun 13 01:07:04 PM PDT 24
Peak memory 209448 kb
Host smart-f2d1b207-41bc-4266-b89f-fd1fba6c7ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687708338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3687708338
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1135518801
Short name T866
Test name
Test status
Simulation time 64650716 ps
CPU time 2.94 seconds
Started Jun 13 01:06:58 PM PDT 24
Finished Jun 13 01:07:04 PM PDT 24
Peak memory 208072 kb
Host smart-4f9530fd-2080-4969-9ff3-b94a39540961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135518801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1135518801
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.997344298
Short name T744
Test name
Test status
Simulation time 385849812 ps
CPU time 4.89 seconds
Started Jun 13 01:06:56 PM PDT 24
Finished Jun 13 01:07:05 PM PDT 24
Peak memory 208056 kb
Host smart-ca65e19d-55b5-4b0f-90f3-b1be7c2b2198
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997344298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.997344298
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.625390336
Short name T840
Test name
Test status
Simulation time 194178719 ps
CPU time 3.02 seconds
Started Jun 13 01:06:56 PM PDT 24
Finished Jun 13 01:07:00 PM PDT 24
Peak memory 206884 kb
Host smart-65288511-4b1c-4eba-acc4-58389696c99b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625390336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.625390336
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1944940524
Short name T235
Test name
Test status
Simulation time 58443005 ps
CPU time 2.24 seconds
Started Jun 13 01:06:55 PM PDT 24
Finished Jun 13 01:06:58 PM PDT 24
Peak memory 206708 kb
Host smart-02973c69-b971-4690-bee1-e70282c40ec4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944940524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1944940524
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3909807322
Short name T708
Test name
Test status
Simulation time 77456133 ps
CPU time 2.86 seconds
Started Jun 13 01:07:03 PM PDT 24
Finished Jun 13 01:07:07 PM PDT 24
Peak memory 214336 kb
Host smart-60d1685c-775f-438c-89de-b8b405238cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909807322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3909807322
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3184890303
Short name T748
Test name
Test status
Simulation time 145491702 ps
CPU time 5.3 seconds
Started Jun 13 01:06:59 PM PDT 24
Finished Jun 13 01:07:07 PM PDT 24
Peak memory 208540 kb
Host smart-e5363bad-57f2-4c88-9bcf-93f78dd588b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184890303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3184890303
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.201117012
Short name T117
Test name
Test status
Simulation time 101020941 ps
CPU time 5.32 seconds
Started Jun 13 01:06:57 PM PDT 24
Finished Jun 13 01:07:06 PM PDT 24
Peak memory 218368 kb
Host smart-3557c046-958e-4a2d-86a2-4b87199a95e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201117012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.201117012
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1310039114
Short name T175
Test name
Test status
Simulation time 71165443 ps
CPU time 2.7 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:10 PM PDT 24
Peak memory 210152 kb
Host smart-77cf7b5e-5ca9-439a-8aba-f151618b4b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310039114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1310039114
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.64283111
Short name T663
Test name
Test status
Simulation time 44014537 ps
CPU time 0.78 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:17 PM PDT 24
Peak memory 205916 kb
Host smart-86d1721e-613f-4183-a927-1b086fee4e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64283111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.64283111
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3281515917
Short name T37
Test name
Test status
Simulation time 203855143 ps
CPU time 3.33 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 210708 kb
Host smart-ef26deae-2d19-4f49-a720-4853812b318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281515917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3281515917
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.4008382686
Short name T111
Test name
Test status
Simulation time 1586731506 ps
CPU time 23.68 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 214288 kb
Host smart-48d6dfea-dc0f-4c13-954f-990fc1a4209b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008382686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.4008382686
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2431345131
Short name T284
Test name
Test status
Simulation time 1001830714 ps
CPU time 7.81 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 214244 kb
Host smart-bf423ac2-c9ef-43df-bf36-f43e22559f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431345131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2431345131
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3339853544
Short name T244
Test name
Test status
Simulation time 97491891 ps
CPU time 4.54 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 210324 kb
Host smart-e33c1a8d-bd10-4905-a017-2c5a73b918b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339853544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3339853544
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1948831243
Short name T778
Test name
Test status
Simulation time 14548742748 ps
CPU time 28.87 seconds
Started Jun 13 01:08:20 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 209332 kb
Host smart-7fb921ea-2d1d-4a4d-8c4e-33e311d3b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948831243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1948831243
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3661072400
Short name T904
Test name
Test status
Simulation time 38233125 ps
CPU time 2.54 seconds
Started Jun 13 01:08:14 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 208552 kb
Host smart-5b40f1c7-4db9-4e35-9f86-26c7282005ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661072400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3661072400
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4156612739
Short name T822
Test name
Test status
Simulation time 462110672 ps
CPU time 5.76 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 208816 kb
Host smart-6cdea8b8-5755-4182-b0a6-b889e899b71d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156612739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4156612739
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.970112653
Short name T486
Test name
Test status
Simulation time 350503030 ps
CPU time 3.85 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 208708 kb
Host smart-1287a777-0de1-45b8-b28c-f51c3ba09e45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970112653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.970112653
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1236535553
Short name T684
Test name
Test status
Simulation time 211399691 ps
CPU time 3.46 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 215764 kb
Host smart-55bc41d9-855e-474a-bf47-15bd58affb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236535553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1236535553
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1141604080
Short name T395
Test name
Test status
Simulation time 168333640 ps
CPU time 3.1 seconds
Started Jun 13 01:08:18 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 208632 kb
Host smart-453eaf0c-ec3e-458a-b541-2aaeb2cfcf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141604080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1141604080
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.971937836
Short name T323
Test name
Test status
Simulation time 356314694 ps
CPU time 19.36 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:37 PM PDT 24
Peak memory 215928 kb
Host smart-f1406ea6-fb91-46e6-985a-826f097b272a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971937836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.971937836
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2137901152
Short name T563
Test name
Test status
Simulation time 460731735 ps
CPU time 4.08 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 208024 kb
Host smart-a07b1f80-9ff8-4f7e-831f-1d5abf6ab328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137901152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2137901152
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3971848374
Short name T203
Test name
Test status
Simulation time 6415359060 ps
CPU time 23.78 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:41 PM PDT 24
Peak memory 211588 kb
Host smart-4691e229-7e07-4473-8425-ddaae181a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971848374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3971848374
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3145148400
Short name T648
Test name
Test status
Simulation time 16337957 ps
CPU time 0.89 seconds
Started Jun 13 01:08:19 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 205904 kb
Host smart-fa9fd451-7aee-4657-8fc9-589c36423d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145148400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3145148400
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1732675441
Short name T157
Test name
Test status
Simulation time 82358209 ps
CPU time 3.07 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 215620 kb
Host smart-f6b9eefa-83e7-40af-b59a-316b313567f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732675441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1732675441
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.511233281
Short name T79
Test name
Test status
Simulation time 65599696 ps
CPU time 2.95 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 214540 kb
Host smart-0268a199-046d-4428-a19e-0210f12ea5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511233281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.511233281
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1238386655
Short name T55
Test name
Test status
Simulation time 94856473 ps
CPU time 2 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 214272 kb
Host smart-49dc42b7-e234-4706-9f5c-378589420c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238386655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1238386655
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2451097771
Short name T691
Test name
Test status
Simulation time 347786038 ps
CPU time 2.96 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 214492 kb
Host smart-9e765e8d-7723-44df-a1e9-f3be117131de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451097771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2451097771
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.941625959
Short name T399
Test name
Test status
Simulation time 62083583 ps
CPU time 2.28 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 214212 kb
Host smart-c5961e0b-bf44-4ca5-b844-61a897ac0d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941625959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.941625959
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1130621385
Short name T551
Test name
Test status
Simulation time 188678071 ps
CPU time 3.4 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:26 PM PDT 24
Peak memory 222392 kb
Host smart-581a91d7-be12-4c47-928d-56511f5bef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130621385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1130621385
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.821178448
Short name T773
Test name
Test status
Simulation time 167055600 ps
CPU time 5.55 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 210024 kb
Host smart-46634d80-6936-4004-a8ce-fc381b7010dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821178448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.821178448
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2709811397
Short name T567
Test name
Test status
Simulation time 65295530 ps
CPU time 3.32 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 206812 kb
Host smart-72eea3ff-9ca2-4b94-aa04-160ad63debab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709811397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2709811397
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3030296964
Short name T682
Test name
Test status
Simulation time 249192929 ps
CPU time 3.14 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 206976 kb
Host smart-f2cc5ebe-ec58-4ea3-bfb2-ecb9d502edf0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030296964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3030296964
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4243915529
Short name T771
Test name
Test status
Simulation time 179685774 ps
CPU time 4.9 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 208636 kb
Host smart-ddb65b49-35f6-4fe8-92eb-a1b85e39d4e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243915529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4243915529
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2526289135
Short name T525
Test name
Test status
Simulation time 58436244 ps
CPU time 2.76 seconds
Started Jun 13 01:08:20 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 209072 kb
Host smart-bdc5936c-2364-4964-b505-a50c3221fd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526289135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2526289135
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1300669100
Short name T747
Test name
Test status
Simulation time 137282393 ps
CPU time 2.06 seconds
Started Jun 13 01:08:15 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 207252 kb
Host smart-cdb2b9f2-3f68-4853-8987-41ada62b4147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300669100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1300669100
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.524390567
Short name T690
Test name
Test status
Simulation time 89132505 ps
CPU time 4.13 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:24 PM PDT 24
Peak memory 207424 kb
Host smart-f6bf9ba9-8d1e-4aae-9435-af904467a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524390567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.524390567
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.28493131
Short name T586
Test name
Test status
Simulation time 69790661 ps
CPU time 1.29 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 209492 kb
Host smart-c15c9f15-56bb-4042-8179-06c1551b48b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28493131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.28493131
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.401270830
Short name T581
Test name
Test status
Simulation time 57050556 ps
CPU time 0.73 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:24 PM PDT 24
Peak memory 205932 kb
Host smart-b6da2e7c-9f95-4b34-8379-437a4f4e64ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401270830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.401270830
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4232140949
Short name T306
Test name
Test status
Simulation time 32780870 ps
CPU time 2.74 seconds
Started Jun 13 01:08:17 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 214268 kb
Host smart-12847f82-6dcc-4120-9ba4-ca9eaa8a6d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232140949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4232140949
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1395047110
Short name T613
Test name
Test status
Simulation time 181961732 ps
CPU time 4.67 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:39 PM PDT 24
Peak memory 222348 kb
Host smart-6e351a6f-b3d1-4c4b-988f-9db3b3197105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395047110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1395047110
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.355369086
Short name T468
Test name
Test status
Simulation time 715356778 ps
CPU time 2.08 seconds
Started Jun 13 01:08:19 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 209296 kb
Host smart-bb73b6b4-5545-4126-bc76-538dcf0ff34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355369086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.355369086
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4057150457
Short name T839
Test name
Test status
Simulation time 837082841 ps
CPU time 12.31 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 214284 kb
Host smart-637f366d-39b7-4dc2-a8e6-e565bd53e94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057150457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4057150457
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3017433466
Short name T300
Test name
Test status
Simulation time 205068135 ps
CPU time 7.54 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 214900 kb
Host smart-2930cb35-6e93-42df-a305-9acfd4fd8301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017433466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3017433466
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3308658540
Short name T114
Test name
Test status
Simulation time 57142880 ps
CPU time 2.15 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 206832 kb
Host smart-de15446b-250b-4d37-8f27-60a01f2a4dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308658540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3308658540
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2915822538
Short name T314
Test name
Test status
Simulation time 1515800188 ps
CPU time 22.23 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 214332 kb
Host smart-ae28c49d-9ac9-4ee9-a09e-3119d366987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915822538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2915822538
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1200531403
Short name T816
Test name
Test status
Simulation time 34388847 ps
CPU time 2.24 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 206804 kb
Host smart-000e76dc-e3e3-49bb-a9ea-86773abf9bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200531403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1200531403
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.4139305329
Short name T231
Test name
Test status
Simulation time 120150975 ps
CPU time 2.48 seconds
Started Jun 13 01:08:20 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 206868 kb
Host smart-eead3d4f-af96-4bbf-b753-5b41279a7e39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139305329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4139305329
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1083602377
Short name T338
Test name
Test status
Simulation time 309569484 ps
CPU time 3.67 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:26 PM PDT 24
Peak memory 208416 kb
Host smart-bbf4679c-a3b5-443b-b7bb-2c8ca20305dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083602377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1083602377
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2109594410
Short name T719
Test name
Test status
Simulation time 32109652 ps
CPU time 2.42 seconds
Started Jun 13 01:08:20 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 206960 kb
Host smart-a8677c96-6cec-4283-b101-a0e4f8992e7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109594410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2109594410
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1912377928
Short name T279
Test name
Test status
Simulation time 73747317 ps
CPU time 2.75 seconds
Started Jun 13 01:08:24 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 208292 kb
Host smart-ad1b7c98-821e-4408-b9a1-45a42ce55c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912377928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1912377928
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2053554068
Short name T577
Test name
Test status
Simulation time 185956439 ps
CPU time 2.44 seconds
Started Jun 13 01:08:25 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 206928 kb
Host smart-bb683e7f-2c59-4c71-83ef-3cc3d76ff460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053554068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2053554068
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.220787343
Short name T602
Test name
Test status
Simulation time 39861276 ps
CPU time 0.76 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 205916 kb
Host smart-c1f327c5-ae57-43e7-ade9-57fdea6f3008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220787343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.220787343
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3751578937
Short name T196
Test name
Test status
Simulation time 3949211141 ps
CPU time 19.97 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:41 PM PDT 24
Peak memory 222636 kb
Host smart-f70311e7-e340-43a7-8227-183e7f9692eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751578937 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3751578937
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1562826262
Short name T706
Test name
Test status
Simulation time 205076780 ps
CPU time 2.77 seconds
Started Jun 13 01:08:16 PM PDT 24
Finished Jun 13 01:08:21 PM PDT 24
Peak memory 214320 kb
Host smart-a94a1b1b-dcf4-4073-b9d0-687b94505bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562826262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1562826262
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2418494706
Short name T745
Test name
Test status
Simulation time 130991102 ps
CPU time 1.41 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:25 PM PDT 24
Peak memory 209716 kb
Host smart-0e035623-a603-4fcd-b63b-10cf528ed1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418494706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2418494706
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3681111197
Short name T18
Test name
Test status
Simulation time 70402697 ps
CPU time 1.16 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 206076 kb
Host smart-662ffd72-dd16-4389-940e-adc4a9a1cbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681111197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3681111197
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.808393281
Short name T307
Test name
Test status
Simulation time 29648796 ps
CPU time 2.84 seconds
Started Jun 13 01:08:27 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 214276 kb
Host smart-b0d4b344-27f8-4592-9931-2abf5cfd5070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808393281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.808393281
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3363934066
Short name T677
Test name
Test status
Simulation time 146690731 ps
CPU time 1.96 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 207676 kb
Host smart-a4dabf56-ea8b-4a4e-b7f9-a082e0ee76f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363934066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3363934066
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2891618320
Short name T514
Test name
Test status
Simulation time 317660095 ps
CPU time 3.56 seconds
Started Jun 13 01:08:25 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 214412 kb
Host smart-c27099fe-4100-44d1-a1cd-437b9ffe4abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891618320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2891618320
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1339457659
Short name T268
Test name
Test status
Simulation time 149857941 ps
CPU time 1.6 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:26 PM PDT 24
Peak memory 214260 kb
Host smart-63f70d37-2520-482a-9782-68603f1c9a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339457659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1339457659
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.3185653668
Short name T772
Test name
Test status
Simulation time 2923545911 ps
CPU time 21.98 seconds
Started Jun 13 01:08:23 PM PDT 24
Finished Jun 13 01:08:47 PM PDT 24
Peak memory 214380 kb
Host smart-f42b3a6c-365e-4332-96b2-e45211a7e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185653668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3185653668
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.825454807
Short name T149
Test name
Test status
Simulation time 289672271 ps
CPU time 2.55 seconds
Started Jun 13 01:08:25 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 207388 kb
Host smart-9ca698c7-b5ea-4b20-8287-a285c276d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825454807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.825454807
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2660627252
Short name T847
Test name
Test status
Simulation time 64286724 ps
CPU time 2.32 seconds
Started Jun 13 01:08:23 PM PDT 24
Finished Jun 13 01:08:27 PM PDT 24
Peak memory 206876 kb
Host smart-e7cec7b5-bb49-4a94-a567-0aabc0e56b82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660627252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2660627252
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2992747686
Short name T488
Test name
Test status
Simulation time 194648701 ps
CPU time 6.16 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 208748 kb
Host smart-7efcb8eb-fa83-4f78-9825-37cc58359d8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992747686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2992747686
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3136679582
Short name T233
Test name
Test status
Simulation time 641817397 ps
CPU time 7.1 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 206980 kb
Host smart-39648011-d6f5-47b2-81b3-4cfc2cc9397c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136679582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3136679582
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1480308591
Short name T276
Test name
Test status
Simulation time 582675406 ps
CPU time 4.95 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 214304 kb
Host smart-c88d2797-c763-4d0d-960c-14ef77c47cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480308591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1480308591
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3970159752
Short name T550
Test name
Test status
Simulation time 902363577 ps
CPU time 4.86 seconds
Started Jun 13 01:08:23 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 206780 kb
Host smart-ef2a0fad-5ef5-45fa-bbd5-0a727d8e136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970159752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3970159752
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1113192857
Short name T83
Test name
Test status
Simulation time 459709228 ps
CPU time 15.81 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 216396 kb
Host smart-09e24b6b-8a5e-408d-abbb-642ce423683c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113192857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1113192857
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2420962889
Short name T152
Test name
Test status
Simulation time 190622137 ps
CPU time 4.28 seconds
Started Jun 13 01:08:22 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 209976 kb
Host smart-33571110-f0f1-49a8-acb3-0b638b8d4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420962889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2420962889
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.34138080
Short name T835
Test name
Test status
Simulation time 74942052 ps
CPU time 2.9 seconds
Started Jun 13 01:08:25 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 210264 kb
Host smart-2639de38-f148-4127-83a0-5e1105d5765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34138080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.34138080
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3418423148
Short name T657
Test name
Test status
Simulation time 87209764 ps
CPU time 0.72 seconds
Started Jun 13 01:08:28 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 205408 kb
Host smart-994c0d65-813e-405f-b869-6b177939a6e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418423148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3418423148
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2120946609
Short name T425
Test name
Test status
Simulation time 262474098 ps
CPU time 4.41 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:39 PM PDT 24
Peak memory 214324 kb
Host smart-b9b2efc9-482a-4074-868e-33752afce522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120946609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2120946609
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.8705042
Short name T248
Test name
Test status
Simulation time 62300535 ps
CPU time 3.17 seconds
Started Jun 13 01:08:28 PM PDT 24
Finished Jun 13 01:08:33 PM PDT 24
Peak memory 222416 kb
Host smart-5d23f6df-c6ef-4e9a-a622-2d5c3c75c045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8705042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.8705042
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3587305914
Short name T913
Test name
Test status
Simulation time 154759215 ps
CPU time 4.21 seconds
Started Jun 13 01:08:23 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 218296 kb
Host smart-ee49e872-a8cc-4342-99fa-3b242eb07f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587305914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3587305914
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3300678127
Short name T285
Test name
Test status
Simulation time 210705941 ps
CPU time 2.14 seconds
Started Jun 13 01:08:25 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 214276 kb
Host smart-95a1bf35-7920-4ef4-be3f-28e2134c4138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300678127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3300678127
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1833756300
Short name T267
Test name
Test status
Simulation time 54474398 ps
CPU time 2.88 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 222332 kb
Host smart-4b7a7476-2fdf-494d-930f-b9c197483433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833756300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1833756300
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3894640542
Short name T374
Test name
Test status
Simulation time 916139059 ps
CPU time 10.92 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 220408 kb
Host smart-b17714b1-a23f-40e1-b8b7-482c21353249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894640542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3894640542
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.843199089
Short name T229
Test name
Test status
Simulation time 8141834903 ps
CPU time 20.28 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:42 PM PDT 24
Peak memory 218328 kb
Host smart-9a6de7a2-afdc-4697-a4ed-e57d48941956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843199089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.843199089
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2187622434
Short name T482
Test name
Test status
Simulation time 35192158 ps
CPU time 2.28 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:35 PM PDT 24
Peak memory 206816 kb
Host smart-feebe9ed-efcc-402c-a879-b2aa74b588d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187622434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2187622434
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3213717036
Short name T472
Test name
Test status
Simulation time 1411614839 ps
CPU time 29.08 seconds
Started Jun 13 01:08:25 PM PDT 24
Finished Jun 13 01:08:55 PM PDT 24
Peak memory 208992 kb
Host smart-f2c9de75-3861-4645-9b18-a1b7c74f988b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213717036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3213717036
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.742211946
Short name T485
Test name
Test status
Simulation time 47130604 ps
CPU time 2.63 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:35 PM PDT 24
Peak memory 206936 kb
Host smart-5158e3f0-c197-405f-8c86-f5a0689e2de0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742211946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.742211946
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3858102325
Short name T200
Test name
Test status
Simulation time 136902142 ps
CPU time 3.94 seconds
Started Jun 13 01:08:40 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 208124 kb
Host smart-a45235be-0612-4dcb-b3c2-d79e3dbbe4b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858102325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3858102325
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4047316442
Short name T828
Test name
Test status
Simulation time 49426890 ps
CPU time 1.79 seconds
Started Jun 13 01:08:28 PM PDT 24
Finished Jun 13 01:08:32 PM PDT 24
Peak memory 209872 kb
Host smart-1fddef9b-0385-4db1-ae36-75f1fa5649e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047316442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4047316442
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2137336681
Short name T874
Test name
Test status
Simulation time 136370866 ps
CPU time 2.83 seconds
Started Jun 13 01:08:32 PM PDT 24
Finished Jun 13 01:08:38 PM PDT 24
Peak memory 208308 kb
Host smart-da4587b3-baf0-4bd0-ad74-535350a90a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137336681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2137336681
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1512554627
Short name T277
Test name
Test status
Simulation time 211517609 ps
CPU time 5.5 seconds
Started Jun 13 01:08:21 PM PDT 24
Finished Jun 13 01:08:29 PM PDT 24
Peak memory 218208 kb
Host smart-c72795c7-1ff1-49af-9768-c9d90c47dea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512554627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1512554627
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1477138305
Short name T583
Test name
Test status
Simulation time 126120616 ps
CPU time 2.93 seconds
Started Jun 13 01:08:32 PM PDT 24
Finished Jun 13 01:08:38 PM PDT 24
Peak memory 209740 kb
Host smart-34aa7c9b-1ef6-4eb0-9ffa-10a4919fcf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477138305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1477138305
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2125603725
Short name T442
Test name
Test status
Simulation time 14158168 ps
CPU time 0.74 seconds
Started Jun 13 01:08:27 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 205924 kb
Host smart-e8c59e71-d846-46c1-9e3f-2dba0c590ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125603725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2125603725
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2627865754
Short name T408
Test name
Test status
Simulation time 162418671 ps
CPU time 4.95 seconds
Started Jun 13 01:08:32 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 214632 kb
Host smart-30f9fd41-d1bf-49a7-80f6-f9e9f3186268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627865754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2627865754
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3967043383
Short name T742
Test name
Test status
Simulation time 120387691 ps
CPU time 3.39 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 208884 kb
Host smart-26eff35b-2d1e-42a5-88f8-cd6e9dff808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967043383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3967043383
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3400822890
Short name T512
Test name
Test status
Simulation time 42433027 ps
CPU time 2.91 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 221800 kb
Host smart-e21a96d2-9412-48ea-bf44-a7612e2b610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400822890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3400822890
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.647886347
Short name T605
Test name
Test status
Simulation time 151866391 ps
CPU time 1.97 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 208588 kb
Host smart-d7364313-9445-4ac7-b857-5332e57e2d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647886347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.647886347
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3293011650
Short name T603
Test name
Test status
Simulation time 750202435 ps
CPU time 8.31 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:39 PM PDT 24
Peak memory 208024 kb
Host smart-fc106005-a302-48e1-9cae-b8b777f9b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293011650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3293011650
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2290736133
Short name T718
Test name
Test status
Simulation time 309376200 ps
CPU time 2.24 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:32 PM PDT 24
Peak memory 206944 kb
Host smart-abf0479d-89e0-4a32-a661-92fbac1f50ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290736133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2290736133
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.835816705
Short name T658
Test name
Test status
Simulation time 118961852 ps
CPU time 2.88 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:33 PM PDT 24
Peak memory 207416 kb
Host smart-fc028f0b-a95f-4163-b2a1-e5eb73b63e2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835816705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.835816705
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3353069491
Short name T868
Test name
Test status
Simulation time 480609719 ps
CPU time 3.46 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 208564 kb
Host smart-acd9c518-6b3c-4619-9ca2-c56d2e69b58b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353069491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3353069491
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2686311511
Short name T861
Test name
Test status
Simulation time 55016351 ps
CPU time 2.88 seconds
Started Jun 13 01:08:27 PM PDT 24
Finished Jun 13 01:08:30 PM PDT 24
Peak memory 206872 kb
Host smart-cccb77e7-e090-4609-93f5-fd41e3ee0b32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686311511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2686311511
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3244781632
Short name T513
Test name
Test status
Simulation time 43181127 ps
CPU time 2.37 seconds
Started Jun 13 01:08:28 PM PDT 24
Finished Jun 13 01:08:31 PM PDT 24
Peak memory 209184 kb
Host smart-ce3bdd18-91a8-4f24-b2b6-250f26190bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244781632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3244781632
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1720225130
Short name T758
Test name
Test status
Simulation time 447064412 ps
CPU time 14.35 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 207940 kb
Host smart-c2c7619c-a07a-4902-8e45-7398da5f15a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720225130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1720225130
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3302112877
Short name T67
Test name
Test status
Simulation time 396720157 ps
CPU time 16.29 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 222584 kb
Host smart-61d94b9f-b2b5-4015-9d3a-6b0b2864c819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302112877 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3302112877
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.603340545
Short name T218
Test name
Test status
Simulation time 92082875 ps
CPU time 3.35 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 209040 kb
Host smart-2d6026de-5625-4252-bafb-bdb5c2450433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603340545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.603340545
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1756813219
Short name T169
Test name
Test status
Simulation time 116825449 ps
CPU time 3.51 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:35 PM PDT 24
Peak memory 210964 kb
Host smart-e71724d7-330f-4a5e-8d53-0c4e26bb868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756813219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1756813219
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3379377455
Short name T431
Test name
Test status
Simulation time 20734221 ps
CPU time 0.89 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 205944 kb
Host smart-b2de3f2b-e0f0-4e10-9444-53fbd7509be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379377455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3379377455
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.726799335
Short name T420
Test name
Test status
Simulation time 258604305 ps
CPU time 14.55 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 215496 kb
Host smart-a6c5a650-7915-4735-8e37-9c5ef1221fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726799335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.726799335
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.353844594
Short name T272
Test name
Test status
Simulation time 93781449 ps
CPU time 3.31 seconds
Started Jun 13 01:08:36 PM PDT 24
Finished Jun 13 01:08:41 PM PDT 24
Peak memory 222708 kb
Host smart-05eb36c9-011d-41a4-a8cb-1d7295afb394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353844594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.353844594
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.113402466
Short name T308
Test name
Test status
Simulation time 1162004653 ps
CPU time 13.5 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:53 PM PDT 24
Peak memory 210516 kb
Host smart-aba3d8d6-07ca-4333-8f17-8395e2f5aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113402466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.113402466
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1009295746
Short name T877
Test name
Test status
Simulation time 131320052 ps
CPU time 3.87 seconds
Started Jun 13 01:08:34 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 214248 kb
Host smart-9359e642-d7a8-489e-bf5f-c3f4868f63b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009295746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1009295746
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2420135008
Short name T355
Test name
Test status
Simulation time 79164155 ps
CPU time 2.92 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 206116 kb
Host smart-595bc920-3abe-4532-8723-37f4ed1ca800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420135008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2420135008
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2167502655
Short name T591
Test name
Test status
Simulation time 62597935 ps
CPU time 4.02 seconds
Started Jun 13 01:08:32 PM PDT 24
Finished Jun 13 01:08:39 PM PDT 24
Peak memory 214204 kb
Host smart-cc8cd8c0-2e07-41e4-9588-ebf26ba4584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167502655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2167502655
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2976794890
Short name T634
Test name
Test status
Simulation time 59462623 ps
CPU time 3.06 seconds
Started Jun 13 01:08:31 PM PDT 24
Finished Jun 13 01:08:37 PM PDT 24
Peak memory 208348 kb
Host smart-302f1f9f-4a61-46e8-a37f-c9ef4077b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976794890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2976794890
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1411967154
Short name T790
Test name
Test status
Simulation time 598492515 ps
CPU time 3.13 seconds
Started Jun 13 01:08:27 PM PDT 24
Finished Jun 13 01:08:31 PM PDT 24
Peak memory 208156 kb
Host smart-54195acb-a5fb-4530-b8cd-a5939cd1c176
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411967154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1411967154
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4161524930
Short name T474
Test name
Test status
Simulation time 32887506 ps
CPU time 2.36 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 206944 kb
Host smart-6df9a131-22e8-422c-beca-f9046e296a2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161524930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4161524930
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2720559551
Short name T524
Test name
Test status
Simulation time 38827457 ps
CPU time 1.8 seconds
Started Jun 13 01:08:30 PM PDT 24
Finished Jun 13 01:08:34 PM PDT 24
Peak memory 206800 kb
Host smart-11793d09-49a8-41cf-b128-84bc8474c7e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720559551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2720559551
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1686627367
Short name T298
Test name
Test status
Simulation time 2227667186 ps
CPU time 14.36 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 218296 kb
Host smart-a40bdd32-43e9-4c7a-a934-8aca56c13eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686627367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1686627367
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.970814155
Short name T709
Test name
Test status
Simulation time 2666026098 ps
CPU time 23.21 seconds
Started Jun 13 01:08:29 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 208552 kb
Host smart-89edd8a6-f2c9-44d1-84db-f7d5252eb883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970814155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.970814155
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1469376902
Short name T281
Test name
Test status
Simulation time 135117308 ps
CPU time 2.8 seconds
Started Jun 13 01:08:36 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 214364 kb
Host smart-93a21329-4f2c-4044-b128-70610c82fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469376902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1469376902
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3351448423
Short name T184
Test name
Test status
Simulation time 44199479 ps
CPU time 2.02 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:42 PM PDT 24
Peak memory 209984 kb
Host smart-3952a659-d6c8-4cff-8924-0443b440bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351448423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3351448423
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1815399174
Short name T210
Test name
Test status
Simulation time 12352560 ps
CPU time 0.73 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 205884 kb
Host smart-f3dde5cc-0c7f-4987-99c3-49a67885e480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815399174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1815399174
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2861386008
Short name T916
Test name
Test status
Simulation time 95556955 ps
CPU time 5.39 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 214268 kb
Host smart-7ad61984-bcb6-4196-b47e-37e65d3e4894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861386008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2861386008
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3236438263
Short name T383
Test name
Test status
Simulation time 173874827 ps
CPU time 2.66 seconds
Started Jun 13 01:08:36 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 222620 kb
Host smart-752a96fc-c2a6-4b87-aff5-1d438001329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236438263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3236438263
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3193949325
Short name T736
Test name
Test status
Simulation time 402014410 ps
CPU time 7.69 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:48 PM PDT 24
Peak memory 214272 kb
Host smart-214bd768-2e47-4f27-bb8a-5f2f85934ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193949325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3193949325
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.261676105
Short name T264
Test name
Test status
Simulation time 294944554 ps
CPU time 3.97 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 209168 kb
Host smart-9857ba3e-ef96-45ab-a893-8c980ba0c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261676105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.261676105
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1108733865
Short name T521
Test name
Test status
Simulation time 294753719 ps
CPU time 3.93 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 214120 kb
Host smart-ffdadfa4-308f-4d14-afcc-686cf088f15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108733865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1108733865
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.408027078
Short name T191
Test name
Test status
Simulation time 141537916 ps
CPU time 3.87 seconds
Started Jun 13 01:08:34 PM PDT 24
Finished Jun 13 01:08:40 PM PDT 24
Peak memory 208592 kb
Host smart-b303dc62-3eb4-4481-9c25-101481e76c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408027078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.408027078
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3790517004
Short name T786
Test name
Test status
Simulation time 54792735 ps
CPU time 3.21 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 207528 kb
Host smart-0c4f808c-36a8-4a18-bb61-c63912bbe014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790517004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3790517004
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3521079003
Short name T680
Test name
Test status
Simulation time 610269643 ps
CPU time 5.35 seconds
Started Jun 13 01:08:37 PM PDT 24
Finished Jun 13 01:08:43 PM PDT 24
Peak memory 206804 kb
Host smart-ac77a78f-b3ed-4a1c-b216-81bf8666745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521079003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3521079003
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4271285227
Short name T759
Test name
Test status
Simulation time 142940301 ps
CPU time 2.77 seconds
Started Jun 13 01:08:36 PM PDT 24
Finished Jun 13 01:08:41 PM PDT 24
Peak memory 208856 kb
Host smart-40ee899a-0d48-4464-a4a6-e6d862ede05b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271285227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4271285227
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1316853982
Short name T119
Test name
Test status
Simulation time 63992589 ps
CPU time 2.85 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 208476 kb
Host smart-cf13e1f7-a035-40b3-bacf-a232a151c0e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316853982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1316853982
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3281701215
Short name T490
Test name
Test status
Simulation time 50644074 ps
CPU time 2.8 seconds
Started Jun 13 01:08:37 PM PDT 24
Finished Jun 13 01:08:42 PM PDT 24
Peak memory 207752 kb
Host smart-1e5c7460-15ed-4b98-90d9-7f37ebd1cf93
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281701215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3281701215
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2724229503
Short name T198
Test name
Test status
Simulation time 122484398 ps
CPU time 5 seconds
Started Jun 13 01:08:37 PM PDT 24
Finished Jun 13 01:08:44 PM PDT 24
Peak memory 210284 kb
Host smart-4b79cc8e-c474-4261-a195-244a49211476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724229503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2724229503
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1501749726
Short name T121
Test name
Test status
Simulation time 197507643 ps
CPU time 2.79 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:42 PM PDT 24
Peak memory 206920 kb
Host smart-98d3c082-97b1-43e8-8a6f-d06355d80a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501749726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1501749726
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3495912671
Short name T292
Test name
Test status
Simulation time 3761172938 ps
CPU time 11.32 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 222672 kb
Host smart-017e4664-b44c-4163-b6f7-8fb3425f9b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495912671 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3495912671
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4196582116
Short name T335
Test name
Test status
Simulation time 228478333 ps
CPU time 6.25 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:46 PM PDT 24
Peak memory 222456 kb
Host smart-ee3738f4-c49a-442a-b8eb-5ed81f60c1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196582116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4196582116
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.476230950
Short name T146
Test name
Test status
Simulation time 81670586 ps
CPU time 2.36 seconds
Started Jun 13 01:08:42 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 210372 kb
Host smart-3c98e921-a463-4369-9360-7e5658c23d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476230950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.476230950
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2684526878
Short name T46
Test name
Test status
Simulation time 870870111 ps
CPU time 3.44 seconds
Started Jun 13 01:08:37 PM PDT 24
Finished Jun 13 01:08:42 PM PDT 24
Peak memory 214220 kb
Host smart-f60ab1af-65bd-4e25-b083-699bf0c9c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684526878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2684526878
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.356208353
Short name T650
Test name
Test status
Simulation time 339930710 ps
CPU time 4.25 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 218352 kb
Host smart-30e7c4ea-d457-40db-b938-cafdbd5658c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356208353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.356208353
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1659291031
Short name T746
Test name
Test status
Simulation time 173904002 ps
CPU time 5 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:46 PM PDT 24
Peak memory 222440 kb
Host smart-86cc3847-c45c-4537-9d3c-469dde38a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659291031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1659291031
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4124684517
Short name T625
Test name
Test status
Simulation time 488002714 ps
CPU time 4.1 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 220416 kb
Host smart-54b13c39-1922-45ca-8000-a930dc146a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124684517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4124684517
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1521965123
Short name T893
Test name
Test status
Simulation time 136420320 ps
CPU time 4.72 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:44 PM PDT 24
Peak memory 220756 kb
Host smart-3ffe5d2f-8d22-4c85-b7eb-b4c2f3e49ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521965123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1521965123
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2846139403
Short name T723
Test name
Test status
Simulation time 820274927 ps
CPU time 9.57 seconds
Started Jun 13 01:08:34 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 209792 kb
Host smart-caa925aa-d4c4-4be1-9617-8771c03abf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846139403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2846139403
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1432278128
Short name T226
Test name
Test status
Simulation time 152907624 ps
CPU time 4.24 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 207804 kb
Host smart-0d4d3556-b26f-490f-b140-0fba9ca75887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432278128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1432278128
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3626691735
Short name T155
Test name
Test status
Simulation time 51334057 ps
CPU time 2.92 seconds
Started Jun 13 01:08:39 PM PDT 24
Finished Jun 13 01:08:43 PM PDT 24
Peak memory 206876 kb
Host smart-26dfe604-f7c7-4a7e-a6b4-77987cd2679f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626691735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3626691735
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2731098683
Short name T522
Test name
Test status
Simulation time 95729332 ps
CPU time 1.9 seconds
Started Jun 13 01:08:38 PM PDT 24
Finished Jun 13 01:08:41 PM PDT 24
Peak memory 207292 kb
Host smart-f3143033-a54b-45f7-9ccc-497d4c4892e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731098683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2731098683
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.836814298
Short name T296
Test name
Test status
Simulation time 790020974 ps
CPU time 9.33 seconds
Started Jun 13 01:08:35 PM PDT 24
Finished Jun 13 01:08:46 PM PDT 24
Peak memory 208760 kb
Host smart-88f0a7f4-6f76-4cac-a6fb-59dc2605a0cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836814298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.836814298
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.707031539
Short name T478
Test name
Test status
Simulation time 189515499 ps
CPU time 2.51 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 209332 kb
Host smart-81c00613-ba24-441b-8db3-747aa8771a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707031539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.707031539
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2704729390
Short name T39
Test name
Test status
Simulation time 22567693 ps
CPU time 1.95 seconds
Started Jun 13 01:08:40 PM PDT 24
Finished Jun 13 01:08:43 PM PDT 24
Peak memory 208204 kb
Host smart-4007f74a-818a-4613-94e1-b9d79db090a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704729390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2704729390
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3416314548
Short name T275
Test name
Test status
Simulation time 1502090234 ps
CPU time 6.24 seconds
Started Jun 13 01:08:37 PM PDT 24
Finished Jun 13 01:08:44 PM PDT 24
Peak memory 218172 kb
Host smart-426b366f-0863-48e3-ab87-a13c30ba5978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416314548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3416314548
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3353324137
Short name T570
Test name
Test status
Simulation time 255010593 ps
CPU time 1.72 seconds
Started Jun 13 01:08:43 PM PDT 24
Finished Jun 13 01:08:45 PM PDT 24
Peak memory 209856 kb
Host smart-195bd9ad-ee74-4693-bf25-563f5c3cb583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353324137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3353324137
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3921176820
Short name T836
Test name
Test status
Simulation time 22541414 ps
CPU time 0.93 seconds
Started Jun 13 01:28:14 PM PDT 24
Finished Jun 13 01:28:15 PM PDT 24
Peak memory 205968 kb
Host smart-574c208c-891b-44ef-9374-45a6f04578b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921176820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3921176820
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1418792797
Short name T529
Test name
Test status
Simulation time 325082031 ps
CPU time 3.54 seconds
Started Jun 13 01:08:43 PM PDT 24
Finished Jun 13 01:08:48 PM PDT 24
Peak memory 216440 kb
Host smart-ed86c505-9086-4478-8bf0-0b5b69ec1dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418792797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1418792797
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2296842420
Short name T86
Test name
Test status
Simulation time 225893184 ps
CPU time 3.79 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:53 PM PDT 24
Peak memory 209768 kb
Host smart-cc41b318-1441-4e7d-9920-f3cfec9f3b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296842420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2296842420
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1226341989
Short name T116
Test name
Test status
Simulation time 105907169 ps
CPU time 1.94 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 214372 kb
Host smart-e8879df3-3917-46f1-8558-de02376b0899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226341989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1226341989
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.4142742736
Short name T270
Test name
Test status
Simulation time 986620440 ps
CPU time 3.79 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 214288 kb
Host smart-b667df6a-4b46-4c85-954d-7df12d5fb1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142742736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4142742736
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3962215288
Short name T60
Test name
Test status
Simulation time 299229915 ps
CPU time 3.41 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 219940 kb
Host smart-b5df1675-72e2-4795-a962-85fdd1d7df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962215288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3962215288
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1650164775
Short name T813
Test name
Test status
Simulation time 1796707332 ps
CPU time 10.99 seconds
Started Jun 13 01:08:42 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 209376 kb
Host smart-39b95cbf-0bf8-4723-9e73-0a2a78765522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650164775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1650164775
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.734710372
Short name T208
Test name
Test status
Simulation time 62453705 ps
CPU time 2.98 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:08:53 PM PDT 24
Peak memory 207044 kb
Host smart-7f7651b7-43be-4b2c-913b-023c938c1429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734710372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.734710372
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3876949515
Short name T705
Test name
Test status
Simulation time 478458145 ps
CPU time 11.99 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 208388 kb
Host smart-12dc7e53-01f3-4a73-a7c2-a06b4f0e643e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876949515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3876949515
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1820038517
Short name T914
Test name
Test status
Simulation time 68147372 ps
CPU time 2.7 seconds
Started Jun 13 01:08:43 PM PDT 24
Finished Jun 13 01:08:47 PM PDT 24
Peak memory 206964 kb
Host smart-99958c95-f4db-4116-a362-75697b88af70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820038517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1820038517
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.58749565
Short name T857
Test name
Test status
Simulation time 698927453 ps
CPU time 3.66 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 206948 kb
Host smart-a0ddf389-7f97-490b-87b8-f16ac2330f16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58749565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.58749565
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1124995097
Short name T324
Test name
Test status
Simulation time 28425445 ps
CPU time 2.28 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:49 PM PDT 24
Peak memory 218408 kb
Host smart-3d3b59a8-33ff-4b3e-bc75-91ebf58a9429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124995097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1124995097
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4209063984
Short name T724
Test name
Test status
Simulation time 38945993 ps
CPU time 2.22 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 208320 kb
Host smart-f4d0d5c8-9ebd-46ed-a725-a6f8e9ae968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209063984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4209063984
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1599693164
Short name T59
Test name
Test status
Simulation time 2522668973 ps
CPU time 54.89 seconds
Started Jun 13 02:48:57 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 222604 kb
Host smart-1e8b9167-1847-481b-8bf0-7d55211ec7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599693164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1599693164
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1919765662
Short name T247
Test name
Test status
Simulation time 315289984 ps
CPU time 14.95 seconds
Started Jun 13 02:20:45 PM PDT 24
Finished Jun 13 02:21:04 PM PDT 24
Peak memory 221108 kb
Host smart-4fd51ed6-4fe9-4d2d-b3cf-67a5cc406117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919765662 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1919765662
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.359294316
Short name T918
Test name
Test status
Simulation time 1435674180 ps
CPU time 6.53 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 209312 kb
Host smart-e0994313-861f-4e73-9287-99e8865e6416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359294316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.359294316
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.4175537325
Short name T894
Test name
Test status
Simulation time 1586871993 ps
CPU time 7.64 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:53 PM PDT 24
Peak memory 211048 kb
Host smart-ec0d3498-bdff-47cb-97cf-877d31ab9e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175537325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.4175537325
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.332748869
Short name T435
Test name
Test status
Simulation time 55175034 ps
CPU time 0.94 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:07 PM PDT 24
Peak memory 206160 kb
Host smart-53717129-628b-4ef4-a804-e377f062d528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332748869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.332748869
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2110698120
Short name T393
Test name
Test status
Simulation time 46410586 ps
CPU time 3.62 seconds
Started Jun 13 01:07:06 PM PDT 24
Finished Jun 13 01:07:11 PM PDT 24
Peak memory 214292 kb
Host smart-9ffca9a2-6d84-4542-9ee3-5b6b7553476c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110698120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2110698120
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1350763683
Short name T371
Test name
Test status
Simulation time 24069423 ps
CPU time 1.96 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:08 PM PDT 24
Peak memory 207692 kb
Host smart-317175b7-cef6-40f4-99be-2080080582a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350763683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1350763683
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.980740153
Short name T304
Test name
Test status
Simulation time 154266194 ps
CPU time 3.9 seconds
Started Jun 13 01:07:07 PM PDT 24
Finished Jun 13 01:07:12 PM PDT 24
Peak memory 208528 kb
Host smart-32b75108-39ed-4712-860c-004c62087e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980740153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.980740153
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1053043494
Short name T2
Test name
Test status
Simulation time 279878154 ps
CPU time 2.81 seconds
Started Jun 13 01:07:17 PM PDT 24
Finished Jun 13 01:07:21 PM PDT 24
Peak memory 219568 kb
Host smart-95774ac6-722d-40c3-ae84-a285f36afc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053043494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1053043494
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.275446755
Short name T282
Test name
Test status
Simulation time 218004926 ps
CPU time 4.18 seconds
Started Jun 13 01:07:06 PM PDT 24
Finished Jun 13 01:07:11 PM PDT 24
Peak memory 214272 kb
Host smart-d70d0018-e9b2-4ddc-8378-68052575e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275446755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.275446755
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.551622012
Short name T854
Test name
Test status
Simulation time 1885218645 ps
CPU time 47.99 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:54 PM PDT 24
Peak memory 208680 kb
Host smart-778c0b53-40e0-4f3f-bc9b-a305b42c3e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551622012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.551622012
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.609508957
Short name T13
Test name
Test status
Simulation time 2144846844 ps
CPU time 20.85 seconds
Started Jun 13 01:07:02 PM PDT 24
Finished Jun 13 01:07:24 PM PDT 24
Peak memory 232288 kb
Host smart-0b743d8a-fee4-4e58-8137-4b851b6a63e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609508957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.609508957
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4205276456
Short name T734
Test name
Test status
Simulation time 1223624347 ps
CPU time 15.79 seconds
Started Jun 13 01:07:03 PM PDT 24
Finished Jun 13 01:07:20 PM PDT 24
Peak memory 208036 kb
Host smart-39a3a9d7-1c0b-40a1-a4a4-56596f928d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205276456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4205276456
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2458061546
Short name T319
Test name
Test status
Simulation time 52171203 ps
CPU time 2.8 seconds
Started Jun 13 01:07:02 PM PDT 24
Finished Jun 13 01:07:06 PM PDT 24
Peak memory 208884 kb
Host smart-83fe3a3c-608c-4d7d-9a4b-809685522ba1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458061546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2458061546
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.937096233
Short name T342
Test name
Test status
Simulation time 104060741 ps
CPU time 4.33 seconds
Started Jun 13 01:07:03 PM PDT 24
Finished Jun 13 01:07:08 PM PDT 24
Peak memory 208364 kb
Host smart-1826450b-2aa4-4ea2-bcd6-2d848fdd0929
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937096233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.937096233
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1099847459
Short name T212
Test name
Test status
Simulation time 219130693 ps
CPU time 5.85 seconds
Started Jun 13 01:07:04 PM PDT 24
Finished Jun 13 01:07:11 PM PDT 24
Peak memory 208424 kb
Host smart-26cbaac0-351d-4d13-baf6-ddc1055f16c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099847459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1099847459
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2724578137
Short name T741
Test name
Test status
Simulation time 1896218691 ps
CPU time 21.41 seconds
Started Jun 13 01:07:08 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 208664 kb
Host smart-ac7c9e85-37d0-4a02-9e80-0d8b92ebc14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724578137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2724578137
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4060965306
Short name T889
Test name
Test status
Simulation time 36214188 ps
CPU time 2.26 seconds
Started Jun 13 01:07:03 PM PDT 24
Finished Jun 13 01:07:07 PM PDT 24
Peak memory 208180 kb
Host smart-a1a86aaf-fd79-4eb0-8b0d-08667c628155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060965306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4060965306
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3995166225
Short name T377
Test name
Test status
Simulation time 1918694791 ps
CPU time 19.98 seconds
Started Jun 13 01:07:04 PM PDT 24
Finished Jun 13 01:07:25 PM PDT 24
Peak memory 221852 kb
Host smart-e6ed13d7-e28e-4a70-8dc9-34ece0e47855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995166225 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3995166225
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3274325529
Short name T673
Test name
Test status
Simulation time 4549417846 ps
CPU time 27.58 seconds
Started Jun 13 01:07:04 PM PDT 24
Finished Jun 13 01:07:33 PM PDT 24
Peak memory 208720 kb
Host smart-4641c7a9-d983-4652-a018-8ac47d03f248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274325529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3274325529
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3952639737
Short name T713
Test name
Test status
Simulation time 99132379 ps
CPU time 3.66 seconds
Started Jun 13 01:07:04 PM PDT 24
Finished Jun 13 01:07:09 PM PDT 24
Peak memory 210196 kb
Host smart-f0c494cb-0b88-40d2-b184-e033f3d2b2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952639737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3952639737
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3468073276
Short name T834
Test name
Test status
Simulation time 13976770 ps
CPU time 0.76 seconds
Started Jun 13 01:35:37 PM PDT 24
Finished Jun 13 01:35:39 PM PDT 24
Peak memory 205908 kb
Host smart-f12579d8-face-4745-b9d2-44d09f4ce964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468073276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3468073276
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4249242301
Short name T412
Test name
Test status
Simulation time 3947302233 ps
CPU time 107.61 seconds
Started Jun 13 01:19:29 PM PDT 24
Finished Jun 13 01:21:18 PM PDT 24
Peak memory 216400 kb
Host smart-e376b02c-9af2-4e3a-9fa1-227fbc308347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249242301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4249242301
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2065254657
Short name T671
Test name
Test status
Simulation time 386808988 ps
CPU time 7.97 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 218396 kb
Host smart-3f80a688-814b-4d5a-9caf-3f3158fef4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065254657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2065254657
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.176461083
Short name T461
Test name
Test status
Simulation time 501966489 ps
CPU time 3.02 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 214336 kb
Host smart-e9ac346b-62f1-4b59-96a6-3272944cdc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176461083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.176461083
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3261953517
Short name T899
Test name
Test status
Simulation time 133442501 ps
CPU time 5.99 seconds
Started Jun 13 02:06:04 PM PDT 24
Finished Jun 13 02:06:11 PM PDT 24
Peak memory 214352 kb
Host smart-639150be-95e8-4233-b253-87ab6fc10346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261953517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3261953517
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.437154077
Short name T666
Test name
Test status
Simulation time 153677355 ps
CPU time 3.62 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 214248 kb
Host smart-cd6800fc-61f6-43a0-b2df-00b72824bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437154077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.437154077
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2773113851
Short name T536
Test name
Test status
Simulation time 198159633 ps
CPU time 5.27 seconds
Started Jun 13 01:54:49 PM PDT 24
Finished Jun 13 01:54:59 PM PDT 24
Peak memory 209224 kb
Host smart-67630adc-b878-4720-a297-89bc592b5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773113851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2773113851
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3011496079
Short name T144
Test name
Test status
Simulation time 545593791 ps
CPU time 6.6 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 208540 kb
Host smart-1d76e3e4-ddda-462a-9627-672479fd43b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011496079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3011496079
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1356644847
Short name T476
Test name
Test status
Simulation time 66044576 ps
CPU time 3.46 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 207068 kb
Host smart-c25e2b24-45ba-4340-aed9-ab89d3656bf9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356644847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1356644847
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.891607959
Short name T619
Test name
Test status
Simulation time 26171504 ps
CPU time 2.12 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 208516 kb
Host smart-d6e1e90f-4519-40ff-9e24-aae67a53f349
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891607959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.891607959
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1815518767
Short name T38
Test name
Test status
Simulation time 45715641 ps
CPU time 2.3 seconds
Started Jun 13 02:30:37 PM PDT 24
Finished Jun 13 02:30:40 PM PDT 24
Peak memory 206916 kb
Host smart-8c324409-f365-42a8-97e3-b516eb5b9cb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815518767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1815518767
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1937441048
Short name T526
Test name
Test status
Simulation time 52528578 ps
CPU time 2.78 seconds
Started Jun 13 01:29:03 PM PDT 24
Finished Jun 13 01:29:07 PM PDT 24
Peak memory 209296 kb
Host smart-317116f8-a4b9-4fad-96a8-9148129f2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937441048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1937441048
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3209994838
Short name T689
Test name
Test status
Simulation time 345935484 ps
CPU time 5.43 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 207336 kb
Host smart-8e61743b-2710-480a-8cf3-7ce3d584d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209994838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3209994838
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2324206258
Short name T89
Test name
Test status
Simulation time 1474077193 ps
CPU time 43.85 seconds
Started Jun 13 01:23:45 PM PDT 24
Finished Jun 13 01:24:29 PM PDT 24
Peak memory 216328 kb
Host smart-83ef8649-2d33-463e-8b74-da657d6dcb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324206258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2324206258
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1862849147
Short name T900
Test name
Test status
Simulation time 1031902623 ps
CPU time 10.8 seconds
Started Jun 13 01:22:38 PM PDT 24
Finished Jun 13 01:22:50 PM PDT 24
Peak memory 222496 kb
Host smart-9acc9be6-e445-41a9-a2fc-2994d4f0d7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862849147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1862849147
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1850511210
Short name T566
Test name
Test status
Simulation time 261998483 ps
CPU time 4.04 seconds
Started Jun 13 01:47:04 PM PDT 24
Finished Jun 13 01:47:10 PM PDT 24
Peak memory 218408 kb
Host smart-5fa0a733-e9b2-4dbf-bcf5-9524d9d61beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850511210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1850511210
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.20216002
Short name T446
Test name
Test status
Simulation time 166604597 ps
CPU time 2.66 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:49 PM PDT 24
Peak memory 210188 kb
Host smart-4f0dc4f8-f2e4-4a52-9fdf-ce053dfd0460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20216002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.20216002
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2070879404
Short name T437
Test name
Test status
Simulation time 34935571 ps
CPU time 0.8 seconds
Started Jun 13 02:21:36 PM PDT 24
Finished Jun 13 02:21:38 PM PDT 24
Peak memory 205916 kb
Host smart-6f019fd3-f7b0-4f1c-bf17-3280760c7877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070879404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2070879404
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1707907071
Short name T422
Test name
Test status
Simulation time 240377398 ps
CPU time 4.21 seconds
Started Jun 13 02:12:39 PM PDT 24
Finished Jun 13 02:12:44 PM PDT 24
Peak memory 215052 kb
Host smart-c7797994-0b52-406b-a271-7eb00cba5d1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707907071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1707907071
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.178284689
Short name T641
Test name
Test status
Simulation time 282134696 ps
CPU time 8.82 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 221828 kb
Host smart-52cb3363-9a78-4059-90d5-97de05ed1054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178284689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.178284689
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2012769299
Short name T635
Test name
Test status
Simulation time 77641429 ps
CPU time 2.02 seconds
Started Jun 13 01:23:34 PM PDT 24
Finished Jun 13 01:23:37 PM PDT 24
Peak memory 209064 kb
Host smart-c95ef251-c973-4d66-b8c6-1e6964f26691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012769299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2012769299
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3156438826
Short name T837
Test name
Test status
Simulation time 277937624 ps
CPU time 8.15 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 219780 kb
Host smart-be017344-8ff7-4d83-8594-918733d95130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156438826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3156438826
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3771336694
Short name T791
Test name
Test status
Simulation time 138839429 ps
CPU time 2.78 seconds
Started Jun 13 01:21:24 PM PDT 24
Finished Jun 13 01:21:27 PM PDT 24
Peak memory 214352 kb
Host smart-0969060c-7d33-4dbe-9824-51488fcc86cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771336694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3771336694
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2303923131
Short name T830
Test name
Test status
Simulation time 280330364 ps
CPU time 8.35 seconds
Started Jun 13 01:28:30 PM PDT 24
Finished Jun 13 01:28:39 PM PDT 24
Peak memory 222508 kb
Host smart-e16dcd1e-1e30-4e0e-a0cf-4f4aa644150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303923131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2303923131
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1199713845
Short name T829
Test name
Test status
Simulation time 4716657254 ps
CPU time 40.55 seconds
Started Jun 13 01:15:05 PM PDT 24
Finished Jun 13 01:15:47 PM PDT 24
Peak memory 208904 kb
Host smart-50cca49f-0cf2-4848-8414-f2754bc009cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199713845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1199713845
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.442898492
Short name T503
Test name
Test status
Simulation time 4911939656 ps
CPU time 13.99 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:09:04 PM PDT 24
Peak memory 208380 kb
Host smart-6e231792-04f5-4bf6-b121-ad2ecb39c423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442898492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.442898492
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1615743499
Short name T620
Test name
Test status
Simulation time 191783139 ps
CPU time 2.86 seconds
Started Jun 13 01:08:48 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 206888 kb
Host smart-8fff64ab-734b-4576-9883-eb3eeaff052b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615743499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1615743499
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2647110188
Short name T509
Test name
Test status
Simulation time 173186446 ps
CPU time 3.38 seconds
Started Jun 13 01:27:57 PM PDT 24
Finished Jun 13 01:28:01 PM PDT 24
Peak memory 208412 kb
Host smart-3168404e-addd-4bbb-aed3-a7f68700bb27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647110188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2647110188
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.232280072
Short name T438
Test name
Test status
Simulation time 235534125 ps
CPU time 2.29 seconds
Started Jun 13 01:19:48 PM PDT 24
Finished Jun 13 01:19:51 PM PDT 24
Peak memory 206876 kb
Host smart-4bbb2568-17e0-413c-a8fc-3c065dd8b9e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232280072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.232280072
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2920716272
Short name T859
Test name
Test status
Simulation time 166045078 ps
CPU time 2.86 seconds
Started Jun 13 02:06:27 PM PDT 24
Finished Jun 13 02:06:31 PM PDT 24
Peak memory 209044 kb
Host smart-f7fcc1ac-5410-46c2-9195-923954914df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920716272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2920716272
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2981404834
Short name T732
Test name
Test status
Simulation time 93030721 ps
CPU time 2.01 seconds
Started Jun 13 01:50:54 PM PDT 24
Finished Jun 13 01:50:59 PM PDT 24
Peak memory 208560 kb
Host smart-bec21ec4-60ba-4096-abb0-8301595bf646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981404834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2981404834
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3094378889
Short name T204
Test name
Test status
Simulation time 22376695160 ps
CPU time 40.4 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:09:27 PM PDT 24
Peak memory 216340 kb
Host smart-f0aaeeab-2d5e-469e-bade-6edb6ee976b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094378889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3094378889
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.939048213
Short name T535
Test name
Test status
Simulation time 737022557 ps
CPU time 6.15 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 214292 kb
Host smart-30fbc012-7453-4574-bac0-e8b067c4d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939048213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.939048213
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2880683275
Short name T502
Test name
Test status
Simulation time 130847196 ps
CPU time 2.1 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 209876 kb
Host smart-eefbc824-eb6f-4d4f-9496-11b63121fd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880683275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2880683275
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3957105954
Short name T788
Test name
Test status
Simulation time 48252686 ps
CPU time 0.79 seconds
Started Jun 13 02:08:26 PM PDT 24
Finished Jun 13 02:08:29 PM PDT 24
Peak memory 205904 kb
Host smart-8a55f463-8935-41d9-89b4-039eae3b9765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957105954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3957105954
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.4203613386
Short name T257
Test name
Test status
Simulation time 938642641 ps
CPU time 4.66 seconds
Started Jun 13 01:30:02 PM PDT 24
Finished Jun 13 01:30:07 PM PDT 24
Peak memory 215564 kb
Host smart-bda3e358-5ee0-4fd4-a307-65f4b9a397f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203613386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4203613386
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.313158379
Short name T890
Test name
Test status
Simulation time 60435809 ps
CPU time 2.24 seconds
Started Jun 13 01:39:21 PM PDT 24
Finished Jun 13 01:39:24 PM PDT 24
Peak memory 214584 kb
Host smart-95ef398c-fbe2-4773-893f-6e80f757aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313158379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.313158379
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1315326174
Short name T350
Test name
Test status
Simulation time 679218629 ps
CPU time 5.12 seconds
Started Jun 13 01:08:43 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 218288 kb
Host smart-66127bed-50d2-47c9-b2ef-14c7959da8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315326174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1315326174
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1750780859
Short name T110
Test name
Test status
Simulation time 1026588768 ps
CPU time 20.1 seconds
Started Jun 13 01:42:48 PM PDT 24
Finished Jun 13 01:43:11 PM PDT 24
Peak memory 209692 kb
Host smart-003cd9dc-f346-42e7-905a-95e02469da21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750780859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1750780859
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_random.1673752465
Short name T345
Test name
Test status
Simulation time 343873212 ps
CPU time 9.24 seconds
Started Jun 13 02:01:20 PM PDT 24
Finished Jun 13 02:01:31 PM PDT 24
Peak memory 218428 kb
Host smart-90708707-2462-416b-bc6b-2f74597f8230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673752465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1673752465
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.923728298
Short name T402
Test name
Test status
Simulation time 2845559564 ps
CPU time 17.29 seconds
Started Jun 13 01:18:38 PM PDT 24
Finished Jun 13 01:18:55 PM PDT 24
Peak memory 207096 kb
Host smart-0b215521-a59f-499d-b7c7-f7a16ad098a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923728298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.923728298
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3531094119
Short name T735
Test name
Test status
Simulation time 313308325 ps
CPU time 4.5 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:32:02 PM PDT 24
Peak memory 208868 kb
Host smart-62df8dd2-998a-4f0a-a157-8f24eda0bd41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531094119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3531094119
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3906327961
Short name T858
Test name
Test status
Simulation time 132872737 ps
CPU time 4.74 seconds
Started Jun 13 02:22:16 PM PDT 24
Finished Jun 13 02:22:21 PM PDT 24
Peak memory 208128 kb
Host smart-359fca09-fea9-432e-b904-3d8ad302d250
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906327961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3906327961
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.379849904
Short name T756
Test name
Test status
Simulation time 323833401 ps
CPU time 3.01 seconds
Started Jun 13 02:21:51 PM PDT 24
Finished Jun 13 02:21:54 PM PDT 24
Peak memory 206928 kb
Host smart-2f2ffd84-f809-43fc-8f14-61b83a63a7d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379849904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.379849904
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.485424061
Short name T343
Test name
Test status
Simulation time 328959956 ps
CPU time 3.19 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 218312 kb
Host smart-93fe4cf4-35b1-4e8c-877c-9893b834f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485424061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.485424061
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3634548099
Short name T471
Test name
Test status
Simulation time 1353069473 ps
CPU time 16.93 seconds
Started Jun 13 02:19:35 PM PDT 24
Finished Jun 13 02:19:56 PM PDT 24
Peak memory 208228 kb
Host smart-fb53359f-8e26-4312-83ff-ffd6e7c21954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634548099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3634548099
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3322822341
Short name T703
Test name
Test status
Simulation time 791502154 ps
CPU time 33.5 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:09:23 PM PDT 24
Peak memory 215088 kb
Host smart-f2a5cf9a-89cc-4d26-80a5-9540ac901a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322822341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3322822341
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3027778689
Short name T649
Test name
Test status
Simulation time 944690882 ps
CPU time 7.38 seconds
Started Jun 13 01:30:59 PM PDT 24
Finished Jun 13 01:31:07 PM PDT 24
Peak memory 207268 kb
Host smart-b642e8b3-dcac-4c23-ae93-a0b61da552b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027778689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3027778689
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1674130655
Short name T814
Test name
Test status
Simulation time 54410719 ps
CPU time 2.05 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 209736 kb
Host smart-3b72b783-25c1-49fd-9933-1513d0059bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674130655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1674130655
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3654315823
Short name T841
Test name
Test status
Simulation time 49986974 ps
CPU time 0.86 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:49 PM PDT 24
Peak memory 205868 kb
Host smart-25a1ad62-cfb6-4aae-b867-109ced8c46be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654315823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3654315823
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.117843357
Short name T337
Test name
Test status
Simulation time 45254729 ps
CPU time 3.46 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:29:59 PM PDT 24
Peak memory 215352 kb
Host smart-1583a95c-3dcb-41f7-a33f-f50b7b34dd94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117843357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.117843357
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3118094098
Short name T242
Test name
Test status
Simulation time 336905375 ps
CPU time 2.55 seconds
Started Jun 13 01:21:13 PM PDT 24
Finished Jun 13 01:21:17 PM PDT 24
Peak memory 209088 kb
Host smart-236ca393-363a-48bb-8cd7-4460f14bdef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118094098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3118094098
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3655202551
Short name T539
Test name
Test status
Simulation time 53079034 ps
CPU time 2.51 seconds
Started Jun 13 01:41:30 PM PDT 24
Finished Jun 13 01:41:33 PM PDT 24
Peak memory 209000 kb
Host smart-e64f1615-b053-4a55-9f6f-b0ee81adad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655202551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3655202551
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2914263020
Short name T105
Test name
Test status
Simulation time 360329162 ps
CPU time 6.8 seconds
Started Jun 13 01:23:20 PM PDT 24
Finished Jun 13 01:23:29 PM PDT 24
Peak memory 214272 kb
Host smart-1efb2eba-38d7-41f3-a455-a4e3bde6c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914263020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2914263020
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3678513623
Short name T757
Test name
Test status
Simulation time 141538492 ps
CPU time 3.23 seconds
Started Jun 13 02:03:29 PM PDT 24
Finished Jun 13 02:03:33 PM PDT 24
Peak memory 222328 kb
Host smart-a236af33-86b6-49f1-805a-17ad839e3dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678513623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3678513623
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1433147095
Short name T540
Test name
Test status
Simulation time 69222801 ps
CPU time 2.43 seconds
Started Jun 13 02:19:41 PM PDT 24
Finished Jun 13 02:19:49 PM PDT 24
Peak memory 219356 kb
Host smart-d0a27274-7094-4ac5-9e4a-0bc02fc269f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433147095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1433147095
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3385370312
Short name T878
Test name
Test status
Simulation time 160455503 ps
CPU time 6.75 seconds
Started Jun 13 01:46:52 PM PDT 24
Finished Jun 13 01:47:01 PM PDT 24
Peak memory 210408 kb
Host smart-e10e8e36-2434-43f6-8ada-470be4702677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385370312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3385370312
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3618599970
Short name T701
Test name
Test status
Simulation time 20553753297 ps
CPU time 65.25 seconds
Started Jun 13 01:53:00 PM PDT 24
Finished Jun 13 01:54:06 PM PDT 24
Peak memory 208392 kb
Host smart-2816bcdc-a09d-45df-b9b9-0435dc8c839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618599970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3618599970
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2915259250
Short name T520
Test name
Test status
Simulation time 258284165 ps
CPU time 3.28 seconds
Started Jun 13 02:05:47 PM PDT 24
Finished Jun 13 02:05:52 PM PDT 24
Peak memory 208412 kb
Host smart-ccfcf253-266a-40d2-9cac-84568bb1f427
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915259250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2915259250
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2654822944
Short name T818
Test name
Test status
Simulation time 1900207086 ps
CPU time 58.2 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:09:45 PM PDT 24
Peak memory 208700 kb
Host smart-be868004-f525-494a-a416-3a7e42453ef2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654822944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2654822944
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3793249216
Short name T622
Test name
Test status
Simulation time 26148409 ps
CPU time 1.97 seconds
Started Jun 13 02:29:47 PM PDT 24
Finished Jun 13 02:29:49 PM PDT 24
Peak memory 207044 kb
Host smart-c6ee272d-024f-40cd-9e11-8678e749c102
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793249216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3793249216
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1931706276
Short name T651
Test name
Test status
Simulation time 61690158 ps
CPU time 2.82 seconds
Started Jun 13 01:14:37 PM PDT 24
Finished Jun 13 01:14:40 PM PDT 24
Peak memory 208364 kb
Host smart-6f87aaa8-ecfd-48cb-be83-e9021fac56b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931706276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1931706276
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2018949476
Short name T907
Test name
Test status
Simulation time 1110706832 ps
CPU time 28.02 seconds
Started Jun 13 02:43:40 PM PDT 24
Finished Jun 13 02:44:17 PM PDT 24
Peak memory 216436 kb
Host smart-1c10ad5f-d022-45e4-96c4-b01e26e6a208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018949476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2018949476
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2567784124
Short name T556
Test name
Test status
Simulation time 1189050866 ps
CPU time 7.25 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 207488 kb
Host smart-fb744ebf-d874-4711-b0b6-f717fab85dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567784124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2567784124
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.36575146
Short name T211
Test name
Test status
Simulation time 52739177 ps
CPU time 0.77 seconds
Started Jun 13 01:35:25 PM PDT 24
Finished Jun 13 01:35:27 PM PDT 24
Peak memory 205900 kb
Host smart-5a29a276-75eb-4e89-959c-5d774ef125e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.36575146
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1651348512
Short name T391
Test name
Test status
Simulation time 136944714 ps
CPU time 2.98 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 214280 kb
Host smart-e6143338-6de7-4c0b-bc52-69ffa19e8a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651348512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1651348512
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3492443477
Short name T584
Test name
Test status
Simulation time 33232346 ps
CPU time 2.06 seconds
Started Jun 13 02:18:39 PM PDT 24
Finished Jun 13 02:18:48 PM PDT 24
Peak memory 219688 kb
Host smart-f641374b-1430-4003-bdc5-c228bcfe87c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492443477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3492443477
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3375501633
Short name T777
Test name
Test status
Simulation time 82565901 ps
CPU time 3.75 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 222516 kb
Host smart-14186d78-999b-45eb-9181-70da064dbd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375501633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3375501633
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.813465394
Short name T289
Test name
Test status
Simulation time 135992077 ps
CPU time 3.75 seconds
Started Jun 13 02:39:42 PM PDT 24
Finished Jun 13 02:39:53 PM PDT 24
Peak memory 221024 kb
Host smart-f76f4530-842c-4602-9a77-c2626114cedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813465394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.813465394
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.964133191
Short name T321
Test name
Test status
Simulation time 139636389 ps
CPU time 2.35 seconds
Started Jun 13 02:10:22 PM PDT 24
Finished Jun 13 02:10:25 PM PDT 24
Peak memory 207716 kb
Host smart-8061604c-dfe4-42e8-ae8b-01dfcfd46343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964133191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.964133191
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.108013032
Short name T898
Test name
Test status
Simulation time 50877769 ps
CPU time 3.6 seconds
Started Jun 13 01:09:10 PM PDT 24
Finished Jun 13 01:09:17 PM PDT 24
Peak memory 208216 kb
Host smart-b55e6e7d-236e-46a7-ae5b-c53bbb085939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108013032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.108013032
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1659779809
Short name T465
Test name
Test status
Simulation time 247257247 ps
CPU time 3.02 seconds
Started Jun 13 01:38:55 PM PDT 24
Finished Jun 13 01:39:00 PM PDT 24
Peak memory 206956 kb
Host smart-c965ad77-3257-4206-9e46-e70e0ce1028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659779809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1659779809
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3567126353
Short name T500
Test name
Test status
Simulation time 594849675 ps
CPU time 15.92 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:09:05 PM PDT 24
Peak memory 207960 kb
Host smart-c2a6166c-5e1b-4cb9-a8f6-ea8bdd292912
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567126353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3567126353
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.18433289
Short name T825
Test name
Test status
Simulation time 931885968 ps
CPU time 13.98 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:09:01 PM PDT 24
Peak memory 208064 kb
Host smart-ed8daa1a-184c-4e74-969a-ae857f5cc853
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18433289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.18433289
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.332623420
Short name T662
Test name
Test status
Simulation time 219985192 ps
CPU time 3.18 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 208280 kb
Host smart-a0dda5e9-d01f-4d02-a877-03eefeaa61fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332623420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.332623420
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3511628348
Short name T628
Test name
Test status
Simulation time 441734653 ps
CPU time 2.88 seconds
Started Jun 13 02:39:35 PM PDT 24
Finished Jun 13 02:39:44 PM PDT 24
Peak memory 215776 kb
Host smart-e16826a3-d298-4b14-b363-3f841e467c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511628348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3511628348
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4252378398
Short name T699
Test name
Test status
Simulation time 155913552 ps
CPU time 2.35 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:49 PM PDT 24
Peak memory 206680 kb
Host smart-0fd6c2b4-79d3-4cb0-bae7-4450576834a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252378398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4252378398
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1766191697
Short name T575
Test name
Test status
Simulation time 241056567 ps
CPU time 0.87 seconds
Started Jun 13 01:41:40 PM PDT 24
Finished Jun 13 01:41:41 PM PDT 24
Peak memory 205924 kb
Host smart-6537d93e-e283-4fed-909b-8f36a2d300e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766191697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1766191697
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2038234353
Short name T729
Test name
Test status
Simulation time 869791450 ps
CPU time 8.05 seconds
Started Jun 13 01:18:40 PM PDT 24
Finished Jun 13 01:18:49 PM PDT 24
Peak memory 209436 kb
Host smart-baf5f479-b4cf-47d0-8d65-95d104ab462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038234353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2038234353
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.474295690
Short name T215
Test name
Test status
Simulation time 191017610 ps
CPU time 3.63 seconds
Started Jun 13 01:08:48 PM PDT 24
Finished Jun 13 01:08:54 PM PDT 24
Peak memory 209908 kb
Host smart-92ba2bd8-3fab-480f-8c67-2e6184d65881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474295690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.474295690
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.69458775
Short name T572
Test name
Test status
Simulation time 33092703 ps
CPU time 0.76 seconds
Started Jun 13 01:24:45 PM PDT 24
Finished Jun 13 01:24:47 PM PDT 24
Peak memory 205824 kb
Host smart-cd607cae-91ae-4bf2-b7e9-b4f651eb6cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69458775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.69458775
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1112896671
Short name T78
Test name
Test status
Simulation time 390535608 ps
CPU time 5.11 seconds
Started Jun 13 01:19:50 PM PDT 24
Finished Jun 13 01:19:56 PM PDT 24
Peak memory 209256 kb
Host smart-e3254091-67cd-40f6-bafd-672ec98a1efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112896671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1112896671
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1349679647
Short name T755
Test name
Test status
Simulation time 79547931 ps
CPU time 1.84 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:49 PM PDT 24
Peak memory 207836 kb
Host smart-46ebdb8a-773d-43c6-a470-303df33f7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349679647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1349679647
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1784363951
Short name T804
Test name
Test status
Simulation time 149491775 ps
CPU time 4.82 seconds
Started Jun 13 01:55:57 PM PDT 24
Finished Jun 13 01:56:04 PM PDT 24
Peak memory 214272 kb
Host smart-dc0e8463-bb12-4076-81e0-5070c77fdf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784363951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1784363951
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.411446474
Short name T710
Test name
Test status
Simulation time 63527025 ps
CPU time 2.99 seconds
Started Jun 13 02:13:00 PM PDT 24
Finished Jun 13 02:13:04 PM PDT 24
Peak memory 214304 kb
Host smart-33c33070-2990-49eb-b865-7d849ce3d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411446474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.411446474
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1228046646
Short name T902
Test name
Test status
Simulation time 136522207 ps
CPU time 3.03 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 208172 kb
Host smart-61a60cda-1e8f-446c-acdd-f32562712020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228046646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1228046646
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3101345561
Short name T519
Test name
Test status
Simulation time 118432358 ps
CPU time 2.7 seconds
Started Jun 13 01:55:55 PM PDT 24
Finished Jun 13 01:55:59 PM PDT 24
Peak memory 207464 kb
Host smart-29f4ad40-095f-449c-bf6b-6dee0534c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101345561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3101345561
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2600543561
Short name T565
Test name
Test status
Simulation time 191321085 ps
CPU time 4.83 seconds
Started Jun 13 01:54:35 PM PDT 24
Finished Jun 13 01:54:46 PM PDT 24
Peak memory 206928 kb
Host smart-e3b5045b-da18-4d6c-be9e-d5135a865569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600543561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2600543561
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1800856029
Short name T477
Test name
Test status
Simulation time 5403490636 ps
CPU time 32.92 seconds
Started Jun 13 01:55:21 PM PDT 24
Finished Jun 13 01:55:54 PM PDT 24
Peak memory 209288 kb
Host smart-d766468a-b107-4ff0-9f03-99d7346a14a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800856029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1800856029
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.935146071
Short name T873
Test name
Test status
Simulation time 49738595 ps
CPU time 2.84 seconds
Started Jun 13 02:34:01 PM PDT 24
Finished Jun 13 02:34:06 PM PDT 24
Peak memory 206868 kb
Host smart-87e44b41-9d4a-4f38-b8ff-b51c96db3b2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935146071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.935146071
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.742956995
Short name T780
Test name
Test status
Simulation time 270698477 ps
CPU time 4.27 seconds
Started Jun 13 01:19:42 PM PDT 24
Finished Jun 13 01:19:47 PM PDT 24
Peak memory 206984 kb
Host smart-3cce3374-4822-4b84-a93a-0419b63d73ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742956995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.742956995
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1863298115
Short name T794
Test name
Test status
Simulation time 338214617 ps
CPU time 3.2 seconds
Started Jun 13 02:17:58 PM PDT 24
Finished Jun 13 02:18:08 PM PDT 24
Peak memory 214320 kb
Host smart-3322e1c3-bfe6-41bc-92c8-943955736e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863298115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1863298115
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2624125701
Short name T656
Test name
Test status
Simulation time 64639955 ps
CPU time 2.85 seconds
Started Jun 13 01:34:45 PM PDT 24
Finished Jun 13 01:34:49 PM PDT 24
Peak memory 208156 kb
Host smart-23465752-b41f-4e6e-a62b-57d3d392f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624125701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2624125701
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4000825259
Short name T201
Test name
Test status
Simulation time 297549972 ps
CPU time 15.22 seconds
Started Jun 13 01:26:23 PM PDT 24
Finished Jun 13 01:26:39 PM PDT 24
Peak memory 215512 kb
Host smart-2026f7a2-e25a-4e83-a81b-fa002ae31f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000825259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4000825259
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.990089875
Short name T195
Test name
Test status
Simulation time 1278696798 ps
CPU time 12.61 seconds
Started Jun 13 02:04:05 PM PDT 24
Finished Jun 13 02:04:19 PM PDT 24
Peak memory 222704 kb
Host smart-2702e316-e514-4d83-94c1-4a0e973437d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990089875 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.990089875
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1198199396
Short name T796
Test name
Test status
Simulation time 814761932 ps
CPU time 6.13 seconds
Started Jun 13 02:36:34 PM PDT 24
Finished Jun 13 02:36:43 PM PDT 24
Peak memory 214320 kb
Host smart-316684aa-0840-4951-9b1b-5ac138ea96e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198199396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1198199396
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.681049091
Short name T781
Test name
Test status
Simulation time 108315132 ps
CPU time 2.67 seconds
Started Jun 13 02:15:41 PM PDT 24
Finished Jun 13 02:15:44 PM PDT 24
Peak memory 209968 kb
Host smart-076ae2f4-af43-4564-9340-63a0774c132c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681049091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.681049091
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3838560805
Short name T863
Test name
Test status
Simulation time 12964460 ps
CPU time 0.93 seconds
Started Jun 13 01:08:47 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 206080 kb
Host smart-ecfba7c8-725e-4fad-8f75-308272990f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838560805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3838560805
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3286770916
Short name T407
Test name
Test status
Simulation time 39312172 ps
CPU time 3.18 seconds
Started Jun 13 01:29:32 PM PDT 24
Finished Jun 13 01:29:36 PM PDT 24
Peak memory 214436 kb
Host smart-80470f60-3056-4097-8b57-7d5a95a18dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286770916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3286770916
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3915682600
Short name T801
Test name
Test status
Simulation time 67419056 ps
CPU time 4.07 seconds
Started Jun 13 02:04:18 PM PDT 24
Finished Jun 13 02:04:23 PM PDT 24
Peak memory 214536 kb
Host smart-6cf43110-e860-48ac-8dda-f9b63f1fedf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915682600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3915682600
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2303303672
Short name T912
Test name
Test status
Simulation time 125132552 ps
CPU time 3.57 seconds
Started Jun 13 02:05:03 PM PDT 24
Finished Jun 13 02:05:07 PM PDT 24
Peak memory 209828 kb
Host smart-7c4b2a68-5b32-4150-8c10-a4e0a95c483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303303672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2303303672
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3323581631
Short name T331
Test name
Test status
Simulation time 214142973 ps
CPU time 2.22 seconds
Started Jun 13 01:42:17 PM PDT 24
Finished Jun 13 01:42:20 PM PDT 24
Peak memory 206696 kb
Host smart-bdb259b1-e945-410b-8996-f387846fcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323581631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3323581631
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4023646877
Short name T562
Test name
Test status
Simulation time 33921548 ps
CPU time 1.81 seconds
Started Jun 13 01:26:18 PM PDT 24
Finished Jun 13 01:26:20 PM PDT 24
Peak memory 214284 kb
Host smart-79ac380e-1b55-4e79-8417-7aaf5abf0c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023646877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4023646877
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.829931343
Short name T418
Test name
Test status
Simulation time 55172825 ps
CPU time 3.6 seconds
Started Jun 13 01:55:25 PM PDT 24
Finished Jun 13 01:55:30 PM PDT 24
Peak memory 209536 kb
Host smart-9bc44259-7932-490d-9cb3-b0be3d8d83f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829931343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.829931343
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3832250810
Short name T871
Test name
Test status
Simulation time 85499333 ps
CPU time 2.43 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:48 PM PDT 24
Peak memory 207236 kb
Host smart-33b49a13-756c-4483-8926-4aac7fd5d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832250810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3832250810
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2228916698
Short name T853
Test name
Test status
Simulation time 2865465023 ps
CPU time 13.23 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:09:03 PM PDT 24
Peak memory 208912 kb
Host smart-6fb65794-0639-471f-a662-dadc9220a086
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228916698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2228916698
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.872167947
Short name T765
Test name
Test status
Simulation time 861468113 ps
CPU time 18.7 seconds
Started Jun 13 01:12:47 PM PDT 24
Finished Jun 13 01:13:07 PM PDT 24
Peak memory 208444 kb
Host smart-344483d1-ab03-4883-92d9-3cfab81e774c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872167947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.872167947
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2590820473
Short name T220
Test name
Test status
Simulation time 112891964 ps
CPU time 4.76 seconds
Started Jun 13 01:54:36 PM PDT 24
Finished Jun 13 01:54:47 PM PDT 24
Peak memory 208404 kb
Host smart-89e8d4c3-5d3f-4c09-bed5-a8148f0537a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590820473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2590820473
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.924525345
Short name T770
Test name
Test status
Simulation time 127131459 ps
CPU time 2.45 seconds
Started Jun 13 01:48:22 PM PDT 24
Finished Jun 13 01:48:25 PM PDT 24
Peak memory 214300 kb
Host smart-42035cb1-cb7f-438d-9bed-dcac7c090bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924525345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.924525345
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3762461799
Short name T580
Test name
Test status
Simulation time 24543308 ps
CPU time 1.82 seconds
Started Jun 13 01:39:21 PM PDT 24
Finished Jun 13 01:39:24 PM PDT 24
Peak memory 206852 kb
Host smart-3fc4bfe1-c1e7-4512-ae1e-e7a62c3a6fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762461799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3762461799
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1588030467
Short name T779
Test name
Test status
Simulation time 133932314 ps
CPU time 2.7 seconds
Started Jun 13 01:19:59 PM PDT 24
Finished Jun 13 01:20:03 PM PDT 24
Peak memory 207480 kb
Host smart-416168fb-8dfc-4297-a4df-20edfe5a8b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588030467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1588030467
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4087847660
Short name T576
Test name
Test status
Simulation time 174490618 ps
CPU time 2.35 seconds
Started Jun 13 01:57:02 PM PDT 24
Finished Jun 13 01:57:06 PM PDT 24
Peak memory 214384 kb
Host smart-e22ed1b0-7a99-4af6-be5f-f62368bf5114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087847660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4087847660
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2819397922
Short name T793
Test name
Test status
Simulation time 33997101 ps
CPU time 0.92 seconds
Started Jun 13 01:26:04 PM PDT 24
Finished Jun 13 01:26:07 PM PDT 24
Peak memory 206068 kb
Host smart-8ba4dae2-cef7-4019-a7c6-e843ae088848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819397922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2819397922
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2411036845
Short name T846
Test name
Test status
Simulation time 903987244 ps
CPU time 5.43 seconds
Started Jun 13 01:32:57 PM PDT 24
Finished Jun 13 01:33:03 PM PDT 24
Peak memory 214236 kb
Host smart-f5516215-7c39-4542-a0a4-79417d9d4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411036845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2411036845
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3042049204
Short name T54
Test name
Test status
Simulation time 78279387 ps
CPU time 1.74 seconds
Started Jun 13 01:44:08 PM PDT 24
Finished Jun 13 01:44:11 PM PDT 24
Peak memory 214284 kb
Host smart-217ac616-c6ff-461c-a09f-245aa14e1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042049204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3042049204
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2309836344
Short name T100
Test name
Test status
Simulation time 210276861 ps
CPU time 3.08 seconds
Started Jun 13 01:46:12 PM PDT 24
Finished Jun 13 01:46:17 PM PDT 24
Peak memory 208336 kb
Host smart-68e5b54f-ef25-4940-ba09-440930009ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309836344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2309836344
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3060822825
Short name T299
Test name
Test status
Simulation time 122822590 ps
CPU time 4.05 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:01 PM PDT 24
Peak memory 222412 kb
Host smart-0e880610-4fce-4ddf-a608-423caddcf9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060822825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3060822825
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3705546867
Short name T52
Test name
Test status
Simulation time 258451238 ps
CPU time 3.25 seconds
Started Jun 13 01:08:45 PM PDT 24
Finished Jun 13 01:08:52 PM PDT 24
Peak memory 209280 kb
Host smart-802033c1-8287-45d2-9b9f-b04ce666f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705546867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3705546867
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1508455560
Short name T557
Test name
Test status
Simulation time 172928192 ps
CPU time 5.65 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:51 PM PDT 24
Peak memory 207400 kb
Host smart-80d383c0-0d05-4759-a350-46a9005ccc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508455560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1508455560
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.667772885
Short name T344
Test name
Test status
Simulation time 679796404 ps
CPU time 21.01 seconds
Started Jun 13 01:08:46 PM PDT 24
Finished Jun 13 01:09:11 PM PDT 24
Peak memory 208280 kb
Host smart-3c75c5f1-1cbe-4294-aec6-2c87f4431e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667772885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.667772885
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.368507149
Short name T632
Test name
Test status
Simulation time 1675332497 ps
CPU time 53.1 seconds
Started Jun 13 02:00:44 PM PDT 24
Finished Jun 13 02:01:38 PM PDT 24
Peak memory 208016 kb
Host smart-6f6e3757-01bd-4177-8fa2-8e0f552af641
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368507149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.368507149
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.857567464
Short name T232
Test name
Test status
Simulation time 102141158 ps
CPU time 2.8 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:50 PM PDT 24
Peak memory 208548 kb
Host smart-38074053-e725-4ce3-aed0-5330f377e8f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857567464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.857567464
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.101233025
Short name T799
Test name
Test status
Simulation time 86230173 ps
CPU time 4.1 seconds
Started Jun 13 01:11:18 PM PDT 24
Finished Jun 13 01:11:23 PM PDT 24
Peak memory 208840 kb
Host smart-2c7643b5-cc15-40a3-a17a-a76492d6a1cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101233025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.101233025
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3211338948
Short name T328
Test name
Test status
Simulation time 225426751 ps
CPU time 3.1 seconds
Started Jun 13 01:19:45 PM PDT 24
Finished Jun 13 01:19:48 PM PDT 24
Peak memory 214300 kb
Host smart-18ddca99-ba56-45de-bee9-e40649874579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211338948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3211338948
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1134516206
Short name T460
Test name
Test status
Simulation time 475793179 ps
CPU time 2.97 seconds
Started Jun 13 01:27:36 PM PDT 24
Finished Jun 13 01:27:41 PM PDT 24
Peak memory 208332 kb
Host smart-80f97ceb-5d72-44c8-8c74-6fca0e2eb092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134516206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1134516206
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.651318312
Short name T776
Test name
Test status
Simulation time 144158240 ps
CPU time 2.69 seconds
Started Jun 13 01:20:35 PM PDT 24
Finished Jun 13 01:20:39 PM PDT 24
Peak memory 207252 kb
Host smart-7a921a27-3949-491e-99c7-5b5b984db028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651318312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.651318312
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2937858460
Short name T384
Test name
Test status
Simulation time 1169807336 ps
CPU time 6.26 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:09:01 PM PDT 24
Peak memory 218860 kb
Host smart-02ef9f4e-2b87-4c06-9e44-7d119e73d11b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937858460 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2937858460
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1219918753
Short name T905
Test name
Test status
Simulation time 1493051824 ps
CPU time 9.12 seconds
Started Jun 13 01:08:44 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 222416 kb
Host smart-d0ef8a9b-0a00-463e-84ee-f4eb9061ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219918753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1219918753
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1981667099
Short name T481
Test name
Test status
Simulation time 1340679235 ps
CPU time 21.09 seconds
Started Jun 13 01:15:32 PM PDT 24
Finished Jun 13 01:15:54 PM PDT 24
Peak memory 210904 kb
Host smart-a62cb2b4-1c63-400a-b5ee-e2401d486be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981667099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1981667099
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1832410706
Short name T209
Test name
Test status
Simulation time 43890516 ps
CPU time 0.76 seconds
Started Jun 13 02:12:02 PM PDT 24
Finished Jun 13 02:12:04 PM PDT 24
Peak memory 205932 kb
Host smart-dcf74546-b522-41ca-a302-3c89f611a1b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832410706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1832410706
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.627034996
Short name T739
Test name
Test status
Simulation time 202161292 ps
CPU time 3.2 seconds
Started Jun 13 01:44:48 PM PDT 24
Finished Jun 13 01:44:51 PM PDT 24
Peak memory 219956 kb
Host smart-20249d4e-28de-4821-be9f-a382f3643b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627034996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.627034996
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2745034872
Short name T727
Test name
Test status
Simulation time 23445098 ps
CPU time 1.77 seconds
Started Jun 13 02:18:14 PM PDT 24
Finished Jun 13 02:18:23 PM PDT 24
Peak memory 209656 kb
Host smart-63bb0d7a-9d20-4a41-a95e-b0c74cb81eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745034872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2745034872
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.705350364
Short name T711
Test name
Test status
Simulation time 870419105 ps
CPU time 6.07 seconds
Started Jun 13 02:07:11 PM PDT 24
Finished Jun 13 02:07:18 PM PDT 24
Peak memory 214404 kb
Host smart-cdd347a6-6666-4df0-bbd7-ea1c55aaded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705350364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.705350364
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.163859018
Short name T717
Test name
Test status
Simulation time 71357550 ps
CPU time 2.56 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 214244 kb
Host smart-91fd4c07-15c2-478c-8c4b-c17c43d63c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163859018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.163859018
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3142555509
Short name T817
Test name
Test status
Simulation time 68851216 ps
CPU time 3.05 seconds
Started Jun 13 01:55:39 PM PDT 24
Finished Jun 13 01:55:43 PM PDT 24
Peak memory 214308 kb
Host smart-83f87d21-4722-4dfa-a52b-5ab91d7e9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142555509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3142555509
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3581344584
Short name T288
Test name
Test status
Simulation time 405183572 ps
CPU time 4.95 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:20:18 PM PDT 24
Peak memory 218288 kb
Host smart-05b6901f-539a-4ee3-ad23-d1323b944543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581344584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3581344584
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.743789668
Short name T867
Test name
Test status
Simulation time 5880224607 ps
CPU time 58.77 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:09:53 PM PDT 24
Peak memory 208020 kb
Host smart-a1f79792-df4d-4cac-a78d-c7bc45972887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743789668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.743789668
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3967770791
Short name T230
Test name
Test status
Simulation time 566281327 ps
CPU time 15.66 seconds
Started Jun 13 01:19:43 PM PDT 24
Finished Jun 13 01:19:59 PM PDT 24
Peak memory 209060 kb
Host smart-5213714a-20c0-4335-b401-c60ad269282c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967770791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3967770791
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1712972755
Short name T743
Test name
Test status
Simulation time 50683052 ps
CPU time 2.72 seconds
Started Jun 13 01:36:41 PM PDT 24
Finished Jun 13 01:36:45 PM PDT 24
Peak memory 208096 kb
Host smart-ee40786b-7da7-473b-8a9d-cfb4dd2744af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712972755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1712972755
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2973782438
Short name T347
Test name
Test status
Simulation time 217476973 ps
CPU time 2.97 seconds
Started Jun 13 01:12:53 PM PDT 24
Finished Jun 13 01:12:56 PM PDT 24
Peak memory 206940 kb
Host smart-6c0616fc-7961-4655-9881-d8c57e9a02b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973782438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2973782438
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.90796642
Short name T693
Test name
Test status
Simulation time 972420622 ps
CPU time 10.55 seconds
Started Jun 13 02:26:06 PM PDT 24
Finished Jun 13 02:26:18 PM PDT 24
Peak memory 218272 kb
Host smart-a68812d2-a5ea-4c54-a085-76fd0db7bb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90796642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.90796642
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1244426243
Short name T707
Test name
Test status
Simulation time 66739892 ps
CPU time 2.48 seconds
Started Jun 13 01:09:18 PM PDT 24
Finished Jun 13 01:09:22 PM PDT 24
Peak memory 206920 kb
Host smart-43613a3b-f8c4-482b-9eb3-854b24d590c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244426243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1244426243
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3373474286
Short name T618
Test name
Test status
Simulation time 4545878790 ps
CPU time 22.96 seconds
Started Jun 13 01:55:49 PM PDT 24
Finished Jun 13 01:56:13 PM PDT 24
Peak memory 218408 kb
Host smart-08840f3a-85e4-4fb4-9efe-1a17087ee768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373474286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3373474286
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3446799353
Short name T74
Test name
Test status
Simulation time 38014175 ps
CPU time 2.32 seconds
Started Jun 13 01:40:39 PM PDT 24
Finished Jun 13 01:40:42 PM PDT 24
Peak memory 210120 kb
Host smart-9a22a38c-a62d-4c9d-b739-1dd66e7009de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446799353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3446799353
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1279336426
Short name T560
Test name
Test status
Simulation time 16779957 ps
CPU time 0.94 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 206096 kb
Host smart-c653f127-0c98-4e77-b929-573bf748c434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279336426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1279336426
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3876240880
Short name T365
Test name
Test status
Simulation time 29366816 ps
CPU time 2.53 seconds
Started Jun 13 01:59:19 PM PDT 24
Finished Jun 13 01:59:24 PM PDT 24
Peak memory 214408 kb
Host smart-9e49eb63-4909-4df4-a377-31138366bbc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876240880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3876240880
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.997798763
Short name T240
Test name
Test status
Simulation time 171627524 ps
CPU time 2.88 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 207596 kb
Host smart-59b075da-cddf-4a47-a95b-5f31810c096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997798763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.997798763
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3149133714
Short name T637
Test name
Test status
Simulation time 103276133 ps
CPU time 2.64 seconds
Started Jun 13 01:14:33 PM PDT 24
Finished Jun 13 01:14:37 PM PDT 24
Peak memory 207156 kb
Host smart-d7a0a4b5-97e4-4008-92cd-8284da671726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149133714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3149133714
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3529881992
Short name T26
Test name
Test status
Simulation time 105941566 ps
CPU time 2.35 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 208528 kb
Host smart-7e7ac42e-e882-481a-a4d6-2cbda6977bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529881992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3529881992
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.732725947
Short name T881
Test name
Test status
Simulation time 37695591 ps
CPU time 2.79 seconds
Started Jun 13 01:45:36 PM PDT 24
Finished Jun 13 01:45:40 PM PDT 24
Peak memory 221424 kb
Host smart-d84ec2aa-bbfc-459d-9932-79b0997328e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732725947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.732725947
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.209513653
Short name T491
Test name
Test status
Simulation time 430584099 ps
CPU time 3.36 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:00 PM PDT 24
Peak memory 220160 kb
Host smart-d3504610-523a-4ab2-9fcd-6bdd61955368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209513653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.209513653
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3645600548
Short name T451
Test name
Test status
Simulation time 137961772 ps
CPU time 6.06 seconds
Started Jun 13 01:25:57 PM PDT 24
Finished Jun 13 01:26:05 PM PDT 24
Peak memory 208800 kb
Host smart-a06d9db2-93f6-4413-a80b-8a3cc5dfa076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645600548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3645600548
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1876278536
Short name T911
Test name
Test status
Simulation time 597458869 ps
CPU time 5.11 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 207580 kb
Host smart-c06d3adf-f43b-416c-b5cd-acd894d7e56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876278536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1876278536
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1297087259
Short name T831
Test name
Test status
Simulation time 60314481 ps
CPU time 2.98 seconds
Started Jun 13 01:15:03 PM PDT 24
Finished Jun 13 01:15:06 PM PDT 24
Peak memory 206940 kb
Host smart-cdb74155-cbb6-4aa7-828e-d4b467009085
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297087259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1297087259
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1293877843
Short name T505
Test name
Test status
Simulation time 127302589 ps
CPU time 3.02 seconds
Started Jun 13 02:45:00 PM PDT 24
Finished Jun 13 02:45:18 PM PDT 24
Peak memory 208808 kb
Host smart-c5c4c121-dc3d-4c81-9331-673b1cc3b28c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293877843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1293877843
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1172044760
Short name T458
Test name
Test status
Simulation time 856233406 ps
CPU time 14.3 seconds
Started Jun 13 01:58:20 PM PDT 24
Finished Jun 13 01:58:36 PM PDT 24
Peak memory 208188 kb
Host smart-658721d7-6936-4d77-9c14-b374100e11a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172044760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1172044760
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2208291852
Short name T302
Test name
Test status
Simulation time 56564812 ps
CPU time 2.38 seconds
Started Jun 13 01:11:21 PM PDT 24
Finished Jun 13 01:11:24 PM PDT 24
Peak memory 222448 kb
Host smart-c31af035-db81-4bef-adeb-37996dc0ea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208291852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2208291852
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.978863150
Short name T621
Test name
Test status
Simulation time 496445615 ps
CPU time 3.9 seconds
Started Jun 13 01:35:32 PM PDT 24
Finished Jun 13 01:35:36 PM PDT 24
Peak memory 208412 kb
Host smart-a782787a-3e1a-4201-8309-c287eb35d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978863150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.978863150
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2778436
Short name T77
Test name
Test status
Simulation time 3059560409 ps
CPU time 10.1 seconds
Started Jun 13 01:43:51 PM PDT 24
Finished Jun 13 01:44:02 PM PDT 24
Peak memory 216056 kb
Host smart-c86f4a7c-79b2-480b-afa8-b9150bf34aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2778436
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3874685105
Short name T623
Test name
Test status
Simulation time 287612519 ps
CPU time 5.99 seconds
Started Jun 13 01:23:08 PM PDT 24
Finished Jun 13 01:23:15 PM PDT 24
Peak memory 222600 kb
Host smart-11a04cdf-6aab-493e-920d-273891d530f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874685105 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3874685105
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4113642748
Short name T329
Test name
Test status
Simulation time 569254726 ps
CPU time 5.31 seconds
Started Jun 13 01:09:04 PM PDT 24
Finished Jun 13 01:09:11 PM PDT 24
Peak memory 207668 kb
Host smart-36fc58c3-b130-4bec-8bfb-283adcd1e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113642748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4113642748
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3188123696
Short name T69
Test name
Test status
Simulation time 240227084 ps
CPU time 3.42 seconds
Started Jun 13 01:57:07 PM PDT 24
Finished Jun 13 01:57:12 PM PDT 24
Peak memory 210996 kb
Host smart-0992c030-df72-40cd-8600-e9c486899442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188123696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3188123696
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2248491733
Short name T433
Test name
Test status
Simulation time 49606691 ps
CPU time 0.88 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:07:13 PM PDT 24
Peak memory 205900 kb
Host smart-ab4b03ab-1935-4b87-83c4-b85da3a15b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248491733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2248491733
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3829551591
Short name T419
Test name
Test status
Simulation time 14331923134 ps
CPU time 96.41 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:08:48 PM PDT 24
Peak memory 215612 kb
Host smart-b682e9fc-c304-4718-911a-8ce22b35b3b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829551591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3829551591
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4156155099
Short name T660
Test name
Test status
Simulation time 122167387 ps
CPU time 3.05 seconds
Started Jun 13 01:07:12 PM PDT 24
Finished Jun 13 01:07:16 PM PDT 24
Peak memory 221348 kb
Host smart-6f395a8e-a173-4b5e-9209-bb2840cc179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156155099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4156155099
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.29891237
Short name T683
Test name
Test status
Simulation time 111182301 ps
CPU time 1.84 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:16 PM PDT 24
Peak memory 207384 kb
Host smart-38626638-afb3-4b8d-bd8a-a62c8f61f36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29891237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.29891237
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1030374428
Short name T25
Test name
Test status
Simulation time 99172648 ps
CPU time 4.66 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:07:16 PM PDT 24
Peak memory 214296 kb
Host smart-1bac557d-5b49-49c9-ad05-5fd93626f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030374428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1030374428
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2712798503
Short name T766
Test name
Test status
Simulation time 38309038 ps
CPU time 1.68 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:15 PM PDT 24
Peak memory 214228 kb
Host smart-1bf4e3fd-f5b2-4ee7-a542-7b484e30769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712798503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2712798503
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2920048219
Short name T199
Test name
Test status
Simulation time 66381694 ps
CPU time 2.35 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:16 PM PDT 24
Peak memory 215484 kb
Host smart-ffd5fa52-4b68-4395-94c3-49a10e6a6aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920048219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2920048219
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3095381890
Short name T274
Test name
Test status
Simulation time 124294332 ps
CPU time 5.23 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:07:17 PM PDT 24
Peak memory 210168 kb
Host smart-cfbb6d63-bd8b-40d5-a6e3-d2a10293ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095381890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3095381890
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3024178942
Short name T115
Test name
Test status
Simulation time 859471605 ps
CPU time 11.35 seconds
Started Jun 13 01:07:12 PM PDT 24
Finished Jun 13 01:07:24 PM PDT 24
Peak memory 229980 kb
Host smart-bd8e2ce4-0c5d-4a40-a9a9-5c8bc277bca7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024178942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3024178942
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1738394568
Short name T531
Test name
Test status
Simulation time 46610104 ps
CPU time 2.47 seconds
Started Jun 13 01:07:03 PM PDT 24
Finished Jun 13 01:07:07 PM PDT 24
Peak memory 208292 kb
Host smart-82cf0fd8-78a7-4306-bd39-a1661a802f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738394568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1738394568
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.346666396
Short name T645
Test name
Test status
Simulation time 55550435 ps
CPU time 2.39 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:09 PM PDT 24
Peak memory 209176 kb
Host smart-bbeb60df-6f24-4617-8447-392450b3ae9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346666396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.346666396
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1817680909
Short name T92
Test name
Test status
Simulation time 138388535 ps
CPU time 3.4 seconds
Started Jun 13 01:07:04 PM PDT 24
Finished Jun 13 01:07:09 PM PDT 24
Peak memory 208932 kb
Host smart-b188ced3-744f-4e1b-8e80-944fd43c1997
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817680909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1817680909
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2358217488
Short name T436
Test name
Test status
Simulation time 786886747 ps
CPU time 4.61 seconds
Started Jun 13 01:07:05 PM PDT 24
Finished Jun 13 01:07:12 PM PDT 24
Peak memory 207920 kb
Host smart-ef063928-5334-4ae8-af0f-fc1538ec2a46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358217488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2358217488
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.802757162
Short name T217
Test name
Test status
Simulation time 442259754 ps
CPU time 3.02 seconds
Started Jun 13 01:07:15 PM PDT 24
Finished Jun 13 01:07:18 PM PDT 24
Peak memory 209128 kb
Host smart-ed0d45fa-79d6-4acd-9272-2f376def95c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802757162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.802757162
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1692467273
Short name T694
Test name
Test status
Simulation time 67202616 ps
CPU time 2.79 seconds
Started Jun 13 01:07:02 PM PDT 24
Finished Jun 13 01:07:06 PM PDT 24
Peak memory 208080 kb
Host smart-f41d5d52-c29f-4452-8af8-f12100846544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692467273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1692467273
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.903714140
Short name T255
Test name
Test status
Simulation time 782451664 ps
CPU time 11.23 seconds
Started Jun 13 01:07:18 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 222408 kb
Host smart-9527a8ca-418b-4d92-af78-976867f898be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903714140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.903714140
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.944361397
Short name T725
Test name
Test status
Simulation time 575753596 ps
CPU time 11.15 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:07:23 PM PDT 24
Peak memory 222560 kb
Host smart-fecc1540-0e37-4eda-9173-380731a919d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944361397 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.944361397
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.68227656
Short name T527
Test name
Test status
Simulation time 224819034 ps
CPU time 6.29 seconds
Started Jun 13 01:07:15 PM PDT 24
Finished Jun 13 01:07:21 PM PDT 24
Peak memory 207468 kb
Host smart-8684d1d1-f1e0-41e5-b6f4-25c34168be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68227656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.68227656
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2141514196
Short name T750
Test name
Test status
Simulation time 2635857099 ps
CPU time 4.6 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:07:17 PM PDT 24
Peak memory 210632 kb
Host smart-69e9e262-b08c-464b-8b06-67a31104e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141514196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2141514196
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1068970516
Short name T803
Test name
Test status
Simulation time 17540052 ps
CPU time 0.75 seconds
Started Jun 13 01:55:39 PM PDT 24
Finished Jun 13 01:55:41 PM PDT 24
Peak memory 205940 kb
Host smart-ff89a63d-6813-4881-83ae-1cf890d54212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068970516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1068970516
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1829066101
Short name T280
Test name
Test status
Simulation time 575933552 ps
CPU time 6.69 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 214312 kb
Host smart-88670665-beb5-4585-b90a-e08c0a48e1dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829066101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1829066101
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2498857440
Short name T45
Test name
Test status
Simulation time 64675749 ps
CPU time 2.5 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:08:55 PM PDT 24
Peak memory 208608 kb
Host smart-fca3fa33-bda6-459d-8158-6ea863a4ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498857440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2498857440
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4067630908
Short name T606
Test name
Test status
Simulation time 76678555 ps
CPU time 3.04 seconds
Started Jun 13 01:14:25 PM PDT 24
Finished Jun 13 01:14:29 PM PDT 24
Peak memory 209256 kb
Host smart-8cb238b6-faac-4250-b7fc-c173bd28b040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067630908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4067630908
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2438189530
Short name T107
Test name
Test status
Simulation time 1057463937 ps
CPU time 7.99 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 222528 kb
Host smart-5b5af360-d830-4136-a7e1-7922acf45ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438189530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2438189530
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.147908739
Short name T380
Test name
Test status
Simulation time 584005181 ps
CPU time 4.32 seconds
Started Jun 13 02:11:20 PM PDT 24
Finished Jun 13 02:11:26 PM PDT 24
Peak memory 222360 kb
Host smart-5b922d97-b946-4273-a753-ed1f13b8341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147908739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.147908739
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.483682185
Short name T397
Test name
Test status
Simulation time 117498123 ps
CPU time 3.47 seconds
Started Jun 13 02:22:56 PM PDT 24
Finished Jun 13 02:23:01 PM PDT 24
Peak memory 214292 kb
Host smart-9b85e52c-16b7-4f77-80bc-be7c99fbac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483682185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.483682185
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1143599151
Short name T336
Test name
Test status
Simulation time 541498235 ps
CPU time 5.46 seconds
Started Jun 13 01:17:45 PM PDT 24
Finished Jun 13 01:17:50 PM PDT 24
Peak memory 214292 kb
Host smart-ea0dc169-28db-4c72-8b35-94ad5b0cd63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143599151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1143599151
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2060459904
Short name T367
Test name
Test status
Simulation time 395646118 ps
CPU time 3.44 seconds
Started Jun 13 01:57:17 PM PDT 24
Finished Jun 13 01:57:23 PM PDT 24
Peak memory 206868 kb
Host smart-c21696e0-45bc-40a0-9fe1-944df33506f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060459904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2060459904
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2767780217
Short name T687
Test name
Test status
Simulation time 159593547 ps
CPU time 2.54 seconds
Started Jun 13 01:20:20 PM PDT 24
Finished Jun 13 01:20:23 PM PDT 24
Peak memory 206984 kb
Host smart-6cfcd063-4c70-4aba-aa36-de0ab81fa797
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767780217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2767780217
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4292631777
Short name T555
Test name
Test status
Simulation time 99790927 ps
CPU time 2.83 seconds
Started Jun 13 02:42:56 PM PDT 24
Finished Jun 13 02:43:00 PM PDT 24
Peak memory 206892 kb
Host smart-76370f0c-08f4-4aae-b0a8-cb3e46444dd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292631777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4292631777
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1051507397
Short name T811
Test name
Test status
Simulation time 347081821 ps
CPU time 7.22 seconds
Started Jun 13 01:38:17 PM PDT 24
Finished Jun 13 01:38:25 PM PDT 24
Peak memory 208064 kb
Host smart-624c347a-9dab-49d5-9ab6-581e41a54212
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051507397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1051507397
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.916126543
Short name T886
Test name
Test status
Simulation time 594585864 ps
CPU time 2.43 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:31:37 PM PDT 24
Peak memory 208184 kb
Host smart-92d97b32-fd4a-43df-a6d9-d7d11f709713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916126543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.916126543
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4213983667
Short name T516
Test name
Test status
Simulation time 5735221822 ps
CPU time 16.69 seconds
Started Jun 13 02:57:03 PM PDT 24
Finished Jun 13 02:57:20 PM PDT 24
Peak memory 208032 kb
Host smart-b5fb0469-cda8-4c92-80bb-8da3a6f92aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213983667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4213983667
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2616186666
Short name T90
Test name
Test status
Simulation time 229826677 ps
CPU time 11.64 seconds
Started Jun 13 01:55:51 PM PDT 24
Finished Jun 13 01:56:03 PM PDT 24
Peak memory 222392 kb
Host smart-10114cde-32c2-469e-b590-445bb5efa0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616186666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2616186666
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4255742482
Short name T532
Test name
Test status
Simulation time 2756885211 ps
CPU time 28.72 seconds
Started Jun 13 01:27:07 PM PDT 24
Finished Jun 13 01:27:37 PM PDT 24
Peak memory 209396 kb
Host smart-155b8cf7-715e-40d0-a6cf-b4857fca6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255742482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4255742482
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2848039123
Short name T504
Test name
Test status
Simulation time 113715178 ps
CPU time 2.03 seconds
Started Jun 13 01:31:10 PM PDT 24
Finished Jun 13 01:31:12 PM PDT 24
Peak memory 210136 kb
Host smart-263db337-fd7d-4a9b-aa6e-2f45b9f80a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848039123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2848039123
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4254772476
Short name T533
Test name
Test status
Simulation time 55969645 ps
CPU time 0.8 seconds
Started Jun 13 02:33:38 PM PDT 24
Finished Jun 13 02:33:41 PM PDT 24
Peak memory 205920 kb
Host smart-82444367-2371-4a5c-8bc4-1f9731b85a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254772476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4254772476
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1106960583
Short name T417
Test name
Test status
Simulation time 297590227 ps
CPU time 14.99 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:09:09 PM PDT 24
Peak memory 214284 kb
Host smart-32033923-b7ac-4164-a8d1-9f729444ca90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106960583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1106960583
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2155749154
Short name T9
Test name
Test status
Simulation time 368042454 ps
CPU time 4.3 seconds
Started Jun 13 01:58:31 PM PDT 24
Finished Jun 13 01:58:36 PM PDT 24
Peak memory 214732 kb
Host smart-e3eded15-de48-409f-ac51-96072d16c2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155749154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2155749154
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4188484857
Short name T457
Test name
Test status
Simulation time 403183603 ps
CPU time 2.34 seconds
Started Jun 13 01:55:12 PM PDT 24
Finished Jun 13 01:55:15 PM PDT 24
Peak memory 207892 kb
Host smart-34ebfa70-200f-4946-9443-ad1f7f432fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188484857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4188484857
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3779276046
Short name T352
Test name
Test status
Simulation time 102675933 ps
CPU time 2.02 seconds
Started Jun 13 01:40:32 PM PDT 24
Finished Jun 13 01:40:35 PM PDT 24
Peak memory 214456 kb
Host smart-1c40cb83-8623-48ea-90d0-b106575af420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779276046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3779276046
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3327076934
Short name T787
Test name
Test status
Simulation time 50544398 ps
CPU time 2.31 seconds
Started Jun 13 02:01:25 PM PDT 24
Finished Jun 13 02:01:28 PM PDT 24
Peak memory 217252 kb
Host smart-c23aacd4-3926-4076-954d-561198228d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327076934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3327076934
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3659335304
Short name T731
Test name
Test status
Simulation time 81740253 ps
CPU time 3.57 seconds
Started Jun 13 01:42:06 PM PDT 24
Finished Jun 13 01:42:11 PM PDT 24
Peak memory 209104 kb
Host smart-371408be-e8c0-4bf3-b364-99e450e3e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659335304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3659335304
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.595224131
Short name T213
Test name
Test status
Simulation time 138511118 ps
CPU time 3.95 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:01 PM PDT 24
Peak memory 208336 kb
Host smart-5ff77dc0-bcc2-4e5f-acf5-b6cf1ee2d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595224131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.595224131
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.633898090
Short name T573
Test name
Test status
Simulation time 127099718 ps
CPU time 1.83 seconds
Started Jun 13 01:51:06 PM PDT 24
Finished Jun 13 01:51:09 PM PDT 24
Peak memory 206988 kb
Host smart-73c4d1ad-e0aa-4c6c-9824-2dd565f24393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633898090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.633898090
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.677040943
Short name T842
Test name
Test status
Simulation time 634084002 ps
CPU time 3.31 seconds
Started Jun 13 01:08:55 PM PDT 24
Finished Jun 13 01:08:59 PM PDT 24
Peak memory 208484 kb
Host smart-87ee17a9-5588-4561-a63e-6b702fdd94b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677040943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.677040943
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1881360875
Short name T588
Test name
Test status
Simulation time 73318530 ps
CPU time 3.03 seconds
Started Jun 13 01:23:07 PM PDT 24
Finished Jun 13 01:23:11 PM PDT 24
Peak memory 206916 kb
Host smart-4f1b8abd-3422-40af-a8af-f19de5d016a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881360875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1881360875
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3515736253
Short name T815
Test name
Test status
Simulation time 6060276067 ps
CPU time 55.24 seconds
Started Jun 13 01:26:46 PM PDT 24
Finished Jun 13 01:27:43 PM PDT 24
Peak memory 208676 kb
Host smart-bd6d0f7f-ae2e-4a00-b520-b60176c7beb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515736253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3515736253
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.782384804
Short name T498
Test name
Test status
Simulation time 27292677 ps
CPU time 2.03 seconds
Started Jun 13 01:49:34 PM PDT 24
Finished Jun 13 01:49:37 PM PDT 24
Peak memory 216128 kb
Host smart-6408a401-b2ba-4636-94f7-1f7ca1bb49f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782384804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.782384804
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2806440662
Short name T216
Test name
Test status
Simulation time 88704438 ps
CPU time 3.35 seconds
Started Jun 13 02:04:45 PM PDT 24
Finished Jun 13 02:04:49 PM PDT 24
Peak memory 207036 kb
Host smart-d0fb41cb-fbac-4a24-abf1-e6191983bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806440662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2806440662
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3638964765
Short name T838
Test name
Test status
Simulation time 4744096326 ps
CPU time 49.69 seconds
Started Jun 13 01:56:17 PM PDT 24
Finished Jun 13 01:57:08 PM PDT 24
Peak memory 222624 kb
Host smart-d1430196-5679-4da0-baa2-60824b9bb161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638964765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3638964765
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.869467398
Short name T193
Test name
Test status
Simulation time 2331491412 ps
CPU time 21.78 seconds
Started Jun 13 02:26:36 PM PDT 24
Finished Jun 13 02:26:59 PM PDT 24
Peak memory 222692 kb
Host smart-656410bc-a79b-4d26-a72d-229789c68a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869467398 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.869467398
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2342458684
Short name T228
Test name
Test status
Simulation time 43436953 ps
CPU time 3.21 seconds
Started Jun 13 01:35:00 PM PDT 24
Finished Jun 13 01:35:04 PM PDT 24
Peak memory 208896 kb
Host smart-ad5b6c86-9485-4efc-8eb6-04dbbfe62fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342458684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2342458684
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2468890345
Short name T386
Test name
Test status
Simulation time 212008414 ps
CPU time 2.48 seconds
Started Jun 13 01:32:05 PM PDT 24
Finished Jun 13 01:32:08 PM PDT 24
Peak memory 210532 kb
Host smart-0b99f775-6af7-49a5-a98c-2ec512066a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468890345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2468890345
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3884248587
Short name T864
Test name
Test status
Simulation time 29638661 ps
CPU time 0.91 seconds
Started Jun 13 02:09:26 PM PDT 24
Finished Jun 13 02:09:28 PM PDT 24
Peak memory 206092 kb
Host smart-ba93dced-fff6-40f7-a665-a4a049cab3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884248587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3884248587
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1476102306
Short name T36
Test name
Test status
Simulation time 378654722 ps
CPU time 2.43 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 217148 kb
Host smart-2fd4d098-d5db-4e43-bb1f-c9af914d62ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476102306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1476102306
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3930256527
Short name T434
Test name
Test status
Simulation time 92124927 ps
CPU time 1.55 seconds
Started Jun 13 01:36:21 PM PDT 24
Finished Jun 13 01:36:23 PM PDT 24
Peak memory 207432 kb
Host smart-2391ccf7-9ad2-4d76-b6c7-90e0d3cf1dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930256527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3930256527
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2881618099
Short name T510
Test name
Test status
Simulation time 117412763 ps
CPU time 1.98 seconds
Started Jun 13 02:37:38 PM PDT 24
Finished Jun 13 02:37:42 PM PDT 24
Peak memory 214288 kb
Host smart-8136a1aa-f21d-4332-9f84-271715d03cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881618099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2881618099
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1683685827
Short name T712
Test name
Test status
Simulation time 235236808 ps
CPU time 2.72 seconds
Started Jun 13 02:05:23 PM PDT 24
Finished Jun 13 02:05:27 PM PDT 24
Peak memory 214212 kb
Host smart-8028581a-6915-4186-a052-b96c84340f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683685827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1683685827
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.600369078
Short name T68
Test name
Test status
Simulation time 250614628 ps
CPU time 4.33 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 209944 kb
Host smart-89586e33-cf9f-4e6f-8805-60323bc7aa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600369078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.600369078
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3851593425
Short name T721
Test name
Test status
Simulation time 114110205 ps
CPU time 3.14 seconds
Started Jun 13 01:12:50 PM PDT 24
Finished Jun 13 01:12:54 PM PDT 24
Peak memory 208416 kb
Host smart-e8845ca0-944f-408d-8dd2-eb0539764e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851593425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3851593425
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.128004178
Short name T812
Test name
Test status
Simulation time 162314067 ps
CPU time 4.17 seconds
Started Jun 13 01:54:03 PM PDT 24
Finished Jun 13 01:54:09 PM PDT 24
Peak memory 206820 kb
Host smart-1611f94f-ba27-4e76-bdc4-650da2c60850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128004178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.128004178
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1203110106
Short name T679
Test name
Test status
Simulation time 27647063 ps
CPU time 1.91 seconds
Started Jun 13 02:00:36 PM PDT 24
Finished Jun 13 02:00:39 PM PDT 24
Peak memory 207504 kb
Host smart-4fb8fd81-799d-4700-85dc-c2097918c5f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203110106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1203110106
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2948021829
Short name T616
Test name
Test status
Simulation time 85547681 ps
CPU time 3.7 seconds
Started Jun 13 01:55:38 PM PDT 24
Finished Jun 13 01:55:43 PM PDT 24
Peak memory 208624 kb
Host smart-352ab0ff-e9f5-40d6-8363-ee82a4a33d0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948021829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2948021829
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3338745123
Short name T447
Test name
Test status
Simulation time 749977044 ps
CPU time 5.66 seconds
Started Jun 13 01:57:57 PM PDT 24
Finished Jun 13 01:58:06 PM PDT 24
Peak memory 208636 kb
Host smart-02b59e43-38bf-4214-9b6b-ac6aa050b596
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338745123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3338745123
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4061923310
Short name T698
Test name
Test status
Simulation time 205042792 ps
CPU time 2.98 seconds
Started Jun 13 02:01:53 PM PDT 24
Finished Jun 13 02:01:57 PM PDT 24
Peak memory 210216 kb
Host smart-b9102eed-d2ac-446a-bcb0-44bb36d11b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061923310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4061923310
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3551314989
Short name T593
Test name
Test status
Simulation time 37087965 ps
CPU time 1.7 seconds
Started Jun 13 02:14:21 PM PDT 24
Finished Jun 13 02:14:23 PM PDT 24
Peak memory 206784 kb
Host smart-bae28396-63c0-4063-9755-851584a9571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551314989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3551314989
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1254925804
Short name T373
Test name
Test status
Simulation time 543758601 ps
CPU time 14.17 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:09:08 PM PDT 24
Peak memory 215704 kb
Host smart-f14eb323-a21e-4bae-bdbd-05b014ae68bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254925804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1254925804
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2551075631
Short name T138
Test name
Test status
Simulation time 706695231 ps
CPU time 13.8 seconds
Started Jun 13 01:15:19 PM PDT 24
Finished Jun 13 01:15:33 PM PDT 24
Peak memory 219712 kb
Host smart-3a2455db-4f99-4c0b-a894-5d44d5e88d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551075631 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2551075631
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2855628104
Short name T349
Test name
Test status
Simulation time 838796098 ps
CPU time 5.57 seconds
Started Jun 13 01:08:51 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 208464 kb
Host smart-bcd8f4f2-3445-474b-8be2-f5e56f526ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855628104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2855628104
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3707737995
Short name T49
Test name
Test status
Simulation time 103006088 ps
CPU time 2.88 seconds
Started Jun 13 02:08:15 PM PDT 24
Finished Jun 13 02:08:19 PM PDT 24
Peak memory 210868 kb
Host smart-66411087-0917-4e24-88eb-2744e1305453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707737995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3707737995
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4132086196
Short name T95
Test name
Test status
Simulation time 47538421 ps
CPU time 0.89 seconds
Started Jun 13 02:34:37 PM PDT 24
Finished Jun 13 02:34:39 PM PDT 24
Peak memory 205916 kb
Host smart-34349cdd-66d3-4ce0-a1b1-2b4f35bea931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132086196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4132086196
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2730389984
Short name T410
Test name
Test status
Simulation time 1435113405 ps
CPU time 69.65 seconds
Started Jun 13 01:08:57 PM PDT 24
Finished Jun 13 01:10:07 PM PDT 24
Peak memory 214452 kb
Host smart-b1d2e7f3-5aad-4a92-897e-705596164fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730389984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2730389984
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3442596710
Short name T76
Test name
Test status
Simulation time 200837992 ps
CPU time 3.21 seconds
Started Jun 13 01:09:05 PM PDT 24
Finished Jun 13 01:09:09 PM PDT 24
Peak memory 208216 kb
Host smart-0887da0d-894c-433d-9ceb-34a563f287a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442596710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3442596710
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3237933715
Short name T351
Test name
Test status
Simulation time 50183820 ps
CPU time 2.14 seconds
Started Jun 13 01:43:35 PM PDT 24
Finished Jun 13 01:43:37 PM PDT 24
Peak memory 214324 kb
Host smart-f4116c35-e059-4e6c-a655-cb4337c8199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237933715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3237933715
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1426867721
Short name T749
Test name
Test status
Simulation time 50990753 ps
CPU time 2.95 seconds
Started Jun 13 01:08:58 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 222460 kb
Host smart-d36040fb-d26b-4c08-ba09-d100d7261406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426867721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1426867721
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1826604463
Short name T360
Test name
Test status
Simulation time 343521665 ps
CPU time 3.7 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:08:59 PM PDT 24
Peak memory 214348 kb
Host smart-994d68cb-9616-45b9-bb4c-a1b1ca0b36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826604463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1826604463
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4007916341
Short name T378
Test name
Test status
Simulation time 377913930 ps
CPU time 4.64 seconds
Started Jun 13 01:08:55 PM PDT 24
Finished Jun 13 01:09:01 PM PDT 24
Peak memory 209108 kb
Host smart-7aa8a325-8db5-4527-b8cb-d25db222fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007916341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4007916341
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1716501717
Short name T659
Test name
Test status
Simulation time 25798846 ps
CPU time 1.93 seconds
Started Jun 13 02:24:11 PM PDT 24
Finished Jun 13 02:24:13 PM PDT 24
Peak memory 208416 kb
Host smart-11adc2c7-0b8c-483a-ac03-f5cebdeae879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716501717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1716501717
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1286742234
Short name T587
Test name
Test status
Simulation time 262783737 ps
CPU time 3.06 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:00 PM PDT 24
Peak memory 206824 kb
Host smart-351997a9-90af-461f-8adc-bd97e918408e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286742234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1286742234
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3919785165
Short name T473
Test name
Test status
Simulation time 169731321 ps
CPU time 2.46 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:08:55 PM PDT 24
Peak memory 206872 kb
Host smart-76756419-291c-4232-9e44-36427904b1b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919785165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3919785165
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3677494413
Short name T452
Test name
Test status
Simulation time 1372515112 ps
CPU time 32.29 seconds
Started Jun 13 01:37:40 PM PDT 24
Finished Jun 13 01:38:13 PM PDT 24
Peak memory 208868 kb
Host smart-a4a36ccb-db44-4ef1-8154-1fd36f12fd3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677494413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3677494413
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3973350376
Short name T762
Test name
Test status
Simulation time 1190391139 ps
CPU time 5.78 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 218184 kb
Host smart-12b7c142-42bd-4c51-8e09-855daab60b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973350376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3973350376
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2825895637
Short name T654
Test name
Test status
Simulation time 152505466 ps
CPU time 3.14 seconds
Started Jun 13 02:00:11 PM PDT 24
Finished Jun 13 02:00:15 PM PDT 24
Peak memory 208460 kb
Host smart-63112c01-f7c8-4a4b-bd97-cdbffa2294a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825895637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2825895637
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3117227152
Short name T785
Test name
Test status
Simulation time 2427028935 ps
CPU time 44.64 seconds
Started Jun 13 01:59:00 PM PDT 24
Finished Jun 13 01:59:46 PM PDT 24
Peak memory 222612 kb
Host smart-7511efe1-34a4-40ce-bb0a-0429ab88c6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117227152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3117227152
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3111416508
Short name T87
Test name
Test status
Simulation time 2416265917 ps
CPU time 26.05 seconds
Started Jun 13 01:44:51 PM PDT 24
Finished Jun 13 01:45:18 PM PDT 24
Peak memory 222496 kb
Host smart-e01bbeca-f461-43e9-a35f-5c894fb4f2d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111416508 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3111416508
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.163758924
Short name T681
Test name
Test status
Simulation time 167924841 ps
CPU time 2.7 seconds
Started Jun 13 01:18:39 PM PDT 24
Finished Jun 13 01:18:42 PM PDT 24
Peak memory 214304 kb
Host smart-49c87e46-b4a3-4069-a0b1-4fb4a65fd3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163758924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.163758924
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1772893461
Short name T545
Test name
Test status
Simulation time 121007261 ps
CPU time 1.88 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:16 PM PDT 24
Peak memory 210092 kb
Host smart-ad78e0ed-adbb-444f-b658-65ce88d9e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772893461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1772893461
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.306748420
Short name T740
Test name
Test status
Simulation time 17952100 ps
CPU time 0.73 seconds
Started Jun 13 01:37:09 PM PDT 24
Finished Jun 13 01:37:10 PM PDT 24
Peak memory 205932 kb
Host smart-ba8e587b-b40d-4944-b106-495703ea3635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306748420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.306748420
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4180576797
Short name T10
Test name
Test status
Simulation time 405205290 ps
CPU time 5.03 seconds
Started Jun 13 01:21:23 PM PDT 24
Finished Jun 13 01:21:29 PM PDT 24
Peak memory 208920 kb
Host smart-3c31c956-5d73-40ee-9dda-9e1e6b71d93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180576797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4180576797
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.754487535
Short name T845
Test name
Test status
Simulation time 42611716 ps
CPU time 2.23 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:08:55 PM PDT 24
Peak memory 210024 kb
Host smart-e19830e8-5534-4ed5-8eda-615487700c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754487535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.754487535
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3472043098
Short name T21
Test name
Test status
Simulation time 291226577 ps
CPU time 7.52 seconds
Started Jun 13 01:48:30 PM PDT 24
Finished Jun 13 01:48:38 PM PDT 24
Peak memory 214340 kb
Host smart-e9b70cfd-11c6-40f9-accf-fab8135297fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472043098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3472043098
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3193409624
Short name T333
Test name
Test status
Simulation time 72485464 ps
CPU time 3.8 seconds
Started Jun 13 01:36:30 PM PDT 24
Finished Jun 13 01:36:35 PM PDT 24
Peak memory 214268 kb
Host smart-a9bff428-1bed-41cf-a1eb-a1d20b28c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193409624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3193409624
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3880199813
Short name T764
Test name
Test status
Simulation time 117163519 ps
CPU time 2.48 seconds
Started Jun 13 01:59:02 PM PDT 24
Finished Jun 13 01:59:05 PM PDT 24
Peak memory 217568 kb
Host smart-f84f2bbb-196e-42a8-9faa-4fc91301517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880199813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3880199813
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3396073961
Short name T630
Test name
Test status
Simulation time 767413827 ps
CPU time 6.9 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:09:00 PM PDT 24
Peak memory 218492 kb
Host smart-af56a830-a93e-4d21-839a-6eb36f9d987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396073961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3396073961
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2961531163
Short name T891
Test name
Test status
Simulation time 662694980 ps
CPU time 7.13 seconds
Started Jun 13 01:30:22 PM PDT 24
Finished Jun 13 01:30:30 PM PDT 24
Peak memory 206712 kb
Host smart-74dd718c-f660-4323-a7fe-73c8244eea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961531163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2961531163
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1541527275
Short name T761
Test name
Test status
Simulation time 771614805 ps
CPU time 24.94 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:09:19 PM PDT 24
Peak memory 208260 kb
Host smart-e6f5b0f8-7e0d-4f02-b475-f2c0125736a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541527275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1541527275
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3125253107
Short name T470
Test name
Test status
Simulation time 276945456 ps
CPU time 3.22 seconds
Started Jun 13 01:09:04 PM PDT 24
Finished Jun 13 01:09:08 PM PDT 24
Peak memory 208536 kb
Host smart-4eecff26-f8dd-41dd-a516-491db7affe03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125253107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3125253107
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4239681777
Short name T455
Test name
Test status
Simulation time 308488356 ps
CPU time 4.13 seconds
Started Jun 13 03:03:04 PM PDT 24
Finished Jun 13 03:03:09 PM PDT 24
Peak memory 208812 kb
Host smart-c83b74f0-0c31-4679-a682-66d8dd450668
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239681777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4239681777
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3539287765
Short name T848
Test name
Test status
Simulation time 463303076 ps
CPU time 7.25 seconds
Started Jun 13 02:19:37 PM PDT 24
Finished Jun 13 02:19:48 PM PDT 24
Peak memory 209592 kb
Host smart-0dd8564c-6e45-430c-8c9b-10646a52dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539287765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3539287765
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2147714943
Short name T225
Test name
Test status
Simulation time 68893229 ps
CPU time 2.78 seconds
Started Jun 13 02:06:44 PM PDT 24
Finished Jun 13 02:06:48 PM PDT 24
Peak memory 206940 kb
Host smart-c0079c4d-ee3f-402c-a55e-e097d184b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147714943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2147714943
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2115234144
Short name T254
Test name
Test status
Simulation time 1939988142 ps
CPU time 22.43 seconds
Started Jun 13 01:31:07 PM PDT 24
Finished Jun 13 01:31:30 PM PDT 24
Peak memory 214364 kb
Host smart-95be98aa-2a83-4410-9747-fff4190a47ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115234144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2115234144
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1715244532
Short name T137
Test name
Test status
Simulation time 479110020 ps
CPU time 8.39 seconds
Started Jun 13 02:26:24 PM PDT 24
Finished Jun 13 02:26:33 PM PDT 24
Peak memory 222592 kb
Host smart-f2766699-2895-4fb2-bcb4-9cabed81edcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715244532 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1715244532
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3677524574
Short name T148
Test name
Test status
Simulation time 2812369725 ps
CPU time 38.48 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:09:33 PM PDT 24
Peak memory 208660 kb
Host smart-392b1b4f-9000-4f97-846c-7e1445d69100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677524574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3677524574
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1640606849
Short name T802
Test name
Test status
Simulation time 187385465 ps
CPU time 2.26 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:29:57 PM PDT 24
Peak memory 210400 kb
Host smart-57fcc47c-19b3-493e-8b69-cac4c6af6dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640606849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1640606849
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.722277283
Short name T589
Test name
Test status
Simulation time 13731553 ps
CPU time 0.87 seconds
Started Jun 13 01:37:26 PM PDT 24
Finished Jun 13 01:37:28 PM PDT 24
Peak memory 205944 kb
Host smart-f2a9a3e1-52aa-4c6b-97c3-b867640fb5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722277283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.722277283
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1906828950
Short name T424
Test name
Test status
Simulation time 140966783 ps
CPU time 7.71 seconds
Started Jun 13 01:30:14 PM PDT 24
Finished Jun 13 01:30:22 PM PDT 24
Peak memory 214308 kb
Host smart-450ddb2e-e3fe-4dfc-9328-127eb4eb9014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906828950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1906828950
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4159952814
Short name T31
Test name
Test status
Simulation time 86722651 ps
CPU time 1.54 seconds
Started Jun 13 01:52:30 PM PDT 24
Finished Jun 13 01:52:33 PM PDT 24
Peak memory 221052 kb
Host smart-63740107-aa47-4c0f-a16c-86575956a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159952814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4159952814
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2235621960
Short name T832
Test name
Test status
Simulation time 283418735 ps
CPU time 1.91 seconds
Started Jun 13 01:46:17 PM PDT 24
Finished Jun 13 01:46:20 PM PDT 24
Peak memory 207452 kb
Host smart-ee80a494-dfbe-45f6-a3a5-7643a7836397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235621960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2235621960
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.25799731
Short name T685
Test name
Test status
Simulation time 58923927 ps
CPU time 3.68 seconds
Started Jun 13 01:56:49 PM PDT 24
Finished Jun 13 01:56:55 PM PDT 24
Peak memory 209696 kb
Host smart-94e90b54-d2dc-46ca-8df3-b8db2660ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25799731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.25799731
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2841719459
Short name T754
Test name
Test status
Simulation time 69157459 ps
CPU time 1.82 seconds
Started Jun 13 02:04:49 PM PDT 24
Finished Jun 13 02:04:52 PM PDT 24
Peak memory 214292 kb
Host smart-69aedd4f-97f6-4750-bb92-2bfd0846b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841719459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2841719459
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3362833997
Short name T315
Test name
Test status
Simulation time 144163082 ps
CPU time 3.71 seconds
Started Jun 13 01:22:33 PM PDT 24
Finished Jun 13 01:22:37 PM PDT 24
Peak memory 215736 kb
Host smart-1f83d69a-06ac-4b7e-915e-fd2f595c6f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362833997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3362833997
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.234120320
Short name T501
Test name
Test status
Simulation time 4860015508 ps
CPU time 49.13 seconds
Started Jun 13 01:46:42 PM PDT 24
Finished Jun 13 01:47:32 PM PDT 24
Peak memory 219992 kb
Host smart-48faecd2-24f2-4b25-92d2-f47987cc4281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234120320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.234120320
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2856015902
Short name T143
Test name
Test status
Simulation time 101636152 ps
CPU time 3.02 seconds
Started Jun 13 02:01:54 PM PDT 24
Finished Jun 13 02:01:58 PM PDT 24
Peak memory 206884 kb
Host smart-ffd4b384-bb91-4e8c-9be4-6f2be43af3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856015902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2856015902
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4084561003
Short name T596
Test name
Test status
Simulation time 217705771 ps
CPU time 3.73 seconds
Started Jun 13 01:57:43 PM PDT 24
Finished Jun 13 01:57:48 PM PDT 24
Peak memory 208844 kb
Host smart-c06c60a3-7801-4de0-ac46-eb4b3352accd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084561003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4084561003
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1578953909
Short name T901
Test name
Test status
Simulation time 92372309 ps
CPU time 3.84 seconds
Started Jun 13 02:23:38 PM PDT 24
Finished Jun 13 02:23:42 PM PDT 24
Peak memory 207004 kb
Host smart-c4b1e460-90aa-4f02-964c-64609855688b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578953909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1578953909
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2232021840
Short name T574
Test name
Test status
Simulation time 237003913 ps
CPU time 3.02 seconds
Started Jun 13 01:09:58 PM PDT 24
Finished Jun 13 01:10:02 PM PDT 24
Peak memory 207100 kb
Host smart-5228aaa2-1b8f-4477-b0fe-16d943cf216e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232021840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2232021840
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.834574128
Short name T601
Test name
Test status
Simulation time 227048082 ps
CPU time 2.69 seconds
Started Jun 13 01:09:02 PM PDT 24
Finished Jun 13 01:09:07 PM PDT 24
Peak memory 209652 kb
Host smart-4de38ae3-9f09-4c00-a6ba-6f88ceef3a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834574128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.834574128
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1359995377
Short name T445
Test name
Test status
Simulation time 190350524 ps
CPU time 4.05 seconds
Started Jun 13 01:24:05 PM PDT 24
Finished Jun 13 01:24:09 PM PDT 24
Peak memory 208544 kb
Host smart-1b9b84ee-a036-41bd-8a22-df1d84517b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359995377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1359995377
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3364018800
Short name T305
Test name
Test status
Simulation time 6765704287 ps
CPU time 209.23 seconds
Started Jun 13 01:37:05 PM PDT 24
Finished Jun 13 01:40:35 PM PDT 24
Peak memory 217144 kb
Host smart-ad74d991-6aeb-461a-8dca-3a4fc66c692a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364018800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3364018800
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3494842148
Short name T322
Test name
Test status
Simulation time 7514306911 ps
CPU time 21.46 seconds
Started Jun 13 01:08:56 PM PDT 24
Finished Jun 13 01:09:18 PM PDT 24
Peak memory 222848 kb
Host smart-e3d0c8d8-25dc-414f-b483-4c2001430ea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494842148 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3494842148
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3720695017
Short name T646
Test name
Test status
Simulation time 462084067 ps
CPU time 11.78 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 218324 kb
Host smart-dd37cfef-709d-43ff-a775-f80541263c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720695017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3720695017
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3823810183
Short name T48
Test name
Test status
Simulation time 108759724 ps
CPU time 3.1 seconds
Started Jun 13 01:43:23 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 210920 kb
Host smart-b195e25c-0fb9-44ba-8c04-b1055cdb7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823810183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3823810183
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2719128508
Short name T430
Test name
Test status
Simulation time 30632805 ps
CPU time 0.77 seconds
Started Jun 13 01:28:12 PM PDT 24
Finished Jun 13 01:28:13 PM PDT 24
Peak memory 205904 kb
Host smart-4a2986b5-b190-4e3c-8fbc-d93582955dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719128508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2719128508
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3375293176
Short name T421
Test name
Test status
Simulation time 571265611 ps
CPU time 7.96 seconds
Started Jun 13 01:45:52 PM PDT 24
Finished Jun 13 01:46:01 PM PDT 24
Peak memory 214272 kb
Host smart-ff3256d2-e373-4361-ac35-f3ecdad5973b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375293176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3375293176
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.632201904
Short name T81
Test name
Test status
Simulation time 40161352 ps
CPU time 1.73 seconds
Started Jun 13 01:29:03 PM PDT 24
Finished Jun 13 01:29:05 PM PDT 24
Peak memory 214176 kb
Host smart-6db452e0-f87e-4e48-a53d-879da4535c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632201904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.632201904
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.581499613
Short name T358
Test name
Test status
Simulation time 3181683225 ps
CPU time 19.4 seconds
Started Jun 13 01:44:10 PM PDT 24
Finished Jun 13 01:44:30 PM PDT 24
Peak memory 219964 kb
Host smart-80925603-cf5c-47ab-91c3-e3f007e1cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581499613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.581499613
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2896393140
Short name T283
Test name
Test status
Simulation time 190296022 ps
CPU time 2.91 seconds
Started Jun 13 01:51:02 PM PDT 24
Finished Jun 13 01:51:07 PM PDT 24
Peak memory 221500 kb
Host smart-59d0acdf-5b21-4a24-8fc8-557d467e4a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896393140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2896393140
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1068355299
Short name T568
Test name
Test status
Simulation time 66383841 ps
CPU time 2.62 seconds
Started Jun 13 01:34:04 PM PDT 24
Finished Jun 13 01:34:07 PM PDT 24
Peak memory 211228 kb
Host smart-09a80ae3-d965-47e5-88f4-0139c7db5d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068355299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1068355299
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1892919526
Short name T53
Test name
Test status
Simulation time 143936304 ps
CPU time 2.69 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:08:57 PM PDT 24
Peak memory 214284 kb
Host smart-c9ad25ad-ede1-4185-9a0d-5253b1886eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892919526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1892919526
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.418992791
Short name T263
Test name
Test status
Simulation time 1197951099 ps
CPU time 27.05 seconds
Started Jun 13 02:22:20 PM PDT 24
Finished Jun 13 02:22:48 PM PDT 24
Peak memory 218484 kb
Host smart-ed99a75c-b89b-4d4b-aa2c-1866412ba3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418992791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.418992791
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.276552533
Short name T594
Test name
Test status
Simulation time 1256305280 ps
CPU time 43.7 seconds
Started Jun 13 01:49:33 PM PDT 24
Finished Jun 13 01:50:18 PM PDT 24
Peak memory 208608 kb
Host smart-4c24cc23-dc9c-4e60-99f0-677fe14618a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276552533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.276552533
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3083163664
Short name T150
Test name
Test status
Simulation time 557900314 ps
CPU time 2.84 seconds
Started Jun 13 01:21:18 PM PDT 24
Finished Jun 13 01:21:22 PM PDT 24
Peak memory 206864 kb
Host smart-46e5c1c9-9255-4e01-8495-756779524b84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083163664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3083163664
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3164497476
Short name T348
Test name
Test status
Simulation time 135857709 ps
CPU time 2.45 seconds
Started Jun 13 02:32:10 PM PDT 24
Finished Jun 13 02:32:20 PM PDT 24
Peak memory 208568 kb
Host smart-57bc2fcd-f4d1-412a-878b-094e7e199c13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164497476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3164497476
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1487410029
Short name T672
Test name
Test status
Simulation time 838400771 ps
CPU time 5.55 seconds
Started Jun 13 01:22:49 PM PDT 24
Finished Jun 13 01:22:57 PM PDT 24
Peak memory 208456 kb
Host smart-a54022ef-666b-4360-8d17-9828c718dc5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487410029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1487410029
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.9576870
Short name T669
Test name
Test status
Simulation time 82544370 ps
CPU time 2.45 seconds
Started Jun 13 01:47:47 PM PDT 24
Finished Jun 13 01:47:51 PM PDT 24
Peak memory 206768 kb
Host smart-84be41dc-62a5-4ac1-a8e1-46e3aa38406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9576870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.9576870
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3127685003
Short name T450
Test name
Test status
Simulation time 46077826 ps
CPU time 2.3 seconds
Started Jun 13 01:13:16 PM PDT 24
Finished Jun 13 01:13:19 PM PDT 24
Peak memory 206840 kb
Host smart-ec4209d7-3750-49a7-a280-b77dd7da4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127685003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3127685003
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2541971844
Short name T798
Test name
Test status
Simulation time 4225406742 ps
CPU time 64.74 seconds
Started Jun 13 01:09:05 PM PDT 24
Finished Jun 13 01:10:11 PM PDT 24
Peak memory 216908 kb
Host smart-c5977f09-e3e9-461a-bc37-df545a962753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541971844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2541971844
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2446176713
Short name T250
Test name
Test status
Simulation time 997370066 ps
CPU time 11.92 seconds
Started Jun 13 02:08:18 PM PDT 24
Finished Jun 13 02:08:32 PM PDT 24
Peak memory 222624 kb
Host smart-c54ee59f-55ee-4abc-8e82-202b1535898d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446176713 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2446176713
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2254474214
Short name T561
Test name
Test status
Simulation time 52043875 ps
CPU time 3 seconds
Started Jun 13 01:08:55 PM PDT 24
Finished Jun 13 01:08:59 PM PDT 24
Peak memory 214288 kb
Host smart-d7241ee3-06f4-47f1-8120-4eff0d14d810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254474214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2254474214
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2175970441
Short name T515
Test name
Test status
Simulation time 134653766 ps
CPU time 1.94 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:24 PM PDT 24
Peak memory 209916 kb
Host smart-79a56198-e709-476a-86f4-b670e1cf3c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175970441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2175970441
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4073797528
Short name T547
Test name
Test status
Simulation time 48970151 ps
CPU time 0.85 seconds
Started Jun 13 01:31:15 PM PDT 24
Finished Jun 13 01:31:16 PM PDT 24
Peak memory 205904 kb
Host smart-21532d7e-0d5b-49d5-b0ba-b1e33ff04b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073797528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4073797528
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3188147990
Short name T297
Test name
Test status
Simulation time 33982201 ps
CPU time 2.47 seconds
Started Jun 13 02:32:15 PM PDT 24
Finished Jun 13 02:32:25 PM PDT 24
Peak memory 214400 kb
Host smart-0a196d92-8ebb-46ef-9511-dc90c0f36a08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188147990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3188147990
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1121737662
Short name T908
Test name
Test status
Simulation time 107466871 ps
CPU time 2.38 seconds
Started Jun 13 02:13:37 PM PDT 24
Finished Jun 13 02:13:40 PM PDT 24
Peak memory 216112 kb
Host smart-b6b65eac-b5df-4d17-b1a4-f88e083254f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121737662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1121737662
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.143107870
Short name T546
Test name
Test status
Simulation time 27873597 ps
CPU time 1.4 seconds
Started Jun 13 01:34:53 PM PDT 24
Finished Jun 13 01:34:55 PM PDT 24
Peak memory 207644 kb
Host smart-be7d4ce4-7860-45d4-9911-a7725d79c027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143107870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.143107870
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3391555541
Short name T851
Test name
Test status
Simulation time 840162482 ps
CPU time 10.36 seconds
Started Jun 13 01:36:29 PM PDT 24
Finished Jun 13 01:36:40 PM PDT 24
Peak memory 209696 kb
Host smart-832feb8a-ae61-483d-8ad4-4db7335a449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391555541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3391555541
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3268333162
Short name T608
Test name
Test status
Simulation time 126519329 ps
CPU time 3.8 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:08:59 PM PDT 24
Peak memory 219992 kb
Host smart-8ba4f333-f1f3-4d52-b48b-427278b11fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268333162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3268333162
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1819194309
Short name T597
Test name
Test status
Simulation time 35017670 ps
CPU time 2.81 seconds
Started Jun 13 01:15:25 PM PDT 24
Finished Jun 13 01:15:29 PM PDT 24
Peak memory 210332 kb
Host smart-7f8cc650-7220-4525-878c-919a8f375bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819194309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1819194309
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1387274359
Short name T697
Test name
Test status
Simulation time 324359042 ps
CPU time 3.88 seconds
Started Jun 13 01:08:51 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 209344 kb
Host smart-65d87897-7f91-4933-8e01-8f21cc2ff477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387274359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1387274359
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.161461073
Short name T678
Test name
Test status
Simulation time 209126136 ps
CPU time 2.73 seconds
Started Jun 13 01:08:54 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 208128 kb
Host smart-c0fe6aa2-6d0b-4c4d-b1d5-1939caa91b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161461073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.161461073
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1969118621
Short name T404
Test name
Test status
Simulation time 62456116 ps
CPU time 3.29 seconds
Started Jun 13 01:17:33 PM PDT 24
Finished Jun 13 01:17:37 PM PDT 24
Peak memory 208644 kb
Host smart-7f070c8d-e654-417a-9095-bff290b3f966
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969118621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1969118621
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1369862517
Short name T454
Test name
Test status
Simulation time 35087760 ps
CPU time 1.86 seconds
Started Jun 13 02:12:57 PM PDT 24
Finished Jun 13 02:13:00 PM PDT 24
Peak memory 206844 kb
Host smart-049c6c9e-7d0c-4471-82fe-30981682de3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369862517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1369862517
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.65053480
Short name T273
Test name
Test status
Simulation time 162497170 ps
CPU time 3.87 seconds
Started Jun 13 01:08:53 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 208924 kb
Host smart-f23feb83-e00b-404a-a24b-38d208349780
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65053480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.65053480
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3574196752
Short name T598
Test name
Test status
Simulation time 223764051 ps
CPU time 6.14 seconds
Started Jun 13 02:37:42 PM PDT 24
Finished Jun 13 02:37:50 PM PDT 24
Peak memory 209908 kb
Host smart-7d978293-7cf7-4052-bc38-b23d8a6868bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574196752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3574196752
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.651352725
Short name T855
Test name
Test status
Simulation time 3167744253 ps
CPU time 31.11 seconds
Started Jun 13 01:19:06 PM PDT 24
Finished Jun 13 01:19:39 PM PDT 24
Peak memory 217180 kb
Host smart-81faf9e0-019a-4de2-a82d-43c4dd92fc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651352725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.651352725
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2554193399
Short name T403
Test name
Test status
Simulation time 1006376351 ps
CPU time 26.88 seconds
Started Jun 13 02:32:34 PM PDT 24
Finished Jun 13 02:33:04 PM PDT 24
Peak memory 214388 kb
Host smart-1541db11-3cda-455d-97c6-fa6756e048fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554193399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2554193399
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2134200263
Short name T469
Test name
Test status
Simulation time 189850291 ps
CPU time 2.52 seconds
Started Jun 13 01:51:19 PM PDT 24
Finished Jun 13 01:51:22 PM PDT 24
Peak memory 209756 kb
Host smart-e5f6f8ec-f1a4-4fc2-9314-cf9ce28a7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134200263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2134200263
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3078061226
Short name T826
Test name
Test status
Simulation time 61531662 ps
CPU time 0.97 seconds
Started Jun 13 01:08:58 PM PDT 24
Finished Jun 13 01:09:00 PM PDT 24
Peak memory 206096 kb
Host smart-2052fb4e-58f3-42c4-9588-bdd2e72c279a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078061226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3078061226
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1302998661
Short name T312
Test name
Test status
Simulation time 117407158 ps
CPU time 4.61 seconds
Started Jun 13 02:23:58 PM PDT 24
Finished Jun 13 02:24:03 PM PDT 24
Peak memory 215212 kb
Host smart-1d67a728-f49b-40d4-b7aa-1ced86f0e698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302998661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1302998661
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.454119770
Short name T236
Test name
Test status
Simulation time 190692480 ps
CPU time 2.43 seconds
Started Jun 13 01:38:36 PM PDT 24
Finished Jun 13 01:38:39 PM PDT 24
Peak memory 206052 kb
Host smart-7c06f826-deb6-453a-856f-993c898a0fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454119770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.454119770
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1289692530
Short name T484
Test name
Test status
Simulation time 984054059 ps
CPU time 22.94 seconds
Started Jun 13 01:38:54 PM PDT 24
Finished Jun 13 01:39:18 PM PDT 24
Peak memory 208516 kb
Host smart-d529eb7e-38e1-4c9b-93d3-ba73b60a28ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289692530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1289692530
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2828786828
Short name T487
Test name
Test status
Simulation time 26507371 ps
CPU time 2.04 seconds
Started Jun 13 01:09:02 PM PDT 24
Finished Jun 13 01:09:06 PM PDT 24
Peak memory 214244 kb
Host smart-0b6dc0d5-2346-45a7-8231-219ca5205796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828786828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2828786828
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3001652483
Short name T101
Test name
Test status
Simulation time 481076042 ps
CPU time 2.77 seconds
Started Jun 13 01:08:58 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 214184 kb
Host smart-085697bf-eac1-425f-997d-763e39c0485c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001652483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3001652483
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3734293956
Short name T75
Test name
Test status
Simulation time 40884204 ps
CPU time 2.89 seconds
Started Jun 13 01:08:52 PM PDT 24
Finished Jun 13 01:08:56 PM PDT 24
Peak memory 219092 kb
Host smart-68d22c13-95c2-4e74-88b3-28eba54c71e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734293956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3734293956
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.4096481241
Short name T370
Test name
Test status
Simulation time 60110414 ps
CPU time 3.57 seconds
Started Jun 13 01:46:57 PM PDT 24
Finished Jun 13 01:47:03 PM PDT 24
Peak memory 207460 kb
Host smart-d3b2465e-1dab-4bd9-9d8d-93fe479e71ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096481241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.4096481241
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.39240679
Short name T644
Test name
Test status
Simulation time 1670508033 ps
CPU time 43.57 seconds
Started Jun 13 02:46:33 PM PDT 24
Finished Jun 13 02:47:26 PM PDT 24
Peak memory 207964 kb
Host smart-d344f64a-969c-438b-b68b-e1c3d19b626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39240679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.39240679
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1537700295
Short name T542
Test name
Test status
Simulation time 182441732 ps
CPU time 2.33 seconds
Started Jun 13 02:13:28 PM PDT 24
Finished Jun 13 02:13:30 PM PDT 24
Peak memory 207096 kb
Host smart-4de17fa7-fb6e-4926-925c-722625f1758e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537700295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1537700295
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4001969221
Short name T774
Test name
Test status
Simulation time 180648562 ps
CPU time 4.65 seconds
Started Jun 13 01:44:05 PM PDT 24
Finished Jun 13 01:44:11 PM PDT 24
Peak memory 207872 kb
Host smart-ca253c78-cc2e-4c22-9139-b016890bcadc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001969221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4001969221
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2261795854
Short name T611
Test name
Test status
Simulation time 2591335780 ps
CPU time 33.69 seconds
Started Jun 13 01:22:55 PM PDT 24
Finished Jun 13 01:23:30 PM PDT 24
Peak memory 208580 kb
Host smart-d0ee6a46-4d63-4b09-80ff-3564c56e09b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261795854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2261795854
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3723573293
Short name T459
Test name
Test status
Simulation time 59694326 ps
CPU time 3.15 seconds
Started Jun 13 01:18:39 PM PDT 24
Finished Jun 13 01:18:43 PM PDT 24
Peak memory 209252 kb
Host smart-53776e34-f122-4dbd-b045-77b212661260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723573293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3723573293
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.127567962
Short name T624
Test name
Test status
Simulation time 484807804 ps
CPU time 3.2 seconds
Started Jun 13 02:24:45 PM PDT 24
Finished Jun 13 02:24:49 PM PDT 24
Peak memory 206800 kb
Host smart-eefde838-864c-4156-ba1b-da21334c6162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127567962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.127567962
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1721110003
Short name T827
Test name
Test status
Simulation time 8185525895 ps
CPU time 52.61 seconds
Started Jun 13 02:13:30 PM PDT 24
Finished Jun 13 02:14:24 PM PDT 24
Peak memory 222672 kb
Host smart-0daead51-8ae4-4fc2-bbfc-feafaf5eb57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721110003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1721110003
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1372804178
Short name T197
Test name
Test status
Simulation time 2636991088 ps
CPU time 13.25 seconds
Started Jun 13 01:19:58 PM PDT 24
Finished Jun 13 01:20:12 PM PDT 24
Peak memory 222720 kb
Host smart-6dbd365c-e966-43cf-816f-a7e2e8e9d55c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372804178 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1372804178
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.824457192
Short name T549
Test name
Test status
Simulation time 6324485304 ps
CPU time 40.59 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:20:10 PM PDT 24
Peak memory 218576 kb
Host smart-08b7c92a-472e-4ddc-ba51-d19c658d79a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824457192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.824457192
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.370084641
Short name T615
Test name
Test status
Simulation time 82906986 ps
CPU time 2.21 seconds
Started Jun 13 01:29:26 PM PDT 24
Finished Jun 13 01:29:29 PM PDT 24
Peak memory 210044 kb
Host smart-7e1e757a-68fe-498c-8c13-46264f2ef4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370084641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.370084641
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.653631230
Short name T541
Test name
Test status
Simulation time 29760179 ps
CPU time 1.15 seconds
Started Jun 13 01:22:43 PM PDT 24
Finished Jun 13 01:22:45 PM PDT 24
Peak memory 206100 kb
Host smart-4751f437-a828-4ee0-ab34-7689807da0bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653631230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.653631230
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.781017205
Short name T28
Test name
Test status
Simulation time 597969725 ps
CPU time 9.17 seconds
Started Jun 13 01:08:59 PM PDT 24
Finished Jun 13 01:09:09 PM PDT 24
Peak memory 214536 kb
Host smart-9187b157-c3ec-4013-b471-706a0b6a4882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781017205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.781017205
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.79105996
Short name T856
Test name
Test status
Simulation time 33584954 ps
CPU time 1.93 seconds
Started Jun 13 01:08:59 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 207672 kb
Host smart-c3e106a5-cd72-4f92-90fa-96a4150b2167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79105996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.79105996
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2258434859
Short name T104
Test name
Test status
Simulation time 971727065 ps
CPU time 7.21 seconds
Started Jun 13 01:22:58 PM PDT 24
Finished Jun 13 01:23:06 PM PDT 24
Peak memory 220944 kb
Host smart-7287101f-0e4f-472e-b3b8-5b7eeddb7e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258434859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2258434859
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3358579077
Short name T332
Test name
Test status
Simulation time 175576566 ps
CPU time 5.76 seconds
Started Jun 13 01:57:33 PM PDT 24
Finished Jun 13 01:57:40 PM PDT 24
Peak memory 207064 kb
Host smart-a5a609a2-b167-4b23-84f0-8d445f19f3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358579077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3358579077
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3499424996
Short name T507
Test name
Test status
Simulation time 536189753 ps
CPU time 2.72 seconds
Started Jun 13 01:08:59 PM PDT 24
Finished Jun 13 01:09:03 PM PDT 24
Peak memory 219792 kb
Host smart-99bc029a-3f5f-474d-8511-9ff09e42b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499424996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3499424996
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.49032077
Short name T222
Test name
Test status
Simulation time 374578427 ps
CPU time 4.31 seconds
Started Jun 13 01:08:58 PM PDT 24
Finished Jun 13 01:09:03 PM PDT 24
Peak memory 218352 kb
Host smart-29cfed35-aa40-49d3-ac1c-578d1c5e6f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49032077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.49032077
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2126471517
Short name T534
Test name
Test status
Simulation time 1555605540 ps
CPU time 7.4 seconds
Started Jun 13 01:25:58 PM PDT 24
Finished Jun 13 01:26:08 PM PDT 24
Peak memory 208444 kb
Host smart-2f404613-6aa3-4a8f-b9c9-02f905b3b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126471517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2126471517
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3109972659
Short name T466
Test name
Test status
Simulation time 393019941 ps
CPU time 4.1 seconds
Started Jun 13 01:58:32 PM PDT 24
Finished Jun 13 01:58:37 PM PDT 24
Peak memory 208828 kb
Host smart-c8337578-ff03-49da-83cc-27f020ee4a80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109972659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3109972659
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.621404336
Short name T872
Test name
Test status
Simulation time 79474674 ps
CPU time 3.78 seconds
Started Jun 13 01:09:03 PM PDT 24
Finished Jun 13 01:09:08 PM PDT 24
Peak memory 208884 kb
Host smart-e7755830-e43e-4e98-81c0-5473bdda98d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621404336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.621404336
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4170385114
Short name T401
Test name
Test status
Simulation time 209800454 ps
CPU time 3.07 seconds
Started Jun 13 01:08:58 PM PDT 24
Finished Jun 13 01:09:02 PM PDT 24
Peak memory 206900 kb
Host smart-2355c286-d3b0-40e2-b635-0893a9f422fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170385114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4170385114
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2797509474
Short name T339
Test name
Test status
Simulation time 3152090192 ps
CPU time 18.89 seconds
Started Jun 13 02:40:20 PM PDT 24
Finished Jun 13 02:40:43 PM PDT 24
Peak memory 209628 kb
Host smart-e2f67c95-2064-4859-8303-a9e8b8f82fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797509474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2797509474
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4074755391
Short name T716
Test name
Test status
Simulation time 51365539 ps
CPU time 2.29 seconds
Started Jun 13 02:06:58 PM PDT 24
Finished Jun 13 02:07:01 PM PDT 24
Peak memory 208616 kb
Host smart-b5f50878-7a53-44e3-943c-b214aa32db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074755391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4074755391
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2119211624
Short name T800
Test name
Test status
Simulation time 1348975021 ps
CPU time 7.64 seconds
Started Jun 13 02:03:47 PM PDT 24
Finished Jun 13 02:03:55 PM PDT 24
Peak memory 219588 kb
Host smart-40a0e2ea-b74d-489c-8916-125595527950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119211624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2119211624
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3384024351
Short name T906
Test name
Test status
Simulation time 1046705795 ps
CPU time 10.79 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:11:03 PM PDT 24
Peak memory 208008 kb
Host smart-800b38c5-87a6-4e98-8a7c-cdef20e57424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384024351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3384024351
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2120287051
Short name T43
Test name
Test status
Simulation time 153888208 ps
CPU time 2.03 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:21:48 PM PDT 24
Peak memory 210076 kb
Host smart-8a6debaa-7756-4f53-88a9-ad4c9adb41f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120287051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2120287051
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.185552921
Short name T448
Test name
Test status
Simulation time 12617640 ps
CPU time 0.9 seconds
Started Jun 13 01:07:19 PM PDT 24
Finished Jun 13 01:07:21 PM PDT 24
Peak memory 205896 kb
Host smart-f0d2266b-57d8-4893-ad03-dc15f23e259a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185552921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.185552921
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3799081879
Short name T492
Test name
Test status
Simulation time 30142450 ps
CPU time 1.83 seconds
Started Jun 13 01:07:22 PM PDT 24
Finished Jun 13 01:07:24 PM PDT 24
Peak memory 207096 kb
Host smart-b08a18f5-c2ae-4cb9-a6c5-c63c98917be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799081879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3799081879
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.463794853
Short name T463
Test name
Test status
Simulation time 111917745 ps
CPU time 3.82 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:17 PM PDT 24
Peak memory 208624 kb
Host smart-3f1e0753-7596-4b94-945e-b8f17dcbbcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463794853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.463794853
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2337270023
Short name T909
Test name
Test status
Simulation time 218219881 ps
CPU time 5.15 seconds
Started Jun 13 01:07:22 PM PDT 24
Finished Jun 13 01:07:28 PM PDT 24
Peak memory 222468 kb
Host smart-6e5c393c-54af-4d2f-9c5d-d29dab98632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337270023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2337270023
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1267682206
Short name T599
Test name
Test status
Simulation time 918931592 ps
CPU time 5.61 seconds
Started Jun 13 01:07:12 PM PDT 24
Finished Jun 13 01:07:19 PM PDT 24
Peak memory 210716 kb
Host smart-b07f872d-f414-4145-b1dc-4beac6c829c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267682206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1267682206
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3053360984
Short name T797
Test name
Test status
Simulation time 4706841961 ps
CPU time 48.72 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:08:02 PM PDT 24
Peak memory 208340 kb
Host smart-d845f0aa-b8d3-4782-91d3-91351189d9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053360984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3053360984
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.735585158
Short name T278
Test name
Test status
Simulation time 68186957 ps
CPU time 2.45 seconds
Started Jun 13 01:07:11 PM PDT 24
Finished Jun 13 01:07:15 PM PDT 24
Peak memory 208416 kb
Host smart-2eef28af-88e8-406b-b78c-1fbe4024620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735585158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.735585158
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2105595023
Short name T508
Test name
Test status
Simulation time 39064526 ps
CPU time 1.79 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:16 PM PDT 24
Peak memory 206780 kb
Host smart-42b1860a-409f-4443-b052-552bf6d6ecaf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105595023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2105595023
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1187313977
Short name T665
Test name
Test status
Simulation time 99867193 ps
CPU time 2.83 seconds
Started Jun 13 01:07:12 PM PDT 24
Finished Jun 13 01:07:15 PM PDT 24
Peak memory 206992 kb
Host smart-f56e6107-cd54-4186-ba8f-50fee3d0d52b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187313977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1187313977
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2810240940
Short name T552
Test name
Test status
Simulation time 244426606 ps
CPU time 5.94 seconds
Started Jun 13 01:07:17 PM PDT 24
Finished Jun 13 01:07:23 PM PDT 24
Peak memory 209052 kb
Host smart-3c43f613-5aa5-48c8-8d3b-236526125e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810240940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2810240940
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1365069014
Short name T480
Test name
Test status
Simulation time 733324964 ps
CPU time 3.07 seconds
Started Jun 13 01:07:13 PM PDT 24
Finished Jun 13 01:07:17 PM PDT 24
Peak memory 208108 kb
Host smart-2639d589-7c25-47f7-ae2a-d7e10a685a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365069014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1365069014
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1398214053
Short name T318
Test name
Test status
Simulation time 319264354 ps
CPU time 6.68 seconds
Started Jun 13 01:07:20 PM PDT 24
Finished Jun 13 01:07:27 PM PDT 24
Peak memory 210184 kb
Host smart-e170acb8-02bd-4f48-9799-64fbe3017395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398214053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1398214053
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3842881063
Short name T882
Test name
Test status
Simulation time 548960454 ps
CPU time 3.16 seconds
Started Jun 13 01:07:16 PM PDT 24
Finished Jun 13 01:07:20 PM PDT 24
Peak memory 210456 kb
Host smart-9b9f7013-5944-45ba-8b10-0c1d449aca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842881063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3842881063
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.117
Short name T585
Test name
Test status
Simulation time 121409249 ps
CPU time 0.83 seconds
Started Jun 13 01:07:28 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 205888 kb
Host smart-6dd6a7f2-d6f0-446d-9c3d-4643c0b14cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.117
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3794356725
Short name T423
Test name
Test status
Simulation time 86712936 ps
CPU time 4.61 seconds
Started Jun 13 01:07:18 PM PDT 24
Finished Jun 13 01:07:23 PM PDT 24
Peak memory 214304 kb
Host smart-6b9beddc-19de-4b40-9b2c-778e2de6ca83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794356725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3794356725
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.596904580
Short name T885
Test name
Test status
Simulation time 77065534 ps
CPU time 4.15 seconds
Started Jun 13 01:07:16 PM PDT 24
Finished Jun 13 01:07:21 PM PDT 24
Peak memory 214584 kb
Host smart-86d678bb-f143-4497-9c76-bf57a7c8b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596904580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.596904580
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3861883874
Short name T639
Test name
Test status
Simulation time 356712921 ps
CPU time 8.32 seconds
Started Jun 13 01:07:19 PM PDT 24
Finished Jun 13 01:07:28 PM PDT 24
Peak memory 209204 kb
Host smart-15850463-ce68-49f7-928d-fd12c4e093ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861883874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3861883874
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3117657690
Short name T850
Test name
Test status
Simulation time 839693890 ps
CPU time 6.51 seconds
Started Jun 13 01:07:18 PM PDT 24
Finished Jun 13 01:07:25 PM PDT 24
Peak memory 214300 kb
Host smart-426c919a-3413-4ef1-8aed-8eb11b4337bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117657690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3117657690
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2929976665
Short name T354
Test name
Test status
Simulation time 85878655 ps
CPU time 2.56 seconds
Started Jun 13 01:07:23 PM PDT 24
Finished Jun 13 01:07:26 PM PDT 24
Peak memory 222384 kb
Host smart-98b3d465-c796-47cd-b83f-19070193ed79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929976665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2929976665
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1321580980
Short name T544
Test name
Test status
Simulation time 72957454 ps
CPU time 3.23 seconds
Started Jun 13 01:07:19 PM PDT 24
Finished Jun 13 01:07:23 PM PDT 24
Peak memory 219668 kb
Host smart-21935032-238e-428d-86b1-e227dd3774fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321580980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1321580980
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1421291230
Short name T464
Test name
Test status
Simulation time 415279754 ps
CPU time 4.73 seconds
Started Jun 13 01:07:22 PM PDT 24
Finished Jun 13 01:07:28 PM PDT 24
Peak memory 208648 kb
Host smart-8a6302e8-4263-44ae-a06c-814b693c071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421291230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1421291230
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.460189109
Short name T862
Test name
Test status
Simulation time 167651162 ps
CPU time 2.53 seconds
Started Jun 13 01:07:23 PM PDT 24
Finished Jun 13 01:07:26 PM PDT 24
Peak memory 208376 kb
Host smart-601ca7a0-9ead-45f6-8d1d-160f39c72aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460189109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.460189109
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1244525501
Short name T440
Test name
Test status
Simulation time 318448540 ps
CPU time 3.75 seconds
Started Jun 13 01:07:17 PM PDT 24
Finished Jun 13 01:07:21 PM PDT 24
Peak memory 206840 kb
Host smart-c27dc492-a256-4f1b-a638-d8154b965200
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244525501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1244525501
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2636933070
Short name T647
Test name
Test status
Simulation time 97340623 ps
CPU time 4.34 seconds
Started Jun 13 01:07:22 PM PDT 24
Finished Jun 13 01:07:27 PM PDT 24
Peak memory 206808 kb
Host smart-1071aef5-cb45-4b49-8a0a-6ee5a501cb78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636933070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2636933070
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.714538399
Short name T887
Test name
Test status
Simulation time 795592345 ps
CPU time 4.41 seconds
Started Jun 13 01:07:17 PM PDT 24
Finished Jun 13 01:07:22 PM PDT 24
Peak memory 208124 kb
Host smart-5e536a70-fb06-4d7d-aa7e-5f1fcfb3b39c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714538399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.714538399
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.593434999
Short name T852
Test name
Test status
Simulation time 43060870 ps
CPU time 1.76 seconds
Started Jun 13 01:07:18 PM PDT 24
Finished Jun 13 01:07:20 PM PDT 24
Peak memory 214292 kb
Host smart-a63ec6ce-be74-459d-9e5f-14406a7205a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593434999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.593434999
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1843454906
Short name T453
Test name
Test status
Simulation time 519960745 ps
CPU time 3.32 seconds
Started Jun 13 01:07:18 PM PDT 24
Finished Jun 13 01:07:22 PM PDT 24
Peak memory 206856 kb
Host smart-0a803b2c-c9df-4eb8-be16-9bb2d0f2cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843454906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1843454906
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1199904596
Short name T642
Test name
Test status
Simulation time 1361990952 ps
CPU time 11.52 seconds
Started Jun 13 01:07:19 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 207340 kb
Host smart-df2faab8-0535-4999-95fc-d23f55d13c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199904596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1199904596
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3110566525
Short name T571
Test name
Test status
Simulation time 110708123 ps
CPU time 2.05 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:29 PM PDT 24
Peak memory 209836 kb
Host smart-16b84f4e-2281-45ce-9e60-bd7358292d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110566525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3110566525
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3033725523
Short name T113
Test name
Test status
Simulation time 85366478 ps
CPU time 0.72 seconds
Started Jun 13 01:07:29 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 205892 kb
Host smart-e763847c-0d20-46d1-a22a-0d49b4d0051a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033725523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3033725523
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.530348519
Short name T61
Test name
Test status
Simulation time 84126609 ps
CPU time 2.06 seconds
Started Jun 13 01:07:27 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 207388 kb
Host smart-abd5f59e-56e1-4c04-a940-aa8273d0bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530348519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.530348519
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.740015962
Short name T22
Test name
Test status
Simulation time 264893636 ps
CPU time 3.34 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 209540 kb
Host smart-17370e70-d4a6-4141-b6b3-ce99cec5d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740015962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.740015962
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1953020969
Short name T843
Test name
Test status
Simulation time 518909978 ps
CPU time 2.99 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 222424 kb
Host smart-c82e1ca1-cac2-400e-a16a-ade5bbaac176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953020969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1953020969
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2293253247
Short name T517
Test name
Test status
Simulation time 99719441 ps
CPU time 2.22 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 206120 kb
Host smart-f92b7df3-0973-4798-937d-b3d1c1594c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293253247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2293253247
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.877335557
Short name T633
Test name
Test status
Simulation time 1115037905 ps
CPU time 7.75 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:36 PM PDT 24
Peak memory 209240 kb
Host smart-842610f8-e883-43db-9adc-6e873728e466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877335557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.877335557
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4252630296
Short name T824
Test name
Test status
Simulation time 72577288 ps
CPU time 2.61 seconds
Started Jun 13 01:07:25 PM PDT 24
Finished Jun 13 01:07:28 PM PDT 24
Peak memory 208644 kb
Host smart-812912e6-9d29-441e-a315-9b1070ac7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252630296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4252630296
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2466500765
Short name T145
Test name
Test status
Simulation time 469789406 ps
CPU time 3.14 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 208600 kb
Host smart-ed77c421-d664-4883-8dff-bfd6d31d0715
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466500765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2466500765
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3389089700
Short name T51
Test name
Test status
Simulation time 337951251 ps
CPU time 5.8 seconds
Started Jun 13 01:07:24 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 208680 kb
Host smart-3322e2a2-357c-459a-bf82-37ca579b76b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389089700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3389089700
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1410297783
Short name T844
Test name
Test status
Simulation time 269452156 ps
CPU time 2.93 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 206848 kb
Host smart-f7954a73-27dc-495c-b765-22ac6ab3a00d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410297783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1410297783
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4267198485
Short name T876
Test name
Test status
Simulation time 192665640 ps
CPU time 2.87 seconds
Started Jun 13 01:07:24 PM PDT 24
Finished Jun 13 01:07:28 PM PDT 24
Peak memory 210376 kb
Host smart-a8414810-7f02-4603-96e7-16c9c8d7f805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267198485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4267198485
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.803109539
Short name T543
Test name
Test status
Simulation time 1303061124 ps
CPU time 3.69 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:32 PM PDT 24
Peak memory 206644 kb
Host smart-f7a01dd7-b922-4e65-8a30-0bf9b95e98e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803109539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.803109539
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1332290773
Short name T206
Test name
Test status
Simulation time 22510793054 ps
CPU time 142.52 seconds
Started Jun 13 01:07:25 PM PDT 24
Finished Jun 13 01:09:48 PM PDT 24
Peak memory 217316 kb
Host smart-36d80950-91a4-4db4-b4e7-3e530edff5b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332290773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1332290773
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2101234335
Short name T88
Test name
Test status
Simulation time 755986447 ps
CPU time 10.83 seconds
Started Jun 13 01:07:27 PM PDT 24
Finished Jun 13 01:07:39 PM PDT 24
Peak memory 221748 kb
Host smart-3e87462b-1662-44e6-b09d-e843540a4110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101234335 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2101234335
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1960877062
Short name T293
Test name
Test status
Simulation time 1032515383 ps
CPU time 27.83 seconds
Started Jun 13 01:07:28 PM PDT 24
Finished Jun 13 01:07:57 PM PDT 24
Peak memory 218236 kb
Host smart-274c181d-3e63-40f8-8adb-687bb4900753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960877062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1960877062
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3916585077
Short name T467
Test name
Test status
Simulation time 277244811 ps
CPU time 1.85 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 209668 kb
Host smart-18253068-8e96-468b-a7dd-99afbb8e39cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916585077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3916585077
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1890100239
Short name T631
Test name
Test status
Simulation time 8498620 ps
CPU time 0.7 seconds
Started Jun 13 01:07:33 PM PDT 24
Finished Jun 13 01:07:35 PM PDT 24
Peak memory 205900 kb
Host smart-33264e6d-d5f0-491a-94a3-d8d24b1e4e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890100239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1890100239
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3853409584
Short name T258
Test name
Test status
Simulation time 281466792 ps
CPU time 4.47 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 215356 kb
Host smart-a9aed0b7-9799-4bd0-8aef-077c51426692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853409584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3853409584
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.662785761
Short name T56
Test name
Test status
Simulation time 91478102 ps
CPU time 1.54 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:34 PM PDT 24
Peak memory 209160 kb
Host smart-8c822d0e-62d6-4eb5-9911-93ee6430c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662785761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.662785761
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3489514553
Short name T311
Test name
Test status
Simulation time 115768838 ps
CPU time 2.36 seconds
Started Jun 13 01:07:38 PM PDT 24
Finished Jun 13 01:07:41 PM PDT 24
Peak memory 214336 kb
Host smart-16a2e665-45be-4bc0-afba-f711bbff61a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489514553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3489514553
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2825856976
Short name T334
Test name
Test status
Simulation time 195279267 ps
CPU time 3.58 seconds
Started Jun 13 01:07:33 PM PDT 24
Finished Jun 13 01:07:38 PM PDT 24
Peak memory 222356 kb
Host smart-4cbd5fd1-7286-4193-8cd7-e88e6e9daab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825856976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2825856976
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2574499994
Short name T405
Test name
Test status
Simulation time 65086161 ps
CPU time 3.44 seconds
Started Jun 13 01:07:34 PM PDT 24
Finished Jun 13 01:07:38 PM PDT 24
Peak memory 209624 kb
Host smart-1cf8b335-42f7-4cba-99b2-ad0aa99bca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574499994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2574499994
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4206604600
Short name T376
Test name
Test status
Simulation time 7874306859 ps
CPU time 53.72 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:08:20 PM PDT 24
Peak memory 209452 kb
Host smart-93d01a20-b1fe-4d26-9d00-352560df635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206604600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4206604600
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1958041382
Short name T610
Test name
Test status
Simulation time 453688365 ps
CPU time 10.86 seconds
Started Jun 13 01:07:25 PM PDT 24
Finished Jun 13 01:07:36 PM PDT 24
Peak memory 207896 kb
Host smart-0e78ed48-789d-44f0-8daf-5443ad4932e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958041382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1958041382
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1347192515
Short name T888
Test name
Test status
Simulation time 40303549 ps
CPU time 2.67 seconds
Started Jun 13 01:07:28 PM PDT 24
Finished Jun 13 01:07:31 PM PDT 24
Peak memory 207360 kb
Host smart-347c8e80-0065-4dea-9a85-e9db7a25cd98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347192515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1347192515
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2723641012
Short name T667
Test name
Test status
Simulation time 109621829 ps
CPU time 2.84 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:29 PM PDT 24
Peak memory 208868 kb
Host smart-854f9b42-0370-4bdf-b507-c694efcbfce6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723641012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2723641012
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1797477018
Short name T96
Test name
Test status
Simulation time 177809703 ps
CPU time 4.05 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:32 PM PDT 24
Peak memory 208552 kb
Host smart-d3951677-fccf-4c1a-a7ff-904b38350f11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797477018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1797477018
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.228522559
Short name T493
Test name
Test status
Simulation time 2285812289 ps
CPU time 23.35 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:56 PM PDT 24
Peak memory 209856 kb
Host smart-701b1bc4-38e2-4a9c-b70b-8835c9224768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228522559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.228522559
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3893915359
Short name T869
Test name
Test status
Simulation time 183005634 ps
CPU time 2.29 seconds
Started Jun 13 01:07:26 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 206596 kb
Host smart-054ee5b9-3cbb-40a5-a704-ae04b0bfe8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893915359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3893915359
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1351275165
Short name T243
Test name
Test status
Simulation time 2478123103 ps
CPU time 43.33 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:08:19 PM PDT 24
Peak memory 222512 kb
Host smart-0034f2c2-30db-483f-ad7f-16344662aff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351275165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1351275165
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2671255748
Short name T73
Test name
Test status
Simulation time 153877940 ps
CPU time 9.03 seconds
Started Jun 13 01:07:37 PM PDT 24
Finished Jun 13 01:07:46 PM PDT 24
Peak memory 220580 kb
Host smart-c836ce21-31b6-4df3-843d-5d79a54559a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671255748 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2671255748
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4148078130
Short name T661
Test name
Test status
Simulation time 505104842 ps
CPU time 4.99 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:07:41 PM PDT 24
Peak memory 218388 kb
Host smart-212f7e41-dd08-44d5-8df5-2e85dde16f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148078130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4148078130
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1935163998
Short name T388
Test name
Test status
Simulation time 203603751 ps
CPU time 2.26 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:34 PM PDT 24
Peak memory 210120 kb
Host smart-270ef495-7a69-49ac-93f3-7028c30fffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935163998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1935163998
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.4138984728
Short name T600
Test name
Test status
Simulation time 41781993 ps
CPU time 0.82 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:07:37 PM PDT 24
Peak memory 205872 kb
Host smart-52c11ea0-c90f-4a19-a71a-b55aae9a5792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138984728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.4138984728
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.281722759
Short name T327
Test name
Test status
Simulation time 132513251 ps
CPU time 7.86 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:41 PM PDT 24
Peak memory 214296 kb
Host smart-fb222f22-d12a-4ce2-8ccb-4d5bb73fb595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281722759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.281722759
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.478677632
Short name T415
Test name
Test status
Simulation time 105173224 ps
CPU time 2.84 seconds
Started Jun 13 01:07:34 PM PDT 24
Finished Jun 13 01:07:38 PM PDT 24
Peak memory 214288 kb
Host smart-dfbf46e9-0773-4b85-ae95-a26f6800fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478677632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.478677632
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3330027678
Short name T99
Test name
Test status
Simulation time 1205769834 ps
CPU time 14.88 seconds
Started Jun 13 01:07:33 PM PDT 24
Finished Jun 13 01:07:49 PM PDT 24
Peak memory 214172 kb
Host smart-c4629050-d456-4aea-b3a4-c15b047cc9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330027678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3330027678
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3012697862
Short name T823
Test name
Test status
Simulation time 86607190 ps
CPU time 2.28 seconds
Started Jun 13 01:07:31 PM PDT 24
Finished Jun 13 01:07:33 PM PDT 24
Peak memory 214272 kb
Host smart-f85e03cd-d8a5-4d8a-bdc4-10d79b5ed58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012697862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3012697862
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2426459693
Short name T7
Test name
Test status
Simulation time 228583555 ps
CPU time 3.7 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:36 PM PDT 24
Peak memory 219452 kb
Host smart-adb9e76c-30b6-4361-964e-79b6f822062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426459693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2426459693
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3832719116
Short name T266
Test name
Test status
Simulation time 132526435 ps
CPU time 4.06 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:07:40 PM PDT 24
Peak memory 207272 kb
Host smart-abf8c2da-b296-4bdb-b4bb-89718ba6a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832719116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3832719116
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2563281961
Short name T636
Test name
Test status
Simulation time 1005876552 ps
CPU time 6.94 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:07:43 PM PDT 24
Peak memory 208080 kb
Host smart-d599c660-0bca-4d52-a32d-0c078f8177c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563281961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2563281961
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2319354905
Short name T151
Test name
Test status
Simulation time 80350211 ps
CPU time 3.94 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:37 PM PDT 24
Peak memory 208920 kb
Host smart-bd0472e7-4102-44fa-8aae-d3b110151798
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319354905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2319354905
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2731591964
Short name T726
Test name
Test status
Simulation time 263708969 ps
CPU time 3.47 seconds
Started Jun 13 01:07:32 PM PDT 24
Finished Jun 13 01:07:36 PM PDT 24
Peak memory 208372 kb
Host smart-ecb28557-5df9-4448-b085-5516fa36eacb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731591964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2731591964
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.4129211566
Short name T789
Test name
Test status
Simulation time 528753872 ps
CPU time 4.51 seconds
Started Jun 13 01:07:33 PM PDT 24
Finished Jun 13 01:07:38 PM PDT 24
Peak memory 208848 kb
Host smart-8ef104e8-934f-4b5b-bc1a-3c791822391a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129211566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.4129211566
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.635719341
Short name T223
Test name
Test status
Simulation time 127735446 ps
CPU time 4.03 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:07:39 PM PDT 24
Peak memory 214340 kb
Host smart-655f5679-b29b-4169-b5d1-e5da37b6b7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635719341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.635719341
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2181811383
Short name T792
Test name
Test status
Simulation time 105048753 ps
CPU time 2.89 seconds
Started Jun 13 01:07:35 PM PDT 24
Finished Jun 13 01:07:38 PM PDT 24
Peak memory 208252 kb
Host smart-65453b2a-c5d5-468f-aa3d-04af143e7b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181811383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2181811383
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.495841707
Short name T494
Test name
Test status
Simulation time 66066416 ps
CPU time 2.72 seconds
Started Jun 13 01:07:36 PM PDT 24
Finished Jun 13 01:07:39 PM PDT 24
Peak memory 207688 kb
Host smart-1460a788-764f-4897-bcc0-01ec2da30ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495841707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.495841707
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3250394703
Short name T70
Test name
Test status
Simulation time 64087991 ps
CPU time 2.79 seconds
Started Jun 13 01:07:31 PM PDT 24
Finished Jun 13 01:07:34 PM PDT 24
Peak memory 209892 kb
Host smart-fdacaefa-b98d-43d8-8019-a911c2785dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250394703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3250394703
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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