SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
75.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 2 | 6 | 75.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 2 | 6 | 75.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 2 | 6 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OtpRootKeyValidLow] | 0 | 1 | 1 | |
auto[FlashOwnerSeedInvalid] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 2 | 1 | T127 | 1 | T236 | 1 | - | - | ||||
auto[LcStateInvalid] | 96 | 1 | T24 | 36 | T96 | 12 | T95 | 24 | ||||
auto[OtpDevIdInvalid] | 60 | 1 | T87 | 12 | T88 | 12 | T237 | 24 | ||||
auto[RomDigestInvalid] | 132 | 1 | T238 | 12 | T239 | 48 | T237 | 12 | ||||
auto[RomDigestValidLow] | 132 | 1 | T24 | 12 | T238 | 24 | T239 | 24 | ||||
auto[FlashCreatorSeedInvalid] | 120 | 1 | T88 | 12 | T91 | 48 | T92 | 36 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |