Group : keymgr_env_pkg::keymgr_env_cov::key_version_compare_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : keymgr_env_pkg::keymgr_env_cov::key_version_compare_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv



Summary for Group keymgr_env_pkg::keymgr_env_cov::key_version_compare_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 18 0 18 100.00


Variables for Group keymgr_env_pkg::keymgr_env_cov::key_version_compare_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
key_version_cmp_cp 3 0 3 100.00 100 1 1 0
op_cp 2 0 2 100.00 100 1 1 0
state_cp 3 0 3 100.00 100 1 1 0


Crosses for Group keymgr_env_pkg::keymgr_env_cov::key_version_compare_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_ver_x_state_x_op_cross 18 0 18 100.00 100 1 1 0


Summary for Variable key_version_cmp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for key_version_cmp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
legal_values[CompareOpEq] 14194 1 T1 2 T2 10 T5 13
legal_values[CompareOpGt] 2619 1 T1 1 T3 1 T4 17
legal_values[CompareOpLt] 4400 1 T1 10 T2 7 T5 2



Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for op_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
legal_states[OpGenSwOut] 4597 1 T1 4 T2 2 T5 5
legal_states[OpGenHwOut] 5138 1 T1 3 T2 8 T4 19



Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for state_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
legal_states[StCreatorRootKey] 3275 1 T1 6 T2 5 T5 2
legal_states[StOwnerIntKey] 2899 1 T1 4 T2 3 T5 2
legal_states[StOwnerKey] 2647 1 T1 1 T2 4 T5 2



Summary for Cross key_ver_x_state_x_op_cross

Samples crossed: key_version_cmp_cp state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 18 0 18 100.00


Automatically Generated Cross Bins for key_ver_x_state_x_op_cross

Bins
key_version_cmp_cpstate_cpop_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
legal_values[CompareOpEq] legal_states[StCreatorRootKey] legal_states[OpGenSwOut] 364 1 T4 1 T16 1 T17 1
legal_values[CompareOpEq] legal_states[StCreatorRootKey] legal_states[OpGenHwOut] 421 1 T2 2 T4 1 T15 1
legal_values[CompareOpEq] legal_states[StOwnerIntKey] legal_states[OpGenSwOut] 45 1 T18 1 T216 1 T61 2
legal_values[CompareOpEq] legal_states[StOwnerIntKey] legal_states[OpGenHwOut] 42 1 T4 1 T18 1 T61 2
legal_values[CompareOpEq] legal_states[StOwnerKey] legal_states[OpGenSwOut] 297 1 T5 1 T4 4 T14 1
legal_values[CompareOpEq] legal_states[StOwnerKey] legal_states[OpGenHwOut] 366 1 T15 1 T67 1 T81 1
legal_values[CompareOpGt] legal_states[StCreatorRootKey] legal_states[OpGenSwOut] 35 1 T16 2 T6 1 T61 2
legal_values[CompareOpGt] legal_states[StCreatorRootKey] legal_states[OpGenHwOut] 40 1 T26 2 T47 1 T6 1
legal_values[CompareOpGt] legal_states[StOwnerIntKey] legal_states[OpGenSwOut] 43 1 T4 1 T26 1 T47 1
legal_values[CompareOpGt] legal_states[StOwnerIntKey] legal_states[OpGenHwOut] 38 1 T26 1 T47 1 T48 2
legal_values[CompareOpGt] legal_states[StOwnerKey] legal_states[OpGenSwOut] 45 1 T47 1 T48 1 T6 1
legal_values[CompareOpGt] legal_states[StOwnerKey] legal_states[OpGenHwOut] 42 1 T4 1 T16 2 T136 2
legal_values[CompareOpLt] legal_states[StCreatorRootKey] legal_states[OpGenSwOut] 298 1 T1 2 T4 4 T26 2
legal_values[CompareOpLt] legal_states[StCreatorRootKey] legal_states[OpGenHwOut] 306 1 T1 2 T4 2 T16 3
legal_values[CompareOpLt] legal_states[StOwnerIntKey] legal_states[OpGenSwOut] 545 1 T1 2 T5 1 T4 3
legal_values[CompareOpLt] legal_states[StOwnerIntKey] legal_states[OpGenHwOut] 608 1 T2 2 T4 2 T15 1
legal_values[CompareOpLt] legal_states[StOwnerKey] legal_states[OpGenSwOut] 207 1 T2 1 T16 1 T228 1
legal_values[CompareOpLt] legal_states[StOwnerKey] legal_states[OpGenHwOut] 232 1 T2 3 T16 4 T26 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%