Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	40	1			T4	1		T39	1		T8	1
auto[OpGenId]	26	1			T16	1		T27	1		T34	1
auto[OpGenSwOut]	22	1			T20	1		T48	1		T6	1
auto[OpGenHwOut]	28	1			T4	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1660	1			T4	1		T101	3		T34	1
auto[StInit]	101	1			T16	1		T31	1		T39	1
auto[StCreatorRootKey]	59	1			T33	1		T19	1		T50	1
auto[StOwnerIntKey]	45	1			T4	2		T101	1		T20	1
auto[StOwnerKey]	40	1			T1	1		T101	2		T56	1
auto[StDisabled]	508	1			T4	5		T16	9		T101	3
auto[StInvalid]	49	1			T3	1		T32	1		T100	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3433

1

T1

2

T2

1

T3

2

auto[1]

116

1

T4

2

T16

1

T39

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1649	1			T4	1		T101	3		T47	4
auto[StReset]	auto[1]	11	1			T34	1		T105	1		T21	1
auto[StInit]	auto[0]	50	1			T31	1		T115	1		T101	1
auto[StInit]	auto[1]	51	1			T16	1		T39	1		T8	1
auto[StCreatorRootKey]	auto[0]	36	1			T33	1		T50	1		T51	1
auto[StCreatorRootKey]	auto[1]	23	1			T19	1		T49	1		T35	1
auto[StOwnerIntKey]	auto[0]	29	1			T101	1		T47	1		T53	1
auto[StOwnerIntKey]	auto[1]	16	1			T4	2		T20	1		T48	2
auto[StOwnerKey]	auto[0]	30	1			T1	1		T101	2		T56	1
auto[StOwnerKey]	auto[1]	10	1			T58	1		T240	1		T241	1
auto[StDisabled]	auto[0]	503	1			T4	5		T16	9		T101	3
auto[StDisabled]	auto[1]	5	1			T117	1		T74	1		T242	1
auto[StInvalid]	auto[0]	49	1			T3	1		T32	1		T100	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[StDisabled]]	[auto[OpGenSwOut]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	9	1			T105	1		T21	1		T44	1
auto[StReset]	auto[OpGenId]	1	1			T34	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T243	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	17	1			T39	1		T8	1		T7	2
auto[StInit]	auto[OpGenId]	10	1			T16	1		T27	1		T144	1
auto[StInit]	auto[OpGenSwOut]	9	1			T6	1		T244	1		T245	1
auto[StInit]	auto[OpGenHwOut]	15	1			T6	1		T7	1		T36	1
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T19	1		T116	1		T246	1
auto[StCreatorRootKey]	auto[OpGenId]	8	1			T247	1		T128	1		T211	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T49	1		T248	1		T44	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T35	1		T249	1		T211	1
auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T4	1		T250	1		T251	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T48	1		T252	1		T251	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T20	1		T48	1		T49	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	4	1			T4	1		T253	1		T254	1
auto[StOwnerKey]	auto[OpAdvance]	4	1			T255	1		T256	1		T212	1
auto[StOwnerKey]	auto[OpGenId]	3	1			T240	1		T257	1		T251	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T258	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T58	1		T241	1		-	-
auto[StDisabled]	auto[OpAdvance]	1	1			T117	1		-	-		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T74	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T242	1		T10	1		T259	1