Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4864

1

T1

1

T2

1

T3

5

auto[1]

589

1

T2

1

T4

2

T15

5

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4864

1

T1

1

T2

1

T3

5

auto[1]

589

1

T2

1

T4

2

T15

5

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4866

1

T1

1

T2

1

T3

5

auto[1]

587

1

T2

1

T4

1

T16

6

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4866

1

T1

1

T2

1

T3

5

auto[1]

587

1

T2

1

T4

1

T16

6

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	399	1			T3	2		T4	4		T16	6
auto[OpGenId]	1176	1			T2	1		T3	1		T4	7
auto[OpGenSwOut]	1213	1			T3	1		T4	7		T16	8
auto[OpGenHwOut]	2590	1			T1	1		T2	1		T3	1
auto[OpDisable]	75	1			T16	1		T41	1		T48	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	399	1			T3	2		T4	4		T16	6
auto[OpGenId]	1176	1			T2	1		T3	1		T4	7
auto[OpGenSwOut]	1213	1			T3	1		T4	7		T16	8
auto[OpGenHwOut]	2590	1			T1	1		T2	1		T3	1
auto[OpDisable]	75	1			T16	1		T41	1		T48	2

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4828

1

T1

1

T2

2

T3

5

auto[1]

625

1

T4

2

T16

3

T18

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4828

1

T1

1

T2

2

T3

5

auto[1]

625

1

T4

2

T16

3

T18

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5137

1

T1

1

T2

2

T3

5

auto[1]

316

1

T18

3

T123

1

T153

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1907	1			T1	1		T2	1		T3	3
auto[1]	736	1			T3	1		T4	3		T15	1
auto[2]	693	1			T2	1		T4	6		T16	2
auto[3]	684	1			T4	1		T15	3		T16	9
auto[4]	394	1			T4	1		T15	1		T67	1
auto[5]	345	1			T4	3		T15	1		T16	1
auto[6]	333	1			T4	2		T16	1		T139	1
auto[7]	361	1			T3	1		T4	2		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1433	1			T3	1		T4	8		T15	3
clear_one[1]	736	1			T3	1		T4	3		T15	1
clear_one[2]	693	1			T2	1		T4	6		T16	2
clear_one[3]	684	1			T4	1		T15	3		T16	9
clear_none	1907	1			T1	1		T2	1		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1012	1			T4	9		T15	2		T16	5
auto[StInit]	687	1			T1	1		T3	1		T4	5
auto[StCreatorRootKey]	583	1			T2	1		T4	3		T15	1
auto[StOwnerIntKey]	495	1			T2	1		T4	2		T15	1
auto[StOwnerKey]	505	1			T4	1		T15	1		T16	3
auto[StDisabled]	1887	1			T4	6		T15	4		T16	13
auto[StInvalid]	284	1			T3	4		T32	1		T100	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1012	1			T4	9		T15	2		T16	5
auto[StInit]	687	1			T1	1		T3	1		T4	5
auto[StCreatorRootKey]	583	1			T2	1		T4	3		T15	1
auto[StOwnerIntKey]	495	1			T2	1		T4	2		T15	1
auto[StOwnerKey]	505	1			T4	1		T15	1		T16	3
auto[StDisabled]	1887	1			T4	6		T15	4		T16	13
auto[StInvalid]	284	1			T3	4		T32	1		T100	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T18	1		T260	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	156	1			T4	1		T24	1		T52	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	170	1			T4	2		T8	1		T226	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	275	1			T4	1		T15	1		T16	3
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T3	1		T4	2		T39	1
auto[0]	auto[StInit]	auto[OpGenId]	101	1			T16	2		T41	1		T101	3
auto[0]	auto[StInit]	auto[OpGenSwOut]	107	1			T17	1		T143	1		T101	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	179	1			T1	1		T67	1		T81	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T47	1		T214	1		T7	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	57	1			T2	1		T82	1		T48	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	50	1			T141	1		T40	1		T48	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	76	1			T15	1		T26	1		T231	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T58	1		T261	1		T262	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	34	1			T47	2		T263	1		T264	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T18	2		T52	1		T48	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T18	1		T233	1		T265	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T16	1		T58	1		T266	2
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T49	1		T59	1		T62	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	30	1			T227	1		T48	1		T61	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	57	1			T140	1		T265	1		T214	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T16	1		T47	1		T59	1
auto[0]	auto[StDisabled]	auto[OpGenId]	53	1			T4	1		T48	3		T214	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T82	1		T226	1		T202	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	175	1			T4	1		T15	1		T67	1
auto[0]	auto[StDisabled]	auto[OpDisable]	19	1			T63	1		T62	1		T267	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	17	1			T3	1		T32	1		T42	1
auto[0]	auto[StInvalid]	auto[OpGenId]	16	1			T42	1		T215	1		T268	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	29	1			T215	1		T269	1		T86	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	25	1			T3	1		T100	1		T43	1
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T59	1		T62	1		T116	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T85	1		T270	1		T271	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	48	1			T140	1		T272	1		T47	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T7	1		T266	1		T273	1
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T4	1		T24	1		T59	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	16	1			T25	1		T58	1		T104	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	25	1			T140	1		T233	1		T272	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T166	1		T167	1		T72	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T143	1		T6	1		T234	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T4	1		T6	1		T59	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T140	1		T136	1		T48	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T7	1		T274	1		T275	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T82	1		T276	1		T261	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T16	1		T47	1		T275	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T137	1		T203	1		T7	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T277	1		T274	1		T278	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T216	1		T130	1		T279	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T47	1		T280	1		T281	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T139	1		T272	1		T47	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	24	1			T26	1		T6	1		T153	1
auto[1]	auto[StDisabled]	auto[OpGenId]	46	1			T4	1		T55	1		T47	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	72	1			T16	3		T101	1		T52	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T15	1		T67	1		T140	1
auto[1]	auto[StDisabled]	auto[OpDisable]	11	1			T229	1		T63	1		T64	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T269	1		T282	1		T283	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T3	1		T42	2		T284	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T285	1		T286	1		T287	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T83	1		T215	1		T288	2
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T289	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	16	1			T4	1		T83	1		T58	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	9	1			T116	1		T290	1		T133	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	36	1			T272	1		T42	1		T25	1
auto[2]	auto[StInit]	auto[OpAdvance]	12	1			T186	1		T291	1		T292	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T6	1		T270	1		T293	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T59	1		T62	1		T116	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T218	1		T203	1		T61	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T4	1		T294	2		T295	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T52	1		T274	1		T130	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T135	1		T47	1		T61	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T233	1		T296	1		T297	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T7	1		T266	1		T298	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T47	1		T210	1		T281	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T59	1		T299	1		T294	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	59	1			T2	1		T4	1		T67	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T16	1		T281	2		T116	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T6	1		T59	1		T62	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T6	1		T63	1		T75	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T67	1		T81	1		T137	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	19	1			T16	1		T6	1		T84	1
auto[2]	auto[StDisabled]	auto[OpGenId]	55	1			T82	1		T136	1		T47	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T4	1		T26	1		T141	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T4	2		T18	1		T67	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T48	1		T61	1		T65	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T43	1		T268	1		T300	1
auto[2]	auto[StInvalid]	auto[OpGenId]	8	1			T100	1		T86	1		T103	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T301	1		T103	1		T284	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T215	1		T284	1		T290	1
auto[3]	auto[StReset]	auto[OpGenId]	31	1			T4	1		T52	1		T47	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	18	1			T6	1		T59	2		T116	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	37	1			T8	1		T19	1		T153	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T25	1		T302	2		T303	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T61	1		T304	1		T95	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T16	1		T49	1		T70	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T48	1		T6	1		T59	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T62	1		T305	1		T306	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T84	1		T59	1		T116	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T216	1		T62	1		T307	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T67	1		T272	1		T28	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T16	1		T308	1		T309	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T16	1		T226	1		T63	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T101	1		T6	1		T202	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T143	1		T232	1		T310	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T294	1		T311	1		T312	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T210	1		T61	1		T7	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T130	1		T313	1		T72	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T15	1		T16	1		T232	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	15	1			T228	1		T6	2		T7	1
auto[3]	auto[StDisabled]	auto[OpGenId]	53	1			T16	1		T18	1		T48	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T16	1		T231	1		T47	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T15	2		T16	2		T139	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T16	1		T41	1		T6	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T85	1		T314	1		T315	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T273	1		T316	1		T317	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T318	1		T301	1		T319	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T42	1		T57	2		T320	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T52	1		T62	1		T248	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	14	1			T226	1		T6	2		T59	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T139	2		T49	1		T63	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T28	1		T261	1		T309	1
auto[4]	auto[StInit]	auto[OpGenId]	9	1			T6	1		T63	1		T96	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T321	1		T322	1		T323	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T15	1		T139	1		T59	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T226	1		T61	1		T62	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T45	1		T324	1		T74	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	30	1			T81	1		T101	1		T207	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T257	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T62	1		T116	1		T325	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T228	1		T216	1		T59	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T81	1		T139	1		T206	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T326	1		T309	1		T327	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	14	1			T6	2		T59	2		T104	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T4	1		T48	1		T167	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T233	1		T48	1		T199	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	23	1			T123	1		T61	1		T49	2
auto[4]	auto[StDisabled]	auto[OpGenId]	35	1			T47	1		T48	1		T61	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	19	1			T214	1		T202	1		T49	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T67	1		T81	2		T140	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T210	1		T62	1		T223	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	6	1			T83	1		T301	1		T315	1
auto[4]	auto[StInvalid]	auto[OpGenId]	8	1			T86	1		T318	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T328	1		T329	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T290	1		T285	1		T286	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T47	1		T330	1		T308	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T4	2		T116	1		T211	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T15	1		T331	1		T332	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T333	1		T88	1		T334	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T16	1		T24	1		T335	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T58	1		T64	1		T336	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T4	1		T24	1		T337	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T44	1		T338	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T202	1		T7	1		T281	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T281	1		T339	1		T246	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T137	1		T217	1		T199	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T214	1		T340	1		T341	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T47	1		T59	1		T167	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T63	1		T133	1		T71	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T342	1		T343	1		T44	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T7	1		T94	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T7	1		T127	1		T270	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T101	1		T44	1		T338	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T344	1		T345	1		T346	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	9	1			T6	1		T63	1		T261	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T231	1		T6	1		T234	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T213	1		T6	1		T84	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T140	1		T137	1		T47	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T48	1		T339	1		T133	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T103	1		T320	1		T268	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T43	1		T320	1		T271	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T83	1		T215	1		T301	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T273	1		T329	1		T347	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T48	1		T58	1		T28	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T6	3		T60	1		T313	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	10	1			T203	1		T273	1		T348	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T58	1		T349	1		T350	1
auto[6]	auto[StInit]	auto[OpGenId]	2	1			T351	1		T91	1		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T44	1		T211	1		T352	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	6	1			T353	1		T354	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T49	1		T236	1		T211	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T48	1		T277	1		T356	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T4	1		T16	1		T203	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T59	1		T357	1		T358	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T4	1		T40	1		T44	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T49	1		T59	1		T186	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	14	1			T61	1		T359	1		T332	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T6	1		T241	1		T357	2
auto[6]	auto[StOwnerKey]	auto[OpGenId]	11	1			T231	1		T48	1		T6	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T360	1		T361	1		T89	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T217	1		T362	1		T363	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T6	1		T61	1		T7	1
auto[6]	auto[StDisabled]	auto[OpGenId]	28	1			T227	1		T78	1		T62	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	39	1			T333	1		T280	1		T235	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T139	1		T232	1		T364	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T211	1		T365	1		T325	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T43	1		T366	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T282	1		T367	1		T368	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T369	1		T370	1		T371	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T301	1		T284	1		T319	1
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T101	1		T116	1		T277	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	15	1			T16	1		T47	1		T25	2
auto[7]	auto[StReset]	auto[OpGenHwOut]	32	1			T4	1		T16	1		T272	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T4	1		T19	1		T372	1
auto[7]	auto[StInit]	auto[OpGenId]	2	1			T63	1		T74	1		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T48	1		T62	1		T95	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T296	1		T362	1		T373	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T16	1		T73	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T16	1		T61	1		T59	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T7	1		T127	1		T187	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T16	1		T139	1		T232	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T261	1		T211	1		T374	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T60	1		T211	1		T352	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T218	1		T133	1		T375	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T15	1		T61	1		T376	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T377	2		T257	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	14	1			T82	1		T40	1		T218	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T63	1		T59	1		T130	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T109	1		T378	1		T379	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T58	1		T59	1		T294	1
auto[7]	auto[StDisabled]	auto[OpGenId]	40	1			T16	1		T143	1		T227	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T16	1		T48	1		T281	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T16	1		T139	1		T137	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T77	1		T304	1		T44	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T380	1		T381	1		T382	1
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T271	1		T383	1		T384	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T3	1		T57	1		T318	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T320	1		T385	1		T386	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1433

1

T3

1

T4

8

T15

3

clear_one[1]

auto[0]

auto[0]

auto[0]

406

1

T3

1

T4

3

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

142

1

T16

3

T101

1

T48

1

clear_one[1]

auto[0]

auto[1]

auto[0]

132

1

T16

1

T140

2

T136

1

clear_one[1]

auto[0]

auto[1]

auto[1]

56

1

T26

1

T55

1

T47

1

clear_one[2]

auto[0]

auto[0]

auto[0]

389

1

T4

4

T16

1

T81

2

clear_one[2]

auto[0]

auto[0]

auto[1]

126

1

T4

1

T18

1

T26

1

clear_one[2]

auto[1]

auto[0]

auto[0]

127

1

T2

1

T4

1

T16

1

clear_one[2]

auto[1]

auto[0]

auto[1]

51

1

T101

1

T136

1

T7

1

clear_one[3]

auto[0]

auto[0]

auto[0]

402

1

T4

1

T16

5

T8

1

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T16

1

T18

1

T231

1

clear_one[3]

auto[1]

auto[0]

auto[0]

119

1

T15

3

T16

1

T67

1

clear_one[3]

auto[1]

auto[1]

auto[0]

33

1

T16

2

T47

1

T61

1

clear_none

auto[0]

auto[0]

auto[0]

1353

1

T1

1

T3

3

T4

7

clear_none

auto[0]

auto[0]

auto[1]

131

1

T143

1

T233

1

T47

1

clear_none

auto[0]

auto[1]

auto[0]

122

1

T2

1

T16

2

T18

2

clear_none

auto[0]

auto[1]

auto[1]

42

1

T40

1

T231

1

T47

1

clear_none

auto[1]

auto[0]

auto[0]

136

1

T15

2

T67

1

T139

1

clear_none

auto[1]

auto[0]

auto[1]

51

1

T47

1

T61

2

T234

1

clear_none

auto[1]

auto[1]

auto[0]

46

1

T55

1

T52

1

T123

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T4

1

T47

1

T49

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1347	1			T3	1		T4	8		T15	3
clear_all	auto[1]	86	1			T153	1		T281	2		T274	2
clear_one[1]	auto[0]	688	1			T3	1		T4	3		T15	1
clear_one[1]	auto[1]	48	1			T281	1		T387	2		T266	1
clear_one[2]	auto[0]	642	1			T2	1		T4	6		T16	2
clear_one[2]	auto[1]	51	1			T281	9		T75	1		T266	3
clear_one[3]	auto[0]	658	1			T4	1		T15	3		T16	9
clear_one[3]	auto[1]	26	1			T75	3		T302	7		T311	2
clear_none	auto[0]	1802	1			T1	1		T2	1		T3	3
clear_none	auto[1]	105	1			T18	3		T123	1		T281	1