Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11232

1

T1

6

T2

8

T5

9

auto[Attestation]

8299

1

T1

5

T2

6

T5

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2871	1			T1	2		T2	2		T5	2
auto[Aes]	3569	1			T1	2		T2	3		T5	2
auto[Kmac]	3490	1			T1	4		T2	3		T5	1
auto[Otbn]	3384	1			T2	2		T5	3		T4	15

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8142	1			T1	4		T2	4		T3	2
auto[OpGenId]	6217	1			T1	3		T2	4		T5	5
auto[OpGenSwOut]	6282	1			T1	4		T2	2		T5	8
auto[OpGenHwOut]	7032	1			T1	4		T2	8		T4	26
auto[OpDisable]	145	1			T16	2		T40	1		T41	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11167

1

T1

13

T2

14

T3

1

auto[OpDoneFail]

16651

1

T1

2

T2

4

T3

1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6605	1			T1	2		T2	1		T3	1
auto[StInit]	3981	1			T1	2		T2	5		T3	1
auto[StCreatorRootKey]	3275	1			T1	6		T2	5		T5	2
auto[StOwnerIntKey]	2899	1			T1	4		T2	3		T5	2
auto[StOwnerKey]	2647	1			T1	1		T2	4		T5	2
auto[StDisabled]	8411	1			T5	7		T4	54		T14	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	328	1			T5	1		T4	1		T16	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T2	1		T4	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T1	1		T4	2		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T4	2		T16	3		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T4	1		T16	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	254	1			T4	1		T16	5		T226	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	339	1			T5	1		T4	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	134	1			T4	1		T16	1		T143	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T16	2		T17	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	79	1			T16	1		T52	1		T227	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	82	1			T4	1		T226	1		T101	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	218	1			T5	1		T4	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	317	1			T16	1		T18	1		T31	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T142	2		T115	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T142	1		T228	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T1	1		T47	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T14	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	216	1			T16	1		T82	1		T228	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	313	1			T5	1		T16	2		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T4	2		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T26	1		T228	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T16	2		T228	1		T229	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	74	1			T2	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	226	1			T4	3		T14	1		T16	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	103	1			T4	3		T16	3		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T4	1		T16	4		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T4	1		T26	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	93	1			T4	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T16	1		T101	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	256	1			T5	1		T4	2		T16	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	97	1			T4	8		T16	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T14	1		T16	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	88	1			T4	1		T16	1		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T1	1		T14	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	69	1			T4	1		T101	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	221	1			T16	5		T18	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	105	1			T4	7		T16	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	109	1			T16	2		T26	1		T231	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T1	1		T135	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T16	2		T55	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	68	1			T18	1		T136	1		T227	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	246	1			T5	1		T14	1		T16	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T4	2		T47	1		T6	8
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	101	1			T31	1		T8	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T4	1		T47	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T5	1		T4	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T4	1		T18	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	217	1			T4	2		T16	1		T141	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	260	1			T16	1		T18	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	109	1			T33	1		T50	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T1	1		T2	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	50	1			T4	2		T16	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T26	1		T143	1		T228	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	170	1			T4	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	498	1			T15	5		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	119	1			T15	1		T67	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	86	1			T4	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	107	1			T17	1		T26	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	79	1			T2	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	292	1			T4	1		T15	1		T16	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	399	1			T1	1		T4	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T2	1		T232	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T1	1		T2	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T16	2		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T81	1		T232	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	301	1			T4	1		T16	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	440	1			T4	1		T8	1		T228	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	125	1			T16	1		T40	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T16	1		T40	1		T228	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	88	1			T17	1		T233	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	79	1			T16	2		T231	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	279	1			T16	4		T18	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	87	1			T4	3		T47	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	112	1			T16	2		T18	1		T142	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T4	1		T18	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T6	4		T61	2		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T61	2		T7	2		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	204	1			T4	3		T16	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T16	3		T47	2		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	120	1			T1	1		T4	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	106	1			T4	1		T67	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	89	1			T2	1		T15	1		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	105	1			T2	1		T16	2		T67	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	276	1			T4	3		T15	3		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T16	2		T47	4		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T17	1		T81	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	117	1			T26	1		T40	1		T231	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T2	1		T16	1		T142	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	84	1			T4	1		T140	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	305	1			T4	1		T16	1		T81	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	57	1			T16	1		T48	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T228	1		T135	1		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T231	1		T101	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	105	1			T4	1		T17	2		T228	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	105	1			T2	1		T16	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	282	1			T4	1		T16	5		T18	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T1	1		T4	4		T16	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	697	1			T2	1		T5	1		T4	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	230	1			T4	1		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	710	1			T5	2		T4	5		T16	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	234	1			T1	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	659	1			T16	2		T18	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	213	1			T2	1		T5	1		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	649	1			T5	1		T4	5		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	205	1			T4	2		T16	2		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	479	1			T5	1		T4	6		T16	11
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	231	1			T1	1		T4	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	441	1			T4	8		T14	1		T16	8
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	225	1			T1	1		T16	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	480	1			T5	1		T4	7		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T5	1		T4	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	416	1			T4	4		T16	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	150	1			T1	1		T2	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	553	1			T4	1		T16	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	257	1			T2	1		T4	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	924	1			T4	1		T15	7		T16	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	269	1			T1	1		T2	1		T16	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	827	1			T1	1		T2	1		T4	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T16	2		T17	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	857	1			T4	1		T16	6		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	163	1			T4	1		T18	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	420	1			T4	6		T16	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	287	1			T2	2		T4	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	489	1			T1	1		T4	4		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T2	1		T16	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	519	1			T4	2		T16	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	302	1			T2	1		T4	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	471	1			T4	1		T16	6		T18	1