Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33918

1

T1

17

T2

19

T3

25

auto[1]

333

1

T18

4

T123

2

T153

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33926	1			T1	17		T2	19		T3	25
auto[134217728:268435455]	13	1			T281	1		T198	1		T220	1
auto[268435456:402653183]	13	1			T266	1		T274	1		T311	1
auto[402653184:536870911]	10	1			T153	1		T198	1		T294	1
auto[536870912:671088639]	10	1			T18	1		T281	1		T294	2
auto[671088640:805306367]	14	1			T75	1		T220	1		T392	1
auto[805306368:939524095]	22	1			T281	1		T387	1		T274	1
auto[939524096:1073741823]	11	1			T281	2		T299	1		T294	1
auto[1073741824:1207959551]	13	1			T18	1		T123	1		T377	1
auto[1207959552:1342177279]	6	1			T377	1		T392	1		T308	1
auto[1342177280:1476395007]	9	1			T387	1		T198	1		T289	1
auto[1476395008:1610612735]	12	1			T75	1		T275	1		T299	1
auto[1610612736:1744830463]	8	1			T18	1		T123	1		T294	1
auto[1744830464:1879048191]	10	1			T18	1		T281	1		T220	1
auto[1879048192:2013265919]	14	1			T387	2		T198	1		T299	1
auto[2013265920:2147483647]	15	1			T387	1		T294	1		T399	2
auto[2147483648:2281701375]	14	1			T299	2		T294	1		T220	1
auto[2281701376:2415919103]	7	1			T281	1		T275	1		T400	1
auto[2415919104:2550136831]	12	1			T274	1		T220	1		T377	1
auto[2550136832:2684354559]	8	1			T275	1		T299	1		T294	1
auto[2684354560:2818572287]	11	1			T387	1		T275	1		T294	1
auto[2818572288:2952790015]	7	1			T75	1		T289	1		T401	1
auto[2952790016:3087007743]	5	1			T274	1		T220	1		T402	1
auto[3087007744:3221225471]	9	1			T266	1		T299	1		T393	1
auto[3221225472:3355443199]	6	1			T387	1		T275	1		T403	1
auto[3355443200:3489660927]	11	1			T399	1		T326	3		T400	2
auto[3489660928:3623878655]	18	1			T266	2		T299	1		T220	1
auto[3623878656:3758096383]	7	1			T281	1		T392	2		T311	2
auto[3758096384:3892314111]	6	1			T75	1		T275	1		T393	1
auto[3892314112:4026531839]	8	1			T75	1		T275	1		T377	1
auto[4026531840:4160749567]	10	1			T274	1		T294	1		T393	1
auto[4160749568:4294967295]	6	1			T75	1		T294	1		T302	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33918	1			T1	17		T2	19		T3	25
auto[0:134217727]	auto[1]	8	1			T153	1		T299	1		T399	2
auto[134217728:268435455]	auto[1]	13	1			T281	1		T198	1		T220	1
auto[268435456:402653183]	auto[1]	13	1			T266	1		T274	1		T311	1
auto[402653184:536870911]	auto[1]	10	1			T153	1		T198	1		T294	1
auto[536870912:671088639]	auto[1]	10	1			T18	1		T281	1		T294	2
auto[671088640:805306367]	auto[1]	14	1			T75	1		T220	1		T392	1
auto[805306368:939524095]	auto[1]	22	1			T281	1		T387	1		T274	1
auto[939524096:1073741823]	auto[1]	11	1			T281	2		T299	1		T294	1
auto[1073741824:1207959551]	auto[1]	13	1			T18	1		T123	1		T377	1
auto[1207959552:1342177279]	auto[1]	6	1			T377	1		T392	1		T308	1
auto[1342177280:1476395007]	auto[1]	9	1			T387	1		T198	1		T289	1
auto[1476395008:1610612735]	auto[1]	12	1			T75	1		T275	1		T299	1
auto[1610612736:1744830463]	auto[1]	8	1			T18	1		T123	1		T294	1
auto[1744830464:1879048191]	auto[1]	10	1			T18	1		T281	1		T220	1
auto[1879048192:2013265919]	auto[1]	14	1			T387	2		T198	1		T299	1
auto[2013265920:2147483647]	auto[1]	15	1			T387	1		T294	1		T399	2
auto[2147483648:2281701375]	auto[1]	14	1			T299	2		T294	1		T220	1
auto[2281701376:2415919103]	auto[1]	7	1			T281	1		T275	1		T400	1
auto[2415919104:2550136831]	auto[1]	12	1			T274	1		T220	1		T377	1
auto[2550136832:2684354559]	auto[1]	8	1			T275	1		T299	1		T294	1
auto[2684354560:2818572287]	auto[1]	11	1			T387	1		T275	1		T294	1
auto[2818572288:2952790015]	auto[1]	7	1			T75	1		T289	1		T401	1
auto[2952790016:3087007743]	auto[1]	5	1			T274	1		T220	1		T402	1
auto[3087007744:3221225471]	auto[1]	9	1			T266	1		T299	1		T393	1
auto[3221225472:3355443199]	auto[1]	6	1			T387	1		T275	1		T403	1
auto[3355443200:3489660927]	auto[1]	11	1			T399	1		T326	3		T400	2
auto[3489660928:3623878655]	auto[1]	18	1			T266	2		T299	1		T220	1
auto[3623878656:3758096383]	auto[1]	7	1			T281	1		T392	2		T311	2
auto[3758096384:3892314111]	auto[1]	6	1			T75	1		T275	1		T393	1
auto[3892314112:4026531839]	auto[1]	8	1			T75	1		T275	1		T377	1
auto[4026531840:4160749567]	auto[1]	10	1			T274	1		T294	1		T393	1
auto[4160749568:4294967295]	auto[1]	6	1			T75	1		T294	1		T302	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1624

1

T1

2

T2

1

T3

4

auto[1]

1819

1

T1

2

T4

15

T16

23

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T3	1		T4	1		T142	1
auto[134217728:268435455]	101	1			T4	1		T16	1		T228	1
auto[268435456:402653183]	101	1			T2	1		T4	1		T16	2
auto[402653184:536870911]	111	1			T3	1		T16	1		T39	2
auto[536870912:671088639]	99	1			T4	1		T228	1		T41	1
auto[671088640:805306367]	112	1			T4	1		T16	1		T18	1
auto[805306368:939524095]	103	1			T1	1		T4	1		T27	1
auto[939524096:1073741823]	103	1			T4	1		T16	1		T100	1
auto[1073741824:1207959551]	108	1			T4	1		T16	2		T32	2
auto[1207959552:1342177279]	103	1			T18	1		T39	1		T24	2
auto[1342177280:1476395007]	106	1			T4	2		T16	2		T18	1
auto[1476395008:1610612735]	111	1			T3	1		T4	2		T16	2
auto[1610612736:1744830463]	125	1			T1	1		T16	3		T100	1
auto[1744830464:1879048191]	112	1			T4	1		T6	2		T333	1
auto[1879048192:2013265919]	124	1			T4	2		T16	1		T18	1
auto[2013265920:2147483647]	93	1			T4	2		T16	2		T231	1
auto[2147483648:2281701375]	98	1			T16	2		T228	1		T231	1
auto[2281701376:2415919103]	102	1			T42	1		T24	1		T83	1
auto[2415919104:2550136831]	123	1			T16	3		T32	1		T228	1
auto[2550136832:2684354559]	107	1			T4	1		T40	1		T20	1
auto[2684354560:2818572287]	105	1			T4	1		T18	1		T20	1
auto[2818572288:2952790015]	114	1			T1	1		T3	1		T4	1
auto[2952790016:3087007743]	112	1			T4	1		T16	2		T41	1
auto[3087007744:3221225471]	87	1			T4	1		T24	1		T136	1
auto[3221225472:3355443199]	112	1			T16	1		T41	1		T101	1
auto[3355443200:3489660927]	108	1			T32	1		T228	1		T19	1
auto[3489660928:3623878655]	109	1			T16	1		T19	1		T43	1
auto[3623878656:3758096383]	98	1			T4	1		T16	2		T18	1
auto[3758096384:3892314111]	113	1			T16	1		T26	1		T8	1
auto[3892314112:4026531839]	122	1			T16	3		T32	1		T40	1
auto[4026531840:4160749567]	101	1			T16	2		T231	1		T101	2
auto[4160749568:4294967295]	108	1			T1	1		T4	1		T43	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T3	1		T4	1		T58	2
auto[0:134217727]	auto[1]	62	1			T142	1		T6	3		T61	1
auto[134217728:268435455]	auto[0]	50	1			T228	1		T135	1		T48	1
auto[134217728:268435455]	auto[1]	51	1			T4	1		T16	1		T101	1
auto[268435456:402653183]	auto[0]	51	1			T2	1		T47	1		T6	1
auto[268435456:402653183]	auto[1]	50	1			T4	1		T16	2		T52	1
auto[402653184:536870911]	auto[0]	54	1			T3	1		T16	1		T39	2
auto[402653184:536870911]	auto[1]	57	1			T142	1		T47	1		T49	2
auto[536870912:671088639]	auto[0]	48	1			T100	1		T34	1		T47	1
auto[536870912:671088639]	auto[1]	51	1			T4	1		T228	1		T41	1
auto[671088640:805306367]	auto[0]	54	1			T16	1		T101	2		T55	1
auto[671088640:805306367]	auto[1]	58	1			T4	1		T18	1		T229	1
auto[805306368:939524095]	auto[0]	47	1			T1	1		T27	1		T48	1
auto[805306368:939524095]	auto[1]	56	1			T4	1		T43	1		T48	1
auto[939524096:1073741823]	auto[0]	47	1			T100	1		T48	1		T61	2
auto[939524096:1073741823]	auto[1]	56	1			T4	1		T16	1		T24	1
auto[1073741824:1207959551]	auto[0]	56	1			T16	1		T32	2		T24	1
auto[1073741824:1207959551]	auto[1]	52	1			T4	1		T16	1		T27	1
auto[1207959552:1342177279]	auto[0]	46	1			T39	1		T24	2		T215	1
auto[1207959552:1342177279]	auto[1]	57	1			T18	1		T6	1		T404	1
auto[1342177280:1476395007]	auto[0]	50	1			T4	1		T16	1		T101	1
auto[1342177280:1476395007]	auto[1]	56	1			T4	1		T16	1		T18	1
auto[1476395008:1610612735]	auto[0]	44	1			T3	1		T4	1		T16	2
auto[1476395008:1610612735]	auto[1]	67	1			T4	1		T48	3		T61	2
auto[1610612736:1744830463]	auto[0]	65	1			T1	1		T16	1		T100	1
auto[1610612736:1744830463]	auto[1]	60	1			T16	2		T136	1		T47	1
auto[1744830464:1879048191]	auto[0]	55	1			T6	2		T7	3		T58	1
auto[1744830464:1879048191]	auto[1]	57	1			T4	1		T333	1		T49	1
auto[1879048192:2013265919]	auto[0]	63	1			T4	1		T39	1		T8	1
auto[1879048192:2013265919]	auto[1]	61	1			T4	1		T16	1		T18	1
auto[2013265920:2147483647]	auto[0]	38	1			T4	1		T16	1		T19	1
auto[2013265920:2147483647]	auto[1]	55	1			T4	1		T16	1		T231	1
auto[2147483648:2281701375]	auto[0]	46	1			T16	1		T228	1		T231	1
auto[2147483648:2281701375]	auto[1]	52	1			T16	1		T43	1		T48	1
auto[2281701376:2415919103]	auto[0]	53	1			T24	1		T83	1		T47	1
auto[2281701376:2415919103]	auto[1]	49	1			T42	1		T48	1		T209	1
auto[2415919104:2550136831]	auto[0]	57	1			T16	2		T32	1		T231	1
auto[2415919104:2550136831]	auto[1]	66	1			T16	1		T228	1		T48	1
auto[2550136832:2684354559]	auto[0]	48	1			T4	1		T47	1		T48	1
auto[2550136832:2684354559]	auto[1]	59	1			T40	1		T20	1		T214	1
auto[2684354560:2818572287]	auto[0]	51	1			T18	1		T47	1		T6	1
auto[2684354560:2818572287]	auto[1]	54	1			T4	1		T20	1		T48	1
auto[2818572288:2952790015]	auto[0]	46	1			T3	1		T142	1		T8	1
auto[2818572288:2952790015]	auto[1]	68	1			T1	1		T4	1		T16	2
auto[2952790016:3087007743]	auto[0]	64	1			T4	1		T16	1		T41	1
auto[2952790016:3087007743]	auto[1]	48	1			T16	1		T47	1		T123	1
auto[3087007744:3221225471]	auto[0]	35	1			T4	1		T24	1		T269	1
auto[3087007744:3221225471]	auto[1]	52	1			T136	1		T229	1		T244	1
auto[3221225472:3355443199]	auto[0]	56	1			T41	1		T55	1		T43	1
auto[3221225472:3355443199]	auto[1]	56	1			T16	1		T101	1		T6	2
auto[3355443200:3489660927]	auto[0]	60	1			T32	1		T19	1		T24	1
auto[3355443200:3489660927]	auto[1]	48	1			T228	1		T216	1		T6	1
auto[3489660928:3623878655]	auto[0]	54	1			T19	1		T43	1		T48	3
auto[3489660928:3623878655]	auto[1]	55	1			T16	1		T48	1		T6	1
auto[3623878656:3758096383]	auto[0]	42	1			T4	1		T55	1		T6	1
auto[3623878656:3758096383]	auto[1]	56	1			T16	2		T18	1		T6	1
auto[3758096384:3892314111]	auto[0]	46	1			T16	1		T26	1		T41	1
auto[3758096384:3892314111]	auto[1]	67	1			T8	1		T101	1		T100	2
auto[3892314112:4026531839]	auto[0]	55	1			T16	1		T8	1		T101	1
auto[3892314112:4026531839]	auto[1]	67	1			T16	2		T32	1		T40	1
auto[4026531840:4160749567]	auto[0]	40	1			T47	1		T48	2		T216	1
auto[4026531840:4160749567]	auto[1]	61	1			T16	2		T231	1		T101	2
auto[4160749568:4294967295]	auto[0]	53	1			T48	1		T61	2		T7	1
auto[4160749568:4294967295]	auto[1]	55	1			T1	1		T4	1		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T1

1

T3

4

T4

11

auto[1]

1826

1

T1

3

T2

1

T4

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T16	2		T41	1		T19	1
auto[134217728:268435455]	97	1			T48	3		T6	1		T61	2
auto[268435456:402653183]	108	1			T101	1		T42	1		T47	1
auto[402653184:536870911]	112	1			T18	1		T32	1		T41	1
auto[536870912:671088639]	112	1			T4	1		T16	1		T228	1
auto[671088640:805306367]	101	1			T4	1		T16	1		T32	2
auto[805306368:939524095]	100	1			T4	1		T16	1		T231	1
auto[939524096:1073741823]	126	1			T4	1		T16	5		T26	1
auto[1073741824:1207959551]	110	1			T4	3		T16	3		T39	1
auto[1207959552:1342177279]	105	1			T4	1		T16	2		T228	1
auto[1342177280:1476395007]	97	1			T16	1		T32	1		T101	1
auto[1476395008:1610612735]	125	1			T16	2		T18	1		T55	1
auto[1610612736:1744830463]	106	1			T4	3		T16	2		T18	1
auto[1744830464:1879048191]	125	1			T16	3		T26	1		T40	2
auto[1879048192:2013265919]	105	1			T231	2		T100	2		T136	1
auto[2013265920:2147483647]	105	1			T3	1		T19	1		T101	1
auto[2147483648:2281701375]	98	1			T1	1		T4	1		T18	1
auto[2281701376:2415919103]	121	1			T4	1		T16	2		T26	1
auto[2415919104:2550136831]	112	1			T4	2		T18	1		T24	1
auto[2550136832:2684354559]	117	1			T228	1		T100	1		T20	2
auto[2684354560:2818572287]	111	1			T4	1		T16	1		T101	2
auto[2818572288:2952790015]	109	1			T142	1		T101	1		T24	3
auto[2952790016:3087007743]	103	1			T16	1		T43	1		T83	1
auto[3087007744:3221225471]	97	1			T2	1		T4	2		T16	1
auto[3221225472:3355443199]	104	1			T1	1		T16	1		T18	1
auto[3355443200:3489660927]	101	1			T39	1		T47	1		T6	1
auto[3489660928:3623878655]	101	1			T1	1		T4	2		T16	3
auto[3623878656:3758096383]	113	1			T3	1		T16	2		T26	1
auto[3758096384:3892314111]	103	1			T1	1		T3	1		T4	1
auto[3892314112:4026531839]	108	1			T4	1		T16	1		T32	1
auto[4026531840:4160749567]	108	1			T3	1		T4	1		T101	1
auto[4160749568:4294967295]	102	1			T4	1		T16	1		T228	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T41	1		T19	1		T100	1
auto[0:134217727]	auto[1]	61	1			T16	2		T48	1		T216	1
auto[134217728:268435455]	auto[0]	55	1			T48	1		T6	1		T61	1
auto[134217728:268435455]	auto[1]	42	1			T48	2		T61	1		T49	1
auto[268435456:402653183]	auto[0]	50	1			T101	1		T48	2		T49	1
auto[268435456:402653183]	auto[1]	58	1			T42	1		T47	1		T123	1
auto[402653184:536870911]	auto[0]	55	1			T32	1		T41	1		T100	1
auto[402653184:536870911]	auto[1]	57	1			T18	1		T7	1		T63	1
auto[536870912:671088639]	auto[0]	56	1			T16	1		T228	1		T136	1
auto[536870912:671088639]	auto[1]	56	1			T4	1		T6	2		T61	1
auto[671088640:805306367]	auto[0]	48	1			T4	1		T32	2		T6	2
auto[671088640:805306367]	auto[1]	53	1			T16	1		T101	1		T47	1
auto[805306368:939524095]	auto[0]	40	1			T48	1		T61	1		T339	1
auto[805306368:939524095]	auto[1]	60	1			T4	1		T16	1		T231	1
auto[939524096:1073741823]	auto[0]	46	1			T16	2		T47	1		T49	1
auto[939524096:1073741823]	auto[1]	80	1			T4	1		T16	3		T26	1
auto[1073741824:1207959551]	auto[0]	50	1			T4	2		T16	1		T39	1
auto[1073741824:1207959551]	auto[1]	60	1			T4	1		T16	2		T142	1
auto[1207959552:1342177279]	auto[0]	54	1			T16	1		T228	1		T27	1
auto[1207959552:1342177279]	auto[1]	51	1			T4	1		T16	1		T48	1
auto[1342177280:1476395007]	auto[0]	41	1			T24	2		T47	1		T215	1
auto[1342177280:1476395007]	auto[1]	56	1			T16	1		T32	1		T101	1
auto[1476395008:1610612735]	auto[0]	55	1			T16	1		T55	1		T48	1
auto[1476395008:1610612735]	auto[1]	70	1			T16	1		T18	1		T61	1
auto[1610612736:1744830463]	auto[0]	55	1			T4	1		T16	2		T47	1
auto[1610612736:1744830463]	auto[1]	51	1			T4	2		T18	1		T8	1
auto[1744830464:1879048191]	auto[0]	62	1			T16	2		T231	1		T24	1
auto[1744830464:1879048191]	auto[1]	63	1			T16	1		T26	1		T40	2
auto[1879048192:2013265919]	auto[0]	51	1			T231	1		T100	1		T34	1
auto[1879048192:2013265919]	auto[1]	54	1			T231	1		T100	1		T136	1
auto[2013265920:2147483647]	auto[0]	52	1			T3	1		T19	1		T101	1
auto[2013265920:2147483647]	auto[1]	53	1			T55	1		T52	1		T49	1
auto[2147483648:2281701375]	auto[0]	42	1			T4	1		T39	1		T47	1
auto[2147483648:2281701375]	auto[1]	56	1			T1	1		T18	1		T39	1
auto[2281701376:2415919103]	auto[0]	69	1			T4	1		T16	1		T26	1
auto[2281701376:2415919103]	auto[1]	52	1			T16	1		T136	2		T43	1
auto[2415919104:2550136831]	auto[0]	47	1			T18	1		T24	1		T48	1
auto[2415919104:2550136831]	auto[1]	65	1			T4	2		T135	1		T48	1
auto[2550136832:2684354559]	auto[0]	52	1			T228	1		T209	1		T65	1
auto[2550136832:2684354559]	auto[1]	65	1			T100	1		T20	2		T6	1
auto[2684354560:2818572287]	auto[0]	53	1			T4	1		T101	1		T47	1
auto[2684354560:2818572287]	auto[1]	58	1			T16	1		T101	1		T47	1
auto[2818572288:2952790015]	auto[0]	55	1			T24	2		T48	1		T216	2
auto[2818572288:2952790015]	auto[1]	54	1			T142	1		T101	1		T24	1
auto[2952790016:3087007743]	auto[0]	48	1			T16	1		T47	1		T318	1
auto[2952790016:3087007743]	auto[1]	55	1			T43	1		T83	1		T6	2
auto[3087007744:3221225471]	auto[0]	50	1			T4	1		T43	1		T48	3
auto[3087007744:3221225471]	auto[1]	47	1			T2	1		T4	1		T16	1
auto[3221225472:3355443199]	auto[0]	45	1			T47	1		T48	1		T280	1
auto[3221225472:3355443199]	auto[1]	59	1			T1	1		T16	1		T18	1
auto[3355443200:3489660927]	auto[0]	52	1			T39	1		T6	1		T61	1
auto[3355443200:3489660927]	auto[1]	49	1			T47	1		T49	1		T7	1
auto[3489660928:3623878655]	auto[0]	38	1			T4	2		T142	1		T24	1
auto[3489660928:3623878655]	auto[1]	63	1			T1	1		T16	3		T228	1
auto[3623878656:3758096383]	auto[0]	61	1			T3	1		T47	1		T48	1
auto[3623878656:3758096383]	auto[1]	52	1			T16	2		T26	1		T27	1
auto[3758096384:3892314111]	auto[0]	51	1			T1	1		T3	1		T16	1
auto[3758096384:3892314111]	auto[1]	52	1			T4	1		T41	1		T100	1
auto[3892314112:4026531839]	auto[0]	52	1			T4	1		T16	1		T32	1
auto[3892314112:4026531839]	auto[1]	56	1			T101	1		T6	1		T49	1
auto[4026531840:4160749567]	auto[0]	48	1			T3	1		T47	2		T48	2
auto[4026531840:4160749567]	auto[1]	60	1			T4	1		T101	1		T48	1
auto[4160749568:4294967295]	auto[0]	44	1			T16	1		T228	1		T269	1
auto[4160749568:4294967295]	auto[1]	58	1			T4	1		T47	1		T48	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1621

1

T1

3

T3

4

T4

13

auto[1]

1822

1

T1

1

T2

1

T4

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T4	2		T228	1		T136	1
auto[134217728:268435455]	107	1			T16	1		T101	1		T100	1
auto[268435456:402653183]	116	1			T4	1		T16	1		T228	1
auto[402653184:536870911]	93	1			T16	2		T40	1		T8	1
auto[536870912:671088639]	128	1			T1	1		T3	1		T4	3
auto[671088640:805306367]	91	1			T1	1		T4	1		T16	2
auto[805306368:939524095]	109	1			T101	1		T43	1		T48	1
auto[939524096:1073741823]	103	1			T4	1		T16	3		T39	1
auto[1073741824:1207959551]	100	1			T18	1		T43	1		T47	1
auto[1207959552:1342177279]	109	1			T4	1		T231	1		T101	1
auto[1342177280:1476395007]	101	1			T16	1		T18	1		T32	1
auto[1476395008:1610612735]	113	1			T2	1		T4	2		T16	1
auto[1610612736:1744830463]	104	1			T16	1		T142	1		T228	1
auto[1744830464:1879048191]	106	1			T16	1		T32	1		T55	1
auto[1879048192:2013265919]	99	1			T4	1		T16	2		T18	1
auto[2013265920:2147483647]	105	1			T8	1		T231	1		T43	1
auto[2147483648:2281701375]	111	1			T4	1		T16	3		T26	1
auto[2281701376:2415919103]	108	1			T18	1		T32	1		T101	1
auto[2415919104:2550136831]	112	1			T1	1		T16	1		T101	1
auto[2550136832:2684354559]	114	1			T3	1		T16	3		T231	1
auto[2684354560:2818572287]	121	1			T16	2		T18	1		T101	1
auto[2818572288:2952790015]	100	1			T16	2		T26	1		T231	1
auto[2952790016:3087007743]	108	1			T4	3		T16	2		T24	3
auto[3087007744:3221225471]	104	1			T4	1		T16	1		T27	1
auto[3221225472:3355443199]	104	1			T4	2		T18	1		T41	1
auto[3355443200:3489660927]	111	1			T4	2		T32	1		T142	1
auto[3489660928:3623878655]	91	1			T4	1		T16	1		T41	1
auto[3623878656:3758096383]	117	1			T1	1		T4	1		T16	1
auto[3758096384:3892314111]	103	1			T16	2		T40	1		T24	1
auto[3892314112:4026531839]	114	1			T16	1		T26	1		T47	2
auto[4026531840:4160749567]	112	1			T39	1		T101	1		T100	1
auto[4160749568:4294967295]	120	1			T3	2		T4	1		T16	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T4	1		T48	2		T6	2
auto[0:134217727]	auto[1]	53	1			T4	1		T228	1		T136	1
auto[134217728:268435455]	auto[0]	52	1			T101	1		T100	1		T55	1
auto[134217728:268435455]	auto[1]	55	1			T16	1		T7	1		T58	1
auto[268435456:402653183]	auto[0]	52	1			T228	1		T19	1		T43	1
auto[268435456:402653183]	auto[1]	64	1			T4	1		T16	1		T52	1
auto[402653184:536870911]	auto[0]	41	1			T40	1		T47	2		T215	1
auto[402653184:536870911]	auto[1]	52	1			T16	2		T8	1		T47	2
auto[536870912:671088639]	auto[0]	62	1			T1	1		T3	1		T4	1
auto[536870912:671088639]	auto[1]	66	1			T4	2		T16	2		T101	1
auto[671088640:805306367]	auto[0]	41	1			T1	1		T4	1		T16	1
auto[671088640:805306367]	auto[1]	50	1			T16	1		T26	1		T228	1
auto[805306368:939524095]	auto[0]	39	1			T216	1		T61	1		T25	1
auto[805306368:939524095]	auto[1]	70	1			T101	1		T43	1		T48	1
auto[939524096:1073741823]	auto[0]	47	1			T39	1		T24	1		T7	1
auto[939524096:1073741823]	auto[1]	56	1			T4	1		T16	3		T42	1
auto[1073741824:1207959551]	auto[0]	52	1			T43	1		T47	1		T48	2
auto[1073741824:1207959551]	auto[1]	48	1			T18	1		T6	2		T333	1
auto[1207959552:1342177279]	auto[0]	51	1			T4	1		T231	1		T101	1
auto[1207959552:1342177279]	auto[1]	58	1			T20	1		T83	1		T6	2
auto[1342177280:1476395007]	auto[0]	49	1			T18	1		T32	1		T8	1
auto[1342177280:1476395007]	auto[1]	52	1			T16	1		T41	1		T47	1
auto[1476395008:1610612735]	auto[0]	60	1			T4	2		T16	1		T101	2
auto[1476395008:1610612735]	auto[1]	53	1			T2	1		T47	1		T61	1
auto[1610612736:1744830463]	auto[0]	49	1			T16	1		T228	1		T48	2
auto[1610612736:1744830463]	auto[1]	55	1			T142	1		T136	1		T20	1
auto[1744830464:1879048191]	auto[0]	51	1			T32	1		T55	1		T7	1
auto[1744830464:1879048191]	auto[1]	55	1			T16	1		T6	1		T209	1
auto[1879048192:2013265919]	auto[0]	49	1			T4	1		T52	1		T47	1
auto[1879048192:2013265919]	auto[1]	50	1			T16	2		T18	1		T100	1
auto[2013265920:2147483647]	auto[0]	50	1			T8	1		T43	1		T48	1
auto[2013265920:2147483647]	auto[1]	55	1			T231	1		T216	1		T6	1
auto[2147483648:2281701375]	auto[0]	52	1			T16	2		T48	3		T215	1
auto[2147483648:2281701375]	auto[1]	59	1			T4	1		T16	1		T26	1
auto[2281701376:2415919103]	auto[0]	57	1			T32	1		T136	1		T48	1
auto[2281701376:2415919103]	auto[1]	51	1			T18	1		T101	1		T48	1
auto[2415919104:2550136831]	auto[0]	53	1			T1	1		T16	1		T135	1
auto[2415919104:2550136831]	auto[1]	59	1			T101	1		T100	1		T55	1
auto[2550136832:2684354559]	auto[0]	48	1			T3	1		T6	1		T25	1
auto[2550136832:2684354559]	auto[1]	66	1			T16	3		T231	1		T134	1
auto[2684354560:2818572287]	auto[0]	60	1			T18	1		T48	2		T6	1
auto[2684354560:2818572287]	auto[1]	61	1			T16	2		T101	1		T55	1
auto[2818572288:2952790015]	auto[0]	46	1			T16	1		T26	1		T27	1
auto[2818572288:2952790015]	auto[1]	54	1			T16	1		T231	1		T48	1
auto[2952790016:3087007743]	auto[0]	54	1			T4	2		T16	1		T24	3
auto[2952790016:3087007743]	auto[1]	54	1			T4	1		T16	1		T43	1
auto[3087007744:3221225471]	auto[0]	50	1			T16	1		T6	1		T61	1
auto[3087007744:3221225471]	auto[1]	54	1			T4	1		T27	1		T61	2
auto[3221225472:3355443199]	auto[0]	46	1			T4	1		T41	1		T47	1
auto[3221225472:3355443199]	auto[1]	58	1			T4	1		T18	1		T101	1
auto[3355443200:3489660927]	auto[0]	52	1			T4	1		T32	1		T142	1
auto[3355443200:3489660927]	auto[1]	59	1			T4	1		T40	1		T101	1
auto[3489660928:3623878655]	auto[0]	43	1			T4	1		T41	1		T34	1
auto[3489660928:3623878655]	auto[1]	48	1			T16	1		T100	1		T42	1
auto[3623878656:3758096383]	auto[0]	53	1			T16	1		T8	1		T228	1
auto[3623878656:3758096383]	auto[1]	64	1			T1	1		T4	1		T6	1
auto[3758096384:3892314111]	auto[0]	49	1			T16	1		T24	1		T48	1
auto[3758096384:3892314111]	auto[1]	54	1			T16	1		T40	1		T48	1
auto[3892314112:4026531839]	auto[0]	37	1			T16	1		T47	1		T48	1
auto[3892314112:4026531839]	auto[1]	77	1			T26	1		T47	1		T48	2
auto[4026531840:4160749567]	auto[0]	56	1			T39	1		T100	1		T48	1
auto[4026531840:4160749567]	auto[1]	56	1			T101	1		T47	1		T61	2
auto[4160749568:4294967295]	auto[0]	64	1			T3	2		T4	1		T16	1
auto[4160749568:4294967295]	auto[1]	56	1			T142	1		T136	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1609

1

T1

2

T2

1

T3

4

auto[1]

1835

1

T1

2

T4

13

T16

22

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	123	1			T4	1		T16	3		T231	1
auto[134217728:268435455]	112	1			T39	1		T231	1		T136	1
auto[268435456:402653183]	115	1			T4	1		T16	1		T8	1
auto[402653184:536870911]	115	1			T24	1		T47	1		T48	2
auto[536870912:671088639]	108	1			T18	1		T26	1		T142	1
auto[671088640:805306367]	109	1			T1	1		T4	1		T24	2
auto[805306368:939524095]	102	1			T4	2		T48	2		T6	2
auto[939524096:1073741823]	96	1			T16	2		T18	1		T228	2
auto[1073741824:1207959551]	114	1			T1	1		T4	1		T16	3
auto[1207959552:1342177279]	115	1			T4	1		T228	1		T41	1
auto[1342177280:1476395007]	110	1			T4	1		T16	2		T26	2
auto[1476395008:1610612735]	106	1			T1	1		T32	1		T40	1
auto[1610612736:1744830463]	130	1			T4	3		T16	1		T26	1
auto[1744830464:1879048191]	98	1			T4	1		T16	2		T18	1
auto[1879048192:2013265919]	113	1			T3	1		T4	2		T16	2
auto[2013265920:2147483647]	95	1			T3	1		T16	1		T228	1
auto[2147483648:2281701375]	108	1			T16	2		T101	1		T100	1
auto[2281701376:2415919103]	95	1			T16	2		T41	1		T24	1
auto[2415919104:2550136831]	121	1			T16	1		T134	1		T55	1
auto[2550136832:2684354559]	100	1			T3	1		T16	2		T39	1
auto[2684354560:2818572287]	105	1			T4	2		T32	1		T8	1
auto[2818572288:2952790015]	101	1			T4	2		T18	1		T100	1
auto[2952790016:3087007743]	105	1			T2	1		T39	1		T142	1
auto[3087007744:3221225471]	122	1			T3	1		T4	1		T16	1
auto[3221225472:3355443199]	102	1			T4	2		T16	1		T231	1
auto[3355443200:3489660927]	103	1			T16	2		T39	1		T228	2
auto[3489660928:3623878655]	96	1			T16	1		T32	1		T100	1
auto[3623878656:3758096383]	115	1			T16	2		T142	1		T27	1
auto[3758096384:3892314111]	110	1			T1	1		T4	1		T16	2
auto[3892314112:4026531839]	106	1			T16	3		T136	1		T55	1
auto[4026531840:4160749567]	94	1			T4	2		T40	1		T101	1
auto[4160749568:4294967295]	100	1			T16	1		T231	1		T19	1