Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4634

1

T1

4

T3

6

T4

36

auto[1]

2254

1

T1

4

T2

2

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	214	1			T4	2		T16	6		T101	2
auto[134217728:268435455]	212	1			T3	2		T4	2		T228	2
auto[268435456:402653183]	226	1			T18	2		T228	2		T136	2
auto[402653184:536870911]	200	1			T1	2		T4	4		T16	2
auto[536870912:671088639]	194	1			T1	2		T4	2		T16	4
auto[671088640:805306367]	256	1			T4	2		T16	4		T40	2
auto[805306368:939524095]	188	1			T4	2		T52	2		T34	2
auto[939524096:1073741823]	230	1			T16	4		T228	2		T231	2
auto[1073741824:1207959551]	232	1			T3	2		T4	2		T16	4
auto[1207959552:1342177279]	222	1			T4	2		T16	4		T18	2
auto[1342177280:1476395007]	208	1			T4	2		T16	2		T42	4
auto[1476395008:1610612735]	210	1			T4	2		T16	2		T39	2
auto[1610612736:1744830463]	192	1			T16	2		T32	2		T48	2
auto[1744830464:1879048191]	180	1			T39	2		T26	2		T231	2
auto[1879048192:2013265919]	214	1			T4	4		T26	2		T41	2
auto[2013265920:2147483647]	214	1			T228	2		T48	4		T216	2
auto[2147483648:2281701375]	194	1			T4	2		T100	2		T48	2
auto[2281701376:2415919103]	210	1			T3	2		T4	2		T231	2
auto[2415919104:2550136831]	236	1			T1	2		T39	2		T101	4
auto[2550136832:2684354559]	248	1			T16	4		T19	2		T48	4
auto[2684354560:2818572287]	254	1			T1	2		T4	4		T16	2
auto[2818572288:2952790015]	206	1			T4	6		T16	4		T8	2
auto[2952790016:3087007743]	202	1			T16	4		T18	2		T26	2
auto[3087007744:3221225471]	236	1			T32	2		T41	2		T27	2
auto[3221225472:3355443199]	196	1			T4	2		T16	4		T32	2
auto[3355443200:3489660927]	192	1			T16	4		T40	2		T41	2
auto[3489660928:3623878655]	218	1			T4	2		T16	6		T100	2
auto[3623878656:3758096383]	226	1			T3	2		T16	2		T18	2
auto[3758096384:3892314111]	194	1			T2	2		T16	6		T18	4
auto[3892314112:4026531839]	228	1			T4	2		T16	2		T39	2
auto[4026531840:4160749567]	206	1			T32	2		T8	2		T47	2
auto[4160749568:4294967295]	250	1			T4	2		T16	2		T142	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	138	1			T16	4		T101	2		T47	2
auto[0:134217727]	auto[1]	76	1			T4	2		T16	2		T43	2
auto[134217728:268435455]	auto[0]	130	1			T3	2		T134	2		T136	2
auto[134217728:268435455]	auto[1]	82	1			T4	2		T228	2		T210	2
auto[268435456:402653183]	auto[0]	160	1			T228	2		T136	2		T55	2
auto[268435456:402653183]	auto[1]	66	1			T18	2		T63	2		T59	2
auto[402653184:536870911]	auto[0]	128	1			T16	2		T100	2		T24	2
auto[402653184:536870911]	auto[1]	72	1			T1	2		T4	4		T41	2
auto[536870912:671088639]	auto[0]	118	1			T4	2		T16	4		T52	2
auto[536870912:671088639]	auto[1]	76	1			T1	2		T40	2		T43	2
auto[671088640:805306367]	auto[0]	176	1			T4	2		T16	2		T40	2
auto[671088640:805306367]	auto[1]	80	1			T16	2		T231	2		T19	2
auto[805306368:939524095]	auto[0]	132	1			T4	2		T52	2		T48	2
auto[805306368:939524095]	auto[1]	56	1			T34	2		T47	2		T215	2
auto[939524096:1073741823]	auto[0]	152	1			T16	2		T228	2		T136	2
auto[939524096:1073741823]	auto[1]	78	1			T16	2		T231	2		T101	2
auto[1073741824:1207959551]	auto[0]	168	1			T4	2		T16	2		T26	2
auto[1073741824:1207959551]	auto[1]	64	1			T3	2		T16	2		T142	2
auto[1207959552:1342177279]	auto[0]	130	1			T4	2		T16	4		T18	2
auto[1207959552:1342177279]	auto[1]	92	1			T6	4		T49	2		T7	2
auto[1342177280:1476395007]	auto[0]	154	1			T4	2		T16	2		T42	4
auto[1342177280:1476395007]	auto[1]	54	1			T24	2		T20	2		T48	4
auto[1476395008:1610612735]	auto[0]	154	1			T16	2		T228	2		T24	2
auto[1476395008:1610612735]	auto[1]	56	1			T4	2		T39	2		T216	2
auto[1610612736:1744830463]	auto[0]	128	1			T32	2		T48	2		T61	4
auto[1610612736:1744830463]	auto[1]	64	1			T16	2		T6	4		T210	2
auto[1744830464:1879048191]	auto[0]	122	1			T26	2		T48	2		T6	2
auto[1744830464:1879048191]	auto[1]	58	1			T39	2		T231	2		T210	2
auto[1879048192:2013265919]	auto[0]	156	1			T4	4		T26	2		T101	4
auto[1879048192:2013265919]	auto[1]	58	1			T41	2		T7	2		T62	2
auto[2013265920:2147483647]	auto[0]	154	1			T228	2		T48	2		T216	2
auto[2013265920:2147483647]	auto[1]	60	1			T48	2		T6	4		T7	2
auto[2147483648:2281701375]	auto[0]	122	1			T4	2		T100	2		T214	2
auto[2147483648:2281701375]	auto[1]	72	1			T48	2		T6	2		T49	2
auto[2281701376:2415919103]	auto[0]	152	1			T3	2		T4	2		T136	2
auto[2281701376:2415919103]	auto[1]	58	1			T231	2		T100	2		T55	2
auto[2415919104:2550136831]	auto[0]	158	1			T1	2		T101	4		T42	2
auto[2415919104:2550136831]	auto[1]	78	1			T39	2		T48	2		T209	2
auto[2550136832:2684354559]	auto[0]	178	1			T16	2		T48	4		T214	2
auto[2550136832:2684354559]	auto[1]	70	1			T16	2		T19	2		T6	2
auto[2684354560:2818572287]	auto[0]	168	1			T1	2		T4	4		T16	2
auto[2684354560:2818572287]	auto[1]	86	1			T19	2		T101	2		T47	2
auto[2818572288:2952790015]	auto[0]	140	1			T4	4		T16	2		T8	2
auto[2818572288:2952790015]	auto[1]	66	1			T4	2		T16	2		T47	2
auto[2952790016:3087007743]	auto[0]	134	1			T16	2		T18	2		T101	2
auto[2952790016:3087007743]	auto[1]	68	1			T16	2		T26	2		T8	2
auto[3087007744:3221225471]	auto[0]	156	1			T32	2		T41	2		T135	2
auto[3087007744:3221225471]	auto[1]	80	1			T27	2		T101	2		T43	2
auto[3221225472:3355443199]	auto[0]	132	1			T4	2		T16	4		T32	2
auto[3221225472:3355443199]	auto[1]	64	1			T43	2		T280	4		T109	2
auto[3355443200:3489660927]	auto[0]	128	1			T16	2		T41	2		T47	2
auto[3355443200:3489660927]	auto[1]	64	1			T16	2		T40	2		T48	2
auto[3489660928:3623878655]	auto[0]	128	1			T4	2		T16	2		T100	2
auto[3489660928:3623878655]	auto[1]	90	1			T16	4		T47	6		T123	2
auto[3623878656:3758096383]	auto[0]	158	1			T3	2		T16	2		T18	2
auto[3623878656:3758096383]	auto[1]	68	1			T48	2		T7	4		T86	2
auto[3758096384:3892314111]	auto[0]	124	1			T16	2		T18	4		T100	2
auto[3758096384:3892314111]	auto[1]	70	1			T2	2		T16	4		T43	2
auto[3892314112:4026531839]	auto[0]	162	1			T4	2		T16	2		T47	2
auto[3892314112:4026531839]	auto[1]	66	1			T39	2		T6	2		T61	2
auto[4026531840:4160749567]	auto[0]	132	1			T32	2		T8	2		T47	2
auto[4026531840:4160749567]	auto[1]	74	1			T110	2		T62	2		T248	2
auto[4160749568:4294967295]	auto[0]	162	1			T4	2		T16	2		T142	2
auto[4160749568:4294967295]	auto[1]	88	1			T101	2		T47	2		T48	4