Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2986

1

T1

4

T2

1

T3

4

auto[1]

297

1

T18

2

T123

1

T153

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T3	1		T4	1		T16	4
auto[134217728:268435455]	99	1			T4	2		T16	1		T8	1
auto[268435456:402653183]	97	1			T4	1		T16	1		T228	1
auto[402653184:536870911]	116	1			T16	2		T32	1		T27	1
auto[536870912:671088639]	100	1			T16	2		T19	1		T136	1
auto[671088640:805306367]	99	1			T2	1		T16	1		T100	1
auto[805306368:939524095]	104	1			T4	1		T41	1		T24	1
auto[939524096:1073741823]	94	1			T1	1		T101	1		T24	1
auto[1073741824:1207959551]	96	1			T4	1		T16	1		T228	1
auto[1207959552:1342177279]	116	1			T4	1		T16	1		T231	1
auto[1342177280:1476395007]	96	1			T4	1		T32	1		T101	1
auto[1476395008:1610612735]	79	1			T3	1		T16	1		T6	1
auto[1610612736:1744830463]	89	1			T1	1		T4	1		T16	2
auto[1744830464:1879048191]	106	1			T4	1		T16	1		T101	2
auto[1879048192:2013265919]	115	1			T1	1		T4	1		T228	1
auto[2013265920:2147483647]	112	1			T4	2		T16	2		T32	1
auto[2147483648:2281701375]	103	1			T16	1		T26	1		T48	1
auto[2281701376:2415919103]	110	1			T16	3		T26	1		T228	1
auto[2415919104:2550136831]	94	1			T4	2		T18	1		T24	1
auto[2550136832:2684354559]	108	1			T32	1		T39	1		T100	1
auto[2684354560:2818572287]	107	1			T18	1		T32	1		T26	1
auto[2818572288:2952790015]	121	1			T16	1		T18	1		T40	1
auto[2952790016:3087007743]	76	1			T16	1		T26	1		T101	1
auto[3087007744:3221225471]	96	1			T18	1		T41	1		T55	1
auto[3221225472:3355443199]	103	1			T1	1		T4	1		T16	1
auto[3355443200:3489660927]	131	1			T16	1		T18	1		T142	1
auto[3489660928:3623878655]	97	1			T3	1		T4	1		T101	1
auto[3623878656:3758096383]	118	1			T16	1		T18	1		T43	1
auto[3758096384:3892314111]	111	1			T16	2		T40	1		T228	1
auto[3892314112:4026531839]	100	1			T4	1		T16	1		T41	1
auto[4026531840:4160749567]	90	1			T3	1		T16	2		T18	1
auto[4160749568:4294967295]	85	1			T4	1		T39	1		T8	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	102	1			T3	1		T4	1		T16	4
auto[0:134217727]	auto[1]	13	1			T18	1		T294	2		T302	1
auto[134217728:268435455]	auto[0]	88	1			T4	2		T16	1		T8	1
auto[134217728:268435455]	auto[1]	11	1			T281	1		T198	1		T399	1
auto[268435456:402653183]	auto[0]	86	1			T4	1		T16	1		T228	1
auto[268435456:402653183]	auto[1]	11	1			T387	3		T220	1		T308	1
auto[402653184:536870911]	auto[0]	106	1			T16	2		T32	1		T27	1
auto[402653184:536870911]	auto[1]	10	1			T198	1		T299	2		T393	1
auto[536870912:671088639]	auto[0]	94	1			T16	2		T19	1		T136	1
auto[536870912:671088639]	auto[1]	6	1			T275	1		T294	1		T406	1
auto[671088640:805306367]	auto[0]	92	1			T2	1		T16	1		T100	1
auto[671088640:805306367]	auto[1]	7	1			T75	2		T294	1		T414	1
auto[805306368:939524095]	auto[0]	99	1			T4	1		T41	1		T24	1
auto[805306368:939524095]	auto[1]	5	1			T377	1		T399	1		T407	1
auto[939524096:1073741823]	auto[0]	82	1			T1	1		T101	1		T24	1
auto[939524096:1073741823]	auto[1]	12	1			T281	1		T387	1		T294	4
auto[1073741824:1207959551]	auto[0]	88	1			T4	1		T16	1		T228	1
auto[1073741824:1207959551]	auto[1]	8	1			T281	1		T266	1		T294	1
auto[1207959552:1342177279]	auto[0]	108	1			T4	1		T16	1		T231	1
auto[1207959552:1342177279]	auto[1]	8	1			T281	1		T75	1		T392	1
auto[1342177280:1476395007]	auto[0]	83	1			T4	1		T32	1		T101	1
auto[1342177280:1476395007]	auto[1]	13	1			T123	1		T281	1		T198	1
auto[1476395008:1610612735]	auto[0]	75	1			T3	1		T16	1		T6	1
auto[1476395008:1610612735]	auto[1]	4	1			T408	1		T401	1		T416	1
auto[1610612736:1744830463]	auto[0]	84	1			T1	1		T4	1		T16	2
auto[1610612736:1744830463]	auto[1]	5	1			T75	1		T392	1		T408	1
auto[1744830464:1879048191]	auto[0]	95	1			T4	1		T16	1		T101	2
auto[1744830464:1879048191]	auto[1]	11	1			T377	2		T399	1		T311	1
auto[1879048192:2013265919]	auto[0]	102	1			T1	1		T4	1		T228	1
auto[1879048192:2013265919]	auto[1]	13	1			T294	1		T399	1		T392	1
auto[2013265920:2147483647]	auto[0]	101	1			T4	2		T16	2		T32	1
auto[2013265920:2147483647]	auto[1]	11	1			T198	1		T299	2		T377	1
auto[2147483648:2281701375]	auto[0]	86	1			T16	1		T26	1		T48	1
auto[2147483648:2281701375]	auto[1]	17	1			T75	2		T266	1		T198	1
auto[2281701376:2415919103]	auto[0]	96	1			T16	3		T26	1		T228	1
auto[2281701376:2415919103]	auto[1]	14	1			T281	2		T299	1		T405	1
auto[2415919104:2550136831]	auto[0]	86	1			T4	2		T18	1		T24	1
auto[2415919104:2550136831]	auto[1]	8	1			T198	1		T403	1		T414	1
auto[2550136832:2684354559]	auto[0]	99	1			T32	1		T39	1		T100	1
auto[2550136832:2684354559]	auto[1]	9	1			T281	1		T75	1		T308	1
auto[2684354560:2818572287]	auto[0]	98	1			T18	1		T32	1		T26	1
auto[2684354560:2818572287]	auto[1]	9	1			T391	1		T357	2		T417	2
auto[2818572288:2952790015]	auto[0]	111	1			T16	1		T18	1		T40	1
auto[2818572288:2952790015]	auto[1]	10	1			T281	1		T275	1		T294	1
auto[2952790016:3087007743]	auto[0]	69	1			T16	1		T26	1		T101	1
auto[2952790016:3087007743]	auto[1]	7	1			T75	1		T311	1		T401	1
auto[3087007744:3221225471]	auto[0]	83	1			T41	1		T55	1		T47	1
auto[3087007744:3221225471]	auto[1]	13	1			T18	1		T294	1		T311	1
auto[3221225472:3355443199]	auto[0]	96	1			T1	1		T4	1		T16	1
auto[3221225472:3355443199]	auto[1]	7	1			T153	1		T294	1		T302	1
auto[3355443200:3489660927]	auto[0]	120	1			T16	1		T18	1		T142	1
auto[3355443200:3489660927]	auto[1]	11	1			T294	2		T399	1		T405	1
auto[3489660928:3623878655]	auto[0]	92	1			T3	1		T4	1		T101	1
auto[3489660928:3623878655]	auto[1]	5	1			T75	1		T377	1		T302	1
auto[3623878656:3758096383]	auto[0]	111	1			T16	1		T18	1		T43	1
auto[3623878656:3758096383]	auto[1]	7	1			T198	1		T275	1		T403	1
auto[3758096384:3892314111]	auto[0]	104	1			T16	2		T40	1		T228	1
auto[3758096384:3892314111]	auto[1]	7	1			T281	1		T299	1		T392	1
auto[3892314112:4026531839]	auto[0]	91	1			T4	1		T16	1		T41	1
auto[3892314112:4026531839]	auto[1]	9	1			T266	1		T393	1		T308	1
auto[4026531840:4160749567]	auto[0]	81	1			T3	1		T16	2		T18	1
auto[4026531840:4160749567]	auto[1]	9	1			T387	1		T266	1		T198	1
auto[4160749568:4294967295]	auto[0]	78	1			T4	1		T39	1		T8	1
auto[4160749568:4294967295]	auto[1]	7	1			T399	1		T407	1		T309	1