Unified Coverage Report :: Group Instance : sealing_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1623

1

T1

2

T3

3

T4

12

auto[1]

1821

1

T1

2

T2

1

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T1	1		T16	1		T100	1
auto[134217728:268435455]	106	1			T16	1		T32	1		T42	1
auto[268435456:402653183]	113	1			T16	3		T26	1		T40	1
auto[402653184:536870911]	116	1			T16	1		T18	1		T26	1
auto[536870912:671088639]	91	1			T4	3		T16	1		T39	1
auto[671088640:805306367]	124	1			T1	1		T4	3		T41	1
auto[805306368:939524095]	108	1			T4	1		T16	1		T32	1
auto[939524096:1073741823]	130	1			T4	1		T19	1		T101	2
auto[1073741824:1207959551]	102	1			T4	2		T16	5		T32	1
auto[1207959552:1342177279]	114	1			T4	2		T16	2		T18	1
auto[1342177280:1476395007]	110	1			T16	3		T41	1		T231	1
auto[1476395008:1610612735]	96	1			T1	1		T4	1		T32	1
auto[1610612736:1744830463]	109	1			T4	2		T16	1		T231	1
auto[1744830464:1879048191]	117	1			T18	1		T26	1		T8	1
auto[1879048192:2013265919]	119	1			T3	1		T4	1		T142	1
auto[2013265920:2147483647]	101	1			T4	1		T16	1		T100	1
auto[2147483648:2281701375]	105	1			T1	1		T4	2		T16	2
auto[2281701376:2415919103]	103	1			T3	1		T16	2		T40	1
auto[2415919104:2550136831]	94	1			T42	1		T136	1		T43	1
auto[2550136832:2684354559]	124	1			T16	2		T32	1		T228	1
auto[2684354560:2818572287]	89	1			T16	3		T101	1		T6	1
auto[2818572288:2952790015]	106	1			T3	1		T4	1		T16	1
auto[2952790016:3087007743]	103	1			T142	1		T19	1		T100	1
auto[3087007744:3221225471]	120	1			T2	1		T4	1		T16	2
auto[3221225472:3355443199]	103	1			T4	1		T18	2		T40	1
auto[3355443200:3489660927]	86	1			T16	1		T101	2		T136	1
auto[3489660928:3623878655]	101	1			T3	1		T16	2		T101	1
auto[3623878656:3758096383]	97	1			T4	2		T142	1		T52	1
auto[3758096384:3892314111]	118	1			T228	1		T24	1		T43	1
auto[3892314112:4026531839]	114	1			T39	2		T42	1		T48	1
auto[4026531840:4160749567]	112	1			T16	1		T19	1		T100	1
auto[4160749568:4294967295]	102	1			T16	1		T18	1		T228	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T1	1		T24	1		T55	1
auto[0:134217727]	auto[1]	55	1			T16	1		T100	1		T48	1
auto[134217728:268435455]	auto[0]	58	1			T32	1		T216	1		T6	2
auto[134217728:268435455]	auto[1]	48	1			T16	1		T42	1		T47	1
auto[268435456:402653183]	auto[0]	52	1			T16	1		T231	1		T24	1
auto[268435456:402653183]	auto[1]	61	1			T16	2		T26	1		T40	1
auto[402653184:536870911]	auto[0]	43	1			T215	1		T61	2		T63	1
auto[402653184:536870911]	auto[1]	73	1			T16	1		T18	1		T26	1
auto[536870912:671088639]	auto[0]	40	1			T4	2		T16	1		T39	1
auto[536870912:671088639]	auto[1]	51	1			T4	1		T231	1		T135	1
auto[671088640:805306367]	auto[0]	56	1			T4	1		T41	1		T48	1
auto[671088640:805306367]	auto[1]	68	1			T1	1		T4	2		T134	1
auto[805306368:939524095]	auto[0]	52	1			T32	1		T24	1		T47	1
auto[805306368:939524095]	auto[1]	56	1			T4	1		T16	1		T100	1
auto[939524096:1073741823]	auto[0]	54	1			T19	1		T100	1		T24	1
auto[939524096:1073741823]	auto[1]	76	1			T4	1		T101	2		T100	1
auto[1073741824:1207959551]	auto[0]	43	1			T16	2		T32	1		T52	1
auto[1073741824:1207959551]	auto[1]	59	1			T4	2		T16	3		T6	2
auto[1207959552:1342177279]	auto[0]	53	1			T4	2		T16	2		T18	1
auto[1207959552:1342177279]	auto[1]	61	1			T26	1		T47	1		T333	1
auto[1342177280:1476395007]	auto[0]	50	1			T231	1		T24	1		T48	1
auto[1342177280:1476395007]	auto[1]	60	1			T16	3		T41	1		T20	1
auto[1476395008:1610612735]	auto[0]	43	1			T32	1		T41	1		T215	1
auto[1476395008:1610612735]	auto[1]	53	1			T1	1		T4	1		T24	1
auto[1610612736:1744830463]	auto[0]	57	1			T4	1		T101	1		T55	1
auto[1610612736:1744830463]	auto[1]	52	1			T4	1		T16	1		T231	1
auto[1744830464:1879048191]	auto[0]	57	1			T8	1		T101	1		T48	1
auto[1744830464:1879048191]	auto[1]	60	1			T18	1		T26	1		T43	1
auto[1879048192:2013265919]	auto[0]	60	1			T3	1		T4	1		T142	1
auto[1879048192:2013265919]	auto[1]	59	1			T48	1		T6	2		T49	1
auto[2013265920:2147483647]	auto[0]	51	1			T4	1		T100	1		T24	1
auto[2013265920:2147483647]	auto[1]	50	1			T16	1		T6	1		T49	1
auto[2147483648:2281701375]	auto[0]	56	1			T1	1		T4	2		T16	1
auto[2147483648:2281701375]	auto[1]	49	1			T16	1		T101	1		T55	1
auto[2281701376:2415919103]	auto[0]	52	1			T3	1		T228	2		T24	1
auto[2281701376:2415919103]	auto[1]	51	1			T16	2		T40	1		T6	1
auto[2415919104:2550136831]	auto[0]	35	1			T49	1		T244	1		T84	1
auto[2415919104:2550136831]	auto[1]	59	1			T42	1		T136	1		T43	1
auto[2550136832:2684354559]	auto[0]	59	1			T16	2		T32	1		T101	1
auto[2550136832:2684354559]	auto[1]	65	1			T228	1		T42	1		T6	2
auto[2684354560:2818572287]	auto[0]	40	1			T16	2		T101	1		T78	1
auto[2684354560:2818572287]	auto[1]	49	1			T16	1		T6	1		T333	1
auto[2818572288:2952790015]	auto[0]	50	1			T4	1		T16	1		T47	1
auto[2818572288:2952790015]	auto[1]	56	1			T3	1		T7	2		T281	1
auto[2952790016:3087007743]	auto[0]	50	1			T19	1		T55	1		T48	1
auto[2952790016:3087007743]	auto[1]	53	1			T142	1		T100	1		T6	1
auto[3087007744:3221225471]	auto[0]	62	1			T16	1		T228	1		T47	1
auto[3087007744:3221225471]	auto[1]	58	1			T2	1		T4	1		T16	1
auto[3221225472:3355443199]	auto[0]	37	1			T215	1		T7	2		T404	1
auto[3221225472:3355443199]	auto[1]	66	1			T4	1		T18	2		T40	1
auto[3355443200:3489660927]	auto[0]	39	1			T47	1		T216	1		T6	1
auto[3355443200:3489660927]	auto[1]	47	1			T16	1		T101	2		T136	1
auto[3489660928:3623878655]	auto[0]	56	1			T3	1		T16	1		T101	1
auto[3489660928:3623878655]	auto[1]	45	1			T16	1		T210	1		T61	2
auto[3623878656:3758096383]	auto[0]	49	1			T4	1		T142	1		T47	2
auto[3623878656:3758096383]	auto[1]	48	1			T4	1		T52	1		T48	2
auto[3758096384:3892314111]	auto[0]	61	1			T47	1		T48	1		T6	3
auto[3758096384:3892314111]	auto[1]	57	1			T228	1		T24	1		T43	1
auto[3892314112:4026531839]	auto[0]	58	1			T39	2		T48	1		T6	1
auto[3892314112:4026531839]	auto[1]	56	1			T42	1		T6	2		T229	1
auto[4026531840:4160749567]	auto[0]	46	1			T19	1		T100	1		T61	1
auto[4026531840:4160749567]	auto[1]	66	1			T16	1		T47	2		T48	1
auto[4160749568:4294967295]	auto[0]	48	1			T16	1		T18	1		T228	1
auto[4160749568:4294967295]	auto[1]	54	1			T34	1		T47	1		T48	2