Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.04 97.83 98.32 100.00 99.02 98.41 91.19


Total test records in report: 1087
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1010 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2425090707 Jun 21 05:02:05 PM PDT 24 Jun 21 05:02:11 PM PDT 24 23426836 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3320759827 Jun 21 05:01:55 PM PDT 24 Jun 21 05:02:00 PM PDT 24 53325089 ps
T1012 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3763158809 Jun 21 05:01:53 PM PDT 24 Jun 21 05:02:05 PM PDT 24 260187537 ps
T1013 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4176643438 Jun 21 05:01:41 PM PDT 24 Jun 21 05:01:44 PM PDT 24 95659948 ps
T1014 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.813602222 Jun 21 05:01:39 PM PDT 24 Jun 21 05:01:48 PM PDT 24 135073904 ps
T1015 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1255617675 Jun 21 05:02:00 PM PDT 24 Jun 21 05:02:04 PM PDT 24 14888810 ps
T1016 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1821551775 Jun 21 05:02:02 PM PDT 24 Jun 21 05:02:06 PM PDT 24 44997228 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4229890902 Jun 21 05:01:49 PM PDT 24 Jun 21 05:01:54 PM PDT 24 49924177 ps
T1018 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.13024034 Jun 21 05:01:48 PM PDT 24 Jun 21 05:01:51 PM PDT 24 21318316 ps
T1019 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3474798213 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:04 PM PDT 24 46051330 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4220964802 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:01 PM PDT 24 9512942 ps
T1021 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3402156259 Jun 21 05:01:59 PM PDT 24 Jun 21 05:02:03 PM PDT 24 74511672 ps
T1022 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1676860354 Jun 21 05:02:03 PM PDT 24 Jun 21 05:02:08 PM PDT 24 22584173 ps
T1023 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1025393003 Jun 21 05:02:07 PM PDT 24 Jun 21 05:02:12 PM PDT 24 83908069 ps
T1024 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.897549138 Jun 21 05:02:00 PM PDT 24 Jun 21 05:02:04 PM PDT 24 96652155 ps
T1025 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1093276604 Jun 21 05:02:08 PM PDT 24 Jun 21 05:02:13 PM PDT 24 190674941 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1896111964 Jun 21 05:01:39 PM PDT 24 Jun 21 05:01:42 PM PDT 24 35259381 ps
T1027 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.718303285 Jun 21 05:01:38 PM PDT 24 Jun 21 05:01:41 PM PDT 24 28543723 ps
T1028 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1025780321 Jun 21 05:01:40 PM PDT 24 Jun 21 05:01:49 PM PDT 24 180084882 ps
T1029 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1106599679 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:56 PM PDT 24 53861439 ps
T1030 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3043754937 Jun 21 05:01:40 PM PDT 24 Jun 21 05:01:43 PM PDT 24 180642538 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2328110765 Jun 21 05:02:03 PM PDT 24 Jun 21 05:02:21 PM PDT 24 1235963952 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3889635216 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:57 PM PDT 24 112758836 ps
T185 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.120952002 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:04 PM PDT 24 1075679374 ps
T1033 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2363246469 Jun 21 05:02:04 PM PDT 24 Jun 21 05:02:09 PM PDT 24 12546456 ps
T1034 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1191293663 Jun 21 05:01:54 PM PDT 24 Jun 21 05:02:01 PM PDT 24 72148872 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.114429214 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:57 PM PDT 24 159073173 ps
T1036 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.44186707 Jun 21 05:01:51 PM PDT 24 Jun 21 05:01:56 PM PDT 24 20928771 ps
T1037 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4030522794 Jun 21 05:01:39 PM PDT 24 Jun 21 05:01:45 PM PDT 24 152235699 ps
T158 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.881206600 Jun 21 05:01:48 PM PDT 24 Jun 21 05:01:59 PM PDT 24 238949809 ps
T1038 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.970114178 Jun 21 05:01:52 PM PDT 24 Jun 21 05:01:59 PM PDT 24 198514147 ps
T1039 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2990617275 Jun 21 05:01:51 PM PDT 24 Jun 21 05:02:04 PM PDT 24 382927287 ps
T1040 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2736278674 Jun 21 05:02:00 PM PDT 24 Jun 21 05:02:04 PM PDT 24 10303580 ps
T1041 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3295747452 Jun 21 05:02:03 PM PDT 24 Jun 21 05:02:07 PM PDT 24 14589135 ps
T1042 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3994669203 Jun 21 05:01:36 PM PDT 24 Jun 21 05:01:39 PM PDT 24 24754144 ps
T1043 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3664684842 Jun 21 05:02:05 PM PDT 24 Jun 21 05:02:10 PM PDT 24 17782916 ps
T1044 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.799692448 Jun 21 05:02:01 PM PDT 24 Jun 21 05:02:07 PM PDT 24 64223861 ps
T1045 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3795154545 Jun 21 05:01:42 PM PDT 24 Jun 21 05:01:46 PM PDT 24 72640267 ps
T176 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.807826085 Jun 21 05:01:54 PM PDT 24 Jun 21 05:02:05 PM PDT 24 179256780 ps
T1046 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2111008639 Jun 21 05:01:49 PM PDT 24 Jun 21 05:01:54 PM PDT 24 112430261 ps
T1047 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.728739519 Jun 21 05:01:59 PM PDT 24 Jun 21 05:02:05 PM PDT 24 36060329 ps
T1048 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3528954363 Jun 21 05:02:02 PM PDT 24 Jun 21 05:02:06 PM PDT 24 9924764 ps
T156 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1138346585 Jun 21 05:01:47 PM PDT 24 Jun 21 05:01:58 PM PDT 24 255647460 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.879247071 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:01 PM PDT 24 20460702 ps
T1050 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.522935871 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:02 PM PDT 24 24445652 ps
T1051 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.727994274 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:54 PM PDT 24 13916775 ps
T1052 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3624355781 Jun 21 05:02:07 PM PDT 24 Jun 21 05:02:12 PM PDT 24 35366254 ps
T1053 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1672728186 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:55 PM PDT 24 23491649 ps
T1054 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1007879139 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:55 PM PDT 24 266687571 ps
T1055 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1747780696 Jun 21 05:01:37 PM PDT 24 Jun 21 05:01:40 PM PDT 24 41116942 ps
T1056 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4100381544 Jun 21 05:01:44 PM PDT 24 Jun 21 05:01:48 PM PDT 24 806909619 ps
T1057 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1367328794 Jun 21 05:02:04 PM PDT 24 Jun 21 05:02:09 PM PDT 24 10451272 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1077887492 Jun 21 05:01:46 PM PDT 24 Jun 21 05:01:53 PM PDT 24 137795843 ps
T1059 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1800209246 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:55 PM PDT 24 337256047 ps
T1060 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3451632895 Jun 21 05:01:52 PM PDT 24 Jun 21 05:01:57 PM PDT 24 36588054 ps
T1061 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1123962815 Jun 21 05:01:54 PM PDT 24 Jun 21 05:01:59 PM PDT 24 14635543 ps
T179 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1022288930 Jun 21 05:01:46 PM PDT 24 Jun 21 05:01:50 PM PDT 24 122939338 ps
T165 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3714424256 Jun 21 05:01:53 PM PDT 24 Jun 21 05:02:04 PM PDT 24 447607975 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1054884469 Jun 21 05:01:38 PM PDT 24 Jun 21 05:01:42 PM PDT 24 65088599 ps
T1063 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4172998042 Jun 21 05:02:05 PM PDT 24 Jun 21 05:02:11 PM PDT 24 42830052 ps
T1064 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.611901792 Jun 21 05:01:51 PM PDT 24 Jun 21 05:01:56 PM PDT 24 86519786 ps
T1065 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4183146292 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:54 PM PDT 24 55888235 ps
T1066 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2293341803 Jun 21 05:01:59 PM PDT 24 Jun 21 05:02:03 PM PDT 24 18612115 ps
T1067 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2618797629 Jun 21 05:02:05 PM PDT 24 Jun 21 05:02:10 PM PDT 24 26696142 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.928476707 Jun 21 05:01:43 PM PDT 24 Jun 21 05:01:52 PM PDT 24 425149953 ps
T1069 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2018225286 Jun 21 05:02:03 PM PDT 24 Jun 21 05:02:07 PM PDT 24 34702784 ps
T1070 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2908519323 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:01 PM PDT 24 48479156 ps
T1071 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3197336563 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:55 PM PDT 24 124569095 ps
T173 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1252722593 Jun 21 05:01:55 PM PDT 24 Jun 21 05:02:08 PM PDT 24 229146348 ps
T1072 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1787462507 Jun 21 05:02:08 PM PDT 24 Jun 21 05:02:14 PM PDT 24 27774586 ps
T1073 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.978791574 Jun 21 05:01:49 PM PDT 24 Jun 21 05:01:54 PM PDT 24 1373892341 ps
T1074 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1721743425 Jun 21 05:01:54 PM PDT 24 Jun 21 05:02:01 PM PDT 24 323882076 ps
T1075 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2624565150 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:58 PM PDT 24 109701060 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.64632971 Jun 21 05:01:39 PM PDT 24 Jun 21 05:01:47 PM PDT 24 166714918 ps
T183 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3676090868 Jun 21 05:01:46 PM PDT 24 Jun 21 05:01:50 PM PDT 24 190302748 ps
T1077 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.137909049 Jun 21 05:01:45 PM PDT 24 Jun 21 05:01:48 PM PDT 24 185972463 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.329883550 Jun 21 05:01:44 PM PDT 24 Jun 21 05:01:55 PM PDT 24 1332031663 ps
T1079 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4256196829 Jun 21 05:01:38 PM PDT 24 Jun 21 05:01:40 PM PDT 24 39163102 ps
T174 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2218733636 Jun 21 05:01:47 PM PDT 24 Jun 21 05:01:57 PM PDT 24 511587751 ps
T1080 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3787332766 Jun 21 05:02:02 PM PDT 24 Jun 21 05:02:07 PM PDT 24 46933721 ps
T1081 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.366011294 Jun 21 05:01:39 PM PDT 24 Jun 21 05:01:43 PM PDT 24 98318014 ps
T1082 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4286906051 Jun 21 05:01:56 PM PDT 24 Jun 21 05:02:03 PM PDT 24 77653030 ps
T1083 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.438735204 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:55 PM PDT 24 175216560 ps
T1084 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.287506655 Jun 21 05:01:54 PM PDT 24 Jun 21 05:02:02 PM PDT 24 891472087 ps
T1085 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.429057061 Jun 21 05:01:50 PM PDT 24 Jun 21 05:01:58 PM PDT 24 212807605 ps
T1086 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.140703151 Jun 21 05:01:52 PM PDT 24 Jun 21 05:02:03 PM PDT 24 194908545 ps
T1087 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1735502897 Jun 21 05:01:41 PM PDT 24 Jun 21 05:01:44 PM PDT 24 19199865 ps

Test location /workspace/coverage/default/40.keymgr_stress_all.4161675311
Short name T16
Test name
Test status
Simulation time 2136956898 ps
CPU time 51.11 seconds
Started Jun 21 05:43:44 PM PDT 24
Finished Jun 21 05:44:36 PM PDT 24
Peak memory 216428 kb
Host smart-efc5f9e0-8e34-48d1-a5ee-3981ad43f155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161675311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4161675311
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2630771151
Short name T48
Test name
Test status
Simulation time 961209172 ps
CPU time 38.95 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:44:22 PM PDT 24
Peak memory 216396 kb
Host smart-41bc17db-b35c-4a97-a091-9ca4ae1fc6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630771151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2630771151
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.169207731
Short name T58
Test name
Test status
Simulation time 503256193 ps
CPU time 24.32 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 222492 kb
Host smart-c2ffd691-249d-4776-9d23-76b1ad3e4b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169207731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.169207731
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2950848596
Short name T11
Test name
Test status
Simulation time 573429404 ps
CPU time 17.21 seconds
Started Jun 21 05:39:42 PM PDT 24
Finished Jun 21 05:40:00 PM PDT 24
Peak memory 239324 kb
Host smart-14b0244a-0c83-4d7f-abe1-4b933ccdb8d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950848596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2950848596
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3006407135
Short name T128
Test name
Test status
Simulation time 358974412 ps
CPU time 8.91 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:37 PM PDT 24
Peak memory 222684 kb
Host smart-142df746-fd59-432c-afd8-5db0312c46f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006407135 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3006407135
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2719204434
Short name T6
Test name
Test status
Simulation time 15254878965 ps
CPU time 300.71 seconds
Started Jun 21 05:44:04 PM PDT 24
Finished Jun 21 05:49:05 PM PDT 24
Peak memory 222596 kb
Host smart-b8e14442-be83-4200-bf03-45aae4fd2fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719204434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2719204434
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1815146801
Short name T281
Test name
Test status
Simulation time 246736320 ps
CPU time 12.82 seconds
Started Jun 21 05:40:57 PM PDT 24
Finished Jun 21 05:41:11 PM PDT 24
Peak memory 222476 kb
Host smart-b9ad43e9-cb77-423d-856a-d946847c802f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815146801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1815146801
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2253679351
Short name T8
Test name
Test status
Simulation time 219240818 ps
CPU time 3.21 seconds
Started Jun 21 05:42:57 PM PDT 24
Finished Jun 21 05:43:01 PM PDT 24
Peak memory 221680 kb
Host smart-56ce60d3-8d64-4ac3-bb64-4525a5da888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253679351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2253679351
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1802824697
Short name T215
Test name
Test status
Simulation time 247323262 ps
CPU time 2.91 seconds
Started Jun 21 05:41:00 PM PDT 24
Finished Jun 21 05:41:04 PM PDT 24
Peak memory 214212 kb
Host smart-0e9c929c-03c1-44fc-a549-f8b76f4c748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802824697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1802824697
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3951041484
Short name T121
Test name
Test status
Simulation time 813404860 ps
CPU time 7.72 seconds
Started Jun 21 05:01:59 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 220668 kb
Host smart-3dcb2c4d-5340-425f-8958-fe7bc0472b10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951041484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3951041484
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2821113193
Short name T75
Test name
Test status
Simulation time 3843829855 ps
CPU time 44.99 seconds
Started Jun 21 05:43:32 PM PDT 24
Finished Jun 21 05:44:18 PM PDT 24
Peak memory 215268 kb
Host smart-f69abcc1-3062-4b5a-ab82-2efc51f759f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821113193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2821113193
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3650296211
Short name T116
Test name
Test status
Simulation time 2926085912 ps
CPU time 36.6 seconds
Started Jun 21 05:42:04 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 222716 kb
Host smart-6db193e8-3ea0-42f7-ba3d-8e586eb8f5d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650296211 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3650296211
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2531791228
Short name T294
Test name
Test status
Simulation time 7824144081 ps
CPU time 121.76 seconds
Started Jun 21 05:40:08 PM PDT 24
Finished Jun 21 05:42:11 PM PDT 24
Peak memory 214436 kb
Host smart-c4770308-b99b-4b5a-855d-b499b5e3e9a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531791228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2531791228
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3226387677
Short name T24
Test name
Test status
Simulation time 126152740 ps
CPU time 4.58 seconds
Started Jun 21 05:41:22 PM PDT 24
Finished Jun 21 05:41:27 PM PDT 24
Peak memory 221056 kb
Host smart-52b9adf9-48b5-4971-8b73-5d20ad9f829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226387677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3226387677
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1466540217
Short name T7
Test name
Test status
Simulation time 79780998720 ps
CPU time 422.63 seconds
Started Jun 21 05:39:25 PM PDT 24
Finished Jun 21 05:46:29 PM PDT 24
Peak memory 217620 kb
Host smart-56073360-09c3-4ee0-b39c-81c63d5d5ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466540217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1466540217
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.798369615
Short name T124
Test name
Test status
Simulation time 210967612 ps
CPU time 2.82 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 214452 kb
Host smart-a9b1085e-6909-408e-ad42-42c0dfca4215
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798369615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.798369615
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.787981234
Short name T33
Test name
Test status
Simulation time 246633658 ps
CPU time 2.43 seconds
Started Jun 21 05:40:23 PM PDT 24
Finished Jun 21 05:40:26 PM PDT 24
Peak memory 210064 kb
Host smart-fde647c0-4994-4060-86ea-f26eec2d2785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787981234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.787981234
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1114020661
Short name T358
Test name
Test status
Simulation time 4346332100 ps
CPU time 64.88 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:40:57 PM PDT 24
Peak memory 222664 kb
Host smart-8f3cc0a9-7ff7-4815-a984-7ea2412e97f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114020661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1114020661
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2604635115
Short name T63
Test name
Test status
Simulation time 1556363416 ps
CPU time 39.56 seconds
Started Jun 21 05:41:21 PM PDT 24
Finished Jun 21 05:42:01 PM PDT 24
Peak memory 215412 kb
Host smart-4db1385f-b982-4e0c-af0f-f8b00f4afe08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604635115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2604635115
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.90705066
Short name T399
Test name
Test status
Simulation time 224869814 ps
CPU time 11.58 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:42:03 PM PDT 24
Peak memory 215400 kb
Host smart-429db39f-cc5e-4d10-8330-92134cd52fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90705066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.90705066
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3652424475
Short name T21
Test name
Test status
Simulation time 102879452 ps
CPU time 3.04 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:55 PM PDT 24
Peak memory 222740 kb
Host smart-c6b13a0f-35c2-4f40-aa0b-e7e80201a04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652424475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3652424475
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2072479771
Short name T807
Test name
Test status
Simulation time 231413767 ps
CPU time 12.6 seconds
Started Jun 21 05:40:29 PM PDT 24
Finished Jun 21 05:40:42 PM PDT 24
Peak memory 214304 kb
Host smart-2ac0571d-4c65-4f0f-ae5b-93bc5a9004b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072479771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2072479771
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1606526501
Short name T62
Test name
Test status
Simulation time 1828130744 ps
CPU time 23.55 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:34 PM PDT 24
Peak memory 216568 kb
Host smart-19db6731-1cc9-48db-9f0e-643d8e07edfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606526501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1606526501
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1425366538
Short name T250
Test name
Test status
Simulation time 91104806 ps
CPU time 4.03 seconds
Started Jun 21 05:42:05 PM PDT 24
Finished Jun 21 05:42:10 PM PDT 24
Peak memory 209772 kb
Host smart-5c640845-0614-49ce-bd88-4c76c987621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425366538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1425366538
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1762383442
Short name T94
Test name
Test status
Simulation time 232104561 ps
CPU time 6.33 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 214256 kb
Host smart-f2e04981-872a-442e-a3bf-8a94ffdcc775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762383442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1762383442
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1332614103
Short name T1
Test name
Test status
Simulation time 403867345 ps
CPU time 4.57 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:33 PM PDT 24
Peak memory 210324 kb
Host smart-b81aeb49-9cb4-4871-a2c8-032b205ec0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332614103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1332614103
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3514729228
Short name T111
Test name
Test status
Simulation time 52195897 ps
CPU time 3.64 seconds
Started Jun 21 05:43:08 PM PDT 24
Finished Jun 21 05:43:13 PM PDT 24
Peak memory 222816 kb
Host smart-4d92dca1-89b4-4ef3-9109-6ca434908760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514729228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3514729228
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.11684815
Short name T44
Test name
Test status
Simulation time 5331521191 ps
CPU time 38.86 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:44:08 PM PDT 24
Peak memory 216096 kb
Host smart-e87eeabf-7593-4971-8ad8-dd1171b6812d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11684815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.11684815
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1824693203
Short name T198
Test name
Test status
Simulation time 283128816 ps
CPU time 13.66 seconds
Started Jun 21 05:42:42 PM PDT 24
Finished Jun 21 05:42:57 PM PDT 24
Peak memory 215216 kb
Host smart-fe0b03f0-134d-4805-9822-5fddd19b85d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824693203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1824693203
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3532830813
Short name T168
Test name
Test status
Simulation time 781903515 ps
CPU time 5.09 seconds
Started Jun 21 05:02:06 PM PDT 24
Finished Jun 21 05:02:16 PM PDT 24
Peak memory 214104 kb
Host smart-14e8580d-b5bf-4113-bf77-2d423f99eb77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532830813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3532830813
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3557819020
Short name T260
Test name
Test status
Simulation time 10809017563 ps
CPU time 44.31 seconds
Started Jun 21 05:43:02 PM PDT 24
Finished Jun 21 05:43:48 PM PDT 24
Peak memory 222536 kb
Host smart-a3add778-6a95-4bdb-8a50-b420b5edd5d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557819020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3557819020
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.77860756
Short name T4
Test name
Test status
Simulation time 4109425152 ps
CPU time 41.31 seconds
Started Jun 21 05:43:41 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 216392 kb
Host smart-96b787c1-a73f-41ec-a7ae-7efb95f9e70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77860756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.77860756
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1151558491
Short name T211
Test name
Test status
Simulation time 13551486442 ps
CPU time 86.34 seconds
Started Jun 21 05:38:49 PM PDT 24
Finished Jun 21 05:40:17 PM PDT 24
Peak memory 217228 kb
Host smart-0ab30842-696a-4b4a-9667-b2f2ba35f3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151558491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1151558491
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2076825615
Short name T80
Test name
Test status
Simulation time 9799674 ps
CPU time 0.75 seconds
Started Jun 21 05:40:45 PM PDT 24
Finished Jun 21 05:40:46 PM PDT 24
Peak memory 205920 kb
Host smart-9702778c-a7e2-4983-917e-5bb07ec212fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076825615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2076825615
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1619248996
Short name T308
Test name
Test status
Simulation time 446917207 ps
CPU time 12.49 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 215764 kb
Host smart-18f4f451-58dd-4ce1-885e-5c5ae82a12ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619248996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1619248996
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1386045309
Short name T161
Test name
Test status
Simulation time 254155371 ps
CPU time 10.08 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 214120 kb
Host smart-bf90fa36-2d8b-42a3-ab76-e66bb79b1bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386045309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1386045309
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.373493755
Short name T103
Test name
Test status
Simulation time 120177054 ps
CPU time 2.3 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:39 PM PDT 24
Peak memory 214292 kb
Host smart-ebeef8ae-fe71-40fe-ac6d-f91d8e282794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373493755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.373493755
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1397256509
Short name T61
Test name
Test status
Simulation time 5535617660 ps
CPU time 24.35 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:39 PM PDT 24
Peak memory 221564 kb
Host smart-6d814749-c799-4a1a-b136-4b9e337bfbe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397256509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1397256509
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3623209271
Short name T803
Test name
Test status
Simulation time 80704009 ps
CPU time 3.08 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:41:55 PM PDT 24
Peak memory 218676 kb
Host smart-2a8aeea3-96e2-49d9-8c3c-7b3d8f1b978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623209271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3623209271
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.798382192
Short name T403
Test name
Test status
Simulation time 2810605427 ps
CPU time 39.67 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:43:08 PM PDT 24
Peak memory 214524 kb
Host smart-1a90e5d3-a2e8-45a5-8469-64e8ddb49625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798382192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.798382192
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4155997652
Short name T20
Test name
Test status
Simulation time 160041032 ps
CPU time 4.43 seconds
Started Jun 21 05:41:21 PM PDT 24
Finished Jun 21 05:41:26 PM PDT 24
Peak memory 209740 kb
Host smart-2c1e3162-a536-4f81-aa4a-413ab9121127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155997652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4155997652
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.881206600
Short name T158
Test name
Test status
Simulation time 238949809 ps
CPU time 9.48 seconds
Started Jun 21 05:01:48 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 213984 kb
Host smart-eb676801-cf22-4d9c-8231-6939107e6084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881206600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
881206600
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1642448308
Short name T90
Test name
Test status
Simulation time 53809604 ps
CPU time 3.38 seconds
Started Jun 21 05:40:46 PM PDT 24
Finished Jun 21 05:40:50 PM PDT 24
Peak memory 214236 kb
Host smart-b7e5ec5d-fc26-40e5-8b68-10da8a1f9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642448308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1642448308
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.120487444
Short name T113
Test name
Test status
Simulation time 101956739 ps
CPU time 4.54 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 218476 kb
Host smart-60e11f07-8596-444a-af07-95cd98409bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120487444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.120487444
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2433998643
Short name T110
Test name
Test status
Simulation time 474741384 ps
CPU time 3.82 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:55 PM PDT 24
Peak memory 217452 kb
Host smart-9e06a1be-bc11-4eb1-861f-73a15ccb01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433998643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2433998643
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3241271486
Short name T74
Test name
Test status
Simulation time 2578606146 ps
CPU time 22.11 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:43:01 PM PDT 24
Peak memory 222736 kb
Host smart-98d20d1a-19cc-4a3b-8d67-9b43c584a9d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241271486 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3241271486
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1070554798
Short name T301
Test name
Test status
Simulation time 149354117 ps
CPU time 3.15 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:42:56 PM PDT 24
Peak memory 214304 kb
Host smart-6855beef-7694-4e02-853b-2ac633035a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070554798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1070554798
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.276426186
Short name T400
Test name
Test status
Simulation time 848408651 ps
CPU time 45.28 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:45:02 PM PDT 24
Peak memory 214584 kb
Host smart-80b4e737-45b4-4139-a33a-88c79a03bbe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276426186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.276426186
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2261692672
Short name T88
Test name
Test status
Simulation time 32828457 ps
CPU time 2.53 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:21 PM PDT 24
Peak memory 208988 kb
Host smart-36fb705c-7765-4dff-b33a-77cba6447795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261692672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2261692672
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3714424256
Short name T165
Test name
Test status
Simulation time 447607975 ps
CPU time 6.41 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 214072 kb
Host smart-da694d02-e78f-4648-a602-c32f03b86cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714424256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3714424256
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4032470007
Short name T13
Test name
Test status
Simulation time 1959301294 ps
CPU time 16.93 seconds
Started Jun 21 05:39:26 PM PDT 24
Finished Jun 21 05:39:43 PM PDT 24
Peak memory 239424 kb
Host smart-52380b1e-b58a-49e4-bf2f-a733ac58de36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032470007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4032470007
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.400844055
Short name T118
Test name
Test status
Simulation time 111727756 ps
CPU time 1.3 seconds
Started Jun 21 05:40:38 PM PDT 24
Finished Jun 21 05:40:41 PM PDT 24
Peak memory 209884 kb
Host smart-b7631d18-4795-492f-861c-7a5769a857be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400844055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.400844055
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1069922672
Short name T792
Test name
Test status
Simulation time 132910123 ps
CPU time 2.53 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 214240 kb
Host smart-e6869ea7-0306-42a3-92f9-9f3418d83fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069922672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1069922672
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1072206140
Short name T401
Test name
Test status
Simulation time 2286291916 ps
CPU time 22.98 seconds
Started Jun 21 05:41:29 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 215040 kb
Host smart-2fb766df-ac8a-49e9-848d-b6fd4fefc060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072206140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1072206140
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2983888467
Short name T59
Test name
Test status
Simulation time 1287126358 ps
CPU time 50.91 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:42:44 PM PDT 24
Peak memory 215824 kb
Host smart-75e0a2f1-c798-4254-ba5c-524aa8bdd75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983888467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2983888467
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3381267011
Short name T257
Test name
Test status
Simulation time 2338084260 ps
CPU time 62.61 seconds
Started Jun 21 05:43:10 PM PDT 24
Finished Jun 21 05:44:13 PM PDT 24
Peak memory 221296 kb
Host smart-891e4193-9a9e-4d2e-8164-a19a849afa77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381267011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3381267011
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3370595109
Short name T127
Test name
Test status
Simulation time 191241250 ps
CPU time 11.84 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:12 PM PDT 24
Peak memory 222620 kb
Host smart-0756deb1-4af9-45d1-af50-b2acd38dd752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370595109 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3370595109
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3022921804
Short name T72
Test name
Test status
Simulation time 896987432 ps
CPU time 33.45 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:40 PM PDT 24
Peak memory 215268 kb
Host smart-75ba5e23-fef3-4dc4-99a4-70cb5b5daf32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022921804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3022921804
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2951923633
Short name T289
Test name
Test status
Simulation time 63751168 ps
CPU time 4.49 seconds
Started Jun 21 05:40:22 PM PDT 24
Finished Jun 21 05:40:27 PM PDT 24
Peak memory 215304 kb
Host smart-a272b0c3-c0f0-45e5-b8a9-539038849e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951923633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2951923633
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3346012805
Short name T112
Test name
Test status
Simulation time 445882773 ps
CPU time 2.98 seconds
Started Jun 21 05:38:49 PM PDT 24
Finished Jun 21 05:38:53 PM PDT 24
Peak memory 217524 kb
Host smart-e86552c1-1ff2-4a1a-8c9d-df578e00c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346012805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3346012805
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3093645233
Short name T114
Test name
Test status
Simulation time 137293639 ps
CPU time 3.98 seconds
Started Jun 21 05:40:23 PM PDT 24
Finished Jun 21 05:40:28 PM PDT 24
Peak memory 214928 kb
Host smart-f7290732-3488-43d1-a690-700b79b5d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093645233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3093645233
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3390935957
Short name T683
Test name
Test status
Simulation time 141744861 ps
CPU time 3.1 seconds
Started Jun 21 05:40:38 PM PDT 24
Finished Jun 21 05:40:42 PM PDT 24
Peak memory 214348 kb
Host smart-ed8c1ba7-4cbe-47fd-abf9-90b0b243beb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390935957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3390935957
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.818015617
Short name T274
Test name
Test status
Simulation time 293129667 ps
CPU time 3.42 seconds
Started Jun 21 05:42:16 PM PDT 24
Finished Jun 21 05:42:20 PM PDT 24
Peak memory 214252 kb
Host smart-1fc8d047-9433-445f-9ed2-d1a415b78cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818015617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.818015617
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2010368607
Short name T309
Test name
Test status
Simulation time 370705423 ps
CPU time 6.17 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:35 PM PDT 24
Peak memory 214540 kb
Host smart-c4926fd3-2718-41b0-a876-b5f3593c83c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010368607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2010368607
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2756034766
Short name T15
Test name
Test status
Simulation time 234320759 ps
CPU time 3.35 seconds
Started Jun 21 05:42:30 PM PDT 24
Finished Jun 21 05:42:34 PM PDT 24
Peak memory 208668 kb
Host smart-6900d381-b0d0-460b-a5b8-da3b8662386c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756034766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2756034766
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1554707548
Short name T371
Test name
Test status
Simulation time 357345759 ps
CPU time 4.4 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:41 PM PDT 24
Peak memory 221560 kb
Host smart-2ee3554b-f1be-46c9-aadc-00a146fef14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554707548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1554707548
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3109876701
Short name T614
Test name
Test status
Simulation time 3658761781 ps
CPU time 45.38 seconds
Started Jun 21 05:44:01 PM PDT 24
Finished Jun 21 05:44:47 PM PDT 24
Peak memory 209028 kb
Host smart-7eda21fe-f9b4-4124-a410-592641326027
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109876701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3109876701
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_random.1691458952
Short name T214
Test name
Test status
Simulation time 7711599537 ps
CPU time 67.2 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:45:25 PM PDT 24
Peak memory 208588 kb
Host smart-8e79f28a-9f93-457f-99a1-64614dd6ed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691458952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1691458952
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.323002264
Short name T3
Test name
Test status
Simulation time 104437285 ps
CPU time 3.56 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:55 PM PDT 24
Peak memory 214204 kb
Host smart-64a6584a-b40e-429f-87e7-b17cbf743f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323002264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.323002264
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3676090868
Short name T183
Test name
Test status
Simulation time 190302748 ps
CPU time 2.54 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:01:50 PM PDT 24
Peak memory 214012 kb
Host smart-aff8a589-f441-4fc8-856f-6d6abcf3be20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676090868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3676090868
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3216405332
Short name T170
Test name
Test status
Simulation time 132309911 ps
CPU time 4.25 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 214064 kb
Host smart-d20550e7-f7b7-4b2b-9fe1-a78eddc97582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216405332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3216405332
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.120952002
Short name T185
Test name
Test status
Simulation time 1075679374 ps
CPU time 4.68 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 214084 kb
Host smart-1a663a4b-9c1a-4761-89cd-92d6c8186e67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120952002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.120952002
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1138346585
Short name T156
Test name
Test status
Simulation time 255647460 ps
CPU time 9.42 seconds
Started Jun 21 05:01:47 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 214068 kb
Host smart-1691835c-4a3d-40b4-822e-c722af94f164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138346585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1138346585
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1104688163
Short name T381
Test name
Test status
Simulation time 292597161 ps
CPU time 2.54 seconds
Started Jun 21 05:38:51 PM PDT 24
Finished Jun 21 05:38:54 PM PDT 24
Peak memory 214172 kb
Host smart-98e78ccb-56b5-4723-b5ea-fc6f394ff066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104688163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1104688163
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.845404362
Short name T323
Test name
Test status
Simulation time 752588051 ps
CPU time 5.71 seconds
Started Jun 21 05:38:43 PM PDT 24
Finished Jun 21 05:38:49 PM PDT 24
Peak memory 214388 kb
Host smart-480b51fc-2e31-4ed7-b1da-66a4eb6cd47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845404362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.845404362
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3739697634
Short name T50
Test name
Test status
Simulation time 68207737 ps
CPU time 1.72 seconds
Started Jun 21 05:40:43 PM PDT 24
Finished Jun 21 05:40:46 PM PDT 24
Peak memory 210220 kb
Host smart-447e51b2-0bcc-4098-9143-15d4cdbc9ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739697634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3739697634
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1046111484
Short name T199
Test name
Test status
Simulation time 151329466 ps
CPU time 4.17 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:19 PM PDT 24
Peak memory 208664 kb
Host smart-18d7ed21-65b4-4866-8e5b-9ee81367b4f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046111484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1046111484
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1411447154
Short name T256
Test name
Test status
Simulation time 167893572 ps
CPU time 3.55 seconds
Started Jun 21 05:41:22 PM PDT 24
Finished Jun 21 05:41:26 PM PDT 24
Peak memory 209724 kb
Host smart-29327951-3e3a-47ce-bf00-1435c7f39dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411447154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1411447154
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2192927548
Short name T238
Test name
Test status
Simulation time 106541783 ps
CPU time 4.28 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:24 PM PDT 24
Peak memory 208688 kb
Host smart-c64c42ca-cfa1-4285-ad9c-b620a72cb1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192927548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2192927548
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3881960599
Short name T259
Test name
Test status
Simulation time 173313725 ps
CPU time 3.39 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:41:55 PM PDT 24
Peak memory 220428 kb
Host smart-edc744ee-690b-452f-9e15-705ffae370c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881960599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3881960599
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2654263038
Short name T271
Test name
Test status
Simulation time 72192410 ps
CPU time 2.65 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:10 PM PDT 24
Peak memory 214240 kb
Host smart-76e4026d-f6a8-46c6-bddc-7462bfd611fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654263038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2654263038
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1820204952
Short name T91
Test name
Test status
Simulation time 1921132812 ps
CPU time 4.68 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:40 PM PDT 24
Peak memory 222420 kb
Host smart-a6f1269b-8457-418f-9868-ab0b4688fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820204952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1820204952
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1566834010
Short name T34
Test name
Test status
Simulation time 109216786 ps
CPU time 2.5 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:05 PM PDT 24
Peak memory 214244 kb
Host smart-fa6be5ce-4d8e-4934-a31b-883ca1041444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566834010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1566834010
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2396077085
Short name T117
Test name
Test status
Simulation time 1481902183 ps
CPU time 12.57 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 222560 kb
Host smart-5deea528-b9a9-4e4f-9c92-fc814e2ae665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396077085 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2396077085
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1451332186
Short name T43
Test name
Test status
Simulation time 241258362 ps
CPU time 3.48 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:05 PM PDT 24
Peak memory 206700 kb
Host smart-bcf23bb5-4dff-4c64-aa7a-213ddba6749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451332186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1451332186
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2286020897
Short name T258
Test name
Test status
Simulation time 637089631 ps
CPU time 8.99 seconds
Started Jun 21 05:43:58 PM PDT 24
Finished Jun 21 05:44:08 PM PDT 24
Peak memory 219732 kb
Host smart-53177713-f27d-460f-ac4e-6d0750a4a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286020897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2286020897
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1093594312
Short name T243
Test name
Test status
Simulation time 65605100 ps
CPU time 1.58 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:27 PM PDT 24
Peak memory 206108 kb
Host smart-d9b45d16-4143-4ab8-940f-f7b2e5cfb69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093594312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1093594312
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3368301958
Short name T982
Test name
Test status
Simulation time 1908129716 ps
CPU time 11.43 seconds
Started Jun 21 05:01:49 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 206004 kb
Host smart-e6a01489-ad78-4f16-abf9-adbbdd1356bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368301958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
368301958
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2908679979
Short name T940
Test name
Test status
Simulation time 3412469743 ps
CPU time 24.18 seconds
Started Jun 21 05:01:35 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205880 kb
Host smart-18fe635b-2ca8-4802-a3c3-d7265cb68951
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908679979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
908679979
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3994669203
Short name T1042
Test name
Test status
Simulation time 24754144 ps
CPU time 0.97 seconds
Started Jun 21 05:01:36 PM PDT 24
Finished Jun 21 05:01:39 PM PDT 24
Peak memory 205876 kb
Host smart-30eb7ab7-cfef-43eb-9662-d2e0f0f5f0eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994669203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
994669203
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2246218861
Short name T1002
Test name
Test status
Simulation time 96221737 ps
CPU time 1.3 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:01:48 PM PDT 24
Peak memory 214136 kb
Host smart-aa6fb79e-2249-4664-8259-8adab0631b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246218861 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2246218861
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.486270375
Short name T150
Test name
Test status
Simulation time 33072442 ps
CPU time 1.56 seconds
Started Jun 21 05:01:35 PM PDT 24
Finished Jun 21 05:01:39 PM PDT 24
Peak memory 205888 kb
Host smart-701789eb-a880-4594-acf5-fbb5ec989f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486270375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.486270375
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4256196829
Short name T1079
Test name
Test status
Simulation time 39163102 ps
CPU time 0.85 seconds
Started Jun 21 05:01:38 PM PDT 24
Finished Jun 21 05:01:40 PM PDT 24
Peak memory 205584 kb
Host smart-ae48a43a-bb95-4802-8cca-80b9ce36efdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256196829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4256196829
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4176643438
Short name T1013
Test name
Test status
Simulation time 95659948 ps
CPU time 1.33 seconds
Started Jun 21 05:01:41 PM PDT 24
Finished Jun 21 05:01:44 PM PDT 24
Peak memory 205880 kb
Host smart-9cb06b19-71e9-4fc4-a1bc-7f3849ec203d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176643438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4176643438
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1692599863
Short name T979
Test name
Test status
Simulation time 157838934 ps
CPU time 4.64 seconds
Started Jun 21 05:01:42 PM PDT 24
Finished Jun 21 05:01:48 PM PDT 24
Peak memory 218928 kb
Host smart-1ec7a737-c127-4d80-8082-9c6c220fe65a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692599863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1692599863
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.64632971
Short name T1076
Test name
Test status
Simulation time 166714918 ps
CPU time 6.61 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:47 PM PDT 24
Peak memory 214372 kb
Host smart-080caaff-4ffa-4a73-a82c-96096af44069
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64632971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_shadow_reg_errors_with_csr_rw.64632971
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.679266912
Short name T963
Test name
Test status
Simulation time 131674395 ps
CPU time 2.21 seconds
Started Jun 21 05:01:32 PM PDT 24
Finished Jun 21 05:01:36 PM PDT 24
Peak memory 214096 kb
Host smart-1aeb10b6-4b29-4ae9-8477-9c721c599ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679266912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.679266912
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.928476707
Short name T1068
Test name
Test status
Simulation time 425149953 ps
CPU time 8.24 seconds
Started Jun 21 05:01:43 PM PDT 24
Finished Jun 21 05:01:52 PM PDT 24
Peak memory 214144 kb
Host smart-ff8fb29a-0f22-43e9-8766-8cf4e9ac3931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928476707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
928476707
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1785420079
Short name T939
Test name
Test status
Simulation time 875733613 ps
CPU time 4.93 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205944 kb
Host smart-924b9232-27d5-49ba-ae4d-66a2994eedd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785420079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
785420079
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1009942985
Short name T1008
Test name
Test status
Simulation time 513584842 ps
CPU time 12.33 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 206004 kb
Host smart-641ebacf-c505-467b-ab9a-8cacfdf0b114
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009942985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
009942985
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1030363782
Short name T924
Test name
Test status
Simulation time 33590738 ps
CPU time 1.03 seconds
Started Jun 21 05:01:41 PM PDT 24
Finished Jun 21 05:01:44 PM PDT 24
Peak memory 205728 kb
Host smart-cac68b96-c45f-4f9f-a75c-d7306991a627
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030363782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
030363782
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1747780696
Short name T1055
Test name
Test status
Simulation time 41116942 ps
CPU time 1.22 seconds
Started Jun 21 05:01:37 PM PDT 24
Finished Jun 21 05:01:40 PM PDT 24
Peak memory 205944 kb
Host smart-ee91ecfa-c2bb-4ab6-88f9-65ae65effb8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747780696 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1747780696
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2066261108
Short name T975
Test name
Test status
Simulation time 462729854 ps
CPU time 1.15 seconds
Started Jun 21 05:01:43 PM PDT 24
Finished Jun 21 05:01:45 PM PDT 24
Peak memory 205796 kb
Host smart-708e7eba-86d4-4b80-9f55-fc0766c184db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066261108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2066261108
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3729688711
Short name T920
Test name
Test status
Simulation time 22768816 ps
CPU time 0.72 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:01:48 PM PDT 24
Peak memory 205576 kb
Host smart-53fb5ef8-5da9-4234-b695-658f2b4ad62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729688711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3729688711
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.114429214
Short name T1035
Test name
Test status
Simulation time 159073173 ps
CPU time 3.54 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 206096 kb
Host smart-4d985207-042e-4d20-a600-7435b9b694ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114429214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.114429214
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.565717890
Short name T941
Test name
Test status
Simulation time 49761381 ps
CPU time 1.86 seconds
Started Jun 21 05:01:48 PM PDT 24
Finished Jun 21 05:01:52 PM PDT 24
Peak memory 214468 kb
Host smart-dcdd21a6-a161-4cd3-801b-6c035341f430
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565717890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.565717890
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3889635216
Short name T1032
Test name
Test status
Simulation time 112758836 ps
CPU time 4.07 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 213844 kb
Host smart-9c440825-0191-487e-ae15-22f1b529db39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889635216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3889635216
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1077887492
Short name T1058
Test name
Test status
Simulation time 137795843 ps
CPU time 4.92 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:01:53 PM PDT 24
Peak memory 216456 kb
Host smart-325c9c23-a586-491d-9dca-cd17c31fad00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077887492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1077887492
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3197336563
Short name T1071
Test name
Test status
Simulation time 124569095 ps
CPU time 1.38 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 214252 kb
Host smart-d565b6d2-76a6-4f75-bee2-b737f5627cd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197336563 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3197336563
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2284757451
Short name T999
Test name
Test status
Simulation time 19850302 ps
CPU time 1.25 seconds
Started Jun 21 05:01:48 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 205880 kb
Host smart-fa8342ad-5570-49aa-a691-1ea07a6eedf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284757451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2284757451
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1821551775
Short name T1016
Test name
Test status
Simulation time 44997228 ps
CPU time 0.79 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205540 kb
Host smart-61a402e5-f74c-430b-bd6f-d362a7a2e85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821551775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1821551775
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1929730551
Short name T983
Test name
Test status
Simulation time 301377461 ps
CPU time 1.53 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 205896 kb
Host smart-e3c971a0-f26a-493b-9dfb-b0d31c546cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929730551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1929730551
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2013012228
Short name T927
Test name
Test status
Simulation time 88122010 ps
CPU time 3.22 seconds
Started Jun 21 05:02:01 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 214048 kb
Host smart-f3286f0b-913c-461f-8f71-cfe9f06faaab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013012228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2013012228
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.807826085
Short name T176
Test name
Test status
Simulation time 179256780 ps
CPU time 6.4 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:05 PM PDT 24
Peak memory 215280 kb
Host smart-d6801f0b-d058-4e92-84e6-511ce1aa2337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807826085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.807826085
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2908519323
Short name T1070
Test name
Test status
Simulation time 48479156 ps
CPU time 1.19 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205944 kb
Host smart-06d77baf-d9e1-472b-a7fa-62f21b608d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908519323 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2908519323
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1413370454
Short name T985
Test name
Test status
Simulation time 25156700 ps
CPU time 1.04 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 205684 kb
Host smart-421696a1-0d9a-4ed9-954e-44ec00238abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413370454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1413370454
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.879247071
Short name T1049
Test name
Test status
Simulation time 20460702 ps
CPU time 0.74 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205580 kb
Host smart-9aa8e152-b0b3-4881-b843-03d56c6d3b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879247071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.879247071
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.611901792
Short name T1064
Test name
Test status
Simulation time 86519786 ps
CPU time 1.36 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 205940 kb
Host smart-28c41032-797d-449f-96b2-ddc2f457c2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611901792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.611901792
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1043781584
Short name T945
Test name
Test status
Simulation time 1195537203 ps
CPU time 2.31 seconds
Started Jun 21 05:02:01 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 214364 kb
Host smart-51d4ad00-f781-494b-83b4-5088208f3a18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043781584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1043781584
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3502720344
Short name T971
Test name
Test status
Simulation time 86066161 ps
CPU time 3.84 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 214416 kb
Host smart-48fbf35d-7ad8-406d-b141-a09daca2cbb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502720344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3502720344
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3474798213
Short name T1019
Test name
Test status
Simulation time 46051330 ps
CPU time 3.47 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 214016 kb
Host smart-02fbfed5-8a3f-4b46-95de-82a86a92f958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474798213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3474798213
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1191293663
Short name T1034
Test name
Test status
Simulation time 72148872 ps
CPU time 1.97 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 214184 kb
Host smart-6b265869-c982-46db-879d-2bebb98b965e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191293663 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1191293663
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1463356421
Short name T936
Test name
Test status
Simulation time 29529429 ps
CPU time 1.3 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205804 kb
Host smart-a6d122e4-3490-4c02-abe4-931bc64a8722
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463356421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1463356421
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3590008687
Short name T921
Test name
Test status
Simulation time 10707788 ps
CPU time 0.74 seconds
Started Jun 21 05:01:48 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 205572 kb
Host smart-4edee8f6-6daf-4545-8900-9895ce4376d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590008687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3590008687
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1672728186
Short name T1053
Test name
Test status
Simulation time 23491649 ps
CPU time 1.45 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 205852 kb
Host smart-ca6481b1-08de-41df-8608-b5c4c216a1a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672728186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1672728186
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2335897532
Short name T932
Test name
Test status
Simulation time 144804738 ps
CPU time 3.11 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 214512 kb
Host smart-e0612f7d-573c-40ee-8f58-c388efe494db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335897532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2335897532
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.140703151
Short name T1086
Test name
Test status
Simulation time 194908545 ps
CPU time 6.88 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 214368 kb
Host smart-7eadcd83-a310-4ed8-882c-8c9ab5b6bdaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140703151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.140703151
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2339984908
Short name T931
Test name
Test status
Simulation time 94320563 ps
CPU time 2.29 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 213976 kb
Host smart-7961b079-5cfa-4246-89ad-acc0e52426b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339984908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2339984908
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1252722593
Short name T173
Test name
Test status
Simulation time 229146348 ps
CPU time 9.15 seconds
Started Jun 21 05:01:55 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 214048 kb
Host smart-137540d4-6776-4ec8-9abd-3dec667b671e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252722593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1252722593
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3021145115
Short name T928
Test name
Test status
Simulation time 26919767 ps
CPU time 1.01 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 205768 kb
Host smart-0a228190-36c1-42af-a7de-567534250a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021145115 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3021145115
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2925512716
Short name T987
Test name
Test status
Simulation time 48148457 ps
CPU time 0.94 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 205776 kb
Host smart-62cfc711-67f8-4109-a9c2-4b8328b6a7f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925512716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2925512716
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.483839230
Short name T934
Test name
Test status
Simulation time 19687287 ps
CPU time 0.85 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 205652 kb
Host smart-9aa593dd-954f-4de8-95d4-48cf461e6898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483839230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.483839230
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2210638968
Short name T998
Test name
Test status
Simulation time 39166089 ps
CPU time 2.48 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 205936 kb
Host smart-10f7e9eb-db9b-4dd0-9952-385076416f21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210638968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2210638968
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1421285782
Short name T1005
Test name
Test status
Simulation time 722897019 ps
CPU time 2.74 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 214452 kb
Host smart-3b8c7338-1e6c-4de2-b798-05655dfcb2df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421285782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1421285782
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3291990166
Short name T978
Test name
Test status
Simulation time 1829627330 ps
CPU time 9.67 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 214348 kb
Host smart-a5c2dced-7df6-4ee9-98c6-11f76faec766
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291990166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3291990166
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.163927631
Short name T1001
Test name
Test status
Simulation time 214623009 ps
CPU time 3.93 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 222224 kb
Host smart-1b180e0b-3730-48db-a66c-f90398416336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163927631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.163927631
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2603843377
Short name T992
Test name
Test status
Simulation time 48630169 ps
CPU time 2.22 seconds
Started Jun 21 05:01:55 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 214304 kb
Host smart-7019330a-8d98-4768-b956-da767546791a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603843377 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2603843377
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1471890244
Short name T959
Test name
Test status
Simulation time 39406597 ps
CPU time 0.97 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 205948 kb
Host smart-22779c56-0386-425b-ae3f-37d2160d1ded
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471890244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1471890244
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3093788344
Short name T951
Test name
Test status
Simulation time 11024324 ps
CPU time 0.87 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 204324 kb
Host smart-989afab0-2f50-4aad-ae92-bcf6664b39b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093788344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3093788344
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.482341311
Short name T953
Test name
Test status
Simulation time 210494470 ps
CPU time 1.57 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205796 kb
Host smart-4940daf4-0156-4833-9df7-facb78143d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482341311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.482341311
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3094519854
Short name T938
Test name
Test status
Simulation time 133533531 ps
CPU time 1.36 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 214448 kb
Host smart-a4482d9e-e4e8-497d-8704-f18d3913956b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094519854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3094519854
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2328110765
Short name T1031
Test name
Test status
Simulation time 1235963952 ps
CPU time 14.9 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:21 PM PDT 24
Peak memory 214332 kb
Host smart-a75bf833-df39-4726-83be-1b2f9f65e065
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328110765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2328110765
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.438735204
Short name T1083
Test name
Test status
Simulation time 175216560 ps
CPU time 1.92 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 214116 kb
Host smart-36328a8e-2e6e-483d-bf4a-a4e9c651d289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438735204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.438735204
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3000531908
Short name T965
Test name
Test status
Simulation time 128803765 ps
CPU time 1.52 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 205976 kb
Host smart-b4001652-c0f2-41bf-961d-981bb67a61f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000531908 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3000531908
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2010092344
Short name T146
Test name
Test status
Simulation time 57879185 ps
CPU time 1.13 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205892 kb
Host smart-f39428a8-1a52-4944-a058-b66148472031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010092344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2010092344
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1507814929
Short name T1007
Test name
Test status
Simulation time 34220836 ps
CPU time 0.85 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 205508 kb
Host smart-4c215860-f682-41f5-b76c-d0593c2a2a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507814929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1507814929
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.44186707
Short name T1036
Test name
Test status
Simulation time 20928771 ps
CPU time 1.24 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 206076 kb
Host smart-d58cb04c-137c-4093-a505-dacc69fdcd91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44186707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sam
e_csr_outstanding.44186707
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1815536023
Short name T1004
Test name
Test status
Simulation time 1072562270 ps
CPU time 2.22 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 214452 kb
Host smart-ad438e88-deaa-4539-8f5f-d7424c0a46e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815536023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1815536023
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3635852122
Short name T977
Test name
Test status
Simulation time 292268489 ps
CPU time 3.7 seconds
Started Jun 21 05:01:49 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 214472 kb
Host smart-fea227a2-7c7b-4d7f-8737-397618d2cc3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635852122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3635852122
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1899914963
Short name T984
Test name
Test status
Simulation time 55493663 ps
CPU time 1.73 seconds
Started Jun 21 05:01:47 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 214108 kb
Host smart-f9a68a2f-a956-4e7f-8cb2-b15f8d2f0af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899914963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1899914963
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3812482486
Short name T163
Test name
Test status
Simulation time 111828719 ps
CPU time 3.85 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 212860 kb
Host smart-600bc275-c907-4713-9956-282de09c8148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812482486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3812482486
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2398360931
Short name T994
Test name
Test status
Simulation time 99648445 ps
CPU time 1.7 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 222336 kb
Host smart-0e550156-f909-4114-9d42-1adaeffa541d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398360931 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2398360931
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2582273405
Short name T148
Test name
Test status
Simulation time 53717332 ps
CPU time 1.47 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205868 kb
Host smart-a46d1cda-c512-4447-ab3b-9a3ab72de80b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582273405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2582273405
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1457799513
Short name T960
Test name
Test status
Simulation time 11470858 ps
CPU time 0.75 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205600 kb
Host smart-9b4c1294-f89c-45a3-bfbf-1867dec72f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457799513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1457799513
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.522935871
Short name T1050
Test name
Test status
Simulation time 24445652 ps
CPU time 1.72 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 204792 kb
Host smart-abf3d938-3357-4900-9cdd-3ce93ff6fa4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522935871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.522935871
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1049095990
Short name T125
Test name
Test status
Simulation time 114310534 ps
CPU time 1.88 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 214632 kb
Host smart-29ea472c-592f-4b9e-b567-493c69cd40da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049095990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1049095990
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2990617275
Short name T1039
Test name
Test status
Simulation time 382927287 ps
CPU time 8.58 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 214588 kb
Host smart-d567e5e6-de82-4ecf-ad14-803299d46b02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990617275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2990617275
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4286906051
Short name T1082
Test name
Test status
Simulation time 77653030 ps
CPU time 2.93 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 215136 kb
Host smart-de889829-2e10-431d-afd5-3813bc9de573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286906051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4286906051
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2288482188
Short name T154
Test name
Test status
Simulation time 99558137 ps
CPU time 2.74 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 205944 kb
Host smart-b8da0f17-0496-4c84-8a07-632292ff4bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288482188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2288482188
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2054334873
Short name T943
Test name
Test status
Simulation time 48785762 ps
CPU time 1.12 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 206020 kb
Host smart-faf202d6-f818-48fd-98b7-0afa62ac7610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054334873 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2054334873
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1286855454
Short name T147
Test name
Test status
Simulation time 88556361 ps
CPU time 1.05 seconds
Started Jun 21 05:01:57 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 205656 kb
Host smart-12d15a7b-7e29-426d-82cc-2866903e2078
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286855454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1286855454
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2107978751
Short name T930
Test name
Test status
Simulation time 116008987 ps
CPU time 0.72 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 205660 kb
Host smart-debaeecb-9d6c-4ab5-a680-594943294451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107978751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2107978751
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.728739519
Short name T1047
Test name
Test status
Simulation time 36060329 ps
CPU time 2.45 seconds
Started Jun 21 05:01:59 PM PDT 24
Finished Jun 21 05:02:05 PM PDT 24
Peak memory 205772 kb
Host smart-8231ae3d-6059-4fdd-b49d-6993e633732c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728739519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.728739519
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.970114178
Short name T1038
Test name
Test status
Simulation time 198514147 ps
CPU time 2.81 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 214632 kb
Host smart-6d03d50c-0878-4148-adaf-254ab5ff7600
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970114178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.970114178
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3029319961
Short name T1009
Test name
Test status
Simulation time 1474733689 ps
CPU time 13.77 seconds
Started Jun 21 05:02:08 PM PDT 24
Finished Jun 21 05:02:27 PM PDT 24
Peak memory 220976 kb
Host smart-07bb888c-9682-4d6c-89d7-f8229d4aff9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029319961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3029319961
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3859445278
Short name T1000
Test name
Test status
Simulation time 22319783 ps
CPU time 1.63 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:10 PM PDT 24
Peak memory 214160 kb
Host smart-19432d0d-1226-4b46-9fc7-df63991d8e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859445278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3859445278
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1725785301
Short name T159
Test name
Test status
Simulation time 88597436 ps
CPU time 1.44 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 214208 kb
Host smart-365106ff-3e55-4b30-ae24-6b250dcbe4c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725785301 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1725785301
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2363246469
Short name T1033
Test name
Test status
Simulation time 12546456 ps
CPU time 1.08 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 205872 kb
Host smart-f4cb8f05-07c1-45f2-aeb8-20780e3fa198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363246469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2363246469
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3402156259
Short name T1021
Test name
Test status
Simulation time 74511672 ps
CPU time 0.74 seconds
Started Jun 21 05:01:59 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 205500 kb
Host smart-7d3acfa2-22ae-4658-b218-22419fe031a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402156259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3402156259
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4114284841
Short name T996
Test name
Test status
Simulation time 94473617 ps
CPU time 1.26 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 205980 kb
Host smart-9b36d2f0-da27-4788-bedf-6be98bf6bcfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114284841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4114284841
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2050648533
Short name T119
Test name
Test status
Simulation time 174952759 ps
CPU time 2.51 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:10 PM PDT 24
Peak memory 214392 kb
Host smart-43bbc28d-3bc6-4388-a85e-8f1bcde57acf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050648533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2050648533
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2969762751
Short name T120
Test name
Test status
Simulation time 295460842 ps
CPU time 3.79 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:14 PM PDT 24
Peak memory 214372 kb
Host smart-d350e7f0-1c33-4288-a5fc-02032448b956
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969762751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2969762751
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.799692448
Short name T1044
Test name
Test status
Simulation time 64223861 ps
CPU time 2.26 seconds
Started Jun 21 05:02:01 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 214104 kb
Host smart-3ec7d285-4227-4261-b6fd-c0267718790e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799692448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.799692448
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1261629725
Short name T182
Test name
Test status
Simulation time 760380750 ps
CPU time 8.05 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:13 PM PDT 24
Peak memory 214136 kb
Host smart-70738631-4814-4344-aa5a-bbf7c0046c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261629725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1261629725
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1767876812
Short name T952
Test name
Test status
Simulation time 103506583 ps
CPU time 1.46 seconds
Started Jun 21 05:02:06 PM PDT 24
Finished Jun 21 05:02:13 PM PDT 24
Peak memory 216540 kb
Host smart-e6b4a5fb-ee5c-4cd8-8a3b-43769b554334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767876812 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1767876812
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3360185242
Short name T1003
Test name
Test status
Simulation time 81438059 ps
CPU time 1.18 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 205948 kb
Host smart-842ec5ae-5902-453e-8add-ab13978decee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360185242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3360185242
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.513329695
Short name T991
Test name
Test status
Simulation time 21613294 ps
CPU time 0.83 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 205660 kb
Host smart-349ed44c-972f-49d7-9bdf-546f9df771ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513329695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.513329695
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1787462507
Short name T1072
Test name
Test status
Simulation time 27774586 ps
CPU time 1.4 seconds
Started Jun 21 05:02:08 PM PDT 24
Finished Jun 21 05:02:14 PM PDT 24
Peak memory 206044 kb
Host smart-6a73d5f7-8b56-40bc-b17c-33ee0b602f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787462507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1787462507
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2071574811
Short name T122
Test name
Test status
Simulation time 93169373 ps
CPU time 2.79 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 218824 kb
Host smart-5cf18097-4276-44f6-8650-b506a256ee67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071574811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2071574811
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3410386054
Short name T151
Test name
Test status
Simulation time 432995916 ps
CPU time 8.15 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:16 PM PDT 24
Peak memory 214368 kb
Host smart-426cef6b-69cc-42e9-a6a4-0b8b7278fab3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410386054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3410386054
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2691545482
Short name T922
Test name
Test status
Simulation time 314729161 ps
CPU time 2.32 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 214044 kb
Host smart-bc48407c-48d6-4f3b-8828-d333afe149a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691545482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2691545482
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2666755980
Short name T175
Test name
Test status
Simulation time 447547899 ps
CPU time 3.89 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 215344 kb
Host smart-a7dcae87-bde5-45b3-8e51-9cf8d68d7bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666755980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2666755980
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3763158809
Short name T1012
Test name
Test status
Simulation time 260187537 ps
CPU time 7.95 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:02:05 PM PDT 24
Peak memory 205944 kb
Host smart-27cf601e-8016-4af9-b8e2-de63b1b3e1d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763158809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
763158809
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1695032881
Short name T956
Test name
Test status
Simulation time 4462862578 ps
CPU time 16.14 seconds
Started Jun 21 05:01:41 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 205956 kb
Host smart-b1696179-9041-49b3-ae24-f54faf220678
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695032881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
695032881
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.735452496
Short name T986
Test name
Test status
Simulation time 14529895 ps
CPU time 1.16 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:01:49 PM PDT 24
Peak memory 205960 kb
Host smart-ab8660cd-8c24-46fd-840a-a17f0470fa4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735452496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.735452496
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.366011294
Short name T1081
Test name
Test status
Simulation time 98318014 ps
CPU time 1.6 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:43 PM PDT 24
Peak memory 214200 kb
Host smart-29f3fe38-297f-4ea4-aead-fb81b4c4d253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366011294 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.366011294
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1735502897
Short name T1087
Test name
Test status
Simulation time 19199865 ps
CPU time 0.91 seconds
Started Jun 21 05:01:41 PM PDT 24
Finished Jun 21 05:01:44 PM PDT 24
Peak memory 205536 kb
Host smart-0f21adfd-185d-4d1e-abbc-aaf8e585994e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735502897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1735502897
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1896111964
Short name T1026
Test name
Test status
Simulation time 35259381 ps
CPU time 0.69 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:42 PM PDT 24
Peak memory 205660 kb
Host smart-6bf906f8-c462-44d7-9320-9fddb74982ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896111964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1896111964
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1054884469
Short name T1062
Test name
Test status
Simulation time 65088599 ps
CPU time 1.84 seconds
Started Jun 21 05:01:38 PM PDT 24
Finished Jun 21 05:01:42 PM PDT 24
Peak memory 205884 kb
Host smart-fd1fd0ed-ac1b-4b8d-9e5a-d4ac83674c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054884469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1054884469
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1808847473
Short name T126
Test name
Test status
Simulation time 209159549 ps
CPU time 3.06 seconds
Started Jun 21 05:01:38 PM PDT 24
Finished Jun 21 05:01:43 PM PDT 24
Peak memory 214520 kb
Host smart-a538bfe9-5189-4bed-b9ca-4cc4e1d9d336
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808847473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1808847473
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1025780321
Short name T1028
Test name
Test status
Simulation time 180084882 ps
CPU time 7.35 seconds
Started Jun 21 05:01:40 PM PDT 24
Finished Jun 21 05:01:49 PM PDT 24
Peak memory 220568 kb
Host smart-fb63c90f-e887-4d95-90a1-d07ab6d84906
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025780321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1025780321
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3795154545
Short name T1045
Test name
Test status
Simulation time 72640267 ps
CPU time 2.45 seconds
Started Jun 21 05:01:42 PM PDT 24
Finished Jun 21 05:01:46 PM PDT 24
Peak memory 214032 kb
Host smart-7e57e3ad-2a8e-4fda-adc3-25654165c723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795154545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3795154545
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1386404044
Short name T162
Test name
Test status
Simulation time 113381226 ps
CPU time 3.11 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:44 PM PDT 24
Peak memory 214148 kb
Host smart-0451f5e1-1287-45dd-bc88-1b98eefe5e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386404044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1386404044
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2293341803
Short name T1066
Test name
Test status
Simulation time 18612115 ps
CPU time 0.95 seconds
Started Jun 21 05:01:59 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 205752 kb
Host smart-76ee8ac1-a98c-4f1c-ab53-318590c98cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293341803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2293341803
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3295747452
Short name T1041
Test name
Test status
Simulation time 14589135 ps
CPU time 0.67 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 205592 kb
Host smart-c9ef64c4-cf05-4bed-a3c4-ca5adce1baa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295747452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3295747452
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2018225286
Short name T1069
Test name
Test status
Simulation time 34702784 ps
CPU time 0.91 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 205640 kb
Host smart-ec26810d-2add-47f4-987f-177cf9ce8a99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018225286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2018225286
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1093276604
Short name T1025
Test name
Test status
Simulation time 190674941 ps
CPU time 0.73 seconds
Started Jun 21 05:02:08 PM PDT 24
Finished Jun 21 05:02:13 PM PDT 24
Peak memory 205584 kb
Host smart-7768a993-fc22-4cbc-b877-04e9fe326934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093276604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1093276604
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2425090707
Short name T1010
Test name
Test status
Simulation time 23426836 ps
CPU time 0.71 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 205524 kb
Host smart-09dced52-fbf1-4f0f-984f-08276b1aec09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425090707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2425090707
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2527466721
Short name T962
Test name
Test status
Simulation time 26555901 ps
CPU time 0.72 seconds
Started Jun 21 05:02:08 PM PDT 24
Finished Jun 21 05:02:13 PM PDT 24
Peak memory 205584 kb
Host smart-ab555c2d-d814-439a-80cd-4eedefc3584f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527466721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2527466721
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.824603420
Short name T964
Test name
Test status
Simulation time 11495557 ps
CPU time 0.73 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 205584 kb
Host smart-50c0d00e-7e7e-4f63-b61a-c0799705903f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824603420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.824603420
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1025393003
Short name T1023
Test name
Test status
Simulation time 83908069 ps
CPU time 0.79 seconds
Started Jun 21 05:02:07 PM PDT 24
Finished Jun 21 05:02:12 PM PDT 24
Peak memory 205652 kb
Host smart-8c996964-556c-4e7e-b5f4-ee0086f14da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025393003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1025393003
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1255617675
Short name T1015
Test name
Test status
Simulation time 14888810 ps
CPU time 0.76 seconds
Started Jun 21 05:02:00 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 205684 kb
Host smart-cf2098a2-af83-4abe-8811-3ffcb5f25629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255617675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1255617675
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3272683255
Short name T970
Test name
Test status
Simulation time 19246412 ps
CPU time 0.86 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205640 kb
Host smart-a10f71b8-8ae4-4571-8943-a2421714e386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272683255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3272683255
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1081867127
Short name T946
Test name
Test status
Simulation time 2529513535 ps
CPU time 16.16 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 205912 kb
Host smart-a98601b2-af37-48a6-9831-5233e6e1f330
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081867127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
081867127
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.813602222
Short name T1014
Test name
Test status
Simulation time 135073904 ps
CPU time 7.9 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:48 PM PDT 24
Peak memory 206024 kb
Host smart-83eb773a-3e2d-437b-b610-7c3043650d4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813602222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.813602222
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3245834068
Short name T201
Test name
Test status
Simulation time 24556905 ps
CPU time 0.93 seconds
Started Jun 21 05:01:45 PM PDT 24
Finished Jun 21 05:01:47 PM PDT 24
Peak memory 205764 kb
Host smart-93ac5dc9-76b7-45bb-a1e8-4ae4fbccff81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245834068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
245834068
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.543011638
Short name T969
Test name
Test status
Simulation time 191224560 ps
CPU time 1.25 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:42 PM PDT 24
Peak memory 205996 kb
Host smart-6b89818d-c89b-406a-a5ac-b2f07f2e3dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543011638 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.543011638
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3074032105
Short name T149
Test name
Test status
Simulation time 83419505 ps
CPU time 1.16 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:54 PM PDT 24
Peak memory 205876 kb
Host smart-af0126fd-53c5-43bc-bd1d-830bdf914de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074032105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3074032105
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3043754937
Short name T1030
Test name
Test status
Simulation time 180642538 ps
CPU time 0.83 seconds
Started Jun 21 05:01:40 PM PDT 24
Finished Jun 21 05:01:43 PM PDT 24
Peak memory 205660 kb
Host smart-a9ac744a-4c7f-4d1f-ab0d-bc554307a0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043754937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3043754937
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3146691390
Short name T954
Test name
Test status
Simulation time 139908401 ps
CPU time 2.11 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 206020 kb
Host smart-0d1ba0ea-1e43-49b4-9e7b-c31956364e59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146691390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3146691390
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.251396777
Short name T990
Test name
Test status
Simulation time 76277235 ps
CPU time 1.87 seconds
Started Jun 21 05:01:37 PM PDT 24
Finished Jun 21 05:01:41 PM PDT 24
Peak memory 214460 kb
Host smart-fdfbc28e-4eaf-486a-858f-bcbdce0b52dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251396777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.251396777
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2433635016
Short name T967
Test name
Test status
Simulation time 361193606 ps
CPU time 5.59 seconds
Started Jun 21 05:01:43 PM PDT 24
Finished Jun 21 05:01:50 PM PDT 24
Peak memory 214284 kb
Host smart-691e4c32-7e2f-4222-87e0-d5ea242909a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433635016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2433635016
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2624565150
Short name T1075
Test name
Test status
Simulation time 109701060 ps
CPU time 4.17 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 214020 kb
Host smart-603468b6-e3d3-4caa-8776-c789cf0291ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624565150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2624565150
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2736278674
Short name T1040
Test name
Test status
Simulation time 10303580 ps
CPU time 0.85 seconds
Started Jun 21 05:02:00 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 205596 kb
Host smart-86d3eea6-4aaa-48c0-9569-0047b3c6bf1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736278674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2736278674
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.897549138
Short name T1024
Test name
Test status
Simulation time 96652155 ps
CPU time 0.78 seconds
Started Jun 21 05:02:00 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 205640 kb
Host smart-8ba76988-1552-4b3d-bbf4-999ee92deeca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897549138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.897549138
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3528954363
Short name T1048
Test name
Test status
Simulation time 9924764 ps
CPU time 0.72 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205660 kb
Host smart-7f48cef7-75ec-4ac3-95b7-f52bff7837f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528954363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3528954363
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3624355781
Short name T1052
Test name
Test status
Simulation time 35366254 ps
CPU time 0.83 seconds
Started Jun 21 05:02:07 PM PDT 24
Finished Jun 21 05:02:12 PM PDT 24
Peak memory 205652 kb
Host smart-7a85dec6-b22c-4c09-a5f6-3443df09a5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624355781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3624355781
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1676860354
Short name T1022
Test name
Test status
Simulation time 22584173 ps
CPU time 0.86 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 205676 kb
Host smart-268f44b4-b2bf-4290-860e-6a6d113b41df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676860354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1676860354
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2754676827
Short name T989
Test name
Test status
Simulation time 8804195 ps
CPU time 0.81 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205584 kb
Host smart-2871a4bb-6d5e-4176-a00a-1597c05ed9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754676827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2754676827
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2429002778
Short name T974
Test name
Test status
Simulation time 67519740 ps
CPU time 0.75 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205668 kb
Host smart-71fbe7e2-aa20-4559-b8d3-63929c527a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429002778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2429002778
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1367328794
Short name T1057
Test name
Test status
Simulation time 10451272 ps
CPU time 0.83 seconds
Started Jun 21 05:02:04 PM PDT 24
Finished Jun 21 05:02:09 PM PDT 24
Peak memory 205660 kb
Host smart-aa63f227-aaa3-4793-8fa0-6e7fe025f0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367328794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1367328794
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.140748547
Short name T955
Test name
Test status
Simulation time 23183276 ps
CPU time 0.79 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205688 kb
Host smart-d2b00b93-36a5-4433-9772-090addcb0c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140748547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.140748547
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3787332766
Short name T1080
Test name
Test status
Simulation time 46933721 ps
CPU time 0.9 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 205660 kb
Host smart-996a56f1-06cb-419e-84a3-b103d16f6bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787332766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3787332766
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1743537053
Short name T937
Test name
Test status
Simulation time 138003876 ps
CPU time 4.34 seconds
Started Jun 21 05:01:49 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 205960 kb
Host smart-14ce84e3-d83b-4108-9d1c-8140cd1bebb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743537053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
743537053
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1963643060
Short name T949
Test name
Test status
Simulation time 258072916 ps
CPU time 12.01 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:02:05 PM PDT 24
Peak memory 206040 kb
Host smart-067c1726-f35f-486d-860a-291a94c8075a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963643060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
963643060
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3170677883
Short name T947
Test name
Test status
Simulation time 70433799 ps
CPU time 0.97 seconds
Started Jun 21 05:01:43 PM PDT 24
Finished Jun 21 05:01:45 PM PDT 24
Peak memory 205772 kb
Host smart-ba3996ca-e650-4723-85fd-45da077f7faf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170677883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
170677883
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2111008639
Short name T1046
Test name
Test status
Simulation time 112430261 ps
CPU time 1.28 seconds
Started Jun 21 05:01:49 PM PDT 24
Finished Jun 21 05:01:54 PM PDT 24
Peak memory 214252 kb
Host smart-c1edd1e7-53fd-4257-9f11-63d8c4c1f2c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111008639 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2111008639
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2548337269
Short name T961
Test name
Test status
Simulation time 32722492 ps
CPU time 1.11 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 205692 kb
Host smart-6702cb1f-77fe-41ca-a967-84ea6ab7731f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548337269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2548337269
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.718303285
Short name T1027
Test name
Test status
Simulation time 28543723 ps
CPU time 0.86 seconds
Started Jun 21 05:01:38 PM PDT 24
Finished Jun 21 05:01:41 PM PDT 24
Peak memory 205644 kb
Host smart-c16592a8-84e3-4753-8cb4-7ed0c70f3dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718303285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.718303285
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4229890902
Short name T1017
Test name
Test status
Simulation time 49924177 ps
CPU time 1.73 seconds
Started Jun 21 05:01:49 PM PDT 24
Finished Jun 21 05:01:54 PM PDT 24
Peak memory 205964 kb
Host smart-2931c725-8915-4e96-acf6-53b35708dd55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229890902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4229890902
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3919648698
Short name T966
Test name
Test status
Simulation time 190316787 ps
CPU time 2.46 seconds
Started Jun 21 05:01:45 PM PDT 24
Finished Jun 21 05:01:49 PM PDT 24
Peak memory 214540 kb
Host smart-1ba7b474-fc79-4cc6-97de-0706a5adf867
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919648698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3919648698
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.329883550
Short name T1078
Test name
Test status
Simulation time 1332031663 ps
CPU time 9.42 seconds
Started Jun 21 05:01:44 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 214512 kb
Host smart-b7226534-bb38-4099-b940-41d20121d9f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329883550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.329883550
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4100381544
Short name T1056
Test name
Test status
Simulation time 806909619 ps
CPU time 3.52 seconds
Started Jun 21 05:01:44 PM PDT 24
Finished Jun 21 05:01:48 PM PDT 24
Peak memory 216260 kb
Host smart-41845ca9-ca68-4405-aa36-a1fc50a5167f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100381544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.4100381544
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2218733636
Short name T174
Test name
Test status
Simulation time 511587751 ps
CPU time 7.44 seconds
Started Jun 21 05:01:47 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 214144 kb
Host smart-e8367617-641a-4a77-8a47-c49693c26522
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218733636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2218733636
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3938392037
Short name T968
Test name
Test status
Simulation time 17582927 ps
CPU time 0.81 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:10 PM PDT 24
Peak memory 205516 kb
Host smart-921ee05d-aab7-43bb-b9f4-9341b7ef46c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938392037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3938392037
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2618797629
Short name T1067
Test name
Test status
Simulation time 26696142 ps
CPU time 0.79 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:10 PM PDT 24
Peak memory 205488 kb
Host smart-3b9431fa-ffaf-4a8c-b067-b1bbe835c26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618797629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2618797629
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4172998042
Short name T1063
Test name
Test status
Simulation time 42830052 ps
CPU time 0.81 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 205516 kb
Host smart-8adf6ce6-91dc-4ad5-acca-7eabe71ec77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172998042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4172998042
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4003650795
Short name T995
Test name
Test status
Simulation time 74184570 ps
CPU time 0.79 seconds
Started Jun 21 05:02:06 PM PDT 24
Finished Jun 21 05:02:12 PM PDT 24
Peak memory 205600 kb
Host smart-147e3e80-0c77-4f05-8923-1849205dff33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003650795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4003650795
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.893800667
Short name T950
Test name
Test status
Simulation time 13469129 ps
CPU time 0.73 seconds
Started Jun 21 05:02:06 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 205600 kb
Host smart-72477cbe-c214-4259-8449-3565cb97126b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893800667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.893800667
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.906815508
Short name T925
Test name
Test status
Simulation time 25731627 ps
CPU time 0.84 seconds
Started Jun 21 05:02:02 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 205660 kb
Host smart-8e3b8ab7-3768-426d-828d-53c1156eb47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906815508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.906815508
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3596528714
Short name T933
Test name
Test status
Simulation time 22559059 ps
CPU time 0.84 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:11 PM PDT 24
Peak memory 205668 kb
Host smart-27a0a426-a69e-4de2-9c6f-465c529274cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596528714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3596528714
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1301944500
Short name T935
Test name
Test status
Simulation time 9415560 ps
CPU time 0.82 seconds
Started Jun 21 05:02:08 PM PDT 24
Finished Jun 21 05:02:14 PM PDT 24
Peak memory 205592 kb
Host smart-3e43f93d-1cfd-4e6c-ac70-9d1547ad9d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301944500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1301944500
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2990437727
Short name T948
Test name
Test status
Simulation time 192548869 ps
CPU time 0.84 seconds
Started Jun 21 05:02:03 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 205600 kb
Host smart-e5181d26-fe35-4e27-9a23-2b1a8cce7fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990437727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2990437727
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3664684842
Short name T1043
Test name
Test status
Simulation time 17782916 ps
CPU time 0.72 seconds
Started Jun 21 05:02:05 PM PDT 24
Finished Jun 21 05:02:10 PM PDT 24
Peak memory 205656 kb
Host smart-6dfd141d-d6e1-42ec-9422-e8b117b7561f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664684842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3664684842
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.137909049
Short name T1077
Test name
Test status
Simulation time 185972463 ps
CPU time 2.04 seconds
Started Jun 21 05:01:45 PM PDT 24
Finished Jun 21 05:01:48 PM PDT 24
Peak memory 214200 kb
Host smart-fc17d600-17de-47bf-871f-98e62e9235dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137909049 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.137909049
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.13024034
Short name T1018
Test name
Test status
Simulation time 21318316 ps
CPU time 0.96 seconds
Started Jun 21 05:01:48 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 205616 kb
Host smart-34173e5f-72d5-4983-b841-2b11ff95b57a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13024034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.13024034
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.727994274
Short name T1051
Test name
Test status
Simulation time 13916775 ps
CPU time 0.9 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:54 PM PDT 24
Peak memory 205780 kb
Host smart-cd20a022-c895-4b8a-9c87-d3b670a8dcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727994274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.727994274
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1073133721
Short name T145
Test name
Test status
Simulation time 162150528 ps
CPU time 1.68 seconds
Started Jun 21 05:01:41 PM PDT 24
Finished Jun 21 05:01:44 PM PDT 24
Peak memory 206008 kb
Host smart-f4ddae34-3f78-4f3b-9109-cd7d06706627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073133721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1073133721
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4030522794
Short name T1037
Test name
Test status
Simulation time 152235699 ps
CPU time 3.77 seconds
Started Jun 21 05:01:39 PM PDT 24
Finished Jun 21 05:01:45 PM PDT 24
Peak memory 214352 kb
Host smart-0deb3d4d-91c3-457f-acca-00d9620bcd4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030522794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4030522794
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2972337883
Short name T944
Test name
Test status
Simulation time 830642973 ps
CPU time 8.61 seconds
Started Jun 21 05:01:40 PM PDT 24
Finished Jun 21 05:01:50 PM PDT 24
Peak memory 214512 kb
Host smart-aac3c86c-d44d-4f18-9204-cd5ca1ae0a8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972337883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2972337883
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1480842250
Short name T958
Test name
Test status
Simulation time 31093924 ps
CPU time 1.83 seconds
Started Jun 21 05:01:44 PM PDT 24
Finished Jun 21 05:01:47 PM PDT 24
Peak memory 214104 kb
Host smart-646594a6-7fa5-491b-9734-d63b0fa3ee11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480842250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1480842250
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1022288930
Short name T179
Test name
Test status
Simulation time 122939338 ps
CPU time 2.85 seconds
Started Jun 21 05:01:46 PM PDT 24
Finished Jun 21 05:01:50 PM PDT 24
Peak memory 214156 kb
Host smart-e679afa8-4ba3-4c19-88fb-7290bdd6ae01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022288930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1022288930
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1007879139
Short name T1054
Test name
Test status
Simulation time 266687571 ps
CPU time 1.5 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 213640 kb
Host smart-e65c0790-ff0f-4a24-9315-7d18c7ad5095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007879139 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1007879139
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4183146292
Short name T1065
Test name
Test status
Simulation time 55888235 ps
CPU time 1.08 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:54 PM PDT 24
Peak memory 205940 kb
Host smart-41298981-40e6-4949-be22-5383427200e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183146292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4183146292
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3451632895
Short name T1060
Test name
Test status
Simulation time 36588054 ps
CPU time 0.84 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 205576 kb
Host smart-fcf9732a-4a39-4494-ada5-6a180f2f84a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451632895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3451632895
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1575718552
Short name T957
Test name
Test status
Simulation time 112475913 ps
CPU time 2.5 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 205924 kb
Host smart-786c6df1-e585-43df-a319-e66f3d1b19a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575718552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1575718552
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3821349184
Short name T942
Test name
Test status
Simulation time 109860598 ps
CPU time 1.88 seconds
Started Jun 21 05:01:40 PM PDT 24
Finished Jun 21 05:01:43 PM PDT 24
Peak memory 214436 kb
Host smart-4de458a5-2a7b-4025-9b48-d842b7eb7a3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821349184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3821349184
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.229950369
Short name T972
Test name
Test status
Simulation time 126833252 ps
CPU time 4.07 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 214460 kb
Host smart-bb88dc37-62bc-49a3-85ea-469abf05521a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229950369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.229950369
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3548010123
Short name T980
Test name
Test status
Simulation time 195266304 ps
CPU time 2.31 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 214020 kb
Host smart-9e2ce0a4-c995-432d-b72d-1d6cd7fed82a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548010123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3548010123
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.429057061
Short name T1085
Test name
Test status
Simulation time 212807605 ps
CPU time 4.45 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 206028 kb
Host smart-85e14732-6c4e-4a8f-9e1f-a4f438c75efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429057061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
429057061
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2004256150
Short name T929
Test name
Test status
Simulation time 147884277 ps
CPU time 1.75 seconds
Started Jun 21 05:01:47 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 214012 kb
Host smart-9adf652e-db2a-4035-af4f-445eedc4a664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004256150 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2004256150
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.703797687
Short name T160
Test name
Test status
Simulation time 133995532 ps
CPU time 0.86 seconds
Started Jun 21 05:01:47 PM PDT 24
Finished Jun 21 05:01:50 PM PDT 24
Peak memory 205728 kb
Host smart-3ac76d9d-387e-4d3c-9d2f-c4845faeef42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703797687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.703797687
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2406801980
Short name T923
Test name
Test status
Simulation time 13975952 ps
CPU time 0.77 seconds
Started Jun 21 05:01:52 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 205580 kb
Host smart-d8b5b063-a35b-4339-9e52-8c3caf469e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406801980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2406801980
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3780826434
Short name T997
Test name
Test status
Simulation time 235309405 ps
CPU time 2.49 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205972 kb
Host smart-d632c1eb-c518-49de-ab30-cbd96040b9fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780826434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3780826434
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1800209246
Short name T1059
Test name
Test status
Simulation time 337256047 ps
CPU time 2.01 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:55 PM PDT 24
Peak memory 214564 kb
Host smart-6bfa8997-8433-4436-a39c-416e267ab3e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800209246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1800209246
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2747853372
Short name T973
Test name
Test status
Simulation time 172917264 ps
CPU time 7.08 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 220528 kb
Host smart-fd12c3a9-185c-43c4-b75e-38df87b70b00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747853372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2747853372
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1685889299
Short name T200
Test name
Test status
Simulation time 339864945 ps
CPU time 3.78 seconds
Started Jun 21 05:01:47 PM PDT 24
Finished Jun 21 05:01:52 PM PDT 24
Peak memory 214160 kb
Host smart-d4419a59-aa85-426c-b89d-f2f4010658ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685889299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1685889299
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1081480632
Short name T184
Test name
Test status
Simulation time 430304078 ps
CPU time 3.85 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 214068 kb
Host smart-788c8016-20cd-47cb-bf87-56b1f53bde51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081480632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1081480632
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3320759827
Short name T1011
Test name
Test status
Simulation time 53325089 ps
CPU time 1.17 seconds
Started Jun 21 05:01:55 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 205964 kb
Host smart-762df629-2a8d-41f0-8897-fcb885925fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320759827 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3320759827
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1123962815
Short name T1061
Test name
Test status
Simulation time 14635543 ps
CPU time 1.08 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:01:59 PM PDT 24
Peak memory 205972 kb
Host smart-b8814fbe-120a-4491-ab69-1f3b83365a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123962815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1123962815
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4220964802
Short name T1020
Test name
Test status
Simulation time 9512942 ps
CPU time 0.8 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 205524 kb
Host smart-51d70807-3109-40c6-83a2-48cc1a309b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220964802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4220964802
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1230692009
Short name T976
Test name
Test status
Simulation time 55103930 ps
CPU time 1.5 seconds
Started Jun 21 05:01:57 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 205912 kb
Host smart-5b1a0ef6-a110-4bd3-ba6e-074bab675960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230692009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1230692009
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1721743425
Short name T1074
Test name
Test status
Simulation time 323882076 ps
CPU time 2.77 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:01 PM PDT 24
Peak memory 214372 kb
Host smart-15e47866-6506-4278-bc18-9e0005504b7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721743425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1721743425
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4011096639
Short name T981
Test name
Test status
Simulation time 333306793 ps
CPU time 5.72 seconds
Started Jun 21 05:01:53 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 214452 kb
Host smart-0c9b9567-7e1a-44f0-bebf-303e15153942
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011096639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4011096639
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.287506655
Short name T1084
Test name
Test status
Simulation time 891472087 ps
CPU time 3.32 seconds
Started Jun 21 05:01:54 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 213940 kb
Host smart-6b26da0e-14ff-42d0-ba0e-a0d328d8e2e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287506655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.287506655
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3703301334
Short name T1006
Test name
Test status
Simulation time 144704320 ps
CPU time 1.7 seconds
Started Jun 21 05:01:51 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 214132 kb
Host smart-93f74624-9314-4875-98d3-694d0d214f0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703301334 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3703301334
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1688241175
Short name T926
Test name
Test status
Simulation time 34595528 ps
CPU time 0.94 seconds
Started Jun 21 05:01:48 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 205776 kb
Host smart-f49fb347-8375-4e66-95eb-bb448ca15098
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688241175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1688241175
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.356170341
Short name T993
Test name
Test status
Simulation time 51497495 ps
CPU time 0.94 seconds
Started Jun 21 05:01:55 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 205804 kb
Host smart-58fb4ced-770f-4d64-b360-e2b57297a152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356170341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.356170341
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.978791574
Short name T1073
Test name
Test status
Simulation time 1373892341 ps
CPU time 3.06 seconds
Started Jun 21 05:01:49 PM PDT 24
Finished Jun 21 05:01:54 PM PDT 24
Peak memory 205868 kb
Host smart-452f88a2-eb15-40e2-8181-004304d89f02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978791574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.978791574
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4150128921
Short name T988
Test name
Test status
Simulation time 332671576 ps
CPU time 4.55 seconds
Started Jun 21 05:01:56 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 218792 kb
Host smart-d8b95961-7bc8-41bb-86a7-42c6573ce4f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150128921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4150128921
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.367867117
Short name T152
Test name
Test status
Simulation time 6470192154 ps
CPU time 9.94 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 221168 kb
Host smart-f52bcfbe-35d8-4eca-82a2-2c6d8e7e2e2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367867117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.367867117
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1106599679
Short name T1029
Test name
Test status
Simulation time 53861439 ps
CPU time 3.04 seconds
Started Jun 21 05:01:50 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 214168 kb
Host smart-62ac0ba9-fb79-42c7-ac0d-c05834a5829d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106599679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1106599679
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1941245228
Short name T830
Test name
Test status
Simulation time 36511073 ps
CPU time 0.85 seconds
Started Jun 21 05:38:51 PM PDT 24
Finished Jun 21 05:38:53 PM PDT 24
Peak memory 205840 kb
Host smart-b433e0e9-4bba-4870-99c7-7eb15a03ce3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941245228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1941245228
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3894970800
Short name T299
Test name
Test status
Simulation time 715225156 ps
CPU time 6.55 seconds
Started Jun 21 05:38:42 PM PDT 24
Finished Jun 21 05:38:49 PM PDT 24
Peak memory 214304 kb
Host smart-fcc70705-eaf4-4e96-b6b4-fa2a7808b663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894970800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3894970800
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2673558609
Short name T77
Test name
Test status
Simulation time 233326102 ps
CPU time 2.25 seconds
Started Jun 21 05:38:43 PM PDT 24
Finished Jun 21 05:38:46 PM PDT 24
Peak memory 214284 kb
Host smart-83a90809-3d02-4955-8f3d-4a2e9771f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673558609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2673558609
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2676032593
Short name T863
Test name
Test status
Simulation time 280342437 ps
CPU time 5.19 seconds
Started Jun 21 05:38:50 PM PDT 24
Finished Jun 21 05:38:56 PM PDT 24
Peak memory 209044 kb
Host smart-2212cee8-815f-42a2-af50-c4fe8195d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676032593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2676032593
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.79685642
Short name T240
Test name
Test status
Simulation time 666662520 ps
CPU time 4.01 seconds
Started Jun 21 05:38:56 PM PDT 24
Finished Jun 21 05:39:01 PM PDT 24
Peak memory 219064 kb
Host smart-42817ea1-0d49-43bf-94c8-28b1a095380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79685642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.79685642
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.867748871
Short name T12
Test name
Test status
Simulation time 3902222890 ps
CPU time 5.05 seconds
Started Jun 21 05:38:51 PM PDT 24
Finished Jun 21 05:38:57 PM PDT 24
Peak memory 229464 kb
Host smart-4dab333c-8140-4b6e-8863-86a77364f4b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867748871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.867748871
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3150527390
Short name T771
Test name
Test status
Simulation time 35503920 ps
CPU time 2.55 seconds
Started Jun 21 05:38:42 PM PDT 24
Finished Jun 21 05:38:45 PM PDT 24
Peak memory 208804 kb
Host smart-f6d55562-b036-485c-8b7e-ee25b7971558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150527390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3150527390
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1983432907
Short name T553
Test name
Test status
Simulation time 150680319 ps
CPU time 2.83 seconds
Started Jun 21 05:38:41 PM PDT 24
Finished Jun 21 05:38:45 PM PDT 24
Peak memory 207300 kb
Host smart-11493360-0f71-414b-b88f-9c6083bbaa21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983432907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1983432907
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.151584331
Short name T348
Test name
Test status
Simulation time 133912765 ps
CPU time 5.55 seconds
Started Jun 21 05:38:42 PM PDT 24
Finished Jun 21 05:38:48 PM PDT 24
Peak memory 208712 kb
Host smart-c44615bd-6ca2-47a8-93cb-fb4ba0661025
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151584331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.151584331
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3510952755
Short name T508
Test name
Test status
Simulation time 144465791 ps
CPU time 2.31 seconds
Started Jun 21 05:38:41 PM PDT 24
Finished Jun 21 05:38:44 PM PDT 24
Peak memory 206796 kb
Host smart-d87fc4ef-ffaa-4635-9310-8ad806fbe220
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510952755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3510952755
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2586580221
Short name T321
Test name
Test status
Simulation time 72366631 ps
CPU time 2.28 seconds
Started Jun 21 05:38:56 PM PDT 24
Finished Jun 21 05:38:59 PM PDT 24
Peak memory 214184 kb
Host smart-d7d530b4-4d72-4ce6-ab75-7d71c4065657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586580221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2586580221
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1777657022
Short name T205
Test name
Test status
Simulation time 133389491 ps
CPU time 3.17 seconds
Started Jun 21 05:38:40 PM PDT 24
Finished Jun 21 05:38:43 PM PDT 24
Peak memory 208564 kb
Host smart-034ee804-0952-41f0-9b67-3fb4189440c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777657022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1777657022
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3331254495
Short name T324
Test name
Test status
Simulation time 636052654 ps
CPU time 22.33 seconds
Started Jun 21 05:38:49 PM PDT 24
Finished Jun 21 05:39:12 PM PDT 24
Peak memory 214284 kb
Host smart-d7be8b5b-7244-43f1-9b47-90fba940f2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331254495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3331254495
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1760892319
Short name T115
Test name
Test status
Simulation time 251911525 ps
CPU time 1.78 seconds
Started Jun 21 05:38:51 PM PDT 24
Finished Jun 21 05:38:53 PM PDT 24
Peak memory 209784 kb
Host smart-ed2e3a80-d2fc-4aab-b11f-93c14ed82598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760892319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1760892319
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1354964977
Short name T697
Test name
Test status
Simulation time 32766933 ps
CPU time 0.88 seconds
Started Jun 21 05:39:11 PM PDT 24
Finished Jun 21 05:39:13 PM PDT 24
Peak memory 205948 kb
Host smart-5d601ff1-6074-4f64-be91-95422146e505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354964977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1354964977
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3331368138
Short name T406
Test name
Test status
Simulation time 57300356 ps
CPU time 4.08 seconds
Started Jun 21 05:39:04 PM PDT 24
Finished Jun 21 05:39:09 PM PDT 24
Peak memory 214500 kb
Host smart-ca7d04a5-b2a8-4e7e-a960-5c343d30b1b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331368138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3331368138
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2579006014
Short name T593
Test name
Test status
Simulation time 74372556 ps
CPU time 2.98 seconds
Started Jun 21 05:39:12 PM PDT 24
Finished Jun 21 05:39:16 PM PDT 24
Peak memory 220460 kb
Host smart-7d9443ad-0b35-43ff-831e-aec54f9d0b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579006014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2579006014
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1455687382
Short name T816
Test name
Test status
Simulation time 143932738 ps
CPU time 1.88 seconds
Started Jun 21 05:39:04 PM PDT 24
Finished Jun 21 05:39:06 PM PDT 24
Peak memory 207408 kb
Host smart-fcfd0bc2-f171-4ab5-b7ad-4a4b3e97c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455687382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1455687382
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3249881446
Short name T318
Test name
Test status
Simulation time 66059794 ps
CPU time 2.99 seconds
Started Jun 21 05:39:03 PM PDT 24
Finished Jun 21 05:39:07 PM PDT 24
Peak memory 214344 kb
Host smart-00a8c4bf-e0a0-4062-870c-4e223c49612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249881446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3249881446
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3010963821
Short name T386
Test name
Test status
Simulation time 63929586 ps
CPU time 2.74 seconds
Started Jun 21 05:39:12 PM PDT 24
Finished Jun 21 05:39:16 PM PDT 24
Peak memory 211652 kb
Host smart-1cc99b2a-abb9-4758-a55b-6fba958a14e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010963821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3010963821
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.857236195
Short name T718
Test name
Test status
Simulation time 222983594 ps
CPU time 3.36 seconds
Started Jun 21 05:39:04 PM PDT 24
Finished Jun 21 05:39:08 PM PDT 24
Peak memory 214404 kb
Host smart-43980aac-4cc1-4ca5-8d68-62e6c29c7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857236195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.857236195
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3893468596
Short name T279
Test name
Test status
Simulation time 100013001 ps
CPU time 5.05 seconds
Started Jun 21 05:39:04 PM PDT 24
Finished Jun 21 05:39:09 PM PDT 24
Peak memory 210424 kb
Host smart-e9f33447-bd31-44b8-a2c5-47d3803b8b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893468596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3893468596
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1352385873
Short name T38
Test name
Test status
Simulation time 489432180 ps
CPU time 11.54 seconds
Started Jun 21 05:39:13 PM PDT 24
Finished Jun 21 05:39:25 PM PDT 24
Peak memory 237308 kb
Host smart-c17b4d64-64dd-4abe-8d2e-389c488fac38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352385873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1352385873
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1299753235
Short name T82
Test name
Test status
Simulation time 103219514 ps
CPU time 2.75 seconds
Started Jun 21 05:38:57 PM PDT 24
Finished Jun 21 05:39:00 PM PDT 24
Peak memory 206916 kb
Host smart-7321a47f-3126-4bfb-b766-c8fe23b94a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299753235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1299753235
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4041883114
Short name T364
Test name
Test status
Simulation time 213560815 ps
CPU time 2.93 seconds
Started Jun 21 05:38:56 PM PDT 24
Finished Jun 21 05:39:00 PM PDT 24
Peak memory 208292 kb
Host smart-1cb138fa-97aa-439e-b80c-1a9290c21483
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041883114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4041883114
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3750237129
Short name T523
Test name
Test status
Simulation time 236594015 ps
CPU time 6.25 seconds
Started Jun 21 05:38:55 PM PDT 24
Finished Jun 21 05:39:02 PM PDT 24
Peak memory 207920 kb
Host smart-a6889817-d5cb-4511-8722-b2352164323c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750237129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3750237129
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.988024864
Short name T861
Test name
Test status
Simulation time 141979183 ps
CPU time 5.8 seconds
Started Jun 21 05:39:03 PM PDT 24
Finished Jun 21 05:39:10 PM PDT 24
Peak memory 209064 kb
Host smart-b4199042-73fb-4944-9db5-81aed9e0cc44
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988024864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.988024864
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1551691401
Short name T583
Test name
Test status
Simulation time 751843797 ps
CPU time 12.83 seconds
Started Jun 21 05:39:10 PM PDT 24
Finished Jun 21 05:39:24 PM PDT 24
Peak memory 209004 kb
Host smart-9bc34069-1d80-4871-96fd-959638384fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551691401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1551691401
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1569623278
Short name T752
Test name
Test status
Simulation time 139780524 ps
CPU time 4.32 seconds
Started Jun 21 05:38:57 PM PDT 24
Finished Jun 21 05:39:02 PM PDT 24
Peak memory 207876 kb
Host smart-52b8983a-436f-4605-927e-5defbb894993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569623278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1569623278
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.622758651
Short name T45
Test name
Test status
Simulation time 1430713302 ps
CPU time 43.21 seconds
Started Jun 21 05:39:11 PM PDT 24
Finished Jun 21 05:39:54 PM PDT 24
Peak memory 222524 kb
Host smart-bc833e84-a038-4ff5-89ea-d41620c59551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622758651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.622758651
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1881493077
Short name T73
Test name
Test status
Simulation time 275296219 ps
CPU time 8.63 seconds
Started Jun 21 05:39:13 PM PDT 24
Finished Jun 21 05:39:22 PM PDT 24
Peak memory 222668 kb
Host smart-bd14d641-1e8b-4aab-86b8-79a74679e9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881493077 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1881493077
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2826883504
Short name T682
Test name
Test status
Simulation time 791207643 ps
CPU time 8.52 seconds
Started Jun 21 05:39:04 PM PDT 24
Finished Jun 21 05:39:12 PM PDT 24
Peak memory 208768 kb
Host smart-c8eb6b03-2ff5-436a-a727-72b353fbf960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826883504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2826883504
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2852122965
Short name T736
Test name
Test status
Simulation time 140754999 ps
CPU time 2.26 seconds
Started Jun 21 05:39:12 PM PDT 24
Finished Jun 21 05:39:15 PM PDT 24
Peak memory 210268 kb
Host smart-c467398a-0f1f-48e4-9ff3-3a1a1601fb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852122965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2852122965
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3514490084
Short name T642
Test name
Test status
Simulation time 76824311 ps
CPU time 0.8 seconds
Started Jun 21 05:40:45 PM PDT 24
Finished Jun 21 05:40:46 PM PDT 24
Peak memory 205912 kb
Host smart-990aabe7-3779-446d-9d0c-77ede86944dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514490084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3514490084
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2089942506
Short name T526
Test name
Test status
Simulation time 254892811 ps
CPU time 3.43 seconds
Started Jun 21 05:40:36 PM PDT 24
Finished Jun 21 05:40:41 PM PDT 24
Peak memory 210460 kb
Host smart-da9b936b-87c4-43f9-a6ec-258f1622ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089942506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2089942506
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1201594948
Short name T485
Test name
Test status
Simulation time 138668476 ps
CPU time 4.25 seconds
Started Jun 21 05:40:30 PM PDT 24
Finished Jun 21 05:40:35 PM PDT 24
Peak memory 207736 kb
Host smart-599b9725-df18-4ab1-9bfc-0db6226620b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201594948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1201594948
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1171237868
Short name T284
Test name
Test status
Simulation time 95054127 ps
CPU time 3.53 seconds
Started Jun 21 05:40:36 PM PDT 24
Finished Jun 21 05:40:41 PM PDT 24
Peak memory 214292 kb
Host smart-89ce53ce-7ca8-485a-91b4-71bad7c2ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171237868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1171237868
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1785889695
Short name T558
Test name
Test status
Simulation time 44653353 ps
CPU time 3.25 seconds
Started Jun 21 05:40:32 PM PDT 24
Finished Jun 21 05:40:35 PM PDT 24
Peak memory 220168 kb
Host smart-caee1d05-b1fd-46af-abd4-c4cb59d13628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785889695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1785889695
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3136390399
Short name T360
Test name
Test status
Simulation time 2132303356 ps
CPU time 8.27 seconds
Started Jun 21 05:40:31 PM PDT 24
Finished Jun 21 05:40:40 PM PDT 24
Peak memory 209216 kb
Host smart-0f38f73d-2261-45ce-900b-4529d8204df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136390399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3136390399
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3643019493
Short name T680
Test name
Test status
Simulation time 44151165 ps
CPU time 2.33 seconds
Started Jun 21 05:40:33 PM PDT 24
Finished Jun 21 05:40:36 PM PDT 24
Peak memory 208276 kb
Host smart-b154407e-191a-4146-9d59-c779478abd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643019493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3643019493
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3179071657
Short name T67
Test name
Test status
Simulation time 671389881 ps
CPU time 7.98 seconds
Started Jun 21 05:40:29 PM PDT 24
Finished Jun 21 05:40:38 PM PDT 24
Peak memory 208116 kb
Host smart-75d8a368-163c-4011-9a31-d5a486ca372d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179071657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3179071657
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1485315634
Short name T878
Test name
Test status
Simulation time 66849451 ps
CPU time 2.59 seconds
Started Jun 21 05:40:30 PM PDT 24
Finished Jun 21 05:40:34 PM PDT 24
Peak memory 208652 kb
Host smart-c8ec6ec5-f47e-4ab5-bda6-0f0cbad74791
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485315634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1485315634
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.697095480
Short name T567
Test name
Test status
Simulation time 272794194 ps
CPU time 3.45 seconds
Started Jun 21 05:40:30 PM PDT 24
Finished Jun 21 05:40:35 PM PDT 24
Peak memory 208604 kb
Host smart-c43e30aa-0d13-40a0-9767-90c8f34c2615
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697095480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.697095480
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4156989953
Short name T278
Test name
Test status
Simulation time 33054746 ps
CPU time 2.28 seconds
Started Jun 21 05:40:36 PM PDT 24
Finished Jun 21 05:40:39 PM PDT 24
Peak memory 207348 kb
Host smart-041145f1-b1a5-4a1a-8237-b28e717c35dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156989953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4156989953
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2033525726
Short name T420
Test name
Test status
Simulation time 818968285 ps
CPU time 8.07 seconds
Started Jun 21 05:40:30 PM PDT 24
Finished Jun 21 05:40:39 PM PDT 24
Peak memory 208572 kb
Host smart-fba664dd-89b2-4cff-8b3a-a55acf6c35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033525726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2033525726
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1145474406
Short name T70
Test name
Test status
Simulation time 2782083705 ps
CPU time 30.5 seconds
Started Jun 21 05:40:45 PM PDT 24
Finished Jun 21 05:41:16 PM PDT 24
Peak memory 220792 kb
Host smart-3cd3d670-1d78-4c11-a790-876940576e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145474406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1145474406
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3565321300
Short name T187
Test name
Test status
Simulation time 632467580 ps
CPU time 12.29 seconds
Started Jun 21 05:40:45 PM PDT 24
Finished Jun 21 05:40:58 PM PDT 24
Peak memory 222576 kb
Host smart-4880e1d4-0c00-4097-9e0e-7f2e6a8d2b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565321300 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3565321300
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.873551258
Short name T192
Test name
Test status
Simulation time 53501379 ps
CPU time 2.08 seconds
Started Jun 21 05:40:29 PM PDT 24
Finished Jun 21 05:40:32 PM PDT 24
Peak memory 207756 kb
Host smart-43bb1e24-ba07-4e62-ac05-1b35a65c8163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873551258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.873551258
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4120873572
Short name T858
Test name
Test status
Simulation time 52460416 ps
CPU time 3.73 seconds
Started Jun 21 05:40:36 PM PDT 24
Finished Jun 21 05:40:40 PM PDT 24
Peak memory 214292 kb
Host smart-f4528542-5a13-4264-85c0-bfd0478fef21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120873572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4120873572
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.575159657
Short name T412
Test name
Test status
Simulation time 4276606590 ps
CPU time 11.81 seconds
Started Jun 21 05:40:43 PM PDT 24
Finished Jun 21 05:40:56 PM PDT 24
Peak memory 221344 kb
Host smart-5f1e9ae1-8ba1-487e-93a2-0ff94d6adf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575159657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.575159657
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3724767136
Short name T486
Test name
Test status
Simulation time 128505563 ps
CPU time 2.86 seconds
Started Jun 21 05:40:38 PM PDT 24
Finished Jun 21 05:40:41 PM PDT 24
Peak memory 214280 kb
Host smart-ec52be96-03b1-4b6f-b34e-573159b62c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724767136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3724767136
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.493753753
Short name T100
Test name
Test status
Simulation time 95803868 ps
CPU time 2.81 seconds
Started Jun 21 05:40:43 PM PDT 24
Finished Jun 21 05:40:47 PM PDT 24
Peak memory 222068 kb
Host smart-1c709dc4-52e5-4820-8d8a-3ef9ca4b57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493753753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.493753753
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1966673817
Short name T852
Test name
Test status
Simulation time 259067443 ps
CPU time 4.38 seconds
Started Jun 21 05:40:38 PM PDT 24
Finished Jun 21 05:40:43 PM PDT 24
Peak memory 220300 kb
Host smart-d4a8bfa6-91a7-4827-b449-f2cdd17a39ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966673817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1966673817
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3337948963
Short name T350
Test name
Test status
Simulation time 791008649 ps
CPU time 6.27 seconds
Started Jun 21 05:40:37 PM PDT 24
Finished Jun 21 05:40:45 PM PDT 24
Peak memory 214368 kb
Host smart-cb972b38-d188-4198-bc44-69e3c776764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337948963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3337948963
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.916928995
Short name T670
Test name
Test status
Simulation time 283005865 ps
CPU time 4.98 seconds
Started Jun 21 05:40:38 PM PDT 24
Finished Jun 21 05:40:44 PM PDT 24
Peak memory 208184 kb
Host smart-294aa290-b343-4ae7-8ab9-d3174cc97515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916928995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.916928995
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2511274525
Short name T907
Test name
Test status
Simulation time 567166755 ps
CPU time 8.33 seconds
Started Jun 21 05:40:37 PM PDT 24
Finished Jun 21 05:40:46 PM PDT 24
Peak memory 208208 kb
Host smart-4e92c44a-5130-46cc-a9ee-c7234be97a7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511274525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2511274525
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3660391471
Short name T765
Test name
Test status
Simulation time 20918886 ps
CPU time 1.94 seconds
Started Jun 21 05:40:42 PM PDT 24
Finished Jun 21 05:40:45 PM PDT 24
Peak memory 207052 kb
Host smart-68fcb677-8435-41f8-8d8e-ecb9f96a7022
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660391471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3660391471
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.232836094
Short name T206
Test name
Test status
Simulation time 1018384442 ps
CPU time 14.58 seconds
Started Jun 21 05:40:37 PM PDT 24
Finished Jun 21 05:40:52 PM PDT 24
Peak memory 208052 kb
Host smart-6667dfc4-9732-4e22-93cb-ff622f54ed1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232836094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.232836094
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1406681415
Short name T483
Test name
Test status
Simulation time 59787358 ps
CPU time 1.34 seconds
Started Jun 21 05:40:47 PM PDT 24
Finished Jun 21 05:40:49 PM PDT 24
Peak memory 208088 kb
Host smart-d12ea7cf-23f3-4154-ae87-eb382f61d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406681415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1406681415
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3537733268
Short name T872
Test name
Test status
Simulation time 85911580 ps
CPU time 2.48 seconds
Started Jun 21 05:40:36 PM PDT 24
Finished Jun 21 05:40:39 PM PDT 24
Peak memory 206672 kb
Host smart-2e8a8dae-367c-4156-a51a-7ec5c9ada6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537733268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3537733268
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4130418758
Short name T484
Test name
Test status
Simulation time 921382201 ps
CPU time 32.84 seconds
Started Jun 21 05:40:44 PM PDT 24
Finished Jun 21 05:41:18 PM PDT 24
Peak memory 222464 kb
Host smart-544798fa-efa8-4c71-b0bb-5cafa2d6db15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130418758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4130418758
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2234878813
Short name T574
Test name
Test status
Simulation time 105603338 ps
CPU time 4.2 seconds
Started Jun 21 05:40:46 PM PDT 24
Finished Jun 21 05:40:51 PM PDT 24
Peak memory 207896 kb
Host smart-8974e607-5b8e-4b8d-9e40-3a1787dbdd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234878813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2234878813
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2093311695
Short name T911
Test name
Test status
Simulation time 63458369 ps
CPU time 0.94 seconds
Started Jun 21 05:40:59 PM PDT 24
Finished Jun 21 05:41:01 PM PDT 24
Peak memory 206080 kb
Host smart-565f08e5-6d56-40e6-a284-a4ec82dc15af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093311695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2093311695
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3846729562
Short name T266
Test name
Test status
Simulation time 176353616 ps
CPU time 3.78 seconds
Started Jun 21 05:40:52 PM PDT 24
Finished Jun 21 05:40:56 PM PDT 24
Peak memory 214304 kb
Host smart-df251e10-0cc9-4a33-825e-f307ba46f479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846729562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3846729562
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3164354668
Short name T19
Test name
Test status
Simulation time 271329587 ps
CPU time 5.03 seconds
Started Jun 21 05:40:51 PM PDT 24
Finished Jun 21 05:40:57 PM PDT 24
Peak memory 221416 kb
Host smart-e4bf59fe-579d-40b9-8e52-5ba70a5f6df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164354668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3164354668
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.535594583
Short name T339
Test name
Test status
Simulation time 145247342 ps
CPU time 3 seconds
Started Jun 21 05:40:50 PM PDT 24
Finished Jun 21 05:40:54 PM PDT 24
Peak memory 218364 kb
Host smart-999c0ca6-f87f-4cc3-8283-5b47e99bda9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535594583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.535594583
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2830034762
Short name T300
Test name
Test status
Simulation time 45520693 ps
CPU time 1.73 seconds
Started Jun 21 05:40:50 PM PDT 24
Finished Jun 21 05:40:53 PM PDT 24
Peak memory 214284 kb
Host smart-47f9dc7c-1bdb-4a7c-9602-74518a56f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830034762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2830034762
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3334391681
Short name T883
Test name
Test status
Simulation time 142403995 ps
CPU time 4.26 seconds
Started Jun 21 05:40:51 PM PDT 24
Finished Jun 21 05:40:56 PM PDT 24
Peak memory 221516 kb
Host smart-58a7e02f-06a0-46d8-a236-b60667ce96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334391681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3334391681
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3292708477
Short name T846
Test name
Test status
Simulation time 66381537 ps
CPU time 2.72 seconds
Started Jun 21 05:40:51 PM PDT 24
Finished Jun 21 05:40:54 PM PDT 24
Peak memory 220192 kb
Host smart-b159d313-1982-4a84-bf02-88ad350192d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292708477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3292708477
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1007002146
Short name T616
Test name
Test status
Simulation time 515352282 ps
CPU time 17.07 seconds
Started Jun 21 05:40:51 PM PDT 24
Finished Jun 21 05:41:08 PM PDT 24
Peak memory 218372 kb
Host smart-7dc1d8a5-9e26-4401-b35d-bdeae57b3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007002146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1007002146
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3419951676
Short name T877
Test name
Test status
Simulation time 93221045 ps
CPU time 4.17 seconds
Started Jun 21 05:40:44 PM PDT 24
Finished Jun 21 05:40:49 PM PDT 24
Peak memory 208648 kb
Host smart-1b2653a0-d3d5-4b36-8fdb-90b2b29c39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419951676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3419951676
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1574742685
Short name T543
Test name
Test status
Simulation time 34726662 ps
CPU time 1.72 seconds
Started Jun 21 05:40:47 PM PDT 24
Finished Jun 21 05:40:50 PM PDT 24
Peak memory 206776 kb
Host smart-dac31350-f46e-48a6-a3d7-ed5e35a0035f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574742685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1574742685
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.316346399
Short name T81
Test name
Test status
Simulation time 368123325 ps
CPU time 3.86 seconds
Started Jun 21 05:40:44 PM PDT 24
Finished Jun 21 05:40:49 PM PDT 24
Peak memory 207000 kb
Host smart-d33c783c-76b4-4210-9534-70a8e50ca884
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316346399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.316346399
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4071033555
Short name T876
Test name
Test status
Simulation time 46991325 ps
CPU time 2.51 seconds
Started Jun 21 05:40:50 PM PDT 24
Finished Jun 21 05:40:53 PM PDT 24
Peak memory 207020 kb
Host smart-6543873c-585e-47cb-ae03-e815be4aae88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071033555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4071033555
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.969193439
Short name T708
Test name
Test status
Simulation time 111312346 ps
CPU time 2.5 seconds
Started Jun 21 05:40:52 PM PDT 24
Finished Jun 21 05:40:55 PM PDT 24
Peak memory 208428 kb
Host smart-15ca30b2-be69-4937-9e55-d5027f722b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969193439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.969193439
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2838661334
Short name T456
Test name
Test status
Simulation time 571108710 ps
CPU time 14.59 seconds
Started Jun 21 05:40:44 PM PDT 24
Finished Jun 21 05:40:59 PM PDT 24
Peak memory 208244 kb
Host smart-d29854a0-07c3-43a9-afb1-797aef1ebf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838661334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2838661334
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1793604720
Short name T646
Test name
Test status
Simulation time 2654248680 ps
CPU time 17.68 seconds
Started Jun 21 05:40:52 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 215204 kb
Host smart-aa27de3f-c2ea-4490-aa1c-77cb7af3e62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793604720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1793604720
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2149517954
Short name T800
Test name
Test status
Simulation time 101386644 ps
CPU time 7.09 seconds
Started Jun 21 05:40:51 PM PDT 24
Finished Jun 21 05:40:59 PM PDT 24
Peak memory 220100 kb
Host smart-495de34d-2972-4026-b3fe-e34374b61264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149517954 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2149517954
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1949743875
Short name T854
Test name
Test status
Simulation time 83945271 ps
CPU time 3.93 seconds
Started Jun 21 05:40:55 PM PDT 24
Finished Jun 21 05:41:00 PM PDT 24
Peak memory 210012 kb
Host smart-9083416b-e380-4908-9fef-8c9128c8887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949743875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1949743875
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1420177873
Short name T740
Test name
Test status
Simulation time 103315512 ps
CPU time 2.46 seconds
Started Jun 21 05:40:55 PM PDT 24
Finished Jun 21 05:40:59 PM PDT 24
Peak memory 210472 kb
Host smart-b83b0125-9b23-423e-9fe3-6a4618916cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420177873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1420177873
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2062115190
Short name T429
Test name
Test status
Simulation time 22630720 ps
CPU time 0.76 seconds
Started Jun 21 05:41:11 PM PDT 24
Finished Jun 21 05:41:12 PM PDT 24
Peak memory 205940 kb
Host smart-8f26ac3d-dfba-4b1e-9f87-5ac92d141639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062115190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2062115190
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.549112423
Short name T738
Test name
Test status
Simulation time 2710507732 ps
CPU time 15.07 seconds
Started Jun 21 05:41:00 PM PDT 24
Finished Jun 21 05:41:16 PM PDT 24
Peak memory 221624 kb
Host smart-311c87a0-1e94-4184-8a3b-5715f0449a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549112423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.549112423
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2075885276
Short name T663
Test name
Test status
Simulation time 115720800 ps
CPU time 2.82 seconds
Started Jun 21 05:40:58 PM PDT 24
Finished Jun 21 05:41:02 PM PDT 24
Peak memory 218472 kb
Host smart-c7a1c343-eb51-4a3c-81d5-17f2358b317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075885276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2075885276
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3631095304
Short name T95
Test name
Test status
Simulation time 53094662 ps
CPU time 3.59 seconds
Started Jun 21 05:40:58 PM PDT 24
Finished Jun 21 05:41:03 PM PDT 24
Peak memory 208804 kb
Host smart-653d9d44-526e-40e8-bfb2-017fac1e2c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631095304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3631095304
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2844118126
Short name T39
Test name
Test status
Simulation time 355872629 ps
CPU time 2.76 seconds
Started Jun 21 05:41:00 PM PDT 24
Finished Jun 21 05:41:03 PM PDT 24
Peak memory 222408 kb
Host smart-347fda74-565d-4a1b-b57d-885b31f768c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844118126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2844118126
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3669804409
Short name T234
Test name
Test status
Simulation time 126568344 ps
CPU time 3.93 seconds
Started Jun 21 05:41:02 PM PDT 24
Finished Jun 21 05:41:07 PM PDT 24
Peak memory 209368 kb
Host smart-57d32159-5f18-4a14-a349-d8d0ae1d7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669804409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3669804409
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.4168432670
Short name T528
Test name
Test status
Simulation time 22566216 ps
CPU time 2.01 seconds
Started Jun 21 05:40:59 PM PDT 24
Finished Jun 21 05:41:02 PM PDT 24
Peak memory 206876 kb
Host smart-fc987017-96fb-4284-86fc-c74c72770ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168432670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.4168432670
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1586112371
Short name T503
Test name
Test status
Simulation time 66454583 ps
CPU time 2.65 seconds
Started Jun 21 05:40:59 PM PDT 24
Finished Jun 21 05:41:03 PM PDT 24
Peak memory 208676 kb
Host smart-39953abb-2475-4df2-bbd9-de726f2a4e1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586112371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1586112371
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.350539600
Short name T603
Test name
Test status
Simulation time 406124620 ps
CPU time 4.29 seconds
Started Jun 21 05:40:59 PM PDT 24
Finished Jun 21 05:41:04 PM PDT 24
Peak memory 208872 kb
Host smart-56607834-caba-40de-86a7-2e7973269230
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350539600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.350539600
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1903996013
Short name T582
Test name
Test status
Simulation time 1167070907 ps
CPU time 27 seconds
Started Jun 21 05:41:01 PM PDT 24
Finished Jun 21 05:41:29 PM PDT 24
Peak memory 208924 kb
Host smart-a1a9fa1f-63a1-4c38-9601-aa58faca7052
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903996013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1903996013
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2904448838
Short name T741
Test name
Test status
Simulation time 118119273 ps
CPU time 1.53 seconds
Started Jun 21 05:40:58 PM PDT 24
Finished Jun 21 05:41:01 PM PDT 24
Peak memory 214288 kb
Host smart-e0e0cee1-71e4-4a52-811f-27761b38da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904448838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2904448838
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1409707868
Short name T530
Test name
Test status
Simulation time 235992117 ps
CPU time 3.06 seconds
Started Jun 21 05:41:00 PM PDT 24
Finished Jun 21 05:41:04 PM PDT 24
Peak memory 207024 kb
Host smart-2a4da6c0-40fb-4238-abde-c672d19e4ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409707868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1409707868
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1327956901
Short name T713
Test name
Test status
Simulation time 89847698098 ps
CPU time 469.84 seconds
Started Jun 21 05:40:59 PM PDT 24
Finished Jun 21 05:48:49 PM PDT 24
Peak memory 219892 kb
Host smart-9487d341-e81c-4105-a1ea-3d80a6232ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327956901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1327956901
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2489876440
Short name T189
Test name
Test status
Simulation time 381916543 ps
CPU time 14.04 seconds
Started Jun 21 05:40:58 PM PDT 24
Finished Jun 21 05:41:13 PM PDT 24
Peak memory 222512 kb
Host smart-763a1011-0c06-4a7a-9f63-028ea9203c97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489876440 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2489876440
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1956499945
Short name T611
Test name
Test status
Simulation time 391401880 ps
CPU time 5.58 seconds
Started Jun 21 05:40:58 PM PDT 24
Finished Jun 21 05:41:04 PM PDT 24
Peak memory 209704 kb
Host smart-ed305f5f-d4e2-4841-8a2e-0cf953ca7d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956499945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1956499945
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.982057436
Short name T722
Test name
Test status
Simulation time 87432684 ps
CPU time 1.67 seconds
Started Jun 21 05:40:59 PM PDT 24
Finished Jun 21 05:41:02 PM PDT 24
Peak memory 210164 kb
Host smart-8dc509cf-f293-4a23-903f-704d323a3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982057436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.982057436
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1934902545
Short name T453
Test name
Test status
Simulation time 18700260 ps
CPU time 0.78 seconds
Started Jun 21 05:41:07 PM PDT 24
Finished Jun 21 05:41:09 PM PDT 24
Peak memory 205912 kb
Host smart-3fd301de-f2e4-435d-97d5-b002892b749a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934902545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1934902545
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.550543054
Short name T387
Test name
Test status
Simulation time 57911922 ps
CPU time 4.13 seconds
Started Jun 21 05:41:07 PM PDT 24
Finished Jun 21 05:41:12 PM PDT 24
Peak memory 214408 kb
Host smart-36ab8589-87f7-4876-9164-bacd7046ab5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550543054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.550543054
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3109083773
Short name T9
Test name
Test status
Simulation time 202273951 ps
CPU time 6.73 seconds
Started Jun 21 05:41:09 PM PDT 24
Finished Jun 21 05:41:17 PM PDT 24
Peak memory 222908 kb
Host smart-a64f5059-d0bc-4d35-b6db-9638138aa230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109083773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3109083773
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1428991250
Short name T65
Test name
Test status
Simulation time 544053740 ps
CPU time 4.45 seconds
Started Jun 21 05:41:05 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 218240 kb
Host smart-4e0d630d-9c8b-4a7e-b011-f03eec2a98a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428991250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1428991250
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2143740960
Short name T96
Test name
Test status
Simulation time 73635966 ps
CPU time 4.06 seconds
Started Jun 21 05:41:07 PM PDT 24
Finished Jun 21 05:41:12 PM PDT 24
Peak memory 222448 kb
Host smart-92fe8c82-f2c9-46f3-ba52-13a1dd390ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143740960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2143740960
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3205853351
Short name T627
Test name
Test status
Simulation time 369839405 ps
CPU time 11.16 seconds
Started Jun 21 05:41:05 PM PDT 24
Finished Jun 21 05:41:17 PM PDT 24
Peak memory 209908 kb
Host smart-e98f6c69-cc96-44c4-ab65-e62a93fda084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205853351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3205853351
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2428146546
Short name T725
Test name
Test status
Simulation time 269162795 ps
CPU time 6.25 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:14 PM PDT 24
Peak memory 218224 kb
Host smart-5bc649cc-bb80-40af-bb1e-824d195c684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428146546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2428146546
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.850965530
Short name T143
Test name
Test status
Simulation time 104640910 ps
CPU time 2.99 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 206748 kb
Host smart-02b8627a-3df3-4580-a72e-e7ac2feada5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850965530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.850965530
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3637048866
Short name T355
Test name
Test status
Simulation time 477954990 ps
CPU time 5.65 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:13 PM PDT 24
Peak memory 208776 kb
Host smart-8f4a3098-5836-41c9-b54a-42b6ef266c1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637048866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3637048866
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2178825441
Short name T197
Test name
Test status
Simulation time 286336710 ps
CPU time 3.37 seconds
Started Jun 21 05:41:07 PM PDT 24
Finished Jun 21 05:41:12 PM PDT 24
Peak memory 206840 kb
Host smart-c3b19a4b-69e8-4ccc-8f71-bdb8f486c4fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178825441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2178825441
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3437089797
Short name T579
Test name
Test status
Simulation time 37689784 ps
CPU time 2.22 seconds
Started Jun 21 05:41:10 PM PDT 24
Finished Jun 21 05:41:13 PM PDT 24
Peak memory 206880 kb
Host smart-b6d39ce2-00f3-4b52-949d-ad2fc7171d0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437089797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3437089797
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.441283463
Short name T709
Test name
Test status
Simulation time 84121159 ps
CPU time 2.59 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:09 PM PDT 24
Peak memory 209000 kb
Host smart-7d9c13fc-cdc6-4f61-b879-e3de3910baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441283463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.441283463
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.586928399
Short name T906
Test name
Test status
Simulation time 3512886054 ps
CPU time 15.79 seconds
Started Jun 21 05:41:09 PM PDT 24
Finished Jun 21 05:41:26 PM PDT 24
Peak memory 208880 kb
Host smart-14f026c4-b7e8-4dee-a815-bc03f12aa159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586928399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.586928399
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.434102795
Short name T835
Test name
Test status
Simulation time 53433417036 ps
CPU time 100.75 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:42:48 PM PDT 24
Peak memory 220512 kb
Host smart-cc4da13a-5729-4c93-a4d8-6b388a39cc86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434102795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.434102795
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2872101294
Short name T236
Test name
Test status
Simulation time 2072809278 ps
CPU time 20.13 seconds
Started Jun 21 05:41:08 PM PDT 24
Finished Jun 21 05:41:29 PM PDT 24
Peak memory 222616 kb
Host smart-22102eb6-4ab5-4e23-94b2-6d25035f037b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872101294 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2872101294
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1624004638
Short name T411
Test name
Test status
Simulation time 1104014722 ps
CPU time 28.96 seconds
Started Jun 21 05:41:08 PM PDT 24
Finished Jun 21 05:41:38 PM PDT 24
Peak memory 208996 kb
Host smart-0d51a8bc-0d54-45ac-81c9-180738b4cbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624004638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1624004638
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2797114372
Short name T188
Test name
Test status
Simulation time 109032360 ps
CPU time 3.12 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 210492 kb
Host smart-4972bfed-18d9-4880-9ee4-389d87d6f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797114372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2797114372
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4212800365
Short name T577
Test name
Test status
Simulation time 17616240 ps
CPU time 0.9 seconds
Started Jun 21 05:41:13 PM PDT 24
Finished Jun 21 05:41:14 PM PDT 24
Peak memory 206136 kb
Host smart-5243df99-84de-4d71-ad80-68a989b8aacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212800365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4212800365
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2623009225
Short name T311
Test name
Test status
Simulation time 183551788 ps
CPU time 8.96 seconds
Started Jun 21 05:41:09 PM PDT 24
Finished Jun 21 05:41:19 PM PDT 24
Peak memory 214672 kb
Host smart-9bdd4f98-4e19-4b4c-94df-88787dc95dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623009225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2623009225
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.738696580
Short name T908
Test name
Test status
Simulation time 210913469 ps
CPU time 4.33 seconds
Started Jun 21 05:41:13 PM PDT 24
Finished Jun 21 05:41:18 PM PDT 24
Peak memory 208900 kb
Host smart-ccebdd97-7646-4d76-8076-60ca1ffbe037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738696580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.738696580
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2572157856
Short name T335
Test name
Test status
Simulation time 136411228 ps
CPU time 2.73 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:09 PM PDT 24
Peak memory 210064 kb
Host smart-a5344a6b-cac3-4eb1-bdf5-a23d9241285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572157856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2572157856
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3114215483
Short name T469
Test name
Test status
Simulation time 333410574 ps
CPU time 4.19 seconds
Started Jun 21 05:41:15 PM PDT 24
Finished Jun 21 05:41:19 PM PDT 24
Peak memory 214296 kb
Host smart-dcf3df9b-d91a-4249-9466-a733d6d52d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114215483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3114215483
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1108799937
Short name T329
Test name
Test status
Simulation time 208369468 ps
CPU time 2.03 seconds
Started Jun 21 05:41:12 PM PDT 24
Finished Jun 21 05:41:15 PM PDT 24
Peak memory 214248 kb
Host smart-ef253179-77fb-420b-8109-975d0ca3ea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108799937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1108799937
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1646310583
Short name T910
Test name
Test status
Simulation time 126966311 ps
CPU time 2.17 seconds
Started Jun 21 05:41:13 PM PDT 24
Finished Jun 21 05:41:16 PM PDT 24
Peak memory 215432 kb
Host smart-b50e620d-c8eb-4fe6-ad80-45e4c77a00f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646310583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1646310583
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.762090240
Short name T751
Test name
Test status
Simulation time 150359090 ps
CPU time 4.26 seconds
Started Jun 21 05:41:05 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 208772 kb
Host smart-a751e18c-23e8-4cf7-b36c-7b3511485aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762090240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.762090240
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2764689694
Short name T426
Test name
Test status
Simulation time 754581105 ps
CPU time 3.12 seconds
Started Jun 21 05:41:09 PM PDT 24
Finished Jun 21 05:41:13 PM PDT 24
Peak memory 206848 kb
Host smart-d4eeea31-e8d9-45b1-9100-6c1a53fe9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764689694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2764689694
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4152433092
Short name T207
Test name
Test status
Simulation time 63437011 ps
CPU time 2.75 seconds
Started Jun 21 05:41:06 PM PDT 24
Finished Jun 21 05:41:10 PM PDT 24
Peak memory 206980 kb
Host smart-e85586ff-5a08-47bb-999d-986a26b93cf9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152433092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4152433092
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2911031624
Short name T359
Test name
Test status
Simulation time 116312402 ps
CPU time 4.03 seconds
Started Jun 21 05:41:09 PM PDT 24
Finished Jun 21 05:41:14 PM PDT 24
Peak memory 207572 kb
Host smart-679711bf-fc80-4122-a829-4abec3b732ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911031624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2911031624
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1642082810
Short name T498
Test name
Test status
Simulation time 59579237 ps
CPU time 3.13 seconds
Started Jun 21 05:41:09 PM PDT 24
Finished Jun 21 05:41:13 PM PDT 24
Peak memory 206964 kb
Host smart-babc02c2-b501-4c3f-b4b3-fea31d83ebc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642082810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1642082810
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3633245465
Short name T531
Test name
Test status
Simulation time 375919160 ps
CPU time 4.37 seconds
Started Jun 21 05:41:13 PM PDT 24
Finished Jun 21 05:41:18 PM PDT 24
Peak memory 216084 kb
Host smart-8337ce55-4bd3-4bc9-bedf-ab62b05be69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633245465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3633245465
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2403428770
Short name T222
Test name
Test status
Simulation time 101117724 ps
CPU time 3.76 seconds
Started Jun 21 05:41:07 PM PDT 24
Finished Jun 21 05:41:12 PM PDT 24
Peak memory 208680 kb
Host smart-a6ea52fc-112b-4de3-80cf-5a6bff6c2709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403428770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2403428770
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.374868842
Short name T190
Test name
Test status
Simulation time 992224667 ps
CPU time 9.07 seconds
Started Jun 21 05:41:12 PM PDT 24
Finished Jun 21 05:41:21 PM PDT 24
Peak memory 222612 kb
Host smart-c6430f15-b621-4347-9ba9-5fffc4c44342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374868842 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.374868842
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1152389441
Short name T507
Test name
Test status
Simulation time 240824235 ps
CPU time 3.34 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:18 PM PDT 24
Peak memory 207376 kb
Host smart-7e0eae5a-a139-476f-a158-1ea3f044a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152389441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1152389441
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.353391238
Short name T390
Test name
Test status
Simulation time 45554395 ps
CPU time 2.14 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:17 PM PDT 24
Peak memory 210064 kb
Host smart-45898e65-26f7-44f6-8020-dc3cbd200248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353391238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.353391238
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3096430841
Short name T757
Test name
Test status
Simulation time 29469898 ps
CPU time 0.81 seconds
Started Jun 21 05:41:20 PM PDT 24
Finished Jun 21 05:41:22 PM PDT 24
Peak memory 205916 kb
Host smart-d7fb976e-6cdd-4cfc-bfb3-725a5aefa520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096430841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3096430841
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1608348590
Short name T408
Test name
Test status
Simulation time 210552842 ps
CPU time 12.43 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:27 PM PDT 24
Peak memory 214312 kb
Host smart-13e6fad6-7710-41e5-8f05-ca018a955251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608348590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1608348590
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.395215168
Short name T570
Test name
Test status
Simulation time 37106930 ps
CPU time 1.82 seconds
Started Jun 21 05:41:12 PM PDT 24
Finished Jun 21 05:41:15 PM PDT 24
Peak memory 207516 kb
Host smart-1542e877-a50d-49a2-b2c2-7fc84d9a8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395215168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.395215168
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3075178563
Short name T283
Test name
Test status
Simulation time 33028691 ps
CPU time 2.48 seconds
Started Jun 21 05:41:22 PM PDT 24
Finished Jun 21 05:41:25 PM PDT 24
Peak memory 220184 kb
Host smart-4c13bb31-6d1e-4f32-92b1-320e1bcee76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075178563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3075178563
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3623438436
Short name T774
Test name
Test status
Simulation time 201016630 ps
CPU time 2.58 seconds
Started Jun 21 05:41:20 PM PDT 24
Finished Jun 21 05:41:24 PM PDT 24
Peak memory 209768 kb
Host smart-125de02c-1e05-4d50-9e89-fcc2d9dbc406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623438436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3623438436
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2708642312
Short name T264
Test name
Test status
Simulation time 151912592 ps
CPU time 4.26 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:19 PM PDT 24
Peak memory 214400 kb
Host smart-5936839d-1879-4cf0-85cf-9b63eb3f4aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708642312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2708642312
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.4133251266
Short name T794
Test name
Test status
Simulation time 174659246 ps
CPU time 4.78 seconds
Started Jun 21 05:41:13 PM PDT 24
Finished Jun 21 05:41:19 PM PDT 24
Peak memory 208748 kb
Host smart-cf0d7639-b483-4515-8bd9-67bcfed46beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133251266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.4133251266
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1427371156
Short name T785
Test name
Test status
Simulation time 199947650 ps
CPU time 6.25 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:21 PM PDT 24
Peak memory 208020 kb
Host smart-ccdf9aea-02ec-4d34-adb2-f5b4406dca15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427371156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1427371156
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.199406179
Short name T655
Test name
Test status
Simulation time 65191066 ps
CPU time 3.15 seconds
Started Jun 21 05:41:14 PM PDT 24
Finished Jun 21 05:41:18 PM PDT 24
Peak memory 208476 kb
Host smart-0fb4a3b4-ccea-4516-b6a3-10325d180fe4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199406179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.199406179
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2755831028
Short name T450
Test name
Test status
Simulation time 83609993 ps
CPU time 1.78 seconds
Started Jun 21 05:41:21 PM PDT 24
Finished Jun 21 05:41:23 PM PDT 24
Peak memory 215440 kb
Host smart-3aed5d43-4ad6-403c-abe6-72dfdf00271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755831028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2755831028
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2290594072
Short name T667
Test name
Test status
Simulation time 259716311 ps
CPU time 4.61 seconds
Started Jun 21 05:41:17 PM PDT 24
Finished Jun 21 05:41:22 PM PDT 24
Peak memory 207976 kb
Host smart-332cbdd1-5111-4cd4-a312-25bfcef1021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290594072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2290594072
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.642156165
Short name T733
Test name
Test status
Simulation time 932392204 ps
CPU time 5.28 seconds
Started Jun 21 05:41:25 PM PDT 24
Finished Jun 21 05:41:30 PM PDT 24
Peak memory 208724 kb
Host smart-b4d25db0-1110-49a9-9515-2c3c156be163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642156165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.642156165
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3611730317
Short name T470
Test name
Test status
Simulation time 38954761 ps
CPU time 2.03 seconds
Started Jun 21 05:41:25 PM PDT 24
Finished Jun 21 05:41:27 PM PDT 24
Peak memory 209644 kb
Host smart-812c6b59-7709-4697-8464-079359a1f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611730317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3611730317
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3622386900
Short name T647
Test name
Test status
Simulation time 14476216 ps
CPU time 0.77 seconds
Started Jun 21 05:41:32 PM PDT 24
Finished Jun 21 05:41:33 PM PDT 24
Peak memory 205920 kb
Host smart-48a83e0d-a622-4f51-bdac-8bd1143e622d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622386900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3622386900
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3104297186
Short name T707
Test name
Test status
Simulation time 40088183 ps
CPU time 3.04 seconds
Started Jun 21 05:41:20 PM PDT 24
Finished Jun 21 05:41:24 PM PDT 24
Peak memory 214312 kb
Host smart-8417724f-83af-45df-b05f-6f65e6881d20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104297186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3104297186
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1717062074
Short name T796
Test name
Test status
Simulation time 116149219 ps
CPU time 1.65 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:31 PM PDT 24
Peak memory 208688 kb
Host smart-b4984681-1d27-4553-bc62-da8765fd0815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717062074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1717062074
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3922519268
Short name T688
Test name
Test status
Simulation time 81817474 ps
CPU time 2.14 seconds
Started Jun 21 05:41:22 PM PDT 24
Finished Jun 21 05:41:25 PM PDT 24
Peak memory 207828 kb
Host smart-e5fbe324-971c-4ae9-a993-d502e52bce4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922519268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3922519268
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2589665157
Short name T268
Test name
Test status
Simulation time 33391543 ps
CPU time 2.47 seconds
Started Jun 21 05:41:29 PM PDT 24
Finished Jun 21 05:41:32 PM PDT 24
Peak memory 214248 kb
Host smart-cad691fc-77cb-446d-969a-888c702d736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589665157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2589665157
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2680893147
Short name T902
Test name
Test status
Simulation time 185618876 ps
CPU time 2.61 seconds
Started Jun 21 05:41:30 PM PDT 24
Finished Jun 21 05:41:34 PM PDT 24
Peak memory 214156 kb
Host smart-74c576ba-8684-48b2-b6ee-b3d41cb78b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680893147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2680893147
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.2422798315
Short name T413
Test name
Test status
Simulation time 816117229 ps
CPU time 5.13 seconds
Started Jun 21 05:41:20 PM PDT 24
Finished Jun 21 05:41:26 PM PDT 24
Peak memory 208156 kb
Host smart-4fb0675c-0004-40ad-abe5-5909cfe84ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422798315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2422798315
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2517107484
Short name T585
Test name
Test status
Simulation time 41510585 ps
CPU time 2.72 seconds
Started Jun 21 05:41:22 PM PDT 24
Finished Jun 21 05:41:25 PM PDT 24
Peak memory 208596 kb
Host smart-2e41d99a-2104-4a15-8ea6-7c87cdd79223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517107484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2517107484
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1443334577
Short name T362
Test name
Test status
Simulation time 154254848 ps
CPU time 6.38 seconds
Started Jun 21 05:41:22 PM PDT 24
Finished Jun 21 05:41:29 PM PDT 24
Peak memory 208712 kb
Host smart-b34ab213-2f3f-45ad-a008-19330efb3bb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443334577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1443334577
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.33751316
Short name T492
Test name
Test status
Simulation time 1088216997 ps
CPU time 16.39 seconds
Started Jun 21 05:41:20 PM PDT 24
Finished Jun 21 05:41:37 PM PDT 24
Peak memory 208552 kb
Host smart-8bfe8c36-c617-49b3-8bbd-90462389be4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33751316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.33751316
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2165742354
Short name T808
Test name
Test status
Simulation time 107224903 ps
CPU time 3.08 seconds
Started Jun 21 05:41:20 PM PDT 24
Finished Jun 21 05:41:24 PM PDT 24
Peak memory 208904 kb
Host smart-b195e723-6a4c-44ae-8ba1-4cfffa3f0c8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165742354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2165742354
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.844211975
Short name T694
Test name
Test status
Simulation time 557902548 ps
CPU time 3.98 seconds
Started Jun 21 05:41:29 PM PDT 24
Finished Jun 21 05:41:34 PM PDT 24
Peak memory 209596 kb
Host smart-37a4f0e4-53de-42f6-9e67-659df5448424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844211975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.844211975
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2297972104
Short name T14
Test name
Test status
Simulation time 132441495 ps
CPU time 2.21 seconds
Started Jun 21 05:41:21 PM PDT 24
Finished Jun 21 05:41:24 PM PDT 24
Peak memory 206816 kb
Host smart-b17a4865-82fb-4f37-95d5-5fb80cff1271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297972104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2297972104
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.94257353
Short name T862
Test name
Test status
Simulation time 3815525269 ps
CPU time 49.19 seconds
Started Jun 21 05:41:27 PM PDT 24
Finished Jun 21 05:42:17 PM PDT 24
Peak memory 220476 kb
Host smart-5de5b7b3-6563-4f2c-b3fc-50b6da9532fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94257353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.94257353
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3062725174
Short name T166
Test name
Test status
Simulation time 936476845 ps
CPU time 16.43 seconds
Started Jun 21 05:41:30 PM PDT 24
Finished Jun 21 05:41:47 PM PDT 24
Peak memory 221652 kb
Host smart-08da88bc-98e6-4a8c-905c-4e129b138729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062725174 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3062725174
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2804664026
Short name T909
Test name
Test status
Simulation time 495439454 ps
CPU time 5.41 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:34 PM PDT 24
Peak memory 210448 kb
Host smart-72217c23-565f-4f0f-9d84-9820567ccdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804664026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2804664026
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3508499999
Short name T54
Test name
Test status
Simulation time 84792406 ps
CPU time 3.25 seconds
Started Jun 21 05:41:32 PM PDT 24
Finished Jun 21 05:41:36 PM PDT 24
Peak memory 210188 kb
Host smart-12912c67-44cb-4d45-a9be-9561db60d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508499999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3508499999
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1137456233
Short name T609
Test name
Test status
Simulation time 22581922 ps
CPU time 0.84 seconds
Started Jun 21 05:41:37 PM PDT 24
Finished Jun 21 05:41:38 PM PDT 24
Peak memory 205908 kb
Host smart-a2e87d4d-5fc3-4581-b2c0-fe42654e7b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137456233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1137456233
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2654476231
Short name T755
Test name
Test status
Simulation time 31329258 ps
CPU time 2.23 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:45 PM PDT 24
Peak memory 210200 kb
Host smart-0446007d-17a0-466f-863a-8c2de774b973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654476231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2654476231
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3960200100
Short name T438
Test name
Test status
Simulation time 216664066 ps
CPU time 2.22 seconds
Started Jun 21 05:41:27 PM PDT 24
Finished Jun 21 05:41:30 PM PDT 24
Peak memory 208120 kb
Host smart-7471d226-3d66-4b94-9bb0-3091ec6e290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960200100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3960200100
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.198351453
Short name T25
Test name
Test status
Simulation time 57674956 ps
CPU time 3.69 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:46 PM PDT 24
Peak memory 220740 kb
Host smart-0a6f3f84-ccc6-4a88-b387-700779073212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198351453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.198351453
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.792562901
Short name T32
Test name
Test status
Simulation time 475941234 ps
CPU time 4.98 seconds
Started Jun 21 05:41:35 PM PDT 24
Finished Jun 21 05:41:41 PM PDT 24
Peak memory 214244 kb
Host smart-578b7b3a-1bc5-4cee-9471-f62b4d0b1c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792562901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.792562901
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3721493597
Short name T598
Test name
Test status
Simulation time 156673728 ps
CPU time 3.03 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:32 PM PDT 24
Peak memory 209004 kb
Host smart-d7fb8d09-813c-443c-9687-dc81b136a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721493597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3721493597
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.480238750
Short name T806
Test name
Test status
Simulation time 392153559 ps
CPU time 12.53 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:42 PM PDT 24
Peak memory 208892 kb
Host smart-4f74383e-50dc-4b10-aacd-59089e49e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480238750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.480238750
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1144013694
Short name T855
Test name
Test status
Simulation time 798161781 ps
CPU time 5.28 seconds
Started Jun 21 05:41:29 PM PDT 24
Finished Jun 21 05:41:35 PM PDT 24
Peak memory 207792 kb
Host smart-eebee58f-32eb-46d6-8591-79bd71f17fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144013694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1144013694
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1666395635
Short name T706
Test name
Test status
Simulation time 486201922 ps
CPU time 3.43 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:32 PM PDT 24
Peak memory 206964 kb
Host smart-ef2fb6e1-affc-4e4e-b8a6-c3b6c68ae746
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666395635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1666395635
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1512474038
Short name T447
Test name
Test status
Simulation time 125583271 ps
CPU time 4.38 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:34 PM PDT 24
Peak memory 206904 kb
Host smart-a402ee6a-15df-4d5b-9416-be3d1b546ded
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512474038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1512474038
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1371199229
Short name T672
Test name
Test status
Simulation time 230741288 ps
CPU time 6.38 seconds
Started Jun 21 05:41:27 PM PDT 24
Finished Jun 21 05:41:33 PM PDT 24
Peak memory 208628 kb
Host smart-5b6f6576-1881-463d-9bee-e2081aa81026
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371199229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1371199229
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1663280915
Short name T341
Test name
Test status
Simulation time 198822790 ps
CPU time 2.82 seconds
Started Jun 21 05:41:37 PM PDT 24
Finished Jun 21 05:41:41 PM PDT 24
Peak memory 207960 kb
Host smart-a29073dc-d431-46a4-9358-e2227ce06289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663280915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1663280915
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4046248165
Short name T451
Test name
Test status
Simulation time 241596273 ps
CPU time 3.61 seconds
Started Jun 21 05:41:28 PM PDT 24
Finished Jun 21 05:41:32 PM PDT 24
Peak memory 208604 kb
Host smart-eaf81f7a-d001-4473-94e2-000d590c77c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046248165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4046248165
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.187073273
Short name T251
Test name
Test status
Simulation time 4274842555 ps
CPU time 51.4 seconds
Started Jun 21 05:41:37 PM PDT 24
Finished Jun 21 05:42:29 PM PDT 24
Peak memory 222608 kb
Host smart-6220f0ec-c6cc-4cba-8d36-46bb6c736109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187073273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.187073273
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3836042771
Short name T745
Test name
Test status
Simulation time 262671813 ps
CPU time 4.8 seconds
Started Jun 21 05:41:43 PM PDT 24
Finished Jun 21 05:41:49 PM PDT 24
Peak memory 206964 kb
Host smart-853b3221-27c1-4343-9d0c-609a52b8c85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836042771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3836042771
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.103227553
Short name T810
Test name
Test status
Simulation time 41212385 ps
CPU time 2.24 seconds
Started Jun 21 05:41:37 PM PDT 24
Finished Jun 21 05:41:40 PM PDT 24
Peak memory 209856 kb
Host smart-bfceb919-066c-4d7c-bb09-dd3abf849b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103227553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.103227553
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1182056957
Short name T195
Test name
Test status
Simulation time 27324269 ps
CPU time 0.77 seconds
Started Jun 21 05:41:43 PM PDT 24
Finished Jun 21 05:41:44 PM PDT 24
Peak memory 205864 kb
Host smart-fd50e999-c355-4f04-b7ab-8a03d11cfcb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182056957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1182056957
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.401036304
Short name T407
Test name
Test status
Simulation time 593180062 ps
CPU time 8.11 seconds
Started Jun 21 05:41:36 PM PDT 24
Finished Jun 21 05:41:45 PM PDT 24
Peak memory 214304 kb
Host smart-d8eecfd7-f833-4cc3-85ad-c2956f205efe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401036304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.401036304
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3938430744
Short name T30
Test name
Test status
Simulation time 35315554 ps
CPU time 2.1 seconds
Started Jun 21 05:41:46 PM PDT 24
Finished Jun 21 05:41:49 PM PDT 24
Peak memory 209452 kb
Host smart-3db0a8f2-1fbd-4d98-94c3-aa4544c937cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938430744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3938430744
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.973272533
Short name T481
Test name
Test status
Simulation time 63310939 ps
CPU time 1.52 seconds
Started Jun 21 05:41:44 PM PDT 24
Finished Jun 21 05:41:46 PM PDT 24
Peak memory 206800 kb
Host smart-29f4838c-93cf-446a-8c8c-a838d85ce4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973272533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.973272533
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2922974418
Short name T89
Test name
Test status
Simulation time 29433024 ps
CPU time 2.47 seconds
Started Jun 21 05:41:43 PM PDT 24
Finished Jun 21 05:41:47 PM PDT 24
Peak memory 210112 kb
Host smart-d2f7c15d-3046-43a8-a220-eb1266cf72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922974418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2922974418
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.586694401
Short name T42
Test name
Test status
Simulation time 385024373 ps
CPU time 4.69 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:48 PM PDT 24
Peak memory 214260 kb
Host smart-92c5da52-d27d-4b78-afd9-430975a61c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586694401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.586694401
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2531930601
Short name T476
Test name
Test status
Simulation time 639977462 ps
CPU time 5.03 seconds
Started Jun 21 05:41:47 PM PDT 24
Finished Jun 21 05:41:53 PM PDT 24
Peak memory 215180 kb
Host smart-3ccc8073-f19a-4fad-9e2d-351ecf5e807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531930601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2531930601
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3108275650
Short name T639
Test name
Test status
Simulation time 27272348 ps
CPU time 2.23 seconds
Started Jun 21 05:41:36 PM PDT 24
Finished Jun 21 05:41:39 PM PDT 24
Peak memory 207372 kb
Host smart-6534bd65-c450-4c41-adee-1dc42d5190bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108275650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3108275650
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3462997866
Short name T793
Test name
Test status
Simulation time 349238427 ps
CPU time 4.62 seconds
Started Jun 21 05:41:36 PM PDT 24
Finished Jun 21 05:41:41 PM PDT 24
Peak memory 207004 kb
Host smart-52267748-7852-4243-9ef3-b37317b6c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462997866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3462997866
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.858777568
Short name T919
Test name
Test status
Simulation time 135734086 ps
CPU time 4.34 seconds
Started Jun 21 05:41:36 PM PDT 24
Finished Jun 21 05:41:41 PM PDT 24
Peak memory 208552 kb
Host smart-8dc102ec-c540-464b-9a24-4bfb33f300f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858777568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.858777568
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2175729219
Short name T602
Test name
Test status
Simulation time 264468675 ps
CPU time 3.47 seconds
Started Jun 21 05:41:37 PM PDT 24
Finished Jun 21 05:41:41 PM PDT 24
Peak memory 208604 kb
Host smart-9e7b6273-aeb3-4a86-b464-44ddca1843f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175729219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2175729219
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1130930821
Short name T474
Test name
Test status
Simulation time 126965622 ps
CPU time 2.55 seconds
Started Jun 21 05:41:36 PM PDT 24
Finished Jun 21 05:41:39 PM PDT 24
Peak memory 208484 kb
Host smart-37f18e5d-09b5-46c9-a1d9-d5ed5d17890a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130930821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1130930821
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2571149461
Short name T802
Test name
Test status
Simulation time 395163942 ps
CPU time 3.19 seconds
Started Jun 21 05:41:45 PM PDT 24
Finished Jun 21 05:41:48 PM PDT 24
Peak memory 209880 kb
Host smart-31db5676-939f-4642-851c-07fa8a59b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571149461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2571149461
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2065995773
Short name T497
Test name
Test status
Simulation time 204724819 ps
CPU time 4.75 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:47 PM PDT 24
Peak memory 208360 kb
Host smart-7cc2d09b-a854-4846-ae21-155a5c7857c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065995773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2065995773
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2369749149
Short name T917
Test name
Test status
Simulation time 1003506301 ps
CPU time 9.72 seconds
Started Jun 21 05:41:46 PM PDT 24
Finished Jun 21 05:41:57 PM PDT 24
Peak memory 220336 kb
Host smart-94fe6796-72f6-46a1-9cb6-d79718ca14d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369749149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2369749149
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1775603280
Short name T539
Test name
Test status
Simulation time 127185098 ps
CPU time 4.82 seconds
Started Jun 21 05:41:47 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 207436 kb
Host smart-b8d39ac5-a540-448a-bdaf-189bbd1d4152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775603280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1775603280
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2882140689
Short name T813
Test name
Test status
Simulation time 41998699 ps
CPU time 2.22 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:46 PM PDT 24
Peak memory 210100 kb
Host smart-e3cca956-ad12-486d-b186-2d5f6fc144ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882140689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2882140689
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1225494918
Short name T465
Test name
Test status
Simulation time 27626040 ps
CPU time 0.73 seconds
Started Jun 21 05:39:26 PM PDT 24
Finished Jun 21 05:39:27 PM PDT 24
Peak memory 205920 kb
Host smart-9e926055-e1d6-4222-b86f-1130c14bd184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225494918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1225494918
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1732640308
Short name T338
Test name
Test status
Simulation time 53234181 ps
CPU time 3.84 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:24 PM PDT 24
Peak memory 214252 kb
Host smart-94ac75d1-2c8a-4b95-ad08-45b7bd9942a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732640308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1732640308
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3066480647
Short name T29
Test name
Test status
Simulation time 384283080 ps
CPU time 3.31 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:24 PM PDT 24
Peak memory 209280 kb
Host smart-c302fad5-24ce-40c3-8357-c375d4abf052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066480647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3066480647
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2235056978
Short name T731
Test name
Test status
Simulation time 117803765 ps
CPU time 2.38 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:22 PM PDT 24
Peak memory 214328 kb
Host smart-d7a8503c-05a5-484c-9d4b-13ebad487033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235056978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2235056978
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4284467069
Short name T273
Test name
Test status
Simulation time 437207648 ps
CPU time 3.32 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:24 PM PDT 24
Peak memory 222400 kb
Host smart-58a410f7-31a8-4a36-ae94-781408ab2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284467069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4284467069
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.479273235
Short name T244
Test name
Test status
Simulation time 59113738 ps
CPU time 2.47 seconds
Started Jun 21 05:39:18 PM PDT 24
Finished Jun 21 05:39:21 PM PDT 24
Peak memory 220228 kb
Host smart-479e10cb-9ffc-43fd-bab5-72234667cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479273235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.479273235
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.518402810
Short name T700
Test name
Test status
Simulation time 332448872 ps
CPU time 4.46 seconds
Started Jun 21 05:39:17 PM PDT 24
Finished Jun 21 05:39:22 PM PDT 24
Peak memory 217960 kb
Host smart-2dff98d8-5bc2-49aa-93a5-22a51af5bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518402810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.518402810
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.373632415
Short name T37
Test name
Test status
Simulation time 628017176 ps
CPU time 17.59 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:37 PM PDT 24
Peak memory 237252 kb
Host smart-c3d87cad-1cf8-4a15-8ee5-165ee9bf37ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373632415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.373632415
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.221545606
Short name T696
Test name
Test status
Simulation time 88746591 ps
CPU time 3.14 seconds
Started Jun 21 05:39:12 PM PDT 24
Finished Jun 21 05:39:16 PM PDT 24
Peak memory 206820 kb
Host smart-cec50e01-a342-444a-b78b-777e888cf0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221545606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.221545606
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.265218001
Short name T556
Test name
Test status
Simulation time 267081186 ps
CPU time 3.41 seconds
Started Jun 21 05:39:10 PM PDT 24
Finished Jun 21 05:39:13 PM PDT 24
Peak memory 208592 kb
Host smart-35c1264e-dace-46b9-9ab9-c2c15094bf30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265218001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.265218001
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2137011162
Short name T554
Test name
Test status
Simulation time 1971218203 ps
CPU time 6.95 seconds
Started Jun 21 05:39:11 PM PDT 24
Finished Jun 21 05:39:19 PM PDT 24
Peak memory 208336 kb
Host smart-c001a478-a0c5-4d60-9e5f-b56770df48c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137011162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2137011162
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3789172371
Short name T870
Test name
Test status
Simulation time 186932850 ps
CPU time 2.66 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:23 PM PDT 24
Peak memory 207004 kb
Host smart-fea4d40b-b423-4bd6-9186-bbc70c49adbd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789172371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3789172371
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1202854194
Short name T2
Test name
Test status
Simulation time 777583440 ps
CPU time 10.42 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:30 PM PDT 24
Peak memory 208448 kb
Host smart-2be5bfb6-8f2b-4a05-a7f0-5e2d2707ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202854194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1202854194
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1870501393
Short name T422
Test name
Test status
Simulation time 19285871 ps
CPU time 1.56 seconds
Started Jun 21 05:39:11 PM PDT 24
Finished Jun 21 05:39:14 PM PDT 24
Peak memory 206776 kb
Host smart-50be96a8-2a3a-4dd3-a9c1-a18596ee1766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870501393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1870501393
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3768030624
Short name T49
Test name
Test status
Simulation time 6198616858 ps
CPU time 36.38 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:56 PM PDT 24
Peak memory 222364 kb
Host smart-65ed0191-8e7e-45d8-a394-b2fcbd3221a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768030624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3768030624
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1242514382
Short name T912
Test name
Test status
Simulation time 497613449 ps
CPU time 7.88 seconds
Started Jun 21 05:39:18 PM PDT 24
Finished Jun 21 05:39:27 PM PDT 24
Peak memory 208156 kb
Host smart-80e6361a-fac5-4a37-9111-64abcb324cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242514382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1242514382
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3894335004
Short name T710
Test name
Test status
Simulation time 1739197479 ps
CPU time 18.93 seconds
Started Jun 21 05:39:19 PM PDT 24
Finished Jun 21 05:39:39 PM PDT 24
Peak memory 210296 kb
Host smart-dfa8ac8d-2021-4fc1-a3ea-59e8656eda3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894335004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3894335004
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.413973581
Short name T612
Test name
Test status
Simulation time 54509896 ps
CPU time 0.78 seconds
Started Jun 21 05:41:49 PM PDT 24
Finished Jun 21 05:41:50 PM PDT 24
Peak memory 205940 kb
Host smart-7de88388-b7c1-479b-acc0-a9443bd60dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413973581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.413973581
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.13010758
Short name T153
Test name
Test status
Simulation time 77910401 ps
CPU time 2.99 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:41:56 PM PDT 24
Peak memory 215604 kb
Host smart-c67da61a-eb0e-4ed4-8801-e9a0c0b192a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13010758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.13010758
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3812293133
Short name T618
Test name
Test status
Simulation time 69167195 ps
CPU time 1.73 seconds
Started Jun 21 05:41:53 PM PDT 24
Finished Jun 21 05:41:56 PM PDT 24
Peak memory 218408 kb
Host smart-74509bd0-8173-42b3-9951-1aca3f416cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812293133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3812293133
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3483444333
Short name T52
Test name
Test status
Simulation time 335219713 ps
CPU time 2.86 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:54 PM PDT 24
Peak memory 214316 kb
Host smart-e4c60428-65ab-4474-b970-3fe6e0ebf323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483444333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3483444333
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.653189105
Short name T839
Test name
Test status
Simulation time 546642882 ps
CPU time 4.03 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:41:57 PM PDT 24
Peak memory 214284 kb
Host smart-af33dc55-1f0f-448f-88cb-d17a8d4097b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653189105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.653189105
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.811914176
Short name T898
Test name
Test status
Simulation time 127233163 ps
CPU time 2.69 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:41:54 PM PDT 24
Peak memory 214276 kb
Host smart-0f587773-425c-4f18-b20f-7fb5958236d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811914176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.811914176
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1695539739
Short name T472
Test name
Test status
Simulation time 954719391 ps
CPU time 8.36 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:59 PM PDT 24
Peak memory 208428 kb
Host smart-c57c6029-3099-4c02-956b-33a209e204fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695539739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1695539739
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3736086303
Short name T263
Test name
Test status
Simulation time 218547538 ps
CPU time 6.4 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:49 PM PDT 24
Peak memory 207956 kb
Host smart-37cf2704-13c3-4d05-8808-c6b82bba93e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736086303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3736086303
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3173524554
Short name T721
Test name
Test status
Simulation time 113220781 ps
CPU time 3.61 seconds
Started Jun 21 05:41:43 PM PDT 24
Finished Jun 21 05:41:48 PM PDT 24
Peak memory 208664 kb
Host smart-f11da08e-b058-4915-a159-eff7c5728e7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173524554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3173524554
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2861833367
Short name T834
Test name
Test status
Simulation time 1562334920 ps
CPU time 19.05 seconds
Started Jun 21 05:41:43 PM PDT 24
Finished Jun 21 05:42:03 PM PDT 24
Peak memory 208536 kb
Host smart-01e11617-f095-4489-acf0-7b140e8e2c18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861833367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2861833367
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3097354209
Short name T345
Test name
Test status
Simulation time 65655655 ps
CPU time 2.44 seconds
Started Jun 21 05:41:49 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 207412 kb
Host smart-fc2a6519-13cb-4ce2-a7bf-255153556123
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097354209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3097354209
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.431979499
Short name T873
Test name
Test status
Simulation time 36603633 ps
CPU time 1.78 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 208700 kb
Host smart-0d7420ba-bb50-45f7-a63b-026b13ae6df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431979499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.431979499
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3804918194
Short name T739
Test name
Test status
Simulation time 1665653453 ps
CPU time 16.65 seconds
Started Jun 21 05:41:42 PM PDT 24
Finished Jun 21 05:41:59 PM PDT 24
Peak memory 208424 kb
Host smart-ac8837c9-43ef-4a36-9e65-837283e94daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804918194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3804918194
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3707862274
Short name T270
Test name
Test status
Simulation time 4433560109 ps
CPU time 102.54 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:43:35 PM PDT 24
Peak memory 222640 kb
Host smart-940739d4-8451-42e7-bb6e-78f1d7c0c293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707862274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3707862274
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2446126903
Short name T167
Test name
Test status
Simulation time 1314827411 ps
CPU time 15.06 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:42:08 PM PDT 24
Peak memory 222616 kb
Host smart-bbb3c5e6-4cf5-4218-96e1-4bdc24938912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446126903 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2446126903
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1769283019
Short name T333
Test name
Test status
Simulation time 160838908 ps
CPU time 5.53 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:41:58 PM PDT 24
Peak memory 214296 kb
Host smart-7ca8a6ea-b45a-4d02-b75f-328a124a925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769283019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1769283019
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3046215056
Short name T782
Test name
Test status
Simulation time 20268057 ps
CPU time 1.39 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 209664 kb
Host smart-038fde6c-d168-4a21-9d9c-92cd6c112622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046215056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3046215056
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1190721539
Short name T565
Test name
Test status
Simulation time 114745280 ps
CPU time 0.77 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 205912 kb
Host smart-2e903b4b-dd18-421b-b4be-44666d7a7f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190721539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1190721539
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1568508990
Short name T28
Test name
Test status
Simulation time 55914959 ps
CPU time 3.56 seconds
Started Jun 21 05:41:53 PM PDT 24
Finished Jun 21 05:41:57 PM PDT 24
Peak memory 210228 kb
Host smart-eed87f04-efe4-46a1-9e50-7612a4b2e218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568508990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1568508990
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3009298752
Short name T395
Test name
Test status
Simulation time 1244031221 ps
CPU time 3.67 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:55 PM PDT 24
Peak memory 214380 kb
Host smart-537c378e-baee-4087-83f3-46755138087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009298752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3009298752
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1383305609
Short name T875
Test name
Test status
Simulation time 287146316 ps
CPU time 3.74 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:54 PM PDT 24
Peak memory 219512 kb
Host smart-a7dc3fe2-f2bb-45d3-be95-ea740c17dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383305609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1383305609
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1493345834
Short name T314
Test name
Test status
Simulation time 61716147 ps
CPU time 2.4 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:53 PM PDT 24
Peak memory 214228 kb
Host smart-f2faa02d-d0e9-498d-be9b-3d8bfac8ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493345834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1493345834
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.2926885663
Short name T564
Test name
Test status
Simulation time 72839041 ps
CPU time 4.27 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:56 PM PDT 24
Peak memory 207904 kb
Host smart-71c51aa8-0021-4565-a970-10148b054ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926885663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2926885663
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.5359460
Short name T202
Test name
Test status
Simulation time 472558149 ps
CPU time 3.93 seconds
Started Jun 21 05:41:51 PM PDT 24
Finished Jun 21 05:41:56 PM PDT 24
Peak memory 208488 kb
Host smart-ec31d26b-db97-40bd-baa2-9c8619d8afbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5359460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.5359460
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3887988205
Short name T787
Test name
Test status
Simulation time 1534566862 ps
CPU time 37.26 seconds
Started Jun 21 05:41:53 PM PDT 24
Finished Jun 21 05:42:31 PM PDT 24
Peak memory 207808 kb
Host smart-be04ceb6-07db-4e3a-b1f0-be3f94f6c3b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887988205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3887988205
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.4176464417
Short name T615
Test name
Test status
Simulation time 3871642617 ps
CPU time 24.49 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:42:18 PM PDT 24
Peak memory 209056 kb
Host smart-3cf72ae9-7d07-4f53-b715-bdbc23e74d5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176464417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.4176464417
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3527964342
Short name T825
Test name
Test status
Simulation time 47413780 ps
CPU time 2.45 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:41:55 PM PDT 24
Peak memory 207056 kb
Host smart-d3fd9710-136c-42ae-bcdd-4291a03c6aa2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527964342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3527964342
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3838605615
Short name T844
Test name
Test status
Simulation time 444922245 ps
CPU time 4.42 seconds
Started Jun 21 05:41:53 PM PDT 24
Finished Jun 21 05:41:58 PM PDT 24
Peak memory 208156 kb
Host smart-c8de0168-736d-4553-8c09-2433c2198128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838605615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3838605615
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4069054786
Short name T563
Test name
Test status
Simulation time 49016920 ps
CPU time 2.26 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:41:55 PM PDT 24
Peak memory 206848 kb
Host smart-f7ff9077-eba5-4d6b-b9fd-10006285d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069054786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4069054786
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4242596661
Short name T130
Test name
Test status
Simulation time 1499856945 ps
CPU time 16.11 seconds
Started Jun 21 05:41:49 PM PDT 24
Finished Jun 21 05:42:06 PM PDT 24
Peak memory 222508 kb
Host smart-74db73b8-077b-4b8d-a6e3-4ab02fb898bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242596661 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4242596661
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2187199747
Short name T789
Test name
Test status
Simulation time 168754786 ps
CPU time 5.04 seconds
Started Jun 21 05:41:52 PM PDT 24
Finished Jun 21 05:41:58 PM PDT 24
Peak memory 209224 kb
Host smart-3dd8dc63-62b9-4399-8df7-2f8bbbf24dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187199747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2187199747
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.131050290
Short name T905
Test name
Test status
Simulation time 436605168 ps
CPU time 2.73 seconds
Started Jun 21 05:41:49 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 210488 kb
Host smart-b8414cbd-d776-47ba-91cf-0607891abf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131050290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.131050290
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2390800034
Short name T467
Test name
Test status
Simulation time 10001554 ps
CPU time 0.84 seconds
Started Jun 21 05:41:57 PM PDT 24
Finished Jun 21 05:41:58 PM PDT 24
Peak memory 205920 kb
Host smart-fdb6336b-1971-473a-a0ec-5312a7eeb0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390800034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2390800034
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3934563023
Short name T415
Test name
Test status
Simulation time 394740360 ps
CPU time 19.83 seconds
Started Jun 21 05:41:57 PM PDT 24
Finished Jun 21 05:42:18 PM PDT 24
Peak memory 214312 kb
Host smart-97d00560-548f-4ea6-8935-9c9a07c118b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3934563023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3934563023
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.437700320
Short name T23
Test name
Test status
Simulation time 193017243 ps
CPU time 2.54 seconds
Started Jun 21 05:41:58 PM PDT 24
Finished Jun 21 05:42:01 PM PDT 24
Peak memory 216880 kb
Host smart-3c3ec1d9-44a5-4a11-bbef-da0d2c3f8a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437700320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.437700320
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3461374496
Short name T617
Test name
Test status
Simulation time 123562601 ps
CPU time 2.21 seconds
Started Jun 21 05:41:55 PM PDT 24
Finished Jun 21 05:41:58 PM PDT 24
Peak memory 214348 kb
Host smart-db6fe892-4107-4888-bbda-0649808d123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461374496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3461374496
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.338217069
Short name T367
Test name
Test status
Simulation time 151540558 ps
CPU time 4.01 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:04 PM PDT 24
Peak memory 214276 kb
Host smart-23f5d365-557c-4f0d-8794-502666fbf43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338217069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.338217069
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1891291686
Short name T328
Test name
Test status
Simulation time 65001959 ps
CPU time 3.42 seconds
Started Jun 21 05:41:55 PM PDT 24
Finished Jun 21 05:41:59 PM PDT 24
Peak memory 214248 kb
Host smart-111fc8fe-6dc9-40f7-a254-691a55376d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891291686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1891291686
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1688268714
Short name T874
Test name
Test status
Simulation time 316336393 ps
CPU time 3.03 seconds
Started Jun 21 05:41:57 PM PDT 24
Finished Jun 21 05:42:00 PM PDT 24
Peak memory 208876 kb
Host smart-5a41eeef-8792-49a8-8948-cc32b8b6b22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688268714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1688268714
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4224424160
Short name T753
Test name
Test status
Simulation time 147456628 ps
CPU time 5.15 seconds
Started Jun 21 05:42:01 PM PDT 24
Finished Jun 21 05:42:07 PM PDT 24
Peak memory 209776 kb
Host smart-50401b94-daf7-443a-98a5-a62ae7161f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224424160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4224424160
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3444696052
Short name T750
Test name
Test status
Simulation time 38647628 ps
CPU time 1.75 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:52 PM PDT 24
Peak memory 206880 kb
Host smart-489af7b8-dfa7-4129-9d51-6c2a6803865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444696052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3444696052
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2645723691
Short name T821
Test name
Test status
Simulation time 550072570 ps
CPU time 3.39 seconds
Started Jun 21 05:41:58 PM PDT 24
Finished Jun 21 05:42:02 PM PDT 24
Peak memory 209096 kb
Host smart-514dcc44-184f-4da3-9035-e0d82ab4bd12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645723691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2645723691
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.844422640
Short name T691
Test name
Test status
Simulation time 115214581 ps
CPU time 2.37 seconds
Started Jun 21 05:41:57 PM PDT 24
Finished Jun 21 05:42:00 PM PDT 24
Peak memory 206980 kb
Host smart-b2648904-961c-4aad-8c3a-b6104b23d5e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844422640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.844422640
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1061238875
Short name T378
Test name
Test status
Simulation time 2665266453 ps
CPU time 6.27 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:06 PM PDT 24
Peak memory 208972 kb
Host smart-c4cb8800-2980-482a-9ebf-1fe10ee88005
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061238875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1061238875
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.117459947
Short name T630
Test name
Test status
Simulation time 320678752 ps
CPU time 2.62 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:02 PM PDT 24
Peak memory 215224 kb
Host smart-06e146cd-21cc-42fe-961e-4596c4352abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117459947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.117459947
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.346461563
Short name T473
Test name
Test status
Simulation time 33676040 ps
CPU time 2.14 seconds
Started Jun 21 05:41:50 PM PDT 24
Finished Jun 21 05:41:53 PM PDT 24
Peak memory 208360 kb
Host smart-c402170e-50e5-48b6-a431-7600a8c06ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346461563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.346461563
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3789658919
Short name T277
Test name
Test status
Simulation time 611583814 ps
CPU time 20.71 seconds
Started Jun 21 05:42:00 PM PDT 24
Finished Jun 21 05:42:21 PM PDT 24
Peak memory 214832 kb
Host smart-5582b59f-625c-44cb-800c-b92b30855e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789658919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3789658919
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.402219791
Short name T786
Test name
Test status
Simulation time 137234441 ps
CPU time 9.02 seconds
Started Jun 21 05:42:01 PM PDT 24
Finished Jun 21 05:42:11 PM PDT 24
Peak memory 219544 kb
Host smart-eb4aac6a-b574-4ead-9b05-804082c8a865
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402219791 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.402219791
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1186565275
Short name T606
Test name
Test status
Simulation time 137839815 ps
CPU time 6.78 seconds
Started Jun 21 05:41:56 PM PDT 24
Finished Jun 21 05:42:03 PM PDT 24
Peak memory 208772 kb
Host smart-321299ac-e3b7-4742-9447-df00f7b74290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186565275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1186565275
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.791009464
Short name T633
Test name
Test status
Simulation time 86069365 ps
CPU time 2.94 seconds
Started Jun 21 05:41:58 PM PDT 24
Finished Jun 21 05:42:01 PM PDT 24
Peak memory 210416 kb
Host smart-dca5b160-1a23-44ae-8cc7-da9302a04049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791009464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.791009464
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1112470378
Short name T457
Test name
Test status
Simulation time 31700385 ps
CPU time 0.7 seconds
Started Jun 21 05:42:05 PM PDT 24
Finished Jun 21 05:42:07 PM PDT 24
Peak memory 205888 kb
Host smart-586a14b6-e70b-483c-ac80-6f0d6fffb8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112470378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1112470378
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1012265078
Short name T374
Test name
Test status
Simulation time 550985500 ps
CPU time 8.49 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:08 PM PDT 24
Peak memory 215368 kb
Host smart-2b45c0ac-1cfa-4632-a1bf-c113a59a0597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012265078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1012265078
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2702537151
Short name T210
Test name
Test status
Simulation time 852791681 ps
CPU time 3.85 seconds
Started Jun 21 05:41:57 PM PDT 24
Finished Jun 21 05:42:01 PM PDT 24
Peak memory 222472 kb
Host smart-7e849135-8022-43c1-8af7-fa47d3fc30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702537151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2702537151
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3589021272
Short name T380
Test name
Test status
Simulation time 51047819 ps
CPU time 2.02 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:09 PM PDT 24
Peak memory 214292 kb
Host smart-0c4b896c-c952-4aca-a5f9-61bfb37202be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589021272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3589021272
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1509876434
Short name T255
Test name
Test status
Simulation time 244474744 ps
CPU time 3.9 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:11 PM PDT 24
Peak memory 218588 kb
Host smart-2f6cb186-5465-4ba6-9857-232f647eb8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509876434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1509876434
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3780123401
Short name T659
Test name
Test status
Simulation time 333258448 ps
CPU time 3.46 seconds
Started Jun 21 05:41:56 PM PDT 24
Finished Jun 21 05:42:00 PM PDT 24
Peak memory 218516 kb
Host smart-2a01a705-3645-425e-ac57-17823a09b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780123401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3780123401
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2107022829
Short name T850
Test name
Test status
Simulation time 157358835 ps
CPU time 2.51 seconds
Started Jun 21 05:41:58 PM PDT 24
Finished Jun 21 05:42:01 PM PDT 24
Peak memory 206792 kb
Host smart-06a33fc8-d791-4c0e-a9e9-ac37dc93adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107022829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2107022829
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1587955691
Short name T272
Test name
Test status
Simulation time 126484734 ps
CPU time 3.21 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:03 PM PDT 24
Peak memory 208452 kb
Host smart-040d3130-56e2-439b-a3ab-0e537cdc2192
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587955691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1587955691
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1098391823
Short name T702
Test name
Test status
Simulation time 2074318380 ps
CPU time 6.73 seconds
Started Jun 21 05:41:58 PM PDT 24
Finished Jun 21 05:42:06 PM PDT 24
Peak memory 208032 kb
Host smart-f984e030-268e-4e70-a1af-9de3b0c6edf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098391823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1098391823
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.4044213528
Short name T742
Test name
Test status
Simulation time 20406823 ps
CPU time 1.92 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:02 PM PDT 24
Peak memory 206940 kb
Host smart-1a792027-1c15-492f-946d-1cda3921fa15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044213528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.4044213528
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.583207191
Short name T196
Test name
Test status
Simulation time 334434900 ps
CPU time 3.04 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:11 PM PDT 24
Peak memory 209296 kb
Host smart-f709e9e2-0c54-4f72-81e8-c80231dae583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583207191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.583207191
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3165127611
Short name T737
Test name
Test status
Simulation time 203709289 ps
CPU time 2.54 seconds
Started Jun 21 05:41:59 PM PDT 24
Finished Jun 21 05:42:02 PM PDT 24
Peak memory 206648 kb
Host smart-32d1905b-d0b8-4e67-8e7d-d0858d8d1d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165127611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3165127611
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3193659648
Short name T664
Test name
Test status
Simulation time 305643982 ps
CPU time 10.27 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:18 PM PDT 24
Peak memory 219072 kb
Host smart-812161a3-e715-44fe-bdb9-9a1f9aabe4ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193659648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3193659648
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1550249508
Short name T76
Test name
Test status
Simulation time 292491503 ps
CPU time 7.95 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:15 PM PDT 24
Peak memory 214300 kb
Host smart-3f34fc1e-7e24-4430-89c7-fa70469cf9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550249508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1550249508
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.682038136
Short name T449
Test name
Test status
Simulation time 452590803 ps
CPU time 6.87 seconds
Started Jun 21 05:42:07 PM PDT 24
Finished Jun 21 05:42:15 PM PDT 24
Peak memory 210308 kb
Host smart-68019d71-117f-4687-8aed-743abd18c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682038136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.682038136
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.331709619
Short name T889
Test name
Test status
Simulation time 22107526 ps
CPU time 0.87 seconds
Started Jun 21 05:42:19 PM PDT 24
Finished Jun 21 05:42:21 PM PDT 24
Peak memory 205936 kb
Host smart-837baf0c-1ed3-4a98-99e2-affcab76e118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331709619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.331709619
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2556773499
Short name T393
Test name
Test status
Simulation time 102116654 ps
CPU time 3.95 seconds
Started Jun 21 05:42:08 PM PDT 24
Finished Jun 21 05:42:13 PM PDT 24
Peak memory 214304 kb
Host smart-2a94b416-d2d5-4e53-9fb5-f527e4cc484d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556773499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2556773499
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4290028961
Short name T241
Test name
Test status
Simulation time 1901742729 ps
CPU time 4.23 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:12 PM PDT 24
Peak memory 209872 kb
Host smart-8e40623e-ba01-48b5-b2bf-66fb60bc198f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290028961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4290028961
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.4041692609
Short name T890
Test name
Test status
Simulation time 97829032 ps
CPU time 1.48 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:09 PM PDT 24
Peak memory 208140 kb
Host smart-28428f9b-21c5-4d34-838d-a7df2c9c30f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041692609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4041692609
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2087815973
Short name T287
Test name
Test status
Simulation time 309276908 ps
CPU time 2.6 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:10 PM PDT 24
Peak memory 214592 kb
Host smart-54bcf6cb-9582-4551-a68f-2514ed55b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087815973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2087815973
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.323221970
Short name T224
Test name
Test status
Simulation time 121162833 ps
CPU time 3.71 seconds
Started Jun 21 05:42:07 PM PDT 24
Finished Jun 21 05:42:12 PM PDT 24
Peak memory 214244 kb
Host smart-267d5fc2-803c-43e3-ab83-434c7a25721d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323221970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.323221970
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.599752880
Short name T452
Test name
Test status
Simulation time 110376356 ps
CPU time 2.69 seconds
Started Jun 21 05:42:05 PM PDT 24
Finished Jun 21 05:42:09 PM PDT 24
Peak memory 219156 kb
Host smart-c9e32867-b837-43d4-b218-8db3c3b8febd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599752880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.599752880
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2369324008
Short name T569
Test name
Test status
Simulation time 56116571 ps
CPU time 2.33 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:10 PM PDT 24
Peak memory 208236 kb
Host smart-b9a713bc-085a-4ef4-a3a6-efb19104145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369324008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2369324008
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1359628723
Short name T437
Test name
Test status
Simulation time 226143241 ps
CPU time 2.98 seconds
Started Jun 21 05:42:07 PM PDT 24
Finished Jun 21 05:42:11 PM PDT 24
Peak memory 206904 kb
Host smart-d012a30b-661f-4a6b-a6f8-80f9549bc0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359628723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1359628723
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3988075870
Short name T766
Test name
Test status
Simulation time 247023343 ps
CPU time 2.42 seconds
Started Jun 21 05:42:05 PM PDT 24
Finished Jun 21 05:42:09 PM PDT 24
Peak memory 206872 kb
Host smart-9f5a3482-9ab3-4462-bbfc-3e8f7a046012
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988075870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3988075870
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4162005434
Short name T853
Test name
Test status
Simulation time 256900245 ps
CPU time 3.92 seconds
Started Jun 21 05:42:05 PM PDT 24
Finished Jun 21 05:42:10 PM PDT 24
Peak memory 206756 kb
Host smart-3c6bf82c-c3e6-4954-a55e-5c42e833eb3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162005434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4162005434
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3297918153
Short name T458
Test name
Test status
Simulation time 144412175 ps
CPU time 4.45 seconds
Started Jun 21 05:42:07 PM PDT 24
Finished Jun 21 05:42:12 PM PDT 24
Peak memory 208932 kb
Host smart-ef780263-cd26-45e2-bd89-c6e566cc9381
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297918153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3297918153
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.167303350
Short name T305
Test name
Test status
Simulation time 42942648 ps
CPU time 2.23 seconds
Started Jun 21 05:42:06 PM PDT 24
Finished Jun 21 05:42:09 PM PDT 24
Peak memory 214408 kb
Host smart-a38c78a6-166a-4c98-bce2-c5eceae73cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167303350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.167303350
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1570766393
Short name T419
Test name
Test status
Simulation time 923407095 ps
CPU time 15.4 seconds
Started Jun 21 05:42:10 PM PDT 24
Finished Jun 21 05:42:26 PM PDT 24
Peak memory 208620 kb
Host smart-aaf61b73-e420-457c-a58a-4d9c2921faa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570766393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1570766393
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2405082876
Short name T375
Test name
Test status
Simulation time 641624160 ps
CPU time 8.92 seconds
Started Jun 21 05:42:04 PM PDT 24
Finished Jun 21 05:42:13 PM PDT 24
Peak memory 222572 kb
Host smart-50f53eb3-1725-4e35-9979-6bf8527ea47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405082876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2405082876
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3812240509
Short name T517
Test name
Test status
Simulation time 177046790 ps
CPU time 5.68 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:25 PM PDT 24
Peak memory 218436 kb
Host smart-591926e4-91cd-47bd-8df1-823d2363f95c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812240509 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3812240509
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3451375789
Short name T491
Test name
Test status
Simulation time 950439419 ps
CPU time 6.9 seconds
Started Jun 21 05:42:05 PM PDT 24
Finished Jun 21 05:42:13 PM PDT 24
Peak memory 208628 kb
Host smart-4c7df527-bea0-413d-b075-ec75648268b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451375789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3451375789
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1750429206
Short name T164
Test name
Test status
Simulation time 292154236 ps
CPU time 3.68 seconds
Started Jun 21 05:42:08 PM PDT 24
Finished Jun 21 05:42:12 PM PDT 24
Peak memory 210412 kb
Host smart-f56413ed-e0a6-43c8-b422-1a9d4eeee4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750429206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1750429206
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.531105367
Short name T836
Test name
Test status
Simulation time 17975399 ps
CPU time 0.79 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:30 PM PDT 24
Peak memory 205916 kb
Host smart-c0f8bc6b-6bb5-4fd6-b561-ea2bea435ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531105367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.531105367
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2550870540
Short name T719
Test name
Test status
Simulation time 48059102 ps
CPU time 2.03 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:21 PM PDT 24
Peak memory 209792 kb
Host smart-71586991-fe68-4e7b-9859-37d6d25b1903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550870540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2550870540
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3580954873
Short name T527
Test name
Test status
Simulation time 73023840 ps
CPU time 2.19 seconds
Started Jun 21 05:42:17 PM PDT 24
Finished Jun 21 05:42:20 PM PDT 24
Peak memory 208832 kb
Host smart-e3443469-461e-42f5-b333-9ae9d4a61665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580954873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3580954873
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1368078922
Short name T833
Test name
Test status
Simulation time 297091816 ps
CPU time 3.1 seconds
Started Jun 21 05:42:17 PM PDT 24
Finished Jun 21 05:42:22 PM PDT 24
Peak memory 214244 kb
Host smart-e7bf14d5-51a5-44c7-91a1-54a7a69edade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368078922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1368078922
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2694519234
Short name T730
Test name
Test status
Simulation time 361099678 ps
CPU time 2.81 seconds
Started Jun 21 05:42:19 PM PDT 24
Finished Jun 21 05:42:22 PM PDT 24
Peak memory 206880 kb
Host smart-d68ff29d-99bf-418e-9c0d-e15f17e56e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694519234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2694519234
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.644880843
Short name T313
Test name
Test status
Simulation time 170730826 ps
CPU time 6.63 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:26 PM PDT 24
Peak memory 219960 kb
Host smart-d05fd449-42a7-4586-a159-f70430ceba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644880843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.644880843
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1942184893
Short name T276
Test name
Test status
Simulation time 30762771 ps
CPU time 2.33 seconds
Started Jun 21 05:42:17 PM PDT 24
Finished Jun 21 05:42:21 PM PDT 24
Peak memory 206880 kb
Host smart-20559a0b-3106-440b-80f0-bd7527072174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942184893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1942184893
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1974148225
Short name T811
Test name
Test status
Simulation time 77251075 ps
CPU time 3.47 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:23 PM PDT 24
Peak memory 208784 kb
Host smart-8f67223a-afaf-4bcc-ae36-3a9c18b53ffc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974148225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1974148225
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3488846426
Short name T515
Test name
Test status
Simulation time 1836344335 ps
CPU time 32.21 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:51 PM PDT 24
Peak memory 208632 kb
Host smart-3ca6081c-b14c-484e-9453-4f5a89324086
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488846426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3488846426
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3913585393
Short name T657
Test name
Test status
Simulation time 149998779 ps
CPU time 2.84 seconds
Started Jun 21 05:42:18 PM PDT 24
Finished Jun 21 05:42:22 PM PDT 24
Peak memory 208744 kb
Host smart-dda3fdc7-bf7e-4f2d-8105-a924732a7ad8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913585393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3913585393
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.302735310
Short name T824
Test name
Test status
Simulation time 2967168164 ps
CPU time 16 seconds
Started Jun 21 05:42:16 PM PDT 24
Finished Jun 21 05:42:33 PM PDT 24
Peak memory 214500 kb
Host smart-26ac45f5-cdbc-42a1-96be-daa176168291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302735310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.302735310
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3272574415
Short name T442
Test name
Test status
Simulation time 425803295 ps
CPU time 3.36 seconds
Started Jun 21 05:42:17 PM PDT 24
Finished Jun 21 05:42:21 PM PDT 24
Peak memory 208512 kb
Host smart-f265d49f-64f0-4e9e-8a5a-061ef924c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272574415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3272574415
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1569804412
Short name T573
Test name
Test status
Simulation time 253370045 ps
CPU time 5.81 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:34 PM PDT 24
Peak memory 222448 kb
Host smart-9d50213e-a142-41e1-94dd-cc781345d63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569804412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1569804412
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.861475029
Short name T759
Test name
Test status
Simulation time 1580770001 ps
CPU time 7.43 seconds
Started Jun 21 05:42:17 PM PDT 24
Finished Jun 21 05:42:25 PM PDT 24
Peak memory 208080 kb
Host smart-5bae1b64-5edc-4388-9846-6d1d1b83e63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861475029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.861475029
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1246451067
Short name T56
Test name
Test status
Simulation time 650970574 ps
CPU time 3.56 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:33 PM PDT 24
Peak memory 210400 kb
Host smart-3b37cde1-0eed-4037-ae7f-88eef90b8a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246451067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1246451067
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3828174449
Short name T99
Test name
Test status
Simulation time 17572866 ps
CPU time 0.79 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:28 PM PDT 24
Peak memory 205920 kb
Host smart-41bae38a-014a-4d86-b057-0de9e6da0d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828174449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3828174449
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3930291853
Short name T356
Test name
Test status
Simulation time 130938597 ps
CPU time 3.3 seconds
Started Jun 21 05:42:32 PM PDT 24
Finished Jun 21 05:42:35 PM PDT 24
Peak memory 209116 kb
Host smart-15170f0c-c94b-4ea9-adec-b8268dd799e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930291853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3930291853
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2819123505
Short name T383
Test name
Test status
Simulation time 356008570 ps
CPU time 4.48 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:42:35 PM PDT 24
Peak memory 222384 kb
Host smart-c55d32b8-fbc3-4c7c-9a33-83e40db21240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819123505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2819123505
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3626015417
Short name T384
Test name
Test status
Simulation time 52264682 ps
CPU time 2.73 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:42:32 PM PDT 24
Peak memory 214292 kb
Host smart-3d35c360-8353-4467-9ba0-175d601e9196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626015417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3626015417
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2023141293
Short name T144
Test name
Test status
Simulation time 95893612 ps
CPU time 2.42 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:30 PM PDT 24
Peak memory 214340 kb
Host smart-b40625cf-3582-40e9-b027-386699c1bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023141293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2023141293
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1747214006
Short name T106
Test name
Test status
Simulation time 127956572 ps
CPU time 4.89 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:42:35 PM PDT 24
Peak memory 208728 kb
Host smart-18a5387e-a0b3-4dce-a550-3695882169eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747214006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1747214006
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1230161168
Short name T869
Test name
Test status
Simulation time 53120940 ps
CPU time 2.81 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:42:33 PM PDT 24
Peak memory 208820 kb
Host smart-76ec50bf-bc95-4bba-a980-437aacf59cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230161168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1230161168
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2610569687
Short name T837
Test name
Test status
Simulation time 131496148 ps
CPU time 3.08 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:31 PM PDT 24
Peak memory 208668 kb
Host smart-7443864e-665f-4aed-82d0-8a37cd3bbe2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610569687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2610569687
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2717497743
Short name T809
Test name
Test status
Simulation time 507718674 ps
CPU time 6.34 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:36 PM PDT 24
Peak memory 208584 kb
Host smart-7e4bbd13-61e2-466d-9cce-32fe434f9981
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717497743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2717497743
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4153162726
Short name T727
Test name
Test status
Simulation time 1726140496 ps
CPU time 6.44 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:34 PM PDT 24
Peak memory 206968 kb
Host smart-00b13abd-1ce6-436a-bb18-c1193e731c4f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153162726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4153162726
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2883766724
Short name T544
Test name
Test status
Simulation time 167797968 ps
CPU time 2.44 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:42:32 PM PDT 24
Peak memory 214288 kb
Host smart-454dffd7-464d-43fe-be16-6d385a27bd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883766724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2883766724
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3473318125
Short name T424
Test name
Test status
Simulation time 160021529 ps
CPU time 2.16 seconds
Started Jun 21 05:42:27 PM PDT 24
Finished Jun 21 05:42:30 PM PDT 24
Peak memory 207140 kb
Host smart-ff34efbf-1ba4-40ba-a4c6-ad6863a8901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473318125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3473318125
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1011298124
Short name T47
Test name
Test status
Simulation time 4767682811 ps
CPU time 44.85 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:43:15 PM PDT 24
Peak memory 216404 kb
Host smart-eed47021-025a-430a-94c8-fa7ef705c899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011298124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1011298124
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1775724742
Short name T191
Test name
Test status
Simulation time 349470535 ps
CPU time 11.73 seconds
Started Jun 21 05:42:30 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 222484 kb
Host smart-264fa7e7-7a13-4ea6-bcc5-7e012b6092de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775724742 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1775724742
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.950031640
Short name T784
Test name
Test status
Simulation time 197118890 ps
CPU time 7.87 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:37 PM PDT 24
Peak memory 214268 kb
Host smart-9a0b4a10-f7f1-4f09-a715-8fa41be6db50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950031640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.950031640
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2225508275
Short name T172
Test name
Test status
Simulation time 482733723 ps
CPU time 3.18 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:42:33 PM PDT 24
Peak memory 209768 kb
Host smart-11c12063-f85d-4e62-afcb-23d6a17af230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225508275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2225508275
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.548901576
Short name T194
Test name
Test status
Simulation time 31132093 ps
CPU time 0.79 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:39 PM PDT 24
Peak memory 205920 kb
Host smart-8eb745f3-7829-47f4-9df8-558b437f90f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548901576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.548901576
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.773457385
Short name T775
Test name
Test status
Simulation time 121308321 ps
CPU time 3.78 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 214324 kb
Host smart-2a7e6a39-816f-43bb-8b9e-4837ef419b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773457385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.773457385
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4166089229
Short name T64
Test name
Test status
Simulation time 74448089 ps
CPU time 2.63 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 209212 kb
Host smart-7c2dcf13-fcdc-4a7f-ad49-d3c7cad187c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166089229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4166089229
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2142755790
Short name T108
Test name
Test status
Simulation time 98476816 ps
CPU time 4.15 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 222348 kb
Host smart-f1b11ad9-ca1c-4607-990c-6fda6e07db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142755790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2142755790
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1227022780
Short name T650
Test name
Test status
Simulation time 94778407 ps
CPU time 3.32 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 219772 kb
Host smart-1cb1217f-5466-40d0-948b-a119d7e25ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227022780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1227022780
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2712649189
Short name T340
Test name
Test status
Simulation time 1129637361 ps
CPU time 8.34 seconds
Started Jun 21 05:42:32 PM PDT 24
Finished Jun 21 05:42:40 PM PDT 24
Peak memory 210332 kb
Host smart-65fffa05-0629-4a1e-b337-d1715d36ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712649189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2712649189
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.583709575
Short name T376
Test name
Test status
Simulation time 2294917917 ps
CPU time 32.67 seconds
Started Jun 21 05:42:29 PM PDT 24
Finished Jun 21 05:43:03 PM PDT 24
Peak memory 209112 kb
Host smart-6ce1eeb9-1db1-4848-906b-73ae4870b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583709575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.583709575
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.672900656
Short name T331
Test name
Test status
Simulation time 1571886628 ps
CPU time 15.39 seconds
Started Jun 21 05:42:26 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 208676 kb
Host smart-52dae58d-a53b-4cd3-b721-e732109ff121
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672900656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.672900656
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2220701275
Short name T698
Test name
Test status
Simulation time 207067331 ps
CPU time 3.58 seconds
Started Jun 21 05:42:28 PM PDT 24
Finished Jun 21 05:42:32 PM PDT 24
Peak memory 208868 kb
Host smart-8e87d940-00be-48f7-9b1c-402854cfdbec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220701275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2220701275
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.759277015
Short name T552
Test name
Test status
Simulation time 606920928 ps
CPU time 3.82 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 215660 kb
Host smart-b8e3aefa-d36c-4b11-b281-150377ce7230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759277015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.759277015
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3507805456
Short name T684
Test name
Test status
Simulation time 176620999 ps
CPU time 2.76 seconds
Started Jun 21 05:42:26 PM PDT 24
Finished Jun 21 05:42:30 PM PDT 24
Peak memory 206784 kb
Host smart-7e83c1c5-f1cc-42a1-b5e9-d6dba860956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507805456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3507805456
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.68101504
Short name T777
Test name
Test status
Simulation time 3357347182 ps
CPU time 35.6 seconds
Started Jun 21 05:42:40 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 217664 kb
Host smart-dd883cc4-0bb4-4c49-80b0-f02b3a179ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68101504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.68101504
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4255122769
Short name T109
Test name
Test status
Simulation time 83055352 ps
CPU time 4.04 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:41 PM PDT 24
Peak memory 209340 kb
Host smart-111810af-ccfb-4121-a741-903bdb34049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255122769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4255122769
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2663102537
Short name T857
Test name
Test status
Simulation time 122793161 ps
CPU time 2 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:38 PM PDT 24
Peak memory 210160 kb
Host smart-65569335-ed56-4809-8a30-cde43e5dc064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663102537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2663102537
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3771592290
Short name T695
Test name
Test status
Simulation time 44641273 ps
CPU time 0.87 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:38 PM PDT 24
Peak memory 205920 kb
Host smart-e5159936-7926-48c9-bc3a-3d6237614061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771592290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3771592290
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1561631539
Short name T405
Test name
Test status
Simulation time 33879114 ps
CPU time 2.53 seconds
Started Jun 21 05:42:40 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 214312 kb
Host smart-2b49ce30-56fd-4112-b8a5-545431c307d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561631539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1561631539
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2355680968
Short name T105
Test name
Test status
Simulation time 87092409 ps
CPU time 3.8 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 215836 kb
Host smart-64c59fdd-bad7-4b3f-abe7-c374f329bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355680968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2355680968
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1677037485
Short name T41
Test name
Test status
Simulation time 33983461 ps
CPU time 1.8 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:40 PM PDT 24
Peak memory 214308 kb
Host smart-8e90195d-a4fa-4699-82e2-c9ffee2942d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677037485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1677037485
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1893368698
Short name T92
Test name
Test status
Simulation time 84054869 ps
CPU time 3.8 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:41 PM PDT 24
Peak memory 214288 kb
Host smart-964b54b8-5a2c-4465-82a7-78cd64cece9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893368698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1893368698
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2575390353
Short name T549
Test name
Test status
Simulation time 658682709 ps
CPU time 5.45 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:41 PM PDT 24
Peak memory 220260 kb
Host smart-a720d783-feca-4ee0-a9d1-818ae96dea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575390353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2575390353
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4153662748
Short name T848
Test name
Test status
Simulation time 441772863 ps
CPU time 4.6 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:41 PM PDT 24
Peak memory 207416 kb
Host smart-2b775aa9-662b-46dd-9adc-15c40d1eb088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153662748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4153662748
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.573934692
Short name T443
Test name
Test status
Simulation time 66672084 ps
CPU time 2.45 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 206712 kb
Host smart-f8a02358-beb9-4689-890d-62a5dcf10d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573934692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.573934692
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3154087131
Short name T818
Test name
Test status
Simulation time 345370838 ps
CPU time 7.22 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:45 PM PDT 24
Peak memory 209116 kb
Host smart-e7a8d153-72ea-458b-bece-7230feba2df6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154087131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3154087131
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.815717765
Short name T671
Test name
Test status
Simulation time 204016526 ps
CPU time 3.2 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:38 PM PDT 24
Peak memory 208604 kb
Host smart-bd3af693-6542-43f3-a5ea-83b2a38d046a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815717765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.815717765
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3339549461
Short name T454
Test name
Test status
Simulation time 319290956 ps
CPU time 2.46 seconds
Started Jun 21 05:42:40 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 206872 kb
Host smart-c9656bb3-c565-4173-949c-16cfe0bdbc35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339549461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3339549461
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.192988237
Short name T535
Test name
Test status
Simulation time 1075307997 ps
CPU time 11.05 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:42:51 PM PDT 24
Peak memory 214252 kb
Host smart-1362908c-19f5-4abd-a438-c934863fdc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192988237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.192988237
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3104302889
Short name T608
Test name
Test status
Simulation time 72371858 ps
CPU time 2.35 seconds
Started Jun 21 05:42:34 PM PDT 24
Finished Jun 21 05:42:37 PM PDT 24
Peak memory 208192 kb
Host smart-36e4d14d-749f-4031-b0aa-0bad32cc5927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104302889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3104302889
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3196820420
Short name T46
Test name
Test status
Simulation time 1131782751 ps
CPU time 33.44 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:43:12 PM PDT 24
Peak memory 222456 kb
Host smart-ef803db1-86a8-4e94-bf04-84c04f1d1fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196820420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3196820420
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3649614819
Short name T714
Test name
Test status
Simulation time 309413428 ps
CPU time 4.28 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 207612 kb
Host smart-7604fbd2-d5fe-4c43-ba39-107ecdb279ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649614819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3649614819
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3668824722
Short name T219
Test name
Test status
Simulation time 102642335 ps
CPU time 1.42 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:40 PM PDT 24
Peak memory 209648 kb
Host smart-4696a59d-a9f4-4d08-acd3-3b5991ca5d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668824722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3668824722
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.606884856
Short name T763
Test name
Test status
Simulation time 44122235 ps
CPU time 0.89 seconds
Started Jun 21 05:42:48 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 205852 kb
Host smart-15974881-bf31-49be-a18c-c4e2b554b23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606884856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.606884856
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.221747499
Short name T302
Test name
Test status
Simulation time 1034439008 ps
CPU time 28.82 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:43:05 PM PDT 24
Peak memory 214964 kb
Host smart-9adb168a-519e-4e42-a241-d6899dbf2eb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221747499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.221747499
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1814177234
Short name T588
Test name
Test status
Simulation time 521959457 ps
CPU time 3.74 seconds
Started Jun 21 05:42:48 PM PDT 24
Finished Jun 21 05:42:53 PM PDT 24
Peak memory 208928 kb
Host smart-2c11a5db-d962-4f1d-9d1a-6ca051dd0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814177234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1814177234
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3584770471
Short name T604
Test name
Test status
Simulation time 852302922 ps
CPU time 9.97 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:47 PM PDT 24
Peak memory 218368 kb
Host smart-1063846b-37e9-407d-858f-e9eed3371396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584770471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3584770471
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3619766683
Short name T269
Test name
Test status
Simulation time 296988126 ps
CPU time 3.08 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 214268 kb
Host smart-83b43048-ddec-4cd2-83fe-7b6aa4cd4460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619766683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3619766683
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.887437993
Short name T689
Test name
Test status
Simulation time 69619422 ps
CPU time 1.59 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:40 PM PDT 24
Peak memory 206100 kb
Host smart-049d3a57-bb90-4cbe-9e08-bff7e63a0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887437993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.887437993
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3870314555
Short name T699
Test name
Test status
Simulation time 461674736 ps
CPU time 5.2 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:43 PM PDT 24
Peak memory 207428 kb
Host smart-36d1437b-5907-4c2d-9e5d-29f148e903cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870314555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3870314555
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1816457340
Short name T445
Test name
Test status
Simulation time 511959529 ps
CPU time 14.71 seconds
Started Jun 21 05:42:37 PM PDT 24
Finished Jun 21 05:42:53 PM PDT 24
Peak memory 207960 kb
Host smart-1dad4b6d-6345-42cb-9d22-20b2062d317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816457340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1816457340
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.582190873
Short name T859
Test name
Test status
Simulation time 10527836723 ps
CPU time 70.42 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:43:49 PM PDT 24
Peak memory 208888 kb
Host smart-217bc1ab-a2fb-4d9e-9e4b-d1fc5f2dd5ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582190873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.582190873
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2374216162
Short name T342
Test name
Test status
Simulation time 1011756423 ps
CPU time 3.41 seconds
Started Jun 21 05:42:38 PM PDT 24
Finished Jun 21 05:42:42 PM PDT 24
Peak memory 206976 kb
Host smart-dfac64da-3d1e-4a08-903e-9c9d21550dc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374216162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2374216162
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1628717118
Short name T645
Test name
Test status
Simulation time 98565947 ps
CPU time 3.36 seconds
Started Jun 21 05:42:36 PM PDT 24
Finished Jun 21 05:42:41 PM PDT 24
Peak memory 206888 kb
Host smart-04f76d1c-4089-43c1-bfea-3d72e95c8614
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628717118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1628717118
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1657405382
Short name T327
Test name
Test status
Simulation time 282098518 ps
CPU time 5.5 seconds
Started Jun 21 05:42:47 PM PDT 24
Finished Jun 21 05:42:54 PM PDT 24
Peak memory 209772 kb
Host smart-a76fc231-c410-4789-8f54-aba0077f5f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657405382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1657405382
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.987690172
Short name T729
Test name
Test status
Simulation time 119162949 ps
CPU time 3.44 seconds
Started Jun 21 05:42:35 PM PDT 24
Finished Jun 21 05:42:40 PM PDT 24
Peak memory 208340 kb
Host smart-da162478-e829-4c9b-98a5-4dca78e070fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987690172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.987690172
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4147456501
Short name T261
Test name
Test status
Simulation time 2879839802 ps
CPU time 83.72 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:44:10 PM PDT 24
Peak memory 216072 kb
Host smart-4f458e61-589f-47c7-935b-6eddb04f89e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147456501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4147456501
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2534927792
Short name T303
Test name
Test status
Simulation time 112874010 ps
CPU time 4.65 seconds
Started Jun 21 05:42:40 PM PDT 24
Finished Jun 21 05:42:45 PM PDT 24
Peak memory 219692 kb
Host smart-1da5e94f-f7d7-4ff7-8cc8-d9bd4fa43fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534927792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2534927792
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2417432942
Short name T460
Test name
Test status
Simulation time 113090464 ps
CPU time 1.7 seconds
Started Jun 21 05:42:48 PM PDT 24
Finished Jun 21 05:42:51 PM PDT 24
Peak memory 210080 kb
Host smart-cf422597-9f82-4bb8-9df4-44fa6b25f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417432942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2417432942
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3402628728
Short name T704
Test name
Test status
Simulation time 23755094 ps
CPU time 0.95 seconds
Started Jun 21 05:39:24 PM PDT 24
Finished Jun 21 05:39:26 PM PDT 24
Peak memory 205948 kb
Host smart-322a97dc-1b36-48f0-b435-bc1605263718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402628728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3402628728
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3593844231
Short name T377
Test name
Test status
Simulation time 4661314208 ps
CPU time 55.61 seconds
Started Jun 21 05:39:27 PM PDT 24
Finished Jun 21 05:40:23 PM PDT 24
Peak memory 215080 kb
Host smart-dd5b066d-fae5-481d-b42d-3c27ff9558c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593844231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3593844231
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2436261813
Short name T254
Test name
Test status
Simulation time 220752281 ps
CPU time 3.09 seconds
Started Jun 21 05:39:25 PM PDT 24
Finished Jun 21 05:39:28 PM PDT 24
Peak memory 210468 kb
Host smart-b00eb660-42d1-4805-be7c-6cf6c71b9b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436261813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2436261813
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.759840436
Short name T780
Test name
Test status
Simulation time 5606179782 ps
CPU time 12.65 seconds
Started Jun 21 05:39:29 PM PDT 24
Finished Jun 21 05:39:43 PM PDT 24
Peak memory 218280 kb
Host smart-eaef4339-d971-42ab-adaa-3530b409c3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759840436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.759840436
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4135604516
Short name T761
Test name
Test status
Simulation time 92284295 ps
CPU time 4.66 seconds
Started Jun 21 05:39:28 PM PDT 24
Finished Jun 21 05:39:34 PM PDT 24
Peak memory 214296 kb
Host smart-b52b3434-aa31-4973-9f12-abbcafa2ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135604516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4135604516
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.568503941
Short name T282
Test name
Test status
Simulation time 78633698 ps
CPU time 2.37 seconds
Started Jun 21 05:39:27 PM PDT 24
Finished Jun 21 05:39:30 PM PDT 24
Peak memory 214308 kb
Host smart-a75d1976-ca02-4204-8195-a64f3306bd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568503941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.568503941
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.933077176
Short name T242
Test name
Test status
Simulation time 94006227 ps
CPU time 3.35 seconds
Started Jun 21 05:39:27 PM PDT 24
Finished Jun 21 05:39:31 PM PDT 24
Peak memory 222448 kb
Host smart-15fcf3c4-37b2-473b-8c3d-66c70d6d587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933077176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.933077176
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2977413153
Short name T262
Test name
Test status
Simulation time 512114207 ps
CPU time 10.61 seconds
Started Jun 21 05:39:29 PM PDT 24
Finished Jun 21 05:39:40 PM PDT 24
Peak memory 214196 kb
Host smart-cd030f0c-f108-4fa3-a84f-8c6ce6116d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977413153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2977413153
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.93667136
Short name T557
Test name
Test status
Simulation time 254358853 ps
CPU time 3.35 seconds
Started Jun 21 05:39:27 PM PDT 24
Finished Jun 21 05:39:31 PM PDT 24
Peak memory 207296 kb
Host smart-496a31fb-00b2-47d4-beb5-98be9619d945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93667136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.93667136
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3891377858
Short name T137
Test name
Test status
Simulation time 70543231 ps
CPU time 2.7 seconds
Started Jun 21 05:39:26 PM PDT 24
Finished Jun 21 05:39:30 PM PDT 24
Peak memory 208112 kb
Host smart-0b1b69fc-1d7c-47f3-94c9-1d30b0eeb1c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891377858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3891377858
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.888715918
Short name T536
Test name
Test status
Simulation time 75579451 ps
CPU time 1.8 seconds
Started Jun 21 05:39:28 PM PDT 24
Finished Jun 21 05:39:30 PM PDT 24
Peak memory 206780 kb
Host smart-6d412b15-9bb1-4fd1-9a51-c7eb58492da6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888715918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.888715918
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1538182922
Short name T678
Test name
Test status
Simulation time 1163443648 ps
CPU time 23.15 seconds
Started Jun 21 05:39:28 PM PDT 24
Finished Jun 21 05:39:52 PM PDT 24
Peak memory 208864 kb
Host smart-d361a3dc-3227-41f5-849a-3b61d5e5a271
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538182922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1538182922
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3889157506
Short name T743
Test name
Test status
Simulation time 157421985 ps
CPU time 3.13 seconds
Started Jun 21 05:39:26 PM PDT 24
Finished Jun 21 05:39:30 PM PDT 24
Peak memory 215912 kb
Host smart-30ddc979-7f60-4551-885b-5b88d05aa4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889157506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3889157506
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1923400046
Short name T674
Test name
Test status
Simulation time 150440321 ps
CPU time 3.46 seconds
Started Jun 21 05:39:27 PM PDT 24
Finished Jun 21 05:39:31 PM PDT 24
Peak memory 208760 kb
Host smart-a3faee48-94b3-48b4-8230-3738b82c951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923400046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1923400046
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.909760435
Short name T856
Test name
Test status
Simulation time 450053245 ps
CPU time 17.54 seconds
Started Jun 21 05:39:28 PM PDT 24
Finished Jun 21 05:39:47 PM PDT 24
Peak memory 222516 kb
Host smart-644fb920-8753-48bc-8e9e-0e1fdb87340d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909760435 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.909760435
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1293877381
Short name T723
Test name
Test status
Simulation time 149285548 ps
CPU time 2.97 seconds
Started Jun 21 05:39:25 PM PDT 24
Finished Jun 21 05:39:29 PM PDT 24
Peak memory 218060 kb
Host smart-778de96a-e5b4-43fa-ba51-9c3d35686f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293877381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1293877381
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1295142861
Short name T389
Test name
Test status
Simulation time 281001148 ps
CPU time 3.03 seconds
Started Jun 21 05:39:25 PM PDT 24
Finished Jun 21 05:39:29 PM PDT 24
Peak memory 210164 kb
Host smart-4c8f62bc-64c5-4c7e-8424-cdc4eec5c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295142861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1295142861
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1733212520
Short name T897
Test name
Test status
Simulation time 43275395 ps
CPU time 0.79 seconds
Started Jun 21 05:42:44 PM PDT 24
Finished Jun 21 05:42:46 PM PDT 24
Peak memory 205916 kb
Host smart-3d59dded-9b37-4306-bf84-a4082475d8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733212520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1733212520
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1795674850
Short name T589
Test name
Test status
Simulation time 245719921 ps
CPU time 6.54 seconds
Started Jun 21 05:42:48 PM PDT 24
Finished Jun 21 05:42:56 PM PDT 24
Peak memory 209896 kb
Host smart-385fa75c-a203-49ca-9e51-3be614cf2724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795674850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1795674850
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1988036258
Short name T790
Test name
Test status
Simulation time 256647085 ps
CPU time 6.47 seconds
Started Jun 21 05:42:46 PM PDT 24
Finished Jun 21 05:42:54 PM PDT 24
Peak memory 218228 kb
Host smart-23386ba5-423b-4105-9b19-078c7ecc6b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988036258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1988036258
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.528938689
Short name T319
Test name
Test status
Simulation time 51411046 ps
CPU time 1.89 seconds
Started Jun 21 05:42:46 PM PDT 24
Finished Jun 21 05:42:49 PM PDT 24
Peak memory 214308 kb
Host smart-b7ba0fa0-e886-4ee1-bd5e-f51e72620cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528938689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.528938689
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3295947644
Short name T317
Test name
Test status
Simulation time 521914393 ps
CPU time 3.93 seconds
Started Jun 21 05:42:47 PM PDT 24
Finished Jun 21 05:42:52 PM PDT 24
Peak memory 222296 kb
Host smart-99bd7f7a-2901-4a7f-8369-6a5063585727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295947644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3295947644
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2916429433
Short name T253
Test name
Test status
Simulation time 95499498 ps
CPU time 3.1 seconds
Started Jun 21 05:42:46 PM PDT 24
Finished Jun 21 05:42:51 PM PDT 24
Peak memory 209680 kb
Host smart-ab28f19d-573a-453d-8961-17cf3ccfe650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916429433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2916429433
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.533864571
Short name T396
Test name
Test status
Simulation time 120738704 ps
CPU time 4.88 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:51 PM PDT 24
Peak memory 209044 kb
Host smart-aa3183db-fcf3-4000-9282-9a25421249cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533864571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.533864571
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1583743330
Short name T576
Test name
Test status
Simulation time 778157546 ps
CPU time 3.23 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 208632 kb
Host smart-88f986a6-dd6e-465c-95d5-56c1489bd938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583743330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1583743330
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1359564279
Short name T353
Test name
Test status
Simulation time 92455298 ps
CPU time 2.78 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 208608 kb
Host smart-6e25eedc-b845-4990-bcea-847451a0873e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359564279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1359564279
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4280879144
Short name T601
Test name
Test status
Simulation time 121868402 ps
CPU time 2.82 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 207048 kb
Host smart-3cc135fa-e309-44be-a733-37362f03e730
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280879144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4280879144
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1572309477
Short name T631
Test name
Test status
Simulation time 4386159302 ps
CPU time 48.11 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:43:35 PM PDT 24
Peak memory 208672 kb
Host smart-dcda0032-44fb-449e-8acf-2dc1ad95b1ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572309477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1572309477
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1982282975
Short name T495
Test name
Test status
Simulation time 219902600 ps
CPU time 2.78 seconds
Started Jun 21 05:42:44 PM PDT 24
Finished Jun 21 05:42:49 PM PDT 24
Peak memory 208588 kb
Host smart-3e26ff39-074c-4bff-9b32-adb68cd6b140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982282975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1982282975
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3028141107
Short name T418
Test name
Test status
Simulation time 158901136 ps
CPU time 4.68 seconds
Started Jun 21 05:42:44 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 208108 kb
Host smart-7f08b614-33b9-4367-85d3-35c67e1ba9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028141107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3028141107
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1361851932
Short name T636
Test name
Test status
Simulation time 2196194707 ps
CPU time 5.5 seconds
Started Jun 21 05:42:46 PM PDT 24
Finished Jun 21 05:42:53 PM PDT 24
Peak memory 214420 kb
Host smart-b991d43a-ef69-4c05-bef8-3a60804651a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361851932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1361851932
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2287740859
Short name T510
Test name
Test status
Simulation time 4694318838 ps
CPU time 10.1 seconds
Started Jun 21 05:42:49 PM PDT 24
Finished Jun 21 05:43:00 PM PDT 24
Peak memory 211712 kb
Host smart-da2028e8-9ab9-4ce9-86b3-5fcd120e0a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287740859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2287740859
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2668876535
Short name T666
Test name
Test status
Simulation time 16793388 ps
CPU time 0.85 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:42:54 PM PDT 24
Peak memory 205916 kb
Host smart-5969f47f-7374-4a82-9ce2-61a2f3ea6ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668876535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2668876535
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1520968564
Short name T851
Test name
Test status
Simulation time 8170991215 ps
CPU time 80.09 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:44:13 PM PDT 24
Peak memory 214432 kb
Host smart-7b5fc879-2d7b-4cc0-af2a-6fedbdf0e63c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520968564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1520968564
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1048094646
Short name T68
Test name
Test status
Simulation time 22242742 ps
CPU time 1.72 seconds
Started Jun 21 05:42:50 PM PDT 24
Finished Jun 21 05:42:53 PM PDT 24
Peak memory 207720 kb
Host smart-a6dbef45-1c2e-40ad-823c-bceb069773a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048094646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1048094646
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3947766296
Short name T734
Test name
Test status
Simulation time 68685712 ps
CPU time 1.55 seconds
Started Jun 21 05:42:54 PM PDT 24
Finished Jun 21 05:42:57 PM PDT 24
Peak memory 214308 kb
Host smart-c83b100a-400d-4297-8bef-7dffa942d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947766296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3947766296
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3749214220
Short name T290
Test name
Test status
Simulation time 691949546 ps
CPU time 4.46 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:42:59 PM PDT 24
Peak memory 214212 kb
Host smart-b3c3ea89-d199-4532-ab90-db141dde9cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749214220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3749214220
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2575914537
Short name T900
Test name
Test status
Simulation time 115190747 ps
CPU time 4.65 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:42:59 PM PDT 24
Peak memory 215664 kb
Host smart-4ee585aa-f63f-4004-abc1-d519eb248373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575914537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2575914537
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.55847709
Short name T711
Test name
Test status
Simulation time 32111274 ps
CPU time 2.4 seconds
Started Jun 21 05:42:55 PM PDT 24
Finished Jun 21 05:42:58 PM PDT 24
Peak memory 208260 kb
Host smart-d7f8b91f-60f3-48a7-869a-f8fc84d7d76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55847709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.55847709
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3182733663
Short name T297
Test name
Test status
Simulation time 39270609 ps
CPU time 1.82 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:49 PM PDT 24
Peak memory 206968 kb
Host smart-df3f480c-4ae5-4db3-87d9-c15aa3fb400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182733663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3182733663
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1141942306
Short name T547
Test name
Test status
Simulation time 184173253 ps
CPU time 2.5 seconds
Started Jun 21 05:42:54 PM PDT 24
Finished Jun 21 05:42:57 PM PDT 24
Peak memory 206960 kb
Host smart-5483b59b-a264-4e87-b4a1-5845eada3285
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141942306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1141942306
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3177751533
Short name T831
Test name
Test status
Simulation time 1140385900 ps
CPU time 8 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:55 PM PDT 24
Peak memory 207996 kb
Host smart-54590d84-ae16-4c1d-8781-972df8f22dbe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177751533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3177751533
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2401087061
Short name T562
Test name
Test status
Simulation time 1038571174 ps
CPU time 25.61 seconds
Started Jun 21 05:42:54 PM PDT 24
Finished Jun 21 05:43:20 PM PDT 24
Peak memory 208552 kb
Host smart-b009f08f-6575-4926-9d6a-4cab59b6b48a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401087061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2401087061
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4139142657
Short name T914
Test name
Test status
Simulation time 229050524 ps
CPU time 2.53 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:42:55 PM PDT 24
Peak memory 207356 kb
Host smart-02b1cd1d-d405-4c8b-8b06-e53f23e1465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139142657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4139142657
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2566967916
Short name T653
Test name
Test status
Simulation time 60797573 ps
CPU time 2.42 seconds
Started Jun 21 05:42:45 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 207408 kb
Host smart-db2ecb69-411b-4bc8-9245-d83627d8d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566967916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2566967916
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1968573858
Short name T832
Test name
Test status
Simulation time 4343850171 ps
CPU time 34.88 seconds
Started Jun 21 05:42:54 PM PDT 24
Finished Jun 21 05:43:30 PM PDT 24
Peak memory 222504 kb
Host smart-2643e0f2-8090-4d8b-835e-483f3e419470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968573858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1968573858
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1979780214
Short name T555
Test name
Test status
Simulation time 81025832 ps
CPU time 3.69 seconds
Started Jun 21 05:42:54 PM PDT 24
Finished Jun 21 05:42:58 PM PDT 24
Peak memory 207508 kb
Host smart-1cb829df-9d22-4fda-80a7-8a1c24505fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979780214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1979780214
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1942522555
Short name T506
Test name
Test status
Simulation time 335892836 ps
CPU time 2.18 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:42:56 PM PDT 24
Peak memory 210492 kb
Host smart-59a596e8-75fe-4d42-b434-b1cb754a5ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942522555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1942522555
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2198540947
Short name T613
Test name
Test status
Simulation time 11952400 ps
CPU time 0.92 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:04 PM PDT 24
Peak memory 205900 kb
Host smart-047d342c-2bb4-4b77-8165-163466610599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198540947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2198540947
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2348254906
Short name T55
Test name
Test status
Simulation time 49843824 ps
CPU time 3.11 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:42:57 PM PDT 24
Peak memory 214308 kb
Host smart-748ca3b4-734b-4aaa-bd74-c31d31300beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348254906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2348254906
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3779757115
Short name T249
Test name
Test status
Simulation time 88193191 ps
CPU time 4.34 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:42:58 PM PDT 24
Peak memory 214304 kb
Host smart-898993d8-1205-46fe-bce2-45a2c2c9b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779757115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3779757115
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3551181567
Short name T444
Test name
Test status
Simulation time 52992454 ps
CPU time 2.88 seconds
Started Jun 21 05:42:57 PM PDT 24
Finished Jun 21 05:43:00 PM PDT 24
Peak memory 207672 kb
Host smart-224c4b33-9be6-4ff9-84ca-1319725b0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551181567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3551181567
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1507477269
Short name T433
Test name
Test status
Simulation time 182922620 ps
CPU time 3.16 seconds
Started Jun 21 05:42:57 PM PDT 24
Finished Jun 21 05:43:01 PM PDT 24
Peak memory 206824 kb
Host smart-4769a2dd-6da5-4930-86d7-45bcd1b94048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507477269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1507477269
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3213556741
Short name T346
Test name
Test status
Simulation time 87180935 ps
CPU time 3.8 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:42:57 PM PDT 24
Peak memory 206832 kb
Host smart-27c448f0-0623-4ddb-a4b3-4560e0bbfe67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213556741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3213556741
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1280247729
Short name T203
Test name
Test status
Simulation time 71132158 ps
CPU time 3.58 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:42:58 PM PDT 24
Peak memory 209052 kb
Host smart-f7f74cdb-0c85-4e39-9850-c0d7af6c01b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280247729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1280247729
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2057808909
Short name T225
Test name
Test status
Simulation time 324347135 ps
CPU time 9.14 seconds
Started Jun 21 05:42:54 PM PDT 24
Finished Jun 21 05:43:04 PM PDT 24
Peak memory 207052 kb
Host smart-d03c7dc0-d90a-4bc9-9fc7-05d866d8cfb9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057808909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2057808909
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.868050796
Short name T524
Test name
Test status
Simulation time 818203915 ps
CPU time 15.27 seconds
Started Jun 21 05:43:00 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 214296 kb
Host smart-edcb0f99-c3fe-4687-8576-54b018f7a228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868050796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.868050796
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.989394055
Short name T685
Test name
Test status
Simulation time 87597452 ps
CPU time 2.56 seconds
Started Jun 21 05:42:53 PM PDT 24
Finished Jun 21 05:42:56 PM PDT 24
Peak memory 206796 kb
Host smart-1f693cb1-48f8-46e4-9003-0d1e4e6e0162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989394055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.989394055
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3914478928
Short name T654
Test name
Test status
Simulation time 1050717914 ps
CPU time 36.23 seconds
Started Jun 21 05:43:00 PM PDT 24
Finished Jun 21 05:43:38 PM PDT 24
Peak memory 216456 kb
Host smart-1a923cf6-4e48-4b26-b660-d2ecd81e04fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914478928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3914478928
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3259807546
Short name T398
Test name
Test status
Simulation time 4664246195 ps
CPU time 58.99 seconds
Started Jun 21 05:42:52 PM PDT 24
Finished Jun 21 05:43:52 PM PDT 24
Peak memory 209256 kb
Host smart-57bd06b3-8a70-483d-87b6-b31ef5f79d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259807546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3259807546
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.149769986
Short name T208
Test name
Test status
Simulation time 91785698 ps
CPU time 2.16 seconds
Started Jun 21 05:43:02 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 209740 kb
Host smart-dbd102e8-f354-4841-b124-cf099def2580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149769986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.149769986
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3096079456
Short name T494
Test name
Test status
Simulation time 11733986 ps
CPU time 0.88 seconds
Started Jun 21 05:43:08 PM PDT 24
Finished Jun 21 05:43:10 PM PDT 24
Peak memory 205892 kb
Host smart-ca6da120-9edc-4c7c-9a7d-ed737d7de75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096079456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3096079456
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3074648070
Short name T584
Test name
Test status
Simulation time 981054725 ps
CPU time 32.93 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:36 PM PDT 24
Peak memory 209244 kb
Host smart-d07bf4cb-aba7-4273-a870-3a8417fbe4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074648070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3074648070
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1729033828
Short name T904
Test name
Test status
Simulation time 286327508 ps
CPU time 2.72 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:05 PM PDT 24
Peak memory 214364 kb
Host smart-8692d375-a2de-49db-b5c0-1d533a553a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729033828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1729033828
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2555790391
Short name T347
Test name
Test status
Simulation time 144742323 ps
CPU time 4.38 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 221732 kb
Host smart-46f8adaa-3c3e-43c2-9b08-af3e4dcb2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555790391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2555790391
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3266687504
Short name T514
Test name
Test status
Simulation time 639436308 ps
CPU time 3.35 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 222388 kb
Host smart-b7a2d9d3-9792-4ee6-bf62-01e380a4bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266687504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3266687504
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2238520348
Short name T336
Test name
Test status
Simulation time 117046746 ps
CPU time 5.83 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:09 PM PDT 24
Peak memory 210376 kb
Host smart-1043c0d6-dbda-47fb-9c2a-67f841d70016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238520348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2238520348
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4164806564
Short name T881
Test name
Test status
Simulation time 607539918 ps
CPU time 4.8 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:07 PM PDT 24
Peak memory 206812 kb
Host smart-c5af2b08-ec9c-47e7-a05f-72303ff30757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164806564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4164806564
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3288586151
Short name T773
Test name
Test status
Simulation time 3784557021 ps
CPU time 27.44 seconds
Started Jun 21 05:43:02 PM PDT 24
Finished Jun 21 05:43:31 PM PDT 24
Peak memory 208348 kb
Host smart-8e98b193-9309-46a8-b392-4c5fb2488196
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288586151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3288586151
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.125389597
Short name T651
Test name
Test status
Simulation time 131467225 ps
CPU time 2.5 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 208696 kb
Host smart-35070440-bcfa-490e-9714-f1debfd45bbe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125389597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.125389597
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3626736010
Short name T532
Test name
Test status
Simulation time 238685884 ps
CPU time 3.85 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 206928 kb
Host smart-f06e19b3-334e-4803-8e88-cfdddb3d1f4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626736010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3626736010
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.341973316
Short name T142
Test name
Test status
Simulation time 474182605 ps
CPU time 3.96 seconds
Started Jun 21 05:43:11 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 214224 kb
Host smart-5fca1282-ae67-4352-80d7-03eacf449fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341973316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.341973316
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2454572620
Short name T5
Test name
Test status
Simulation time 39017094 ps
CPU time 2.49 seconds
Started Jun 21 05:43:02 PM PDT 24
Finished Jun 21 05:43:06 PM PDT 24
Peak memory 208320 kb
Host smart-ee6592b9-3275-44f4-b1cc-2a9fb7bcb784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454572620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2454572620
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.4166880424
Short name T132
Test name
Test status
Simulation time 443797725 ps
CPU time 8.73 seconds
Started Jun 21 05:43:08 PM PDT 24
Finished Jun 21 05:43:18 PM PDT 24
Peak memory 222664 kb
Host smart-10d7d557-0f0b-4592-8afd-507afdc0f313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166880424 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.4166880424
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.199924931
Short name T26
Test name
Test status
Simulation time 10247708665 ps
CPU time 68.55 seconds
Started Jun 21 05:43:01 PM PDT 24
Finished Jun 21 05:44:12 PM PDT 24
Peak memory 209304 kb
Host smart-f8226740-3722-4485-95d3-4e2d9cc13710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199924931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.199924931
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1195924169
Short name T901
Test name
Test status
Simulation time 63529433 ps
CPU time 1.89 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:11 PM PDT 24
Peak memory 210720 kb
Host smart-e667366e-e83c-4e30-ab37-c955b7a88f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195924169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1195924169
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1444222376
Short name T629
Test name
Test status
Simulation time 96118611 ps
CPU time 0.9 seconds
Started Jun 21 05:43:17 PM PDT 24
Finished Jun 21 05:43:19 PM PDT 24
Peak memory 205916 kb
Host smart-1a9bb3e9-9efb-4fdc-b493-f4271e7e1bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444222376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1444222376
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.115707840
Short name T392
Test name
Test status
Simulation time 2842582193 ps
CPU time 33.95 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 214784 kb
Host smart-88f71de5-d643-4bd2-bd90-b57687b1c4fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115707840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.115707840
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2450475965
Short name T10
Test name
Test status
Simulation time 885414198 ps
CPU time 11.13 seconds
Started Jun 21 05:43:11 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 222896 kb
Host smart-2971cd94-2cf7-4b15-8f1c-71ef01187275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450475965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2450475965
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1956448729
Short name T40
Test name
Test status
Simulation time 106672520 ps
CPU time 4.58 seconds
Started Jun 21 05:43:12 PM PDT 24
Finished Jun 21 05:43:17 PM PDT 24
Peak memory 207988 kb
Host smart-aeeecab2-e38f-4730-a905-caa8e0c79f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956448729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1956448729
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2710445265
Short name T316
Test name
Test status
Simulation time 135948595 ps
CPU time 2.28 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:13 PM PDT 24
Peak memory 214244 kb
Host smart-e8d886fd-2649-4203-bef1-93c603a2cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710445265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2710445265
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.738925348
Short name T686
Test name
Test status
Simulation time 85813662 ps
CPU time 3.75 seconds
Started Jun 21 05:43:08 PM PDT 24
Finished Jun 21 05:43:13 PM PDT 24
Peak memory 209628 kb
Host smart-eac4d531-0807-4a04-81a7-d5642f94cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738925348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.738925348
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.366263080
Short name T231
Test name
Test status
Simulation time 9098015861 ps
CPU time 92.78 seconds
Started Jun 21 05:43:10 PM PDT 24
Finished Jun 21 05:44:43 PM PDT 24
Peak memory 208880 kb
Host smart-2bb0129d-626b-4998-8edb-0a4dcb207ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366263080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.366263080
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1906505597
Short name T625
Test name
Test status
Simulation time 834552998 ps
CPU time 4.64 seconds
Started Jun 21 05:43:11 PM PDT 24
Finished Jun 21 05:43:17 PM PDT 24
Peak memory 206984 kb
Host smart-33ded1a2-e0a7-43ca-9a9c-421bf1013069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906505597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1906505597
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.210444644
Short name T866
Test name
Test status
Simulation time 53404533 ps
CPU time 1.85 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:12 PM PDT 24
Peak memory 206728 kb
Host smart-49d7a6fc-78b6-4029-adbd-25896ae6a284
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210444644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.210444644
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3201114623
Short name T847
Test name
Test status
Simulation time 94219652 ps
CPU time 2.85 seconds
Started Jun 21 05:43:12 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 208648 kb
Host smart-44a541fa-fe94-42c6-b259-e02ae6ad8e59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201114623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3201114623
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2010839298
Short name T882
Test name
Test status
Simulation time 734652748 ps
CPU time 8.65 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:19 PM PDT 24
Peak memory 208444 kb
Host smart-c4fce5fe-7fc4-41d5-b4cb-5cfb1cb751bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010839298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2010839298
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.474911806
Short name T537
Test name
Test status
Simulation time 215869282 ps
CPU time 5.64 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 209744 kb
Host smart-a0aabfbc-2458-47bf-8a4a-805c914bc327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474911806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.474911806
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2083471881
Short name T551
Test name
Test status
Simulation time 100774767 ps
CPU time 3.52 seconds
Started Jun 21 05:43:09 PM PDT 24
Finished Jun 21 05:43:14 PM PDT 24
Peak memory 208660 kb
Host smart-d02300e0-da1c-4f28-9310-3bd2b31125a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083471881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2083471881
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3102989015
Short name T916
Test name
Test status
Simulation time 597061645 ps
CPU time 23.61 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 222540 kb
Host smart-c2259a7f-b79f-41b1-b1be-6a6565606da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102989015 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3102989015
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1174545136
Short name T298
Test name
Test status
Simulation time 138624716 ps
CPU time 5.9 seconds
Started Jun 21 05:43:12 PM PDT 24
Finished Jun 21 05:43:19 PM PDT 24
Peak memory 218340 kb
Host smart-7ee1ad76-7a74-4273-8920-8ea514df4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174545136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1174545136
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1809326031
Short name T849
Test name
Test status
Simulation time 61483651 ps
CPU time 2.36 seconds
Started Jun 21 05:43:13 PM PDT 24
Finished Jun 21 05:43:16 PM PDT 24
Peak memory 210216 kb
Host smart-8db659e4-8aff-4496-968a-98620a22bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809326031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1809326031
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.755782160
Short name T828
Test name
Test status
Simulation time 42645029 ps
CPU time 0.69 seconds
Started Jun 21 05:43:16 PM PDT 24
Finished Jun 21 05:43:17 PM PDT 24
Peak memory 205920 kb
Host smart-210503c2-51ce-4018-ad75-9af39507559a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755782160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.755782160
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.867565175
Short name T357
Test name
Test status
Simulation time 396075644 ps
CPU time 19.98 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:40 PM PDT 24
Peak memory 214408 kb
Host smart-1ce8d2f7-40a3-4b28-81da-53a86481e332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867565175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.867565175
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.920252162
Short name T267
Test name
Test status
Simulation time 338878939 ps
CPU time 2.79 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:22 PM PDT 24
Peak memory 207428 kb
Host smart-623ea639-703e-44ec-9502-a22b2392423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920252162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.920252162
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3207592598
Short name T239
Test name
Test status
Simulation time 194464427 ps
CPU time 3.68 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:22 PM PDT 24
Peak memory 221968 kb
Host smart-73729e38-15cc-4d44-b836-5ba99e490d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207592598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3207592598
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.975135238
Short name T715
Test name
Test status
Simulation time 74760366 ps
CPU time 1.9 seconds
Started Jun 21 05:43:20 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 214228 kb
Host smart-842b478f-38e9-4743-8924-10ab6038ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975135238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.975135238
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1336095108
Short name T245
Test name
Test status
Simulation time 90738692 ps
CPU time 3.64 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 209048 kb
Host smart-3a0a1524-ccc9-4bb8-bf72-69d1732d71ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336095108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1336095108
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.829637500
Short name T480
Test name
Test status
Simulation time 126408141 ps
CPU time 2.25 seconds
Started Jun 21 05:43:17 PM PDT 24
Finished Jun 21 05:43:20 PM PDT 24
Peak memory 207308 kb
Host smart-31cfab3a-bb98-4e23-9cf4-5dcf9c1c7035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829637500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.829637500
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.874903079
Short name T343
Test name
Test status
Simulation time 345466058 ps
CPU time 6.37 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:26 PM PDT 24
Peak memory 207104 kb
Host smart-1e80ec74-b0c8-4f2d-942b-47a21b170554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874903079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.874903079
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.377245290
Short name T139
Test name
Test status
Simulation time 102516929 ps
CPU time 1.99 seconds
Started Jun 21 05:43:20 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 207480 kb
Host smart-7f2d278c-0b35-4beb-9549-e6511793e1b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377245290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.377245290
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3798784400
Short name T840
Test name
Test status
Simulation time 36724136129 ps
CPU time 71.37 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:44:30 PM PDT 24
Peak memory 208912 kb
Host smart-2513e863-25c5-4adf-a0ca-171da22cdb23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798784400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3798784400
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1399733588
Short name T781
Test name
Test status
Simulation time 871604589 ps
CPU time 6.53 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:26 PM PDT 24
Peak memory 208412 kb
Host smart-d4874eb4-e750-4d01-8dd0-89a2b41fd8ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399733588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1399733588
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4185038334
Short name T310
Test name
Test status
Simulation time 218155786 ps
CPU time 3.41 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 216028 kb
Host smart-2b026da6-42be-4a05-a251-478250f76f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185038334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4185038334
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.723505051
Short name T571
Test name
Test status
Simulation time 61084295 ps
CPU time 2.29 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:22 PM PDT 24
Peak memory 206916 kb
Host smart-e42ad2f0-cf20-4868-a418-b94317138170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723505051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.723505051
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.694908242
Short name T823
Test name
Test status
Simulation time 209005630 ps
CPU time 3.62 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:24 PM PDT 24
Peak memory 207604 kb
Host smart-31448ed5-0df5-475b-9957-629c8dbae88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694908242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.694908242
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.4154347821
Short name T171
Test name
Test status
Simulation time 234195310 ps
CPU time 1.96 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:22 PM PDT 24
Peak memory 210276 kb
Host smart-f7c7d529-c7c4-4a5e-be14-fa9dfddf602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154347821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4154347821
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3679836687
Short name T623
Test name
Test status
Simulation time 15090886 ps
CPU time 0.82 seconds
Started Jun 21 05:43:30 PM PDT 24
Finished Jun 21 05:43:33 PM PDT 24
Peak memory 205916 kb
Host smart-94ca4f07-35eb-46e4-8be0-8b7015878ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679836687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3679836687
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3983898935
Short name T913
Test name
Test status
Simulation time 150985226 ps
CPU time 3.03 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:22 PM PDT 24
Peak memory 215300 kb
Host smart-f7161291-0c85-4580-aa48-1a553397c45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983898935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3983898935
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.645300056
Short name T22
Test name
Test status
Simulation time 107857401 ps
CPU time 1.77 seconds
Started Jun 21 05:43:17 PM PDT 24
Finished Jun 21 05:43:20 PM PDT 24
Peak memory 216228 kb
Host smart-631f0ede-09ab-4ac7-af7e-0b808049191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645300056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.645300056
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1295127595
Short name T915
Test name
Test status
Simulation time 120434639 ps
CPU time 2.36 seconds
Started Jun 21 05:43:17 PM PDT 24
Finished Jun 21 05:43:20 PM PDT 24
Peak memory 207540 kb
Host smart-0126b3f2-fb69-4975-bd07-e9d015bf1c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295127595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1295127595
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2532527641
Short name T822
Test name
Test status
Simulation time 225287449 ps
CPU time 3.45 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 219956 kb
Host smart-debc8d11-78ce-4d41-a352-b0afebee55b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532527641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2532527641
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2834580436
Short name T320
Test name
Test status
Simulation time 79804395 ps
CPU time 4.4 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:24 PM PDT 24
Peak memory 221944 kb
Host smart-5010c998-139f-42ae-808a-0f3d6d557162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834580436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2834580436
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3391562041
Short name T693
Test name
Test status
Simulation time 36356915 ps
CPU time 2.58 seconds
Started Jun 21 05:43:16 PM PDT 24
Finished Jun 21 05:43:19 PM PDT 24
Peak memory 220304 kb
Host smart-497d73c3-f2c9-478c-82d6-634d3f6f9cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391562041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3391562041
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1981448565
Short name T334
Test name
Test status
Simulation time 296748374 ps
CPU time 8.05 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:28 PM PDT 24
Peak memory 210400 kb
Host smart-01575ab5-ae3a-4f49-9106-c95695a12398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981448565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1981448565
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1499181879
Short name T226
Test name
Test status
Simulation time 82720734 ps
CPU time 2.98 seconds
Started Jun 21 05:43:21 PM PDT 24
Finished Jun 21 05:43:25 PM PDT 24
Peak memory 208304 kb
Host smart-354244b3-eb87-4837-b5b1-0fcb806344c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499181879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1499181879
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.614268559
Short name T599
Test name
Test status
Simulation time 784250353 ps
CPU time 9.73 seconds
Started Jun 21 05:43:17 PM PDT 24
Finished Jun 21 05:43:28 PM PDT 24
Peak memory 208764 kb
Host smart-f31c7abe-7556-4250-bae6-ae14fcbe4c97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614268559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.614268559
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.475614634
Short name T632
Test name
Test status
Simulation time 361336880 ps
CPU time 2.44 seconds
Started Jun 21 05:43:19 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 207004 kb
Host smart-7d976444-23a0-457d-86af-e6206170263a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475614634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.475614634
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.111189678
Short name T430
Test name
Test status
Simulation time 44514878 ps
CPU time 2.99 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:23 PM PDT 24
Peak memory 208968 kb
Host smart-a62107ca-c112-445c-9248-731326da4b3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111189678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.111189678
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2072347105
Short name T17
Test name
Test status
Simulation time 136733010 ps
CPU time 2.31 seconds
Started Jun 21 05:43:27 PM PDT 24
Finished Jun 21 05:43:30 PM PDT 24
Peak memory 214568 kb
Host smart-a0877695-aef6-4c16-af56-db2513994d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072347105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2072347105
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3376177214
Short name T566
Test name
Test status
Simulation time 331122025 ps
CPU time 3.96 seconds
Started Jun 21 05:43:17 PM PDT 24
Finished Jun 21 05:43:22 PM PDT 24
Peak memory 206924 kb
Host smart-3629e302-6fe5-4102-add1-5cd9e94eebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376177214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3376177214
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1370436232
Short name T568
Test name
Test status
Simulation time 377162577 ps
CPU time 12.26 seconds
Started Jun 21 05:43:29 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 219876 kb
Host smart-a2af867e-68d9-430f-9449-11989192ac8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370436232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1370436232
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3441172309
Short name T186
Test name
Test status
Simulation time 1074455679 ps
CPU time 19.74 seconds
Started Jun 21 05:43:33 PM PDT 24
Finished Jun 21 05:43:53 PM PDT 24
Peak memory 222568 kb
Host smart-49116e02-f117-4d2a-b877-18dc0243283d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441172309 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3441172309
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3107829902
Short name T435
Test name
Test status
Simulation time 109870966 ps
CPU time 4.67 seconds
Started Jun 21 05:43:18 PM PDT 24
Finished Jun 21 05:43:24 PM PDT 24
Peak memory 207620 kb
Host smart-74162b34-f0ea-40c8-9cd4-ae16057fc817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107829902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3107829902
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3861077307
Short name T138
Test name
Test status
Simulation time 123679757 ps
CPU time 2.55 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 210284 kb
Host smart-df6a232a-9732-4a23-ad09-eed1aab9393e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861077307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3861077307
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.645584837
Short name T717
Test name
Test status
Simulation time 51431300 ps
CPU time 0.69 seconds
Started Jun 21 05:43:31 PM PDT 24
Finished Jun 21 05:43:33 PM PDT 24
Peak memory 205840 kb
Host smart-26539cb0-975e-4892-80f1-7b61d0b423f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645584837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.645584837
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3947608046
Short name T529
Test name
Test status
Simulation time 152586172 ps
CPU time 5.47 seconds
Started Jun 21 05:43:30 PM PDT 24
Finished Jun 21 05:43:37 PM PDT 24
Peak memory 222700 kb
Host smart-a89376c4-ead8-4086-9b32-e96abda46d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947608046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3947608046
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1243563070
Short name T705
Test name
Test status
Simulation time 179238589 ps
CPU time 2.16 seconds
Started Jun 21 05:43:27 PM PDT 24
Finished Jun 21 05:43:30 PM PDT 24
Peak memory 210184 kb
Host smart-349f8b12-a5f4-4274-aabc-b1328e1ab7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243563070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1243563070
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4084743951
Short name T867
Test name
Test status
Simulation time 222982053 ps
CPU time 4.68 seconds
Started Jun 21 05:43:27 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 209688 kb
Host smart-8cffcc20-e348-4397-8aea-1c16c4f8e65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084743951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4084743951
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1303631131
Short name T845
Test name
Test status
Simulation time 1093985193 ps
CPU time 4.7 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:33 PM PDT 24
Peak memory 222380 kb
Host smart-0a745185-2db8-4eeb-bd58-149f477420d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303631131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1303631131
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4258709006
Short name T247
Test name
Test status
Simulation time 175030415 ps
CPU time 2.96 seconds
Started Jun 21 05:43:27 PM PDT 24
Finished Jun 21 05:43:31 PM PDT 24
Peak memory 222344 kb
Host smart-ccb88c7f-3e84-48bc-b008-b22c7e02f487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258709006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4258709006
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1695034377
Short name T586
Test name
Test status
Simulation time 188485722 ps
CPU time 3.93 seconds
Started Jun 21 05:43:31 PM PDT 24
Finished Jun 21 05:43:36 PM PDT 24
Peak memory 208592 kb
Host smart-94bcb302-17aa-495a-b6db-5232daaed24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695034377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1695034377
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1680661079
Short name T104
Test name
Test status
Simulation time 901868297 ps
CPU time 7.03 seconds
Started Jun 21 05:43:29 PM PDT 24
Finished Jun 21 05:43:37 PM PDT 24
Peak memory 208784 kb
Host smart-ea513c52-5437-4f58-b823-c0ca9de09171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680661079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1680661079
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1700775769
Short name T363
Test name
Test status
Simulation time 56097512 ps
CPU time 3.11 seconds
Started Jun 21 05:43:30 PM PDT 24
Finished Jun 21 05:43:34 PM PDT 24
Peak memory 208772 kb
Host smart-a3886887-d23a-49e9-b041-05197a617bbe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700775769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1700775769
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.687082908
Short name T427
Test name
Test status
Simulation time 179641388 ps
CPU time 2.49 seconds
Started Jun 21 05:43:30 PM PDT 24
Finished Jun 21 05:43:34 PM PDT 24
Peak memory 206900 kb
Host smart-afbaae6d-443c-427e-b9be-e13dbca5757c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687082908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.687082908
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3194358274
Short name T749
Test name
Test status
Simulation time 213180156 ps
CPU time 2.82 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 208632 kb
Host smart-87a90428-3d9f-4005-a7fb-fa7bd50d95d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194358274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3194358274
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4055802710
Short name T330
Test name
Test status
Simulation time 59560671 ps
CPU time 2.47 seconds
Started Jun 21 05:43:29 PM PDT 24
Finished Jun 21 05:43:33 PM PDT 24
Peak memory 218156 kb
Host smart-1ac7c497-9ec5-4345-87cb-846a5f0b225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055802710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4055802710
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.173630116
Short name T665
Test name
Test status
Simulation time 111125311 ps
CPU time 2.21 seconds
Started Jun 21 05:43:29 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 206708 kb
Host smart-0d5ea848-6805-454d-8785-61c64d67d77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173630116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.173630116
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.650494190
Short name T129
Test name
Test status
Simulation time 281288932 ps
CPU time 7.11 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:36 PM PDT 24
Peak memory 222616 kb
Host smart-751b1d41-a8ab-4cd1-bbcc-a2290f9cb12e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650494190 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.650494190
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1921863467
Short name T500
Test name
Test status
Simulation time 332999451 ps
CPU time 5.8 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:35 PM PDT 24
Peak memory 208244 kb
Host smart-ea9ed6a6-e1f3-42d7-945a-1f74b629b4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921863467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1921863467
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1773940426
Short name T180
Test name
Test status
Simulation time 191489320 ps
CPU time 1.59 seconds
Started Jun 21 05:43:27 PM PDT 24
Finished Jun 21 05:43:29 PM PDT 24
Peak memory 209972 kb
Host smart-6f645738-f039-4817-8ee3-c68d3b4e4da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773940426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1773940426
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.868948331
Short name T726
Test name
Test status
Simulation time 10856116 ps
CPU time 0.87 seconds
Started Jun 21 05:43:40 PM PDT 24
Finished Jun 21 05:43:42 PM PDT 24
Peak memory 205928 kb
Host smart-a7c822b0-5433-4f34-ad68-46bd44930c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868948331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.868948331
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2203092645
Short name T220
Test name
Test status
Simulation time 61062609 ps
CPU time 4.25 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:33 PM PDT 24
Peak memory 214696 kb
Host smart-e1338546-c3f2-40e5-a720-901c0aed2baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203092645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2203092645
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.654998745
Short name T428
Test name
Test status
Simulation time 860430500 ps
CPU time 2.45 seconds
Started Jun 21 05:43:38 PM PDT 24
Finished Jun 21 05:43:42 PM PDT 24
Peak memory 217856 kb
Host smart-47ca7208-9b25-4d40-9ef1-8a35cf6b9930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654998745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.654998745
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2692061411
Short name T804
Test name
Test status
Simulation time 202597266 ps
CPU time 5.45 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:35 PM PDT 24
Peak memory 218508 kb
Host smart-9944e443-4f58-4833-a19d-4cb62e2cbeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692061411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2692061411
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1990840226
Short name T778
Test name
Test status
Simulation time 897707239 ps
CPU time 19.97 seconds
Started Jun 21 05:43:37 PM PDT 24
Finished Jun 21 05:43:58 PM PDT 24
Peak memory 209316 kb
Host smart-7a20c890-79f0-486d-a0ba-f67651713221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990840226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1990840226
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4273588902
Short name T511
Test name
Test status
Simulation time 66684802 ps
CPU time 2.57 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 214212 kb
Host smart-05da508a-48b9-42d1-bb0f-4e3e59550557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273588902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4273588902
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1021647698
Short name T423
Test name
Test status
Simulation time 125067760 ps
CPU time 3.26 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 220232 kb
Host smart-861ae30a-90cb-4d1b-836a-5361f92b03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021647698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1021647698
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1541476499
Short name T349
Test name
Test status
Simulation time 97885704 ps
CPU time 4.58 seconds
Started Jun 21 05:43:32 PM PDT 24
Finished Jun 21 05:43:38 PM PDT 24
Peak memory 210616 kb
Host smart-fcd3a140-5b4b-4725-ab0d-6821a1108550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541476499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1541476499
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.141721570
Short name T732
Test name
Test status
Simulation time 59688206 ps
CPU time 2.84 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:32 PM PDT 24
Peak memory 208512 kb
Host smart-b29bbbb5-5496-4475-b3e5-f66bd3eacd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141721570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.141721570
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.339635794
Short name T332
Test name
Test status
Simulation time 203007636 ps
CPU time 5.82 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:36 PM PDT 24
Peak memory 208680 kb
Host smart-d46720fd-c8f1-430e-a714-f4d4e4a6865b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339635794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.339635794
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3888422914
Short name T886
Test name
Test status
Simulation time 49775166 ps
CPU time 2.62 seconds
Started Jun 21 05:43:28 PM PDT 24
Finished Jun 21 05:43:31 PM PDT 24
Peak memory 206916 kb
Host smart-4bcb5da7-eb57-4141-9c7e-ce6c6e5dcda4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888422914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3888422914
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3104003161
Short name T344
Test name
Test status
Simulation time 1186504233 ps
CPU time 8.34 seconds
Started Jun 21 05:43:27 PM PDT 24
Finished Jun 21 05:43:36 PM PDT 24
Peak memory 207148 kb
Host smart-5592c9da-2a34-46f6-846b-60fce6e8fdf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104003161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3104003161
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.144969171
Short name T538
Test name
Test status
Simulation time 416406719 ps
CPU time 3.56 seconds
Started Jun 21 05:43:35 PM PDT 24
Finished Jun 21 05:43:40 PM PDT 24
Peak memory 210400 kb
Host smart-a023a045-29e0-4d62-bfe2-89072947c755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144969171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.144969171
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3100626141
Short name T701
Test name
Test status
Simulation time 107472048 ps
CPU time 2.94 seconds
Started Jun 21 05:43:32 PM PDT 24
Finished Jun 21 05:43:36 PM PDT 24
Peak memory 208516 kb
Host smart-a827479b-5842-46fd-9d7b-649d78ed4086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100626141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3100626141
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1789313820
Short name T619
Test name
Test status
Simulation time 201930918 ps
CPU time 8.66 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:43:46 PM PDT 24
Peak memory 222656 kb
Host smart-fdaf2cce-1f23-4817-946c-6c8f85835580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789313820 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1789313820
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1101061785
Short name T756
Test name
Test status
Simulation time 800643283 ps
CPU time 5.6 seconds
Started Jun 21 05:43:30 PM PDT 24
Finished Jun 21 05:43:37 PM PDT 24
Peak memory 207368 kb
Host smart-e4a9c80c-55fc-40ef-b2e4-f892966a3073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101061785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1101061785
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.603856641
Short name T388
Test name
Test status
Simulation time 188901333 ps
CPU time 2.31 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:43:40 PM PDT 24
Peak memory 210468 kb
Host smart-06ca2990-626f-4933-8809-8cc98c55c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603856641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.603856641
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3574809958
Short name T102
Test name
Test status
Simulation time 13593087 ps
CPU time 0.75 seconds
Started Jun 21 05:43:35 PM PDT 24
Finished Jun 21 05:43:37 PM PDT 24
Peak memory 205916 kb
Host smart-f3c160df-1fbe-4c68-b2b5-987ddb034732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574809958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3574809958
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4061997189
Short name T326
Test name
Test status
Simulation time 271153461 ps
CPU time 4.98 seconds
Started Jun 21 05:43:38 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 215456 kb
Host smart-c89af3f2-dcf3-4d08-8c7b-77a8739ae633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061997189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4061997189
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2452983406
Short name T252
Test name
Test status
Simulation time 988553118 ps
CPU time 4.11 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 221692 kb
Host smart-1ca060aa-c28d-4896-8944-026044047320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452983406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2452983406
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.105511458
Short name T764
Test name
Test status
Simulation time 19962110 ps
CPU time 1.64 seconds
Started Jun 21 05:43:34 PM PDT 24
Finished Jun 21 05:43:37 PM PDT 24
Peak memory 214380 kb
Host smart-20461559-f7b9-44c1-9d62-bbc3bb5e1d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105511458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.105511458
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2352058025
Short name T865
Test name
Test status
Simulation time 73067458 ps
CPU time 2.96 seconds
Started Jun 21 05:43:41 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 214296 kb
Host smart-bf5a8eff-c352-4448-849b-717088272864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352058025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2352058025
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2051798460
Short name T812
Test name
Test status
Simulation time 1139322330 ps
CPU time 2.91 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:42 PM PDT 24
Peak memory 214156 kb
Host smart-e60f8440-632f-4f4e-94f8-fc3043e34542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051798460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2051798460
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4208818738
Short name T561
Test name
Test status
Simulation time 101836646 ps
CPU time 1.76 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:43:39 PM PDT 24
Peak memory 214420 kb
Host smart-9e7cc841-f54f-4ead-bcac-0b725a296069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208818738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4208818738
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1802802966
Short name T580
Test name
Test status
Simulation time 225818987 ps
CPU time 6.78 seconds
Started Jun 21 05:43:34 PM PDT 24
Finished Jun 21 05:43:42 PM PDT 24
Peak memory 219188 kb
Host smart-ac492717-fb60-4630-8d2d-5a635497dc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802802966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1802802966
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3470283621
Short name T293
Test name
Test status
Simulation time 78202971 ps
CPU time 3.43 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 207484 kb
Host smart-726552c7-33da-48aa-962c-a847534874ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470283621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3470283621
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3517672238
Short name T805
Test name
Test status
Simulation time 64420998 ps
CPU time 3.42 seconds
Started Jun 21 05:43:35 PM PDT 24
Finished Jun 21 05:43:40 PM PDT 24
Peak memory 208592 kb
Host smart-81cf312f-3fe2-4021-a816-1e8c53dd7044
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517672238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3517672238
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3916893498
Short name T692
Test name
Test status
Simulation time 435481354 ps
CPU time 5.04 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:44 PM PDT 24
Peak memory 207040 kb
Host smart-a6f84a38-adff-41d3-8720-0669e94ba52c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916893498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3916893498
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3385160217
Short name T649
Test name
Test status
Simulation time 104567100 ps
CPU time 2.21 seconds
Started Jun 21 05:43:40 PM PDT 24
Finished Jun 21 05:43:42 PM PDT 24
Peak memory 206852 kb
Host smart-7917baa9-8f2d-4349-ac28-286b49184b52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385160217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3385160217
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1733321952
Short name T432
Test name
Test status
Simulation time 78072394 ps
CPU time 2.53 seconds
Started Jun 21 05:43:37 PM PDT 24
Finished Jun 21 05:43:41 PM PDT 24
Peak memory 208620 kb
Host smart-ad2383f2-d433-4a92-ac4a-224973ece65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733321952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1733321952
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1581623452
Short name T887
Test name
Test status
Simulation time 311863394 ps
CPU time 8.78 seconds
Started Jun 21 05:43:34 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 208732 kb
Host smart-78687992-f635-4111-bc47-46fd8719f021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581623452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1581623452
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.146976075
Short name T325
Test name
Test status
Simulation time 9856263393 ps
CPU time 41.2 seconds
Started Jun 21 05:43:40 PM PDT 24
Finished Jun 21 05:44:22 PM PDT 24
Peak memory 215240 kb
Host smart-2220f9bf-1297-4825-80bc-afffd9335e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146976075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.146976075
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3009025265
Short name T235
Test name
Test status
Simulation time 178727031 ps
CPU time 3.31 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 207944 kb
Host smart-c1a882ca-bdb9-4e60-b20c-e533f45430cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009025265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3009025265
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3550057891
Short name T107
Test name
Test status
Simulation time 52934336 ps
CPU time 2.28 seconds
Started Jun 21 05:43:35 PM PDT 24
Finished Jun 21 05:43:39 PM PDT 24
Peak memory 210036 kb
Host smart-ff9a2497-3d11-4062-bae4-c1b05a08e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550057891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3550057891
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3735010439
Short name T436
Test name
Test status
Simulation time 12190421 ps
CPU time 0.77 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:53 PM PDT 24
Peak memory 205904 kb
Host smart-f776b238-2be0-46d1-9ce1-1c6ff8ee6387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735010439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3735010439
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3596056171
Short name T595
Test name
Test status
Simulation time 468261537 ps
CPU time 3.33 seconds
Started Jun 21 05:39:45 PM PDT 24
Finished Jun 21 05:39:49 PM PDT 24
Peak memory 209800 kb
Host smart-c2d7c8e1-70ac-43e5-bd47-2d175cb172bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596056171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3596056171
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2866390079
Short name T69
Test name
Test status
Simulation time 71453014 ps
CPU time 2.09 seconds
Started Jun 21 05:39:35 PM PDT 24
Finished Jun 21 05:39:38 PM PDT 24
Peak memory 214216 kb
Host smart-60977937-8d81-445b-aecd-2ff8cebf3afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866390079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2866390079
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2450495196
Short name T587
Test name
Test status
Simulation time 32163467 ps
CPU time 2.69 seconds
Started Jun 21 05:39:40 PM PDT 24
Finished Jun 21 05:39:44 PM PDT 24
Peak memory 215968 kb
Host smart-40073abb-ef53-49a0-afd9-2c7d867b4f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450495196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2450495196
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2020434145
Short name T285
Test name
Test status
Simulation time 150311084 ps
CPU time 5.3 seconds
Started Jun 21 05:39:42 PM PDT 24
Finished Jun 21 05:39:48 PM PDT 24
Peak memory 214396 kb
Host smart-1fbf82d9-475f-49f9-948b-1f33dc15f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020434145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2020434145
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4181258619
Short name T838
Test name
Test status
Simulation time 307119178 ps
CPU time 9.39 seconds
Started Jun 21 05:39:39 PM PDT 24
Finished Jun 21 05:39:49 PM PDT 24
Peak memory 222324 kb
Host smart-64786708-aeae-4bca-b4da-0d8515e4e555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181258619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4181258619
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2147625039
Short name T572
Test name
Test status
Simulation time 147592582 ps
CPU time 4.23 seconds
Started Jun 21 05:39:34 PM PDT 24
Finished Jun 21 05:39:39 PM PDT 24
Peak memory 208932 kb
Host smart-cce8e458-0c12-4951-a082-145d8d9fac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147625039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2147625039
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3407329096
Short name T842
Test name
Test status
Simulation time 1397518822 ps
CPU time 29.68 seconds
Started Jun 21 05:39:38 PM PDT 24
Finished Jun 21 05:40:09 PM PDT 24
Peak memory 208424 kb
Host smart-032c9081-f370-4e5b-b2e2-aa5b8beb23a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407329096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3407329096
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.180690192
Short name T265
Test name
Test status
Simulation time 187937927 ps
CPU time 6.35 seconds
Started Jun 21 05:39:35 PM PDT 24
Finished Jun 21 05:39:42 PM PDT 24
Peak memory 208060 kb
Host smart-1b9d89b5-814b-408e-9e42-0b7001d5da96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180690192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.180690192
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2446317347
Short name T354
Test name
Test status
Simulation time 461826782 ps
CPU time 2.57 seconds
Started Jun 21 05:39:35 PM PDT 24
Finished Jun 21 05:39:39 PM PDT 24
Peak memory 208676 kb
Host smart-d9e79f81-8b2e-4a8f-b96d-9a56b68f7e55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446317347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2446317347
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.592736477
Short name T652
Test name
Test status
Simulation time 81285680 ps
CPU time 2.43 seconds
Started Jun 21 05:39:39 PM PDT 24
Finished Jun 21 05:39:42 PM PDT 24
Peak memory 208696 kb
Host smart-e9346eb6-a253-45a9-bc19-e0842c3851cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592736477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.592736477
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.378534624
Short name T512
Test name
Test status
Simulation time 164617764 ps
CPU time 2.96 seconds
Started Jun 21 05:39:42 PM PDT 24
Finished Jun 21 05:39:46 PM PDT 24
Peak memory 215756 kb
Host smart-17f233e6-7b71-4f04-9564-61aa5e6a9305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378534624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.378534624
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1517003331
Short name T463
Test name
Test status
Simulation time 134208802 ps
CPU time 2.92 seconds
Started Jun 21 05:39:34 PM PDT 24
Finished Jun 21 05:39:37 PM PDT 24
Peak memory 206692 kb
Host smart-bb81fc33-8718-46a9-8ee0-9cf97598616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517003331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1517003331
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2154739608
Short name T575
Test name
Test status
Simulation time 10527052641 ps
CPU time 273.21 seconds
Started Jun 21 05:39:45 PM PDT 24
Finished Jun 21 05:44:19 PM PDT 24
Peak memory 217652 kb
Host smart-6ebf5dac-3d2c-49d9-bcbe-d68f1100d19d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154739608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2154739608
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.963154134
Short name T404
Test name
Test status
Simulation time 1068018584 ps
CPU time 5.75 seconds
Started Jun 21 05:39:35 PM PDT 24
Finished Jun 21 05:39:41 PM PDT 24
Peak memory 207388 kb
Host smart-a5266906-7c74-4e51-97b5-9db37162278a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963154134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.963154134
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.593741892
Short name T177
Test name
Test status
Simulation time 40623277 ps
CPU time 2.68 seconds
Started Jun 21 05:39:42 PM PDT 24
Finished Jun 21 05:39:45 PM PDT 24
Peak memory 210380 kb
Host smart-51d7e38f-85fe-43ad-939f-0aa9b13863ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593741892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.593741892
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3860385270
Short name T496
Test name
Test status
Simulation time 9744282 ps
CPU time 0.71 seconds
Started Jun 21 05:43:54 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 205856 kb
Host smart-071b9319-90a4-47bc-ab3c-b7dc25974044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860385270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3860385270
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2578858395
Short name T417
Test name
Test status
Simulation time 209234112 ps
CPU time 4.05 seconds
Started Jun 21 05:43:48 PM PDT 24
Finished Jun 21 05:43:52 PM PDT 24
Peak memory 215152 kb
Host smart-724c074b-ef97-41d1-b241-cc871e414b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578858395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2578858395
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3414946208
Short name T27
Test name
Test status
Simulation time 150848430 ps
CPU time 2.66 seconds
Started Jun 21 05:43:45 PM PDT 24
Finished Jun 21 05:43:48 PM PDT 24
Peak memory 209304 kb
Host smart-b8bc58dd-e209-40a6-bf01-680f23390722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414946208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3414946208
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1593308749
Short name T628
Test name
Test status
Simulation time 171788124 ps
CPU time 3.55 seconds
Started Jun 21 05:43:38 PM PDT 24
Finished Jun 21 05:43:43 PM PDT 24
Peak memory 207592 kb
Host smart-d74bc7d2-9762-478b-909e-cb7adc1b75b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593308749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1593308749
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2183660477
Short name T559
Test name
Test status
Simulation time 62631541 ps
CPU time 2.29 seconds
Started Jun 21 05:43:50 PM PDT 24
Finished Jun 21 05:43:53 PM PDT 24
Peak memory 214232 kb
Host smart-d4bcc1bf-b23a-409b-a37f-644d6875c212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183660477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2183660477
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2567960207
Short name T673
Test name
Test status
Simulation time 156246475 ps
CPU time 4.58 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:43:42 PM PDT 24
Peak memory 222008 kb
Host smart-e390e42d-4452-4dd7-8266-77ae3864330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567960207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2567960207
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2294902474
Short name T455
Test name
Test status
Simulation time 380023899 ps
CPU time 16.57 seconds
Started Jun 21 05:43:39 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 220660 kb
Host smart-8aea3f65-cc0f-418a-813c-11962041ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294902474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2294902474
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3502360587
Short name T622
Test name
Test status
Simulation time 125743776 ps
CPU time 5.34 seconds
Started Jun 21 05:43:50 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 214236 kb
Host smart-b04b1e4d-5a5a-4019-a5e8-dde0c03bdfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502360587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3502360587
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1412343540
Short name T703
Test name
Test status
Simulation time 2548801124 ps
CPU time 16.4 seconds
Started Jun 21 05:43:41 PM PDT 24
Finished Jun 21 05:43:58 PM PDT 24
Peak memory 208656 kb
Host smart-b5c56d59-207d-4414-a768-935239bdf6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412343540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1412343540
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1938100348
Short name T888
Test name
Test status
Simulation time 97914782 ps
CPU time 3.93 seconds
Started Jun 21 05:43:35 PM PDT 24
Finished Jun 21 05:43:41 PM PDT 24
Peak memory 209020 kb
Host smart-c27a1c50-146f-4685-aaaf-a45ad24d33b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938100348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1938100348
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1204437025
Short name T626
Test name
Test status
Simulation time 447564038 ps
CPU time 7.13 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:43:45 PM PDT 24
Peak memory 206972 kb
Host smart-f7977a13-3a97-4a69-894e-6e9c24913f47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204437025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1204437025
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2548811954
Short name T134
Test name
Test status
Simulation time 26503980 ps
CPU time 1.79 seconds
Started Jun 21 05:43:52 PM PDT 24
Finished Jun 21 05:43:55 PM PDT 24
Peak memory 208104 kb
Host smart-85bc7a21-923a-44c4-b80a-8680b622942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548811954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2548811954
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3788142296
Short name T431
Test name
Test status
Simulation time 118410272 ps
CPU time 3.12 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:43:41 PM PDT 24
Peak memory 208620 kb
Host smart-7c00ee29-172a-46d8-8881-6f9f9ae6c847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788142296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3788142296
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.228328123
Short name T868
Test name
Test status
Simulation time 197610477 ps
CPU time 12.3 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 222512 kb
Host smart-b0822966-b64d-453b-a5ee-9a0c3e1dfa90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228328123 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.228328123
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2127233511
Short name T410
Test name
Test status
Simulation time 11410492416 ps
CPU time 76.24 seconds
Started Jun 21 05:43:36 PM PDT 24
Finished Jun 21 05:44:53 PM PDT 24
Peak memory 209800 kb
Host smart-8954fbf1-0b74-41bc-92d6-b285df601272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127233511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2127233511
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3939295944
Short name T204
Test name
Test status
Simulation time 63380574 ps
CPU time 1.8 seconds
Started Jun 21 05:43:47 PM PDT 24
Finished Jun 21 05:43:49 PM PDT 24
Peak memory 209912 kb
Host smart-de8b1e87-b88c-49cb-ae9e-13bc7b7013d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939295944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3939295944
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2401805791
Short name T471
Test name
Test status
Simulation time 9948080 ps
CPU time 0.75 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:53 PM PDT 24
Peak memory 205916 kb
Host smart-1246542d-74c8-4ab0-941d-065ade28fca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401805791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2401805791
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.665402440
Short name T409
Test name
Test status
Simulation time 320509761 ps
CPU time 7.78 seconds
Started Jun 21 05:43:54 PM PDT 24
Finished Jun 21 05:44:03 PM PDT 24
Peak memory 214312 kb
Host smart-687d7abf-d4f4-41da-9e83-9cdfc085cdd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665402440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.665402440
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3079575306
Short name T35
Test name
Test status
Simulation time 176396434 ps
CPU time 2.95 seconds
Started Jun 21 05:43:44 PM PDT 24
Finished Jun 21 05:43:48 PM PDT 24
Peak memory 208496 kb
Host smart-792e8c72-e2be-40b9-8b35-69bed156e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079575306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3079575306
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1349097959
Short name T71
Test name
Test status
Simulation time 127803310 ps
CPU time 2.65 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:47 PM PDT 24
Peak memory 214324 kb
Host smart-3b745632-240b-4f56-8d63-1e7591381e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349097959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1349097959
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.266820541
Short name T87
Test name
Test status
Simulation time 13978263160 ps
CPU time 25.2 seconds
Started Jun 21 05:43:54 PM PDT 24
Finished Jun 21 05:44:20 PM PDT 24
Peak memory 214444 kb
Host smart-e88c363a-6802-4fe6-b1fb-2cb673edcdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266820541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.266820541
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1958986895
Short name T286
Test name
Test status
Simulation time 56663660 ps
CPU time 2.09 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:47 PM PDT 24
Peak memory 214240 kb
Host smart-28139ea2-d123-46b6-b88c-aa0faa3e8a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958986895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1958986895
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1828330565
Short name T637
Test name
Test status
Simulation time 298491565 ps
CPU time 3.67 seconds
Started Jun 21 05:43:54 PM PDT 24
Finished Jun 21 05:43:59 PM PDT 24
Peak memory 209672 kb
Host smart-b80f4156-9c8d-4834-9cee-533609522c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828330565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1828330565
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3931864057
Short name T295
Test name
Test status
Simulation time 100769907 ps
CPU time 2.52 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:46 PM PDT 24
Peak memory 207196 kb
Host smart-f542ae07-f9c4-4fc2-9df9-37a2cd8ac150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931864057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3931864057
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2488586701
Short name T479
Test name
Test status
Simulation time 197216388 ps
CPU time 2.45 seconds
Started Jun 21 05:43:44 PM PDT 24
Finished Jun 21 05:43:48 PM PDT 24
Peak memory 206956 kb
Host smart-1b30d864-7604-492b-94d9-b4226cd14a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488586701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2488586701
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2763386822
Short name T550
Test name
Test status
Simulation time 37621899 ps
CPU time 2.39 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:45 PM PDT 24
Peak memory 206816 kb
Host smart-dce0e7e9-d178-43f0-8aa2-36ac3bd37517
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763386822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2763386822
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3083947335
Short name T232
Test name
Test status
Simulation time 90033776 ps
CPU time 2.82 seconds
Started Jun 21 05:43:44 PM PDT 24
Finished Jun 21 05:43:48 PM PDT 24
Peak memory 206872 kb
Host smart-4880c62b-49a9-47d4-a440-d205eb0ea81e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083947335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3083947335
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3327589334
Short name T534
Test name
Test status
Simulation time 314259351 ps
CPU time 4.07 seconds
Started Jun 21 05:43:53 PM PDT 24
Finished Jun 21 05:43:58 PM PDT 24
Peak memory 206796 kb
Host smart-5b1aa1a9-38ec-462e-bcc0-508355e86e32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327589334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3327589334
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.809314085
Short name T489
Test name
Test status
Simulation time 20949602 ps
CPU time 1.92 seconds
Started Jun 21 05:43:44 PM PDT 24
Finished Jun 21 05:43:47 PM PDT 24
Peak memory 214296 kb
Host smart-1e705878-72a7-4c38-b231-430965044ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809314085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.809314085
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.464345512
Short name T468
Test name
Test status
Simulation time 2459258721 ps
CPU time 4.23 seconds
Started Jun 21 05:43:52 PM PDT 24
Finished Jun 21 05:43:58 PM PDT 24
Peak memory 208400 kb
Host smart-b819312c-a3c1-40c8-b29f-f19b000d95fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464345512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.464345512
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1290852596
Short name T545
Test name
Test status
Simulation time 4960818574 ps
CPU time 17.07 seconds
Started Jun 21 05:43:44 PM PDT 24
Finished Jun 21 05:44:02 PM PDT 24
Peak memory 222184 kb
Host smart-cdfb23d6-7e8d-4fed-a316-60da8dfe82df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290852596 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1290852596
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.308649610
Short name T687
Test name
Test status
Simulation time 871401182 ps
CPU time 8.68 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:53 PM PDT 24
Peak memory 208600 kb
Host smart-bf8926fe-e425-465a-8d7b-f625fcc7e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308649610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.308649610
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2272642078
Short name T478
Test name
Test status
Simulation time 249799193 ps
CPU time 2.33 seconds
Started Jun 21 05:43:43 PM PDT 24
Finished Jun 21 05:43:46 PM PDT 24
Peak memory 209844 kb
Host smart-2a06813b-7781-4042-beb5-da41df51d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272642078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2272642078
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2420948425
Short name T841
Test name
Test status
Simulation time 12217866 ps
CPU time 0.94 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:01 PM PDT 24
Peak memory 206108 kb
Host smart-41694b75-b27e-4f81-ae39-658af4b25431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420948425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2420948425
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1550808859
Short name T372
Test name
Test status
Simulation time 389542931 ps
CPU time 6.18 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:58 PM PDT 24
Peak memory 215752 kb
Host smart-da043f72-36b7-4db4-a359-74cae095ba68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550808859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1550808859
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3479677731
Short name T769
Test name
Test status
Simulation time 179866698 ps
CPU time 2.15 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:54 PM PDT 24
Peak memory 207892 kb
Host smart-a41b41b1-5ce7-459c-97c7-b0670aceb206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479677731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3479677731
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1655723260
Short name T93
Test name
Test status
Simulation time 122081099 ps
CPU time 3.71 seconds
Started Jun 21 05:43:53 PM PDT 24
Finished Jun 21 05:43:58 PM PDT 24
Peak memory 209288 kb
Host smart-b217f852-24e5-44a7-a383-1b7ae7deb6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655723260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1655723260
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3369859465
Short name T369
Test name
Test status
Simulation time 252713349 ps
CPU time 2.85 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:55 PM PDT 24
Peak memory 220776 kb
Host smart-a2ec4385-de98-4755-9d31-849130fd1c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369859465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3369859465
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3274177151
Short name T860
Test name
Test status
Simulation time 140101314 ps
CPU time 2.87 seconds
Started Jun 21 05:43:52 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 207804 kb
Host smart-7c06d347-e577-4298-87dd-c47e7f688e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274177151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3274177151
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.186571755
Short name T216
Test name
Test status
Simulation time 76831359 ps
CPU time 4.69 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:57 PM PDT 24
Peak memory 210232 kb
Host smart-2bd68a0d-25e3-4aee-a114-1b5fd1315d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186571755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.186571755
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3182887294
Short name T218
Test name
Test status
Simulation time 86576079 ps
CPU time 1.91 seconds
Started Jun 21 05:43:53 PM PDT 24
Finished Jun 21 05:43:56 PM PDT 24
Peak memory 207504 kb
Host smart-32f32e47-8e95-47ed-9547-5a52d8f52d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182887294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3182887294
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1927982702
Short name T296
Test name
Test status
Simulation time 628955066 ps
CPU time 4.98 seconds
Started Jun 21 05:43:52 PM PDT 24
Finished Jun 21 05:43:57 PM PDT 24
Peak memory 208384 kb
Host smart-fe97837b-4c8f-43cf-831c-6f2e147f6a46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927982702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1927982702
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1769366598
Short name T724
Test name
Test status
Simulation time 471492316 ps
CPU time 4.08 seconds
Started Jun 21 05:43:52 PM PDT 24
Finished Jun 21 05:43:57 PM PDT 24
Peak memory 206948 kb
Host smart-b64bd124-85d9-44c7-842c-2b39c712e9f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769366598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1769366598
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1382708159
Short name T640
Test name
Test status
Simulation time 237972542 ps
CPU time 6.58 seconds
Started Jun 21 05:43:51 PM PDT 24
Finished Jun 21 05:43:59 PM PDT 24
Peak memory 208156 kb
Host smart-86a73142-f58c-4fc4-b25c-af8ff045746c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382708159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1382708159
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1987041080
Short name T209
Test name
Test status
Simulation time 70794569 ps
CPU time 3.08 seconds
Started Jun 21 05:43:53 PM PDT 24
Finished Jun 21 05:43:57 PM PDT 24
Peak memory 214296 kb
Host smart-c6f121d4-877e-4f3d-93df-d9a3ca139284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987041080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1987041080
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4237688839
Short name T518
Test name
Test status
Simulation time 292959144 ps
CPU time 2.71 seconds
Started Jun 21 05:43:53 PM PDT 24
Finished Jun 21 05:43:57 PM PDT 24
Peak memory 208428 kb
Host smart-94f2d2fa-9656-4e18-aa13-53fa5eca6233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237688839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4237688839
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3836313069
Short name T280
Test name
Test status
Simulation time 488687960 ps
CPU time 5.69 seconds
Started Jun 21 05:43:53 PM PDT 24
Finished Jun 21 05:43:59 PM PDT 24
Peak memory 214236 kb
Host smart-1d8208f6-14eb-4fde-8aa5-073c58ae0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836313069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3836313069
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3381615908
Short name T31
Test name
Test status
Simulation time 73625458 ps
CPU time 2.98 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 210228 kb
Host smart-fa5938a1-0cb8-4da5-b237-1596f72bc486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381615908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3381615908
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.610721112
Short name T648
Test name
Test status
Simulation time 17713874 ps
CPU time 0.78 seconds
Started Jun 21 05:44:04 PM PDT 24
Finished Jun 21 05:44:06 PM PDT 24
Peak memory 205908 kb
Host smart-1825d1c7-b72e-476f-a4a8-2a79709a255d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610721112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.610721112
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3184039749
Short name T18
Test name
Test status
Simulation time 204378617 ps
CPU time 4.32 seconds
Started Jun 21 05:43:58 PM PDT 24
Finished Jun 21 05:44:03 PM PDT 24
Peak memory 215080 kb
Host smart-d5321930-ef5e-4301-ba46-aa3000d1e5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184039749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3184039749
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3771506619
Short name T66
Test name
Test status
Simulation time 43098164 ps
CPU time 1.97 seconds
Started Jun 21 05:44:03 PM PDT 24
Finished Jun 21 05:44:06 PM PDT 24
Peak memory 215056 kb
Host smart-ae515684-b877-499b-ab7b-1a7b8f3ca071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771506619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3771506619
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2225214356
Short name T788
Test name
Test status
Simulation time 59669093 ps
CPU time 1.79 seconds
Started Jun 21 05:44:04 PM PDT 24
Finished Jun 21 05:44:07 PM PDT 24
Peak memory 207824 kb
Host smart-23621d61-71bf-4301-ad33-fb0c669dd48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225214356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2225214356
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2765684906
Short name T85
Test name
Test status
Simulation time 180787179 ps
CPU time 4.25 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 215368 kb
Host smart-566dae72-553e-4baf-a46c-22814c25c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765684906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2765684906
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1259458240
Short name T97
Test name
Test status
Simulation time 419150507 ps
CPU time 5.95 seconds
Started Jun 21 05:44:05 PM PDT 24
Finished Jun 21 05:44:12 PM PDT 24
Peak memory 214276 kb
Host smart-14086871-f632-4ce2-9e91-16bbcd45f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259458240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1259458240
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.338827557
Short name T728
Test name
Test status
Simulation time 160172404 ps
CPU time 4.25 seconds
Started Jun 21 05:43:58 PM PDT 24
Finished Jun 21 05:44:03 PM PDT 24
Peak memory 220288 kb
Host smart-37e11997-644e-40be-b775-24996ed4a9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338827557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.338827557
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2919187401
Short name T590
Test name
Test status
Simulation time 4657160438 ps
CPU time 49.77 seconds
Started Jun 21 05:44:02 PM PDT 24
Finished Jun 21 05:44:53 PM PDT 24
Peak memory 214380 kb
Host smart-df629b1a-30bb-469b-b837-cdd8a8f0ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919187401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2919187401
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3207939963
Short name T322
Test name
Test status
Simulation time 81502732 ps
CPU time 3.09 seconds
Started Jun 21 05:43:58 PM PDT 24
Finished Jun 21 05:44:02 PM PDT 24
Peak memory 208464 kb
Host smart-9126f115-ed3f-42c9-8d00-983d2e7710e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207939963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3207939963
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.21937661
Short name T504
Test name
Test status
Simulation time 237313618 ps
CPU time 5.8 seconds
Started Jun 21 05:44:02 PM PDT 24
Finished Jun 21 05:44:09 PM PDT 24
Peak memory 208644 kb
Host smart-6244275f-5209-4395-b335-ecf8e6cea8ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21937661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.21937661
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4002153260
Short name T658
Test name
Test status
Simulation time 87285985 ps
CPU time 3.01 seconds
Started Jun 21 05:44:02 PM PDT 24
Finished Jun 21 05:44:06 PM PDT 24
Peak memory 206952 kb
Host smart-b03e24a7-2c4e-4d75-aa2f-1c5c54902ea5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002153260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4002153260
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.840416838
Short name T744
Test name
Test status
Simulation time 281299728 ps
CPU time 3.35 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 208668 kb
Host smart-31b37467-d11f-4c99-b167-ec6bc03ae8a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840416838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.840416838
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4169017518
Short name T509
Test name
Test status
Simulation time 208033114 ps
CPU time 2.86 seconds
Started Jun 21 05:44:01 PM PDT 24
Finished Jun 21 05:44:05 PM PDT 24
Peak memory 210100 kb
Host smart-ea823f5f-7f0f-4294-8973-655a5695e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169017518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4169017518
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2287882895
Short name T679
Test name
Test status
Simulation time 2245383250 ps
CPU time 4.36 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:06 PM PDT 24
Peak memory 207896 kb
Host smart-577b108f-7308-46e7-9f5a-f42e18c5f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287882895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2287882895
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2843890087
Short name T783
Test name
Test status
Simulation time 1407415932 ps
CPU time 51.49 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:51 PM PDT 24
Peak memory 215820 kb
Host smart-8127d6f0-9f52-40d5-b695-be6391721922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843890087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2843890087
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.371486155
Short name T644
Test name
Test status
Simulation time 140882058 ps
CPU time 5.37 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:06 PM PDT 24
Peak memory 207268 kb
Host smart-e76c48a3-a673-4acb-aba1-922a4a38d9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371486155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.371486155
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2036383355
Short name T768
Test name
Test status
Simulation time 368501678 ps
CPU time 4.16 seconds
Started Jun 21 05:44:06 PM PDT 24
Finished Jun 21 05:44:11 PM PDT 24
Peak memory 210944 kb
Host smart-02e16d65-b5c4-4eb1-a031-7db8221d5f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036383355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2036383355
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.268292378
Short name T894
Test name
Test status
Simulation time 17769905 ps
CPU time 0.81 seconds
Started Jun 21 05:44:05 PM PDT 24
Finished Jun 21 05:44:07 PM PDT 24
Peak memory 205932 kb
Host smart-86bba3eb-ff90-48bf-a331-d9200aca3c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268292378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.268292378
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2618095893
Short name T402
Test name
Test status
Simulation time 1292239265 ps
CPU time 7.45 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:07 PM PDT 24
Peak memory 215260 kb
Host smart-19c3dffa-fcfd-4a15-86b7-3f6ffe880055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618095893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2618095893
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2159087717
Short name T306
Test name
Test status
Simulation time 194181186 ps
CPU time 2.75 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 221188 kb
Host smart-3745577a-405e-4529-90ef-34bbd5f725c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159087717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2159087717
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3973941973
Short name T441
Test name
Test status
Simulation time 20912709 ps
CPU time 1.47 seconds
Started Jun 21 05:44:06 PM PDT 24
Finished Jun 21 05:44:09 PM PDT 24
Peak memory 208276 kb
Host smart-fb06ea7a-7867-45a7-9de7-4c4398b6f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973941973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3973941973
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1247163758
Short name T382
Test name
Test status
Simulation time 39968494 ps
CPU time 2.88 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 214300 kb
Host smart-a7c89b1e-3516-4760-a6a0-db3ab0754138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247163758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1247163758
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.1949429666
Short name T690
Test name
Test status
Simulation time 30893633 ps
CPU time 2.39 seconds
Started Jun 21 05:44:01 PM PDT 24
Finished Jun 21 05:44:05 PM PDT 24
Peak memory 207664 kb
Host smart-438b6660-3b01-4289-b241-a2634dd908bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949429666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1949429666
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2991863646
Short name T227
Test name
Test status
Simulation time 609582209 ps
CPU time 6.65 seconds
Started Jun 21 05:43:59 PM PDT 24
Finished Jun 21 05:44:06 PM PDT 24
Peak memory 207936 kb
Host smart-17ac081a-8c38-4ecf-b98d-c330ebb90a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991863646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2991863646
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2215378721
Short name T519
Test name
Test status
Simulation time 40441894 ps
CPU time 2.39 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:03 PM PDT 24
Peak memory 206784 kb
Host smart-6408a65a-51b4-43ea-81df-dd274f77bd88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215378721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2215378721
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2088452292
Short name T140
Test name
Test status
Simulation time 490953419 ps
CPU time 5.77 seconds
Started Jun 21 05:44:00 PM PDT 24
Finished Jun 21 05:44:07 PM PDT 24
Peak memory 208764 kb
Host smart-2da05cde-0ac6-49fd-b78f-b2ba2305e0ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088452292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2088452292
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1038980666
Short name T135
Test name
Test status
Simulation time 91328848 ps
CPU time 1.8 seconds
Started Jun 21 05:44:01 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 207648 kb
Host smart-11eddd9d-1d3d-4250-8cae-afdc8f539008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038980666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1038980666
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3467157191
Short name T541
Test name
Test status
Simulation time 64673932 ps
CPU time 2.79 seconds
Started Jun 21 05:44:01 PM PDT 24
Finished Jun 21 05:44:04 PM PDT 24
Peak memory 208092 kb
Host smart-ecac6d79-285d-4013-9812-595e38416635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467157191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3467157191
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1314320077
Short name T747
Test name
Test status
Simulation time 953017010 ps
CPU time 21.53 seconds
Started Jun 21 05:44:06 PM PDT 24
Finished Jun 21 05:44:28 PM PDT 24
Peak memory 208148 kb
Host smart-09d60700-6395-424d-a572-0a7afeffc7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314320077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1314320077
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4279800559
Short name T136
Test name
Test status
Simulation time 230657761 ps
CPU time 6.35 seconds
Started Jun 21 05:44:03 PM PDT 24
Finished Jun 21 05:44:10 PM PDT 24
Peak memory 207396 kb
Host smart-f4ae6ea8-0f1e-411e-b02c-c3e6e372f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279800559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4279800559
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.259228812
Short name T520
Test name
Test status
Simulation time 55248726 ps
CPU time 2.81 seconds
Started Jun 21 05:44:06 PM PDT 24
Finished Jun 21 05:44:10 PM PDT 24
Peak memory 210000 kb
Host smart-2a79e799-edcc-48ff-8e33-0a57fbda9985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259228812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.259228812
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.208646891
Short name T607
Test name
Test status
Simulation time 11387281 ps
CPU time 0.86 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:10 PM PDT 24
Peak memory 205968 kb
Host smart-90e97206-bc98-4eb3-98a8-06b5cb3094d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208646891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.208646891
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2312037640
Short name T123
Test name
Test status
Simulation time 48278226 ps
CPU time 3.52 seconds
Started Jun 21 05:44:06 PM PDT 24
Finished Jun 21 05:44:11 PM PDT 24
Peak memory 214288 kb
Host smart-f4e395ae-8e01-4102-b3f6-64515385de2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312037640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2312037640
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.778126188
Short name T772
Test name
Test status
Simulation time 147562006 ps
CPU time 1.63 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:10 PM PDT 24
Peak memory 215004 kb
Host smart-a1431265-e553-4a76-9df1-93e3ce8ad527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778126188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.778126188
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2215256498
Short name T716
Test name
Test status
Simulation time 185635620 ps
CPU time 2.77 seconds
Started Jun 21 05:44:07 PM PDT 24
Finished Jun 21 05:44:11 PM PDT 24
Peak memory 209484 kb
Host smart-30511d86-0862-419e-bbf5-c0687fee9ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215256498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2215256498
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2230254363
Short name T83
Test name
Test status
Simulation time 129576057 ps
CPU time 2.76 seconds
Started Jun 21 05:44:07 PM PDT 24
Finished Jun 21 05:44:11 PM PDT 24
Peak memory 214296 kb
Host smart-f0e33a34-3624-4351-af9e-692dafc9d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230254363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2230254363
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3274028975
Short name T57
Test name
Test status
Simulation time 119653360 ps
CPU time 4.29 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:14 PM PDT 24
Peak memory 222060 kb
Host smart-19f978ca-85cb-4bd9-a33d-561ca006958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274028975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3274028975
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.863887311
Short name T248
Test name
Test status
Simulation time 266315274 ps
CPU time 4.37 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:13 PM PDT 24
Peak memory 222540 kb
Host smart-ba650a3b-17a7-441e-8894-69042a081ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863887311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.863887311
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3218853035
Short name T448
Test name
Test status
Simulation time 142283370 ps
CPU time 5.72 seconds
Started Jun 21 05:44:10 PM PDT 24
Finished Jun 21 05:44:16 PM PDT 24
Peak memory 218224 kb
Host smart-77b7e5ff-88f6-4870-8d67-afd10b28fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218853035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3218853035
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1874324832
Short name T79
Test name
Test status
Simulation time 34634548 ps
CPU time 2.18 seconds
Started Jun 21 05:44:07 PM PDT 24
Finished Jun 21 05:44:10 PM PDT 24
Peak memory 206964 kb
Host smart-db6688f6-0f54-4789-b28a-962b0045e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874324832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1874324832
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1132122871
Short name T748
Test name
Test status
Simulation time 59149372 ps
CPU time 2.52 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:12 PM PDT 24
Peak memory 207008 kb
Host smart-dc4ec731-e269-4a9d-86df-0f773d7c7b33
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132122871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1132122871
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2598404449
Short name T394
Test name
Test status
Simulation time 113680143 ps
CPU time 3.09 seconds
Started Jun 21 05:44:07 PM PDT 24
Finished Jun 21 05:44:11 PM PDT 24
Peak memory 208704 kb
Host smart-e771d6f3-ece8-41ec-b921-ef3ecbd60888
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598404449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2598404449
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1802652026
Short name T879
Test name
Test status
Simulation time 200698418 ps
CPU time 4.66 seconds
Started Jun 21 05:44:07 PM PDT 24
Finished Jun 21 05:44:13 PM PDT 24
Peak memory 206932 kb
Host smart-2ed4a5b7-c89a-4e74-83d5-022bb68d515d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802652026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1802652026
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1006236480
Short name T499
Test name
Test status
Simulation time 88640973 ps
CPU time 3.67 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:13 PM PDT 24
Peak memory 214296 kb
Host smart-ce82d5f7-f036-47e1-adc6-f581ad0f32be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006236480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1006236480
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3283886408
Short name T819
Test name
Test status
Simulation time 1322131538 ps
CPU time 24.75 seconds
Started Jun 21 05:44:04 PM PDT 24
Finished Jun 21 05:44:30 PM PDT 24
Peak memory 208656 kb
Host smart-447ca33e-947a-4274-bfb5-f1aa8348ee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283886408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3283886408
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2471085566
Short name T365
Test name
Test status
Simulation time 15561277045 ps
CPU time 33.82 seconds
Started Jun 21 05:44:08 PM PDT 24
Finished Jun 21 05:44:43 PM PDT 24
Peak memory 222520 kb
Host smart-5eb1e92a-37c7-4949-adac-49827d562f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471085566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2471085566
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.712911081
Short name T133
Test name
Test status
Simulation time 1231771510 ps
CPU time 20.79 seconds
Started Jun 21 05:44:09 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 220724 kb
Host smart-ba589109-1469-43fa-9b01-4893f456b9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712911081 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.712911081
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3820405470
Short name T610
Test name
Test status
Simulation time 188314811 ps
CPU time 8.1 seconds
Started Jun 21 05:44:11 PM PDT 24
Finished Jun 21 05:44:20 PM PDT 24
Peak memory 218144 kb
Host smart-2489f1db-0ffb-4c66-b375-3bd5f10b471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820405470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3820405470
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2704555954
Short name T546
Test name
Test status
Simulation time 277070718 ps
CPU time 2.79 seconds
Started Jun 21 05:44:07 PM PDT 24
Finished Jun 21 05:44:11 PM PDT 24
Peak memory 210240 kb
Host smart-90310202-9b13-42f0-ab59-acd054fe9245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704555954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2704555954
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3597962602
Short name T482
Test name
Test status
Simulation time 15580880 ps
CPU time 0.93 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:18 PM PDT 24
Peak memory 206084 kb
Host smart-fef4be68-bfd1-4717-8921-74c9c3128224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597962602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3597962602
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3439884196
Short name T414
Test name
Test status
Simulation time 270208382 ps
CPU time 4.7 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 214968 kb
Host smart-fcd304cb-7abc-4385-b1de-170a50ce07ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439884196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3439884196
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1738737590
Short name T493
Test name
Test status
Simulation time 225370649 ps
CPU time 3.09 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:21 PM PDT 24
Peak memory 208740 kb
Host smart-1d03ea24-e1d0-42b3-ae86-dc5f6c6ac612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738737590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1738737590
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.141460144
Short name T676
Test name
Test status
Simulation time 26545994 ps
CPU time 1.93 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:22 PM PDT 24
Peak memory 207148 kb
Host smart-d9fa8a2d-6649-48fa-a324-33caeb4dfe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141460144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.141460144
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4292744639
Short name T735
Test name
Test status
Simulation time 196887886 ps
CPU time 2.38 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:21 PM PDT 24
Peak memory 214484 kb
Host smart-5a6e1dc1-4642-4980-b46b-1956eff6b913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292744639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4292744639
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2960222538
Short name T288
Test name
Test status
Simulation time 430977608 ps
CPU time 2.56 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:19 PM PDT 24
Peak memory 214244 kb
Host smart-0f83a402-97cb-4305-81b9-8a607ec74297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960222538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2960222538
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3425803769
Short name T720
Test name
Test status
Simulation time 627233918 ps
CPU time 3.26 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:20 PM PDT 24
Peak memory 220412 kb
Host smart-6096c794-1606-4648-b99c-39c8aa8ed8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425803769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3425803769
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.240030689
Short name T352
Test name
Test status
Simulation time 142041400 ps
CPU time 5.09 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 219248 kb
Host smart-d1ed3912-a6da-4ab2-8008-2b7df017d4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240030689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.240030689
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3467618340
Short name T513
Test name
Test status
Simulation time 508964039 ps
CPU time 3.89 seconds
Started Jun 21 05:44:15 PM PDT 24
Finished Jun 21 05:44:20 PM PDT 24
Peak memory 208772 kb
Host smart-28ac876f-72f1-4402-8817-490e5abd69a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467618340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3467618340
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1557032381
Short name T791
Test name
Test status
Simulation time 67504143 ps
CPU time 3.52 seconds
Started Jun 21 05:44:15 PM PDT 24
Finished Jun 21 05:44:19 PM PDT 24
Peak memory 209028 kb
Host smart-d4e52d5e-b2cf-44b0-8f6d-5fb6b9b44aa4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557032381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1557032381
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.519678618
Short name T462
Test name
Test status
Simulation time 34709398 ps
CPU time 2.41 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:22 PM PDT 24
Peak memory 208036 kb
Host smart-31c3b00b-8ca2-417a-98ad-41fa8c7e90ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519678618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.519678618
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1330217414
Short name T600
Test name
Test status
Simulation time 83771515 ps
CPU time 3.92 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:21 PM PDT 24
Peak memory 208688 kb
Host smart-cd53cc9d-6c69-4717-aa19-02e0a0aae0ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330217414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1330217414
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3984275202
Short name T440
Test name
Test status
Simulation time 119674338 ps
CPU time 2.88 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 218224 kb
Host smart-52b59ca7-0e07-4829-bcd2-a76e450f24e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984275202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3984275202
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3238696034
Short name T895
Test name
Test status
Simulation time 1492515498 ps
CPU time 12.71 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:29 PM PDT 24
Peak memory 207780 kb
Host smart-55f292f6-c564-4220-b96d-1f4305f90bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238696034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3238696034
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.30486692
Short name T871
Test name
Test status
Simulation time 856463471 ps
CPU time 12.48 seconds
Started Jun 21 05:44:18 PM PDT 24
Finished Jun 21 05:44:32 PM PDT 24
Peak memory 218772 kb
Host smart-b490f5d9-dddd-43e7-a7cd-d44980195288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30486692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.30486692
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.798078221
Short name T487
Test name
Test status
Simulation time 176813788 ps
CPU time 3.06 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:21 PM PDT 24
Peak memory 207396 kb
Host smart-7e381ef8-eaae-4216-9047-db65ee443ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798078221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.798078221
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1537831117
Short name T157
Test name
Test status
Simulation time 131876992 ps
CPU time 3.31 seconds
Started Jun 21 05:44:18 PM PDT 24
Finished Jun 21 05:44:22 PM PDT 24
Peak memory 210484 kb
Host smart-4579a308-1510-43e1-8108-3a263b067ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537831117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1537831117
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3139949336
Short name T635
Test name
Test status
Simulation time 13332164 ps
CPU time 0.75 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:21 PM PDT 24
Peak memory 205872 kb
Host smart-021ba570-0b0f-438b-b682-6eeb674cfee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139949336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3139949336
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1336771519
Short name T475
Test name
Test status
Simulation time 107572159 ps
CPU time 4.76 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 208884 kb
Host smart-fbb4afc6-b791-4d5d-874a-a6298fed95a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336771519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1336771519
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1286041056
Short name T490
Test name
Test status
Simulation time 74074205 ps
CPU time 3.45 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:21 PM PDT 24
Peak memory 218424 kb
Host smart-93ebda59-de71-409b-a717-6b2b635ae794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286041056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1286041056
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2522171876
Short name T84
Test name
Test status
Simulation time 2875291877 ps
CPU time 32.32 seconds
Started Jun 21 05:44:15 PM PDT 24
Finished Jun 21 05:44:48 PM PDT 24
Peak memory 221572 kb
Host smart-b0658eaf-83d7-4b23-ae3c-a782bb1e4fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522171876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2522171876
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.106550211
Short name T597
Test name
Test status
Simulation time 42002173 ps
CPU time 1.6 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:18 PM PDT 24
Peak memory 214244 kb
Host smart-c18cc6a7-6a13-45a1-a277-e9861c7c802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106550211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.106550211
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.219861876
Short name T620
Test name
Test status
Simulation time 84133240 ps
CPU time 4.09 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:22 PM PDT 24
Peak memory 216180 kb
Host smart-a343bb56-ffb2-4dcd-b763-460e002d72cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219861876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.219861876
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3772528891
Short name T754
Test name
Test status
Simulation time 29750000 ps
CPU time 2.19 seconds
Started Jun 21 05:44:15 PM PDT 24
Finished Jun 21 05:44:18 PM PDT 24
Peak memory 206876 kb
Host smart-3a3b30ea-e79e-434d-ab8a-2175bcd1cd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772528891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3772528891
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2165843393
Short name T760
Test name
Test status
Simulation time 239477571 ps
CPU time 6.2 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:25 PM PDT 24
Peak memory 208684 kb
Host smart-302e8cc1-8839-4abf-9701-52710e8b56d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165843393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2165843393
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3355108844
Short name T525
Test name
Test status
Simulation time 5427223123 ps
CPU time 58.23 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:45:19 PM PDT 24
Peak memory 209168 kb
Host smart-2393519b-4474-4c5b-9a35-a5d77373ea34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355108844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3355108844
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3394029052
Short name T591
Test name
Test status
Simulation time 501250487 ps
CPU time 7.78 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:25 PM PDT 24
Peak memory 208808 kb
Host smart-019081e3-0b5f-46d0-b667-5663aa1c2a1e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394029052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3394029052
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3900585231
Short name T826
Test name
Test status
Simulation time 679274468 ps
CPU time 16.91 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:37 PM PDT 24
Peak memory 209100 kb
Host smart-1d8b424b-4969-4fb7-bd90-f47872907b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900585231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3900585231
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1176197045
Short name T885
Test name
Test status
Simulation time 238910204 ps
CPU time 2.77 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:23 PM PDT 24
Peak memory 208300 kb
Host smart-2bcb96a5-9222-417e-a46b-617c764b3965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176197045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1176197045
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.201491348
Short name T797
Test name
Test status
Simulation time 549079137 ps
CPU time 25.31 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:43 PM PDT 24
Peak memory 215680 kb
Host smart-297c659b-c5b7-416d-ad8e-843df9f3d067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201491348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.201491348
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3520704602
Short name T131
Test name
Test status
Simulation time 403804044 ps
CPU time 17.08 seconds
Started Jun 21 05:44:19 PM PDT 24
Finished Jun 21 05:44:38 PM PDT 24
Peak memory 222516 kb
Host smart-a87b4fad-bf50-4e13-8e86-f63609352550
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520704602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3520704602
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3090861622
Short name T776
Test name
Test status
Simulation time 1229512772 ps
CPU time 37.55 seconds
Started Jun 21 05:44:17 PM PDT 24
Finished Jun 21 05:44:55 PM PDT 24
Peak memory 214340 kb
Host smart-8b8b4113-b52f-4c6a-97cf-ef89726f6b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090861622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3090861622
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2451183164
Short name T51
Test name
Test status
Simulation time 625920542 ps
CPU time 2.58 seconds
Started Jun 21 05:44:16 PM PDT 24
Finished Jun 21 05:44:19 PM PDT 24
Peak memory 210388 kb
Host smart-6f7bdde6-6d70-42d3-9824-2631b7b276dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451183164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2451183164
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2726995163
Short name T795
Test name
Test status
Simulation time 55136247 ps
CPU time 0.8 seconds
Started Jun 21 05:44:28 PM PDT 24
Finished Jun 21 05:44:29 PM PDT 24
Peak memory 205928 kb
Host smart-bb76a743-9ada-407f-a867-5b92de278a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726995163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2726995163
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1063598702
Short name T416
Test name
Test status
Simulation time 57184130 ps
CPU time 4.39 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:30 PM PDT 24
Peak memory 215336 kb
Host smart-2c0494e0-35a3-48ce-9aa9-67388266468f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063598702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1063598702
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.170307593
Short name T542
Test name
Test status
Simulation time 327002760 ps
CPU time 3.81 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 222776 kb
Host smart-520f46d5-c5c0-4c85-a5ac-9b08d1528e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170307593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.170307593
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2638108615
Short name T434
Test name
Test status
Simulation time 1136670591 ps
CPU time 12.95 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 05:44:40 PM PDT 24
Peak memory 208472 kb
Host smart-bc12e9c7-6b3e-4f46-a7b1-5fb7941114c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638108615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2638108615
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1388599786
Short name T820
Test name
Test status
Simulation time 123314851 ps
CPU time 2.6 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:29 PM PDT 24
Peak memory 214352 kb
Host smart-9a0291a5-06f1-4a88-a69e-4a1a4c587bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388599786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1388599786
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3027702276
Short name T385
Test name
Test status
Simulation time 140936679 ps
CPU time 3.75 seconds
Started Jun 21 05:44:28 PM PDT 24
Finished Jun 21 05:44:33 PM PDT 24
Peak memory 214316 kb
Host smart-4c9b05c4-2e15-4daa-8da7-a86395facf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027702276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3027702276
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3646430489
Short name T505
Test name
Test status
Simulation time 565299636 ps
CPU time 6.31 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 05:44:34 PM PDT 24
Peak memory 209860 kb
Host smart-bb53ff40-70b7-4821-959f-b7e7fbcea700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646430489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3646430489
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2205299558
Short name T762
Test name
Test status
Simulation time 827735284 ps
CPU time 7.05 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 05:44:35 PM PDT 24
Peak memory 207768 kb
Host smart-7c0a05fc-ad20-4335-8155-c1bc7ca2ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205299558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2205299558
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2949171322
Short name T361
Test name
Test status
Simulation time 448250030 ps
CPU time 7.03 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:34 PM PDT 24
Peak memory 208472 kb
Host smart-d9766b43-0a62-4275-bcd1-1b02d5e34a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949171322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2949171322
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.972368543
Short name T893
Test name
Test status
Simulation time 556047907 ps
CPU time 4.9 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:32 PM PDT 24
Peak memory 208892 kb
Host smart-a6ea065c-0ce0-452f-aedb-b63e94ca4428
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972368543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.972368543
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1625203186
Short name T540
Test name
Test status
Simulation time 293964262 ps
CPU time 4.49 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:29 PM PDT 24
Peak memory 208756 kb
Host smart-69b342d5-b786-483f-99d1-99dd081ce343
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625203186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1625203186
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.721593811
Short name T373
Test name
Test status
Simulation time 205581082 ps
CPU time 7.61 seconds
Started Jun 21 05:44:27 PM PDT 24
Finished Jun 21 05:44:36 PM PDT 24
Peak memory 208396 kb
Host smart-9909d69d-1340-40c5-b708-3753fa36f470
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721593811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.721593811
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1502195747
Short name T307
Test name
Test status
Simulation time 228338431 ps
CPU time 2.87 seconds
Started Jun 21 05:44:27 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 209012 kb
Host smart-644444e9-4e6d-45ea-86aa-3c482d3ba7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502195747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1502195747
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.936205453
Short name T638
Test name
Test status
Simulation time 485565119 ps
CPU time 4.04 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 206824 kb
Host smart-d9b9bd72-1dbb-4e1d-bc5b-438d443c23fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936205453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.936205453
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3285311077
Short name T799
Test name
Test status
Simulation time 426604168 ps
CPU time 4.46 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:30 PM PDT 24
Peak memory 209124 kb
Host smart-f78422c0-5693-41c2-ae23-19f1b74a2b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285311077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3285311077
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3297497336
Short name T292
Test name
Test status
Simulation time 354684184 ps
CPU time 18.89 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:44 PM PDT 24
Peak memory 222720 kb
Host smart-3a5db42a-3e12-4b81-9f1b-93b4fde334ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297497336 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3297497336
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2553962077
Short name T767
Test name
Test status
Simulation time 842297772 ps
CPU time 30.98 seconds
Started Jun 21 05:44:28 PM PDT 24
Finished Jun 21 05:45:00 PM PDT 24
Peak memory 209716 kb
Host smart-83f4dd5b-a7f2-4550-8e8a-7651d98efc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553962077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2553962077
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.567694851
Short name T155
Test name
Test status
Simulation time 390802971 ps
CPU time 5.96 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:33 PM PDT 24
Peak memory 210440 kb
Host smart-fb3aacd5-686c-4a61-9ef7-51553912bce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567694851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.567694851
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4028734598
Short name T488
Test name
Test status
Simulation time 12062420 ps
CPU time 0.77 seconds
Started Jun 21 05:44:23 PM PDT 24
Finished Jun 21 05:44:25 PM PDT 24
Peak memory 205916 kb
Host smart-924a8c1e-97df-45e7-a8a4-e9e57f9df5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028734598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4028734598
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3510475970
Short name T391
Test name
Test status
Simulation time 44260516 ps
CPU time 3.56 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 214356 kb
Host smart-28b217e6-ab58-4774-885b-0c941265fa9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510475970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3510475970
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2967628734
Short name T229
Test name
Test status
Simulation time 452758178 ps
CPU time 3.79 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:29 PM PDT 24
Peak memory 214284 kb
Host smart-0bde389d-dde8-4e80-a421-406811af6759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967628734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2967628734
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3969787090
Short name T366
Test name
Test status
Simulation time 45625455 ps
CPU time 2.43 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:30 PM PDT 24
Peak memory 214312 kb
Host smart-b2ae8cd3-794c-4806-a6a8-b3d44c02cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969787090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3969787090
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.949568997
Short name T315
Test name
Test status
Simulation time 49516666 ps
CPU time 2.61 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:29 PM PDT 24
Peak memory 214248 kb
Host smart-23a66503-1050-4060-a939-1f4b37bc0591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949568997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.949568997
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4159314033
Short name T896
Test name
Test status
Simulation time 56839102 ps
CPU time 2.41 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:27 PM PDT 24
Peak memory 208184 kb
Host smart-62170a50-01f2-4913-8219-64697ccdfc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159314033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4159314033
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2892496935
Short name T880
Test name
Test status
Simulation time 150664039 ps
CPU time 4.99 seconds
Started Jun 21 05:44:26 PM PDT 24
Finished Jun 21 05:44:33 PM PDT 24
Peak memory 207240 kb
Host smart-c4c7aa47-ef5a-4aa6-b1f0-53eeafd99c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892496935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2892496935
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2359008305
Short name T351
Test name
Test status
Simulation time 77175908 ps
CPU time 3.83 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 208660 kb
Host smart-8c6103bc-498c-4c86-9312-138f1bf7171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359008305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2359008305
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2817894498
Short name T770
Test name
Test status
Simulation time 615276167 ps
CPU time 4.87 seconds
Started Jun 21 05:44:27 PM PDT 24
Finished Jun 21 05:44:33 PM PDT 24
Peak memory 208768 kb
Host smart-fd511702-7991-4ee8-8432-d980c09a5b6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817894498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2817894498
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1386236521
Short name T662
Test name
Test status
Simulation time 52718575 ps
CPU time 2.92 seconds
Started Jun 21 05:44:29 PM PDT 24
Finished Jun 21 05:44:32 PM PDT 24
Peak memory 207812 kb
Host smart-58a21c76-b291-490f-a61e-0ea01a8f54d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386236521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1386236521
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4055010341
Short name T641
Test name
Test status
Simulation time 197868366 ps
CPU time 3.01 seconds
Started Jun 21 05:44:28 PM PDT 24
Finished Jun 21 05:44:32 PM PDT 24
Peak memory 206820 kb
Host smart-e58c46c5-3bd6-4c00-af87-9da34c7a842a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055010341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4055010341
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3015423043
Short name T291
Test name
Test status
Simulation time 1197698719 ps
CPU time 7 seconds
Started Jun 21 05:44:25 PM PDT 24
Finished Jun 21 05:44:33 PM PDT 24
Peak memory 220380 kb
Host smart-b607c793-2e23-4255-9b08-76fad7371e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015423043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3015423043
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2431535970
Short name T421
Test name
Test status
Simulation time 141907528 ps
CPU time 3.2 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:28 PM PDT 24
Peak memory 208616 kb
Host smart-9809cbd6-b1a5-4820-98e2-cbfafe5fad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431535970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2431535970
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1173723052
Short name T827
Test name
Test status
Simulation time 132831924 ps
CPU time 7.37 seconds
Started Jun 21 05:44:23 PM PDT 24
Finished Jun 21 05:44:32 PM PDT 24
Peak memory 220392 kb
Host smart-9d6ac80a-f994-458e-ab5f-195bd1a1731b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173723052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1173723052
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3131894637
Short name T312
Test name
Test status
Simulation time 201181082 ps
CPU time 4.98 seconds
Started Jun 21 05:44:24 PM PDT 24
Finished Jun 21 05:44:30 PM PDT 24
Peak memory 208796 kb
Host smart-85d8bce5-cbec-400a-9652-3c356c418621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131894637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3131894637
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.275309548
Short name T181
Test name
Test status
Simulation time 104033640 ps
CPU time 2.76 seconds
Started Jun 21 05:44:27 PM PDT 24
Finished Jun 21 05:44:31 PM PDT 24
Peak memory 210468 kb
Host smart-053584a7-8436-44b9-a42c-3c3d07f2c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275309548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.275309548
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.945707434
Short name T98
Test name
Test status
Simulation time 31366558 ps
CPU time 0.81 seconds
Started Jun 21 05:39:56 PM PDT 24
Finished Jun 21 05:39:58 PM PDT 24
Peak memory 206016 kb
Host smart-3456abc8-be2c-4f6d-89b5-fbc206e49de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945707434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.945707434
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2369051691
Short name T304
Test name
Test status
Simulation time 91557559 ps
CPU time 4.28 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:56 PM PDT 24
Peak memory 214308 kb
Host smart-36733312-2140-4c0c-8bb3-14b172be1315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369051691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2369051691
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1965379215
Short name T237
Test name
Test status
Simulation time 169779940 ps
CPU time 4.5 seconds
Started Jun 21 05:39:49 PM PDT 24
Finished Jun 21 05:39:53 PM PDT 24
Peak memory 220620 kb
Host smart-f3183ea7-79e9-4341-a2c9-97662693b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965379215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1965379215
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1897030193
Short name T843
Test name
Test status
Simulation time 500356283 ps
CPU time 3.12 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:55 PM PDT 24
Peak memory 214516 kb
Host smart-95cfd8ce-135f-4bf1-a97a-8eed3a9406f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897030193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1897030193
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2413327994
Short name T903
Test name
Test status
Simulation time 246917010 ps
CPU time 8.87 seconds
Started Jun 21 05:39:53 PM PDT 24
Finished Jun 21 05:40:02 PM PDT 24
Peak memory 217932 kb
Host smart-dc3d6b03-2f07-4133-bff2-d354ca28bec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413327994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2413327994
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1808839471
Short name T918
Test name
Test status
Simulation time 918230295 ps
CPU time 6.08 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:58 PM PDT 24
Peak memory 208620 kb
Host smart-d4dba046-173b-42c7-aa13-fca38f57b8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808839471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1808839471
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3922059815
Short name T379
Test name
Test status
Simulation time 1806528979 ps
CPU time 35.25 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:40:26 PM PDT 24
Peak memory 208512 kb
Host smart-f369437c-fad7-4263-b72f-7f4b6f480f6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922059815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3922059815
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2155303468
Short name T397
Test name
Test status
Simulation time 143520676 ps
CPU time 4.76 seconds
Started Jun 21 05:39:50 PM PDT 24
Finished Jun 21 05:39:55 PM PDT 24
Peak memory 208104 kb
Host smart-54c8d440-f9af-49f4-90de-e13ae35257ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155303468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2155303468
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1024023722
Short name T758
Test name
Test status
Simulation time 430327432 ps
CPU time 3.99 seconds
Started Jun 21 05:39:49 PM PDT 24
Finished Jun 21 05:39:54 PM PDT 24
Peak memory 208400 kb
Host smart-5f33f42f-e1d0-43b8-a269-a53359cd0680
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024023722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1024023722
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2596093753
Short name T660
Test name
Test status
Simulation time 606145798 ps
CPU time 18.97 seconds
Started Jun 21 05:39:52 PM PDT 24
Finished Jun 21 05:40:12 PM PDT 24
Peak memory 209040 kb
Host smart-6f943fd6-a3c5-4708-83ba-f8aab6276304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596093753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2596093753
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3638164452
Short name T605
Test name
Test status
Simulation time 549795796 ps
CPU time 3.3 seconds
Started Jun 21 05:39:49 PM PDT 24
Finished Jun 21 05:39:52 PM PDT 24
Peak memory 208240 kb
Host smart-7797ce1e-4a78-4c45-a7ac-ff7df7c34701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638164452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3638164452
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.69952912
Short name T212
Test name
Test status
Simulation time 1613479761 ps
CPU time 37.31 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:37 PM PDT 24
Peak memory 217092 kb
Host smart-f92d3d66-bce6-49fa-be99-88748b0ac7bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69952912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.69952912
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.974508240
Short name T101
Test name
Test status
Simulation time 342228157 ps
CPU time 13.09 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:12 PM PDT 24
Peak memory 222480 kb
Host smart-9f8f014b-f0b0-4080-94cf-bd078b460b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974508240 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.974508240
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1476706336
Short name T78
Test name
Test status
Simulation time 322310822 ps
CPU time 4.32 seconds
Started Jun 21 05:39:50 PM PDT 24
Finished Jun 21 05:39:55 PM PDT 24
Peak memory 207864 kb
Host smart-caa30fbb-6f75-4dc3-8ef2-b3d9095c9572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476706336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1476706336
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.619776090
Short name T178
Test name
Test status
Simulation time 418903853 ps
CPU time 1.83 seconds
Started Jun 21 05:39:51 PM PDT 24
Finished Jun 21 05:39:54 PM PDT 24
Peak memory 209796 kb
Host smart-9741fa9a-9772-49c4-bad3-749011ea8e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619776090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.619776090
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2427542096
Short name T425
Test name
Test status
Simulation time 30569664 ps
CPU time 0.78 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:06 PM PDT 24
Peak memory 205924 kb
Host smart-099c9644-8436-4c11-a457-a38c579ce623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427542096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2427542096
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1504714043
Short name T798
Test name
Test status
Simulation time 1219750887 ps
CPU time 8.66 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:08 PM PDT 24
Peak memory 214868 kb
Host smart-27ea829b-722d-493f-9c3e-5f729ac246bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504714043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1504714043
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.37957458
Short name T521
Test name
Test status
Simulation time 205323511 ps
CPU time 2.17 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:01 PM PDT 24
Peak memory 214296 kb
Host smart-e1cb79dd-46db-4722-acc6-b901cf7deebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37957458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.37957458
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1623199097
Short name T829
Test name
Test status
Simulation time 79059595 ps
CPU time 1.67 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:01 PM PDT 24
Peak memory 218164 kb
Host smart-0dd2d05c-4eaa-4e2f-9194-fe317922442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623199097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1623199097
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1968810620
Short name T801
Test name
Test status
Simulation time 634184022 ps
CPU time 8.9 seconds
Started Jun 21 05:39:57 PM PDT 24
Finished Jun 21 05:40:08 PM PDT 24
Peak memory 214284 kb
Host smart-e1b5a0f3-02c9-4759-810d-54728e698f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968810620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1968810620
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2514097148
Short name T370
Test name
Test status
Simulation time 45963556 ps
CPU time 2.39 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:02 PM PDT 24
Peak memory 214248 kb
Host smart-a223e32b-40c4-4806-b539-a56f6a0c55e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514097148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2514097148
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2015152718
Short name T477
Test name
Test status
Simulation time 89733604 ps
CPU time 2.47 seconds
Started Jun 21 05:39:57 PM PDT 24
Finished Jun 21 05:40:01 PM PDT 24
Peak memory 209484 kb
Host smart-c1287e3b-9c9e-4e02-8f9a-ee67faaf9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015152718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2015152718
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4211053925
Short name T228
Test name
Test status
Simulation time 126612592 ps
CPU time 5.18 seconds
Started Jun 21 05:39:57 PM PDT 24
Finished Jun 21 05:40:03 PM PDT 24
Peak memory 209736 kb
Host smart-b8f78e61-45b0-4781-b88a-30dc7b33875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211053925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4211053925
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2329820857
Short name T643
Test name
Test status
Simulation time 118640987 ps
CPU time 3.16 seconds
Started Jun 21 05:39:57 PM PDT 24
Finished Jun 21 05:40:02 PM PDT 24
Peak memory 206868 kb
Host smart-258c8e17-c3d7-425a-abb8-8d050ec0d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329820857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2329820857
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3459753405
Short name T779
Test name
Test status
Simulation time 63149167 ps
CPU time 2.51 seconds
Started Jun 21 05:39:59 PM PDT 24
Finished Jun 21 05:40:02 PM PDT 24
Peak memory 207000 kb
Host smart-9300bfeb-d192-40f5-b8c5-661260f0dc02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459753405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3459753405
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1410572904
Short name T560
Test name
Test status
Simulation time 606959962 ps
CPU time 4.95 seconds
Started Jun 21 05:39:56 PM PDT 24
Finished Jun 21 05:40:03 PM PDT 24
Peak memory 206924 kb
Host smart-170576a7-c580-4720-b9f2-cd64a0bfc399
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410572904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1410572904
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.572898666
Short name T501
Test name
Test status
Simulation time 319200686 ps
CPU time 7.06 seconds
Started Jun 21 05:39:56 PM PDT 24
Finished Jun 21 05:40:04 PM PDT 24
Peak memory 208580 kb
Host smart-3377f4c3-30ad-4541-ab0e-da5b88d56d38
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572898666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.572898666
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.19876356
Short name T712
Test name
Test status
Simulation time 1263314812 ps
CPU time 9.44 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:16 PM PDT 24
Peak memory 209828 kb
Host smart-5bf71663-5d6c-4078-9010-0f1ca0c1a522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19876356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.19876356
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1393640041
Short name T892
Test name
Test status
Simulation time 290462293 ps
CPU time 2.63 seconds
Started Jun 21 05:39:58 PM PDT 24
Finished Jun 21 05:40:02 PM PDT 24
Peak memory 208396 kb
Host smart-9c43b7a3-3119-4a73-99c2-df0b9ec501dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393640041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1393640041
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2196447139
Short name T548
Test name
Test status
Simulation time 72223234 ps
CPU time 3.86 seconds
Started Jun 21 05:40:00 PM PDT 24
Finished Jun 21 05:40:04 PM PDT 24
Peak memory 207464 kb
Host smart-08394818-1d51-4df8-ae0f-d8bfd4cdd892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196447139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2196447139
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2338240214
Short name T53
Test name
Test status
Simulation time 48962541 ps
CPU time 2.34 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:09 PM PDT 24
Peak memory 209972 kb
Host smart-7f4f52cf-8b75-4e73-add0-45c8e7777d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338240214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2338240214
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.702874338
Short name T461
Test name
Test status
Simulation time 49396526 ps
CPU time 0.72 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:18 PM PDT 24
Peak memory 205892 kb
Host smart-26d81774-79c1-4a18-8735-1178b858eca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702874338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.702874338
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.226297912
Short name T899
Test name
Test status
Simulation time 214183545 ps
CPU time 3.35 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:09 PM PDT 24
Peak memory 209920 kb
Host smart-b87d1a42-95f3-41b7-869e-4cd1bf5fd2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226297912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.226297912
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3353565040
Short name T223
Test name
Test status
Simulation time 16071701 ps
CPU time 1.61 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:07 PM PDT 24
Peak memory 214300 kb
Host smart-27fdeb1e-2c24-4219-8d76-7e8236c8b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353565040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3353565040
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2712478923
Short name T661
Test name
Test status
Simulation time 1468133401 ps
CPU time 26.37 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:33 PM PDT 24
Peak memory 222364 kb
Host smart-08833f6c-f9a1-4920-9028-0473512051c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712478923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2712478923
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2128548706
Short name T368
Test name
Test status
Simulation time 51770345 ps
CPU time 2.17 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:08 PM PDT 24
Peak memory 214344 kb
Host smart-c26adfdd-b6b2-4d2c-a4b2-575a3867c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128548706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2128548706
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1463850764
Short name T221
Test name
Test status
Simulation time 321304839 ps
CPU time 2.5 seconds
Started Jun 21 05:40:08 PM PDT 24
Finished Jun 21 05:40:11 PM PDT 24
Peak memory 214384 kb
Host smart-0d840705-e2f3-4831-8f44-ef2b37c4ad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463850764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1463850764
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4000108501
Short name T502
Test name
Test status
Simulation time 78214383 ps
CPU time 3.9 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:10 PM PDT 24
Peak memory 207848 kb
Host smart-4200e9fd-f3d0-4879-b320-55d1fde87355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000108501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4000108501
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.570782714
Short name T213
Test name
Test status
Simulation time 4498930472 ps
CPU time 42.2 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:49 PM PDT 24
Peak memory 208144 kb
Host smart-9047af33-f72a-4507-97ba-2ce6e303a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570782714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.570782714
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2328578928
Short name T466
Test name
Test status
Simulation time 1788579173 ps
CPU time 9.78 seconds
Started Jun 21 05:40:05 PM PDT 24
Finished Jun 21 05:40:17 PM PDT 24
Peak memory 206936 kb
Host smart-43557e58-7a67-4425-90a7-eb5ce0174715
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328578928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2328578928
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2886050713
Short name T193
Test name
Test status
Simulation time 591481075 ps
CPU time 7.43 seconds
Started Jun 21 05:40:04 PM PDT 24
Finished Jun 21 05:40:12 PM PDT 24
Peak memory 207076 kb
Host smart-5230703d-73e8-402e-9e9e-c9d97f071f41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886050713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2886050713
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.432702041
Short name T233
Test name
Test status
Simulation time 675230547 ps
CPU time 4.55 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:12 PM PDT 24
Peak memory 208476 kb
Host smart-d23a5d4d-cdf5-49c9-8af3-a86802e4ef99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432702041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.432702041
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3101566818
Short name T464
Test name
Test status
Simulation time 422575669 ps
CPU time 2.53 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:20 PM PDT 24
Peak memory 207116 kb
Host smart-40c91100-3881-4941-a481-9d721aadc7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101566818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3101566818
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.88442448
Short name T230
Test name
Test status
Simulation time 71522599 ps
CPU time 2.21 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:09 PM PDT 24
Peak memory 206976 kb
Host smart-b8fe5a5f-c572-4f2f-9e4f-67358030fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88442448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.88442448
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4019913631
Short name T60
Test name
Test status
Simulation time 1165556064 ps
CPU time 13.23 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:30 PM PDT 24
Peak memory 215244 kb
Host smart-fbe575cf-ae1d-468e-9f96-6f1c53cf2700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019913631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4019913631
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3291641970
Short name T522
Test name
Test status
Simulation time 96564629 ps
CPU time 5.92 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:22 PM PDT 24
Peak memory 222552 kb
Host smart-36ac9c6f-f859-4705-bc18-561d63def70e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291641970 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3291641970
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1662631735
Short name T817
Test name
Test status
Simulation time 348185022 ps
CPU time 6.85 seconds
Started Jun 21 05:40:06 PM PDT 24
Finished Jun 21 05:40:14 PM PDT 24
Peak memory 208996 kb
Host smart-859082d3-6414-4c4e-8f39-c0743d4ac7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662631735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1662631735
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2885872565
Short name T169
Test name
Test status
Simulation time 890537155 ps
CPU time 2.59 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:18 PM PDT 24
Peak memory 209944 kb
Host smart-9487cd31-c38e-444f-ae7a-2d5919215904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885872565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2885872565
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1285309811
Short name T516
Test name
Test status
Simulation time 15107493 ps
CPU time 0.95 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:26 PM PDT 24
Peak memory 206068 kb
Host smart-1988e6ec-1af0-49d5-92ea-5336bd0e9a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285309811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1285309811
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.57868318
Short name T275
Test name
Test status
Simulation time 182100292 ps
CPU time 4.04 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:21 PM PDT 24
Peak memory 214340 kb
Host smart-0bef8671-b424-4c4a-a069-31c436d3f879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57868318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.57868318
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.206658027
Short name T634
Test name
Test status
Simulation time 310878301 ps
CPU time 5.53 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:21 PM PDT 24
Peak memory 209028 kb
Host smart-f77477be-c74a-4ce2-92b6-d3536e758aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206658027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.206658027
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2310081467
Short name T446
Test name
Test status
Simulation time 2365082514 ps
CPU time 13.63 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:30 PM PDT 24
Peak memory 221792 kb
Host smart-46f8aeb5-6291-4eb5-b96e-d5ba5d1a8e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310081467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2310081467
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1380612047
Short name T246
Test name
Test status
Simulation time 108655805 ps
CPU time 4.2 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:21 PM PDT 24
Peak memory 209600 kb
Host smart-3fc279fa-e182-4f1a-8e75-b991fa17853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380612047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1380612047
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1144517888
Short name T621
Test name
Test status
Simulation time 1097581144 ps
CPU time 9.15 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:27 PM PDT 24
Peak memory 218184 kb
Host smart-581c3f3b-5f41-4080-9f5f-b17e7f1f102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144517888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1144517888
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4208057011
Short name T746
Test name
Test status
Simulation time 63774903 ps
CPU time 3.08 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:21 PM PDT 24
Peak memory 206916 kb
Host smart-1dce4cea-34a8-4e3c-a1de-a4603566861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208057011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4208057011
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1850818777
Short name T337
Test name
Test status
Simulation time 22059232 ps
CPU time 1.88 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:19 PM PDT 24
Peak memory 207320 kb
Host smart-07fbb4f1-fdf5-4079-b5f7-ebea709672d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850818777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1850818777
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.103704517
Short name T439
Test name
Test status
Simulation time 60336785 ps
CPU time 3.01 seconds
Started Jun 21 05:40:16 PM PDT 24
Finished Jun 21 05:40:20 PM PDT 24
Peak memory 207932 kb
Host smart-3cb31c90-d35f-4eb4-9757-27ae58c2188d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103704517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.103704517
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1185009231
Short name T217
Test name
Test status
Simulation time 1013027320 ps
CPU time 7.79 seconds
Started Jun 21 05:40:18 PM PDT 24
Finished Jun 21 05:40:27 PM PDT 24
Peak memory 207148 kb
Host smart-698ca1fc-9266-4196-ad96-15e8189504f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185009231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1185009231
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2431529582
Short name T596
Test name
Test status
Simulation time 393125505 ps
CPU time 3.67 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:29 PM PDT 24
Peak memory 218104 kb
Host smart-95bfc1d1-617c-4a20-ad3d-d9b7a7c9eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431529582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2431529582
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2722467538
Short name T677
Test name
Test status
Simulation time 289009254 ps
CPU time 2.6 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:19 PM PDT 24
Peak memory 206884 kb
Host smart-f7a48318-1e37-4f97-842d-c44a328fc7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722467538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2722467538
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1412044946
Short name T681
Test name
Test status
Simulation time 1237442698 ps
CPU time 21.56 seconds
Started Jun 21 05:40:25 PM PDT 24
Finished Jun 21 05:40:48 PM PDT 24
Peak memory 216468 kb
Host smart-892b74a2-bf6f-4a05-8dc8-2ed8c1551b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412044946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1412044946
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3799378987
Short name T592
Test name
Test status
Simulation time 742340580 ps
CPU time 11.33 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:37 PM PDT 24
Peak memory 218784 kb
Host smart-659fab53-96ed-4134-97b5-71f9e06d1f97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799378987 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3799378987
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.687402903
Short name T459
Test name
Test status
Simulation time 521219108 ps
CPU time 7.45 seconds
Started Jun 21 05:40:15 PM PDT 24
Finished Jun 21 05:40:24 PM PDT 24
Peak memory 207332 kb
Host smart-057da313-bbe3-4d3f-ac02-152ce4067ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687402903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.687402903
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2147571559
Short name T656
Test name
Test status
Simulation time 14823844 ps
CPU time 0.84 seconds
Started Jun 21 05:40:31 PM PDT 24
Finished Jun 21 05:40:33 PM PDT 24
Peak memory 205912 kb
Host smart-f0282ec4-40fd-4713-bf49-ea263e07f7e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147571559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2147571559
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.777659897
Short name T36
Test name
Test status
Simulation time 83793897 ps
CPU time 2 seconds
Started Jun 21 05:40:22 PM PDT 24
Finished Jun 21 05:40:25 PM PDT 24
Peak memory 209184 kb
Host smart-417fdbcc-c04e-4023-8912-ce3d4c84b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777659897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.777659897
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2159292136
Short name T891
Test name
Test status
Simulation time 771977556 ps
CPU time 3.12 seconds
Started Jun 21 05:40:23 PM PDT 24
Finished Jun 21 05:40:27 PM PDT 24
Peak memory 219692 kb
Host smart-476cc5ea-dc93-4564-b741-c320565b3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159292136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2159292136
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1421349574
Short name T86
Test name
Test status
Simulation time 395282862 ps
CPU time 3.99 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:29 PM PDT 24
Peak memory 214728 kb
Host smart-81f81eb9-0147-44b9-b6c0-ea635ba78124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421349574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1421349574
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1039818149
Short name T669
Test name
Test status
Simulation time 309731438 ps
CPU time 5.05 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:30 PM PDT 24
Peak memory 222436 kb
Host smart-352c3ef7-77bb-4cb0-9618-9e160b15dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039818149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1039818149
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1634496586
Short name T581
Test name
Test status
Simulation time 72297806 ps
CPU time 2.81 seconds
Started Jun 21 05:40:26 PM PDT 24
Finished Jun 21 05:40:29 PM PDT 24
Peak memory 220288 kb
Host smart-8d3257d4-c940-4340-8f27-057ba3c6b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634496586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1634496586
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2244397316
Short name T884
Test name
Test status
Simulation time 647439261 ps
CPU time 5.19 seconds
Started Jun 21 05:40:25 PM PDT 24
Finished Jun 21 05:40:31 PM PDT 24
Peak memory 207308 kb
Host smart-8b652fa3-3572-4289-ab4d-4feeae149ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244397316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2244397316
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.590318408
Short name T141
Test name
Test status
Simulation time 47520326 ps
CPU time 2 seconds
Started Jun 21 05:40:25 PM PDT 24
Finished Jun 21 05:40:28 PM PDT 24
Peak memory 207316 kb
Host smart-6a750a05-a07c-467b-8fce-04160e86abdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590318408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.590318408
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3536637497
Short name T814
Test name
Test status
Simulation time 52578319 ps
CPU time 2.75 seconds
Started Jun 21 05:40:22 PM PDT 24
Finished Jun 21 05:40:26 PM PDT 24
Peak memory 208692 kb
Host smart-9abfc1e3-39f5-430b-bdab-2de16c951b3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536637497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3536637497
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3737346568
Short name T815
Test name
Test status
Simulation time 237651558 ps
CPU time 4.88 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:30 PM PDT 24
Peak memory 206828 kb
Host smart-8ea94299-cf2d-4488-8de9-49d646af45aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737346568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3737346568
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.4177992215
Short name T624
Test name
Test status
Simulation time 62045824 ps
CPU time 3.13 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:29 PM PDT 24
Peak memory 206904 kb
Host smart-a5fe0183-2400-491a-b84b-bc255deed0b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177992215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.4177992215
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.4223437389
Short name T578
Test name
Test status
Simulation time 28155630 ps
CPU time 1.32 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:27 PM PDT 24
Peak memory 207492 kb
Host smart-a97d5902-d4de-4e49-a346-b5f2b2f3e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223437389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.4223437389
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3977975257
Short name T594
Test name
Test status
Simulation time 701182656 ps
CPU time 2.91 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:28 PM PDT 24
Peak memory 206740 kb
Host smart-6da90585-499f-42de-9633-85911ab4fa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977975257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3977975257
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2173716569
Short name T864
Test name
Test status
Simulation time 65323196 ps
CPU time 4.09 seconds
Started Jun 21 05:40:29 PM PDT 24
Finished Jun 21 05:40:34 PM PDT 24
Peak memory 221548 kb
Host smart-c8855225-00d6-44fb-838c-8844058a7bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173716569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2173716569
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.4129384393
Short name T668
Test name
Test status
Simulation time 234649205 ps
CPU time 10.62 seconds
Started Jun 21 05:40:32 PM PDT 24
Finished Jun 21 05:40:43 PM PDT 24
Peak memory 222520 kb
Host smart-8b59a793-dec9-4ac0-974c-15e8126ffd44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129384393 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.4129384393
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3309899861
Short name T675
Test name
Test status
Simulation time 151024652 ps
CPU time 3.65 seconds
Started Jun 21 05:40:24 PM PDT 24
Finished Jun 21 05:40:29 PM PDT 24
Peak memory 218248 kb
Host smart-fce49c8c-8abe-4e74-aca6-a17668c8d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309899861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3309899861
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3001481333
Short name T533
Test name
Test status
Simulation time 327622479 ps
CPU time 3.24 seconds
Started Jun 21 05:40:29 PM PDT 24
Finished Jun 21 05:40:33 PM PDT 24
Peak memory 210140 kb
Host smart-d3c4a579-29be-4b1e-9090-298610d7ad0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001481333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3001481333
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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