Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
54224 |
1 |
|
|
T1 |
51 |
|
T2 |
55 |
|
T3 |
778 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32680 |
1 |
|
|
T1 |
51 |
|
T2 |
22 |
|
T3 |
398 |
auto[1] |
21544 |
1 |
|
|
T2 |
33 |
|
T3 |
380 |
|
T4 |
137 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
26803 |
1 |
|
|
T1 |
26 |
|
T2 |
28 |
|
T3 |
465 |
auto[1] |
27421 |
1 |
|
|
T1 |
25 |
|
T2 |
27 |
|
T3 |
313 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16133 |
1 |
|
|
T1 |
26 |
|
T2 |
11 |
|
T3 |
233 |
all_values[0] |
auto[0] |
auto[1] |
16547 |
1 |
|
|
T1 |
25 |
|
T2 |
11 |
|
T3 |
165 |
all_values[0] |
auto[1] |
auto[0] |
10670 |
1 |
|
|
T2 |
17 |
|
T3 |
232 |
|
T4 |
70 |
all_values[0] |
auto[1] |
auto[1] |
10874 |
1 |
|
|
T2 |
16 |
|
T3 |
148 |
|
T4 |
67 |