Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4659

1

T1

7

T2

13

T3

43

auto[1]

538

1

T1

4

T3

5

T4

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4659

1

T1

7

T2

13

T3

43

auto[1]

538

1

T1

4

T3

5

T4

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4663

1

T1

11

T2

13

T3

44

auto[1]

534

1

T3

4

T4

3

T22

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4663

1

T1

11

T2

13

T3

44

auto[1]

534

1

T3

4

T4

3

T22

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	402	1			T3	3		T4	4		T36	1
auto[OpGenId]	1012	1			T3	15		T4	5		T5	1
auto[OpGenSwOut]	1118	1			T3	12		T4	11		T15	2
auto[OpGenHwOut]	2593	1			T1	11		T2	13		T3	15
auto[OpDisable]	72	1			T3	3		T5	1		T16	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	402	1			T3	3		T4	4		T36	1
auto[OpGenId]	1012	1			T3	15		T4	5		T5	1
auto[OpGenSwOut]	1118	1			T3	12		T4	11		T15	2
auto[OpGenHwOut]	2593	1			T1	11		T2	13		T3	15
auto[OpDisable]	72	1			T3	3		T5	1		T16	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4653

1

T1

11

T2

10

T3

40

auto[1]

544

1

T2

3

T3

8

T4

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4653

1

T1

11

T2

10

T3

40

auto[1]

544

1

T2

3

T3

8

T4

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4933

1

T1

11

T2

13

T3

48

auto[1]

264

1

T109

12

T101

4

T149

9

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1772	1			T1	3		T2	2		T3	20
auto[1]	719	1			T1	2		T2	4		T3	6
auto[2]	624	1			T1	1		T2	1		T3	5
auto[3]	660	1			T1	3		T2	3		T3	3
auto[4]	347	1			T3	6		T4	3		T38	1
auto[5]	343	1			T1	1		T3	3		T4	2
auto[6]	376	1			T2	3		T3	3		T4	3
auto[7]	356	1			T1	1		T3	2		T4	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1422	1			T1	2		T2	3		T3	14
clear_one[1]	719	1			T1	2		T2	4		T3	6
clear_one[2]	624	1			T1	1		T2	1		T3	5
clear_one[3]	660	1			T1	3		T2	3		T3	3
clear_none	1772	1			T1	3		T2	2		T3	20

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	986	1			T1	3		T2	5		T3	8
auto[StInit]	633	1			T1	1		T2	1		T3	9
auto[StCreatorRootKey]	546	1			T1	1		T2	1		T3	6
auto[StOwnerIntKey]	499	1			T1	1		T2	1		T3	2
auto[StOwnerKey]	459	1			T1	1		T2	1		T3	3
auto[StDisabled]	1811	1			T1	4		T2	4		T3	20
auto[StInvalid]	263	1			T36	3		T38	5		T44	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	986	1			T1	3		T2	5		T3	8
auto[StInit]	633	1			T1	1		T2	1		T3	9
auto[StCreatorRootKey]	546	1			T1	1		T2	1		T3	6
auto[StOwnerIntKey]	499	1			T1	1		T2	1		T3	2
auto[StOwnerKey]	459	1			T1	1		T2	1		T3	3
auto[StDisabled]	1811	1			T1	4		T2	4		T3	20
auto[StInvalid]	263	1			T36	3		T38	5		T44	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[1] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[1] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T238	1		T239	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	159	1			T3	1		T4	1		T44	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	160	1			T3	2		T4	2		T16	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	244	1			T1	2		T2	1		T3	2
auto[0]	auto[StInit]	auto[OpAdvance]	39	1			T3	1		T22	1		T208	1
auto[0]	auto[StInit]	auto[OpGenId]	83	1			T3	3		T5	1		T15	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	94	1			T3	1		T4	1		T74	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	192	1			T2	1		T3	1		T4	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	14	1			T22	1		T240	1		T241	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	48	1			T242	1		T47	2		T64	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	49	1			T205	1		T71	1		T6	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	59	1			T3	1		T83	1		T127	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T4	1		T150	1		T75	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	23	1			T3	1		T4	1		T55	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	33	1			T3	1		T4	1		T48	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T214	1		T47	1		T130	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T243	1		T244	1		T245	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T64	1		T101	1		T246	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	27	1			T128	1		T55	1		T47	2
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	53	1			T213	1		T135	1		T119	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	25	1			T55	1		T101	1		T75	1
auto[0]	auto[StDisabled]	auto[OpGenId]	46	1			T3	1		T55	1		T47	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T55	1		T64	1		T102	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	172	1			T1	1		T3	4		T4	1
auto[0]	auto[StDisabled]	auto[OpDisable]	16	1			T3	1		T247	1		T248	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	16	1			T38	1		T50	2		T249	1
auto[0]	auto[StInvalid]	auto[OpGenId]	15	1			T89	1		T250	1		T251	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T252	1		T250	1		T253	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	29	1			T36	1		T38	1		T51	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T3	1		T16	1		T55	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T4	1		T131	1		T64	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	49	1			T1	1		T2	2		T35	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T150	3		T254	1		T8	1
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T121	1		T255	1		T256	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T195	1		T257	1		T258	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	30	1			T35	1		T126	1		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T55	1		T150	1		T48	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T3	1		T99	1		T102	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T8	1		T69	1		T76	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T213	1		T135	1		T260	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T138	1		T261	2		T262	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T4	2		T208	1		T150	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T93	1		T263	1		T70	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T1	1		T2	1		T55	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T55	1		T264	1		T85	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	20	1			T4	1		T121	1		T109	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T3	1		T65	1		T265	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T126	1		T55	1		T130	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	29	1			T4	1		T101	1		T150	1
auto[1]	auto[StDisabled]	auto[OpGenId]	42	1			T3	1		T22	1		T207	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T3	1		T4	2		T16	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T2	1		T4	2		T39	1
auto[1]	auto[StDisabled]	auto[OpDisable]	17	1			T3	1		T47	1		T64	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	10	1			T89	1		T266	1		T267	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T249	2		T90	1		T89	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T96	1		T268	1		T253	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T44	1		T249	1		T269	1
auto[2]	auto[StReset]	auto[OpGenId]	19	1			T56	1		T41	1		T112	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	25	1			T39	1		T47	2		T131	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	37	1			T55	1		T48	1		T270	2
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T221	1		T271	1		T272	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T273	1		T91	1		T92	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	7	1			T76	1		T267	1		T274	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	11	1			T213	1		T192	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T69	1		T275	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T265	1		T84	1		T258	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T138	2		T154	1		T62	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T1	1		T3	1		T39	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T47	1		T138	1		T244	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T111	1		T265	2		T154	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T276	1		T94	1		T33	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T5	1		T55	1		T71	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T139	2		T277	1		T278	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T3	1		T64	1		T63	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T55	1		T48	1		T279	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T214	1		T47	1		T48	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T3	1		T4	1		T87	1
auto[2]	auto[StDisabled]	auto[OpGenId]	36	1			T47	1		T103	1		T137	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T128	1		T242	2		T47	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T2	1		T3	2		T4	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T55	1		T47	2		T65	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T36	1		T280	1		T281	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T51	1		T86	1		T282	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T253	1		T283	1		T284	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T269	1		T285	1		T286	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T47	1		T287	1		T73	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	27	1			T55	1		T47	1		T264	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	40	1			T2	1		T213	2		T55	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T85	1		T288	1		T289	1
auto[3]	auto[StInit]	auto[OpGenId]	13	1			T211	1		T242	1		T23	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	11	1			T96	1		T91	1		T92	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	18	1			T1	1		T55	1		T99	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T290	1		-	-		-	-
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T47	1		T291	1		T69	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T3	1		T55	1		T64	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T35	1		T126	1		T55	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T198	1		T279	1		T221	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T15	1		T64	1		T240	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T292	3		T277	1		T200	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T135	1		T136	1		T270	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T120	1		T138	2		T293	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T47	1		T291	1		T294	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T100	1		T111	1		T114	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T1	1		T2	1		T131	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	33	1			T205	1		T208	1		T47	1
auto[3]	auto[StDisabled]	auto[OpGenId]	44	1			T208	1		T47	1		T48	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T3	2		T15	1		T208	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T1	1		T2	1		T35	2
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T5	1		T16	1		T47	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T50	1		T96	1		T287	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T50	1		T295	1		T86	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T38	1		T251	1		T296	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T36	1		T269	1		T268	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T55	2		T139	1		T297	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T55	1		T90	1		T96	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T55	1		T298	1		T299	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T4	1		T23	1		T289	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T3	1		T42	1		T229	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T102	1		T300	1		T24	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	7	1			T3	1		T193	1		T24	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T301	1		T302	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T48	1		T304	1		T234	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T109	1		T276	1		T85	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T4	1		T132	1		T63	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T48	1		T305	1		T306	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T8	1		T291	1		T69	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T254	1		T307	1		T114	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T109	1		T98	1		T298	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T308	1		T309	1		T310	2
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T254	1		T8	1		T229	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T311	1		T137	1		T226	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T260	1		T254	2		T312	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T87	1		T55	1		T244	2
auto[4]	auto[StDisabled]	auto[OpGenId]	29	1			T3	2		T242	1		T109	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T4	1		T205	1		T71	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T3	1		T22	1		T214	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T3	1		T76	1		T313	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T314	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T38	1		T96	1		T88	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T51	1		T90	1		T89	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T287	1		T315	2		-	-
auto[5]	auto[StReset]	auto[OpAdvance]	1	1			T316	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T317	1		T73	1		T69	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T4	1		T195	1		T69	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T3	1		T122	1		T318	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T140	1		T319	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T8	1		T199	1		T32	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	8	1			T3	1		T47	2		T23	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	10	1			T260	1		T320	1		T271	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T26	1		T157	1		T185	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T121	1		T264	1		T69	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T15	1		T55	1		T321	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T215	1		T259	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T199	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T153	1		T84	1		T63	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T4	1		T22	1		T131	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T35	1		T27	1		T323	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T3	1		T324	1		T325	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T276	1		T63	1		T326	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T63	1		T69	1		T327	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T35	1		T47	1		T132	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	14	1			T55	1		T304	1		T229	1
auto[5]	auto[StDisabled]	auto[OpGenId]	22	1			T208	1		T124	1		T103	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T55	1		T247	1		T136	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T1	1		T127	1		T207	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T74	1		T47	1		T255	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T267	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	11	1			T50	1		T89	1		T328	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T38	1		T252	1		T253	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T252	1		T329	1		T330	1
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T28	1		T328	1		T255	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T112	1		T251	1		T289	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	28	1			T2	1		T3	1		T35	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T331	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T55	1		T24	1		T69	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T55	1		T141	1		T69	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	19	1			T122	1		T332	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T299	1		T291	1		T238	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T324	1		T69	2		T200	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T3	1		T229	1		T271	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T2	1		T74	1		T130	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T141	1		T308	1		T334	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T87	1		T291	1		T70	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T304	1		T198	1		T229	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T260	1		T333	1		T322	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	11	1			T335	1		T263	1		T294	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T63	1		T69	1		T199	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T98	1		T193	1		T323	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	15	1			T149	3		T111	1		T336	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T149	2		T75	1		T93	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T3	1		T4	1		T55	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T2	1		T4	2		T55	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T198	1		T229	1		T337	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T338	1		T339	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T329	1		T340	1		T341	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T96	1		T283	1		T342	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T343	1		T267	1		T344	1
auto[7]	auto[StReset]	auto[OpGenId]	4	1			T75	1		T188	1		T190	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T25	1		T55	1		T86	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	29	1			T193	1		T345	1		T346	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T219	1		T347	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T44	1		T92	1		T70	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	2	1			T23	1		T8	1		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T25	1		T64	1		T289	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T139	1		T222	1		T348	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T3	1		T349	1		T350	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T310	5		T351	1		T352	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T4	1		T5	1		T206	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T55	1		T149	1		T237	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T83	1		T205	1		T353	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T102	1		T139	1		T309	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T126	1		T213	1		T132	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T47	1		T154	1		T354	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T149	1		T355	1		T356	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T357	1		T358	1		T359	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T242	1		T149	1		T360	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	6	1			T39	1		T288	1		T272	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T3	1		T128	1		T64	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T64	1		T100	1		T361	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T1	1		T35	2		T214	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T64	1		T362	1		T77	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T90	1		T89	1		T285	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T44	1		T328	1		T317	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T50	1		T287	1		T86	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T90	1		T250	1		T330	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1422

1

T1

2

T2

3

T3

14

clear_one[1]

auto[0]

auto[0]

auto[0]

414

1

T1

2

T2

2

T3

4

clear_one[1]

auto[0]

auto[0]

auto[1]

132

1

T2

2

T3

1

T4

2

clear_one[1]

auto[0]

auto[1]

auto[0]

128

1

T4

2

T22

1

T213

2

clear_one[1]

auto[0]

auto[1]

auto[1]

45

1

T3

1

T4

1

T208

1

clear_one[2]

auto[0]

auto[0]

auto[0]

353

1

T3

2

T36

1

T39

1

clear_one[2]

auto[0]

auto[0]

auto[1]

117

1

T2

1

T3

1

T39

1

clear_one[2]

auto[1]

auto[0]

auto[0]

108

1

T1

1

T4

2

T5

1

clear_one[2]

auto[1]

auto[0]

auto[1]

46

1

T3

2

T47

1

T136

1

clear_one[3]

auto[0]

auto[0]

auto[0]

381

1

T1

1

T2

3

T3

1

clear_one[3]

auto[0]

auto[1]

auto[0]

110

1

T213

1

T214

1

T208

2

clear_one[3]

auto[1]

auto[0]

auto[0]

135

1

T1

2

T3

1

T5

1

clear_one[3]

auto[1]

auto[1]

auto[0]

34

1

T3

1

T208

1

T47

1

clear_none

auto[0]

auto[0]

auto[0]

1261

1

T1

2

T2

2

T3

15

clear_none

auto[0]

auto[0]

auto[1]

131

1

T3

2

T128

1

T55

1

clear_none

auto[0]

auto[1]

auto[0]

137

1

T3

2

T213

1

T214

1

clear_none

auto[0]

auto[1]

auto[1]

28

1

T101

2

T254

1

T8

1

clear_none

auto[1]

auto[0]

auto[0]

137

1

T1

1

T4

1

T83

1

clear_none

auto[1]

auto[0]

auto[1]

26

1

T3

1

T4

1

T55

1

clear_none

auto[1]

auto[1]

auto[0]

33

1

T22

1

T64

1

T8

1

clear_none

auto[1]

auto[1]

auto[1]

19

1

T47

2

T355

1

T273

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1351	1			T1	2		T2	3		T3	14
clear_all	auto[1]	71	1			T109	7		T149	6		T254	2
clear_one[1]	auto[0]	655	1			T1	2		T2	4		T3	6
clear_one[1]	auto[1]	64	1			T109	4		T101	1		T150	6
clear_one[2]	auto[0]	592	1			T1	1		T2	1		T3	5
clear_one[2]	auto[1]	32	1			T149	3		T265	2		T138	2
clear_one[3]	auto[0]	634	1			T1	3		T2	3		T3	3
clear_one[3]	auto[1]	26	1			T150	1		T151	4		T254	1
clear_none	auto[0]	1701	1			T1	3		T2	2		T3	20
clear_none	auto[1]	71	1			T109	1		T101	3		T150	1