Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10667

1

T1

12

T2

17

T3

123

auto[Attestation]

7263

1

T1

5

T2

2

T3

99

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2604	1			T3	32		T4	36		T5	1
auto[Aes]	3245	1			T1	17		T3	40		T4	29
auto[Kmac]	3245	1			T3	34		T4	27		T5	2
auto[Otbn]	3226	1			T2	19		T3	29		T4	26

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7214	1			T1	8		T2	8		T3	75
auto[OpGenId]	5610	1			T3	87		T4	41		T5	6
auto[OpGenSwOut]	5470	1			T3	59		T4	52		T5	5
auto[OpGenHwOut]	6850	1			T1	17		T2	19		T3	76
auto[OpDisable]	135	1			T3	3		T4	1		T5	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10107

1

T1

8

T2

8

T3

117

auto[OpDoneFail]

15172

1

T1

17

T2

19

T3

183

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6192	1			T1	10		T2	12		T3	55
auto[StInit]	3609	1			T1	2		T2	2		T3	51
auto[StCreatorRootKey]	2982	1			T1	2		T2	2		T3	32
auto[StOwnerIntKey]	2689	1			T1	2		T2	2		T3	32
auto[StOwnerKey]	2341	1			T1	2		T2	2		T3	28
auto[StDisabled]	7466	1			T1	7		T2	7		T3	102

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	288	1			T3	2		T4	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T4	1		T55	2		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T3	1		T4	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T3	3		T87	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T55	2		T101	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	228	1			T3	3		T4	3		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	291	1			T3	3		T4	5		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	100	1			T4	1		T55	2		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	73	1			T3	2		T4	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	70	1			T5	1		T207	1		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	49	1			T4	3		T131	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	179	1			T3	4		T4	2		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	305	1			T3	3		T4	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T54	1		T205	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	68	1			T55	1		T208	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T4	1		T22	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T3	1		T4	2		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	237	1			T3	7		T4	3		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	328	1			T3	1		T4	3		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	81	1			T3	1		T74	1		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T3	1		T15	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T3	2		T4	3		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	48	1			T3	1		T55	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	198	1			T3	1		T4	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T4	2		T55	3		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	106	1			T4	1		T18	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T3	2		T127	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T55	1		T66	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	43	1			T37	1		T47	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	197	1			T3	3		T4	4		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T3	1		T55	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	87	1			T3	2		T209	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	76	1			T3	2		T211	1		T64	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T212	1		T47	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	66	1			T3	1		T210	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	223	1			T3	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T4	1		T55	3		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	84	1			T3	2		T37	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T4	1		T22	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T4	1		T87	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T127	1		T128	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	197	1			T3	2		T4	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T4	1		T55	5		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	88	1			T3	2		T4	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	64	1			T3	1		T5	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T3	1		T16	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T3	1		T37	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	199	1			T3	1		T4	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	280	1			T3	1		T4	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T3	2		T36	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	69	1			T3	2		T4	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	81	1			T3	1		T4	1		T128	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T3	1		T4	3		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	167	1			T3	3		T4	5		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	503	1			T1	9		T3	5		T4	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	101	1			T3	2		T16	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	106	1			T1	1		T4	3		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	101	1			T3	1		T39	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	77	1			T1	1		T35	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	280	1			T1	1		T3	2		T4	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	439	1			T3	3		T4	5		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T3	1		T213	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T211	1		T215	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T3	2		T22	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	89	1			T4	2		T208	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	265	1			T3	4		T4	5		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	448	1			T2	11		T3	4		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	107	1			T2	1		T3	2		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T2	1		T3	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T128	1		T55	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T2	1		T3	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	280	1			T2	3		T3	3		T4	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T3	3		T4	2		T55	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T3	2		T4	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	74	1			T4	2		T55	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T3	1		T4	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T3	1		T15	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	153	1			T3	1		T4	3		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	55	1			T3	2		T4	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	115	1			T1	1		T3	3		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	112	1			T4	1		T22	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	76	1			T1	1		T3	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	97	1			T3	2		T4	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	273	1			T1	3		T3	5		T35	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	53	1			T3	2		T55	3		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	109	1			T3	1		T83	1		T55	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T4	1		T39	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T3	2		T22	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	88	1			T3	1		T127	2		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	289	1			T3	3		T4	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	54	1			T3	1		T4	1		T55	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	148	1			T3	1		T4	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T5	1		T16	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T2	1		T4	2		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T71	1		T47	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	255	1			T2	1		T3	3		T4	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T3	4		T4	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	617	1			T3	5		T4	6		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T3	2		T4	4		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	579	1			T3	7		T4	8		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	185	1			T3	1		T4	3		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	671	1			T3	10		T4	4		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	172	1			T3	3		T4	3		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	624	1			T3	4		T4	5		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	173	1			T3	2		T37	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	383	1			T3	3		T4	7		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	191	1			T3	3		T210	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	396	1			T3	5		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T4	2		T22	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	365	1			T3	4		T4	4		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	182	1			T3	3		T5	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	386	1			T3	3		T4	4		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	190	1			T3	4		T4	5		T128	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	555	1			T3	6		T4	6		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	270	1			T1	2		T3	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	898	1			T1	10		T3	9		T4	8
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T3	2		T4	2		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	832	1			T3	8		T4	10		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	268	1			T2	2		T3	2		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	845	1			T2	15		T3	9		T4	7
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T3	2		T4	5		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	320	1			T3	6		T4	6		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	271	1			T1	1		T3	2		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	457	1			T1	4		T3	11		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T3	2		T4	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	473	1			T3	7		T4	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T2	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T2	1		T3	5		T4	6