Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30981

1

T1

29

T2

31

T3

351

auto[1]

271

1

T109

11

T101

3

T149

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30988	1			T1	29		T2	31		T3	351
auto[134217728:268435455]	7	1			T101	1		T151	1		T137	1
auto[268435456:402653183]	5	1			T310	1		T293	1		T389	2
auto[402653184:536870911]	7	1			T254	1		T357	1		T390	1
auto[536870912:671088639]	10	1			T151	1		T137	1		T261	1
auto[671088640:805306367]	8	1			T149	1		T138	1		T261	1
auto[805306368:939524095]	3	1			T149	1		T265	1		T391	1
auto[939524096:1073741823]	8	1			T109	1		T151	1		T141	1
auto[1073741824:1207959551]	11	1			T151	2		T378	1		T391	1
auto[1207959552:1342177279]	8	1			T109	1		T150	1		T139	1
auto[1342177280:1476395007]	8	1			T109	1		T139	1		T261	1
auto[1476395008:1610612735]	7	1			T151	1		T319	1		T392	1
auto[1610612736:1744830463]	8	1			T139	1		T244	1		T379	1
auto[1744830464:1879048191]	10	1			T150	1		T357	2		T292	1
auto[1879048192:2013265919]	7	1			T150	1		T151	1		T139	1
auto[2013265920:2147483647]	6	1			T109	1		T151	1		T292	1
auto[2147483648:2281701375]	12	1			T101	1		T292	1		T390	1
auto[2281701376:2415919103]	11	1			T109	1		T151	1		T139	2
auto[2415919104:2550136831]	4	1			T357	1		T292	1		T272	1
auto[2550136832:2684354559]	9	1			T151	2		T139	1		T310	1
auto[2684354560:2818572287]	17	1			T149	1		T265	2		T141	1
auto[2818572288:2952790015]	6	1			T150	1		T244	1		T288	1
auto[2952790016:3087007743]	8	1			T149	1		T151	2		T393	1
auto[3087007744:3221225471]	9	1			T377	1		T319	1		T394	1
auto[3221225472:3355443199]	5	1			T151	1		T357	1		T244	1
auto[3355443200:3489660927]	8	1			T109	1		T150	1		T151	1
auto[3489660928:3623878655]	7	1			T261	1		T392	1		T379	1
auto[3623878656:3758096383]	8	1			T109	1		T149	1		T151	1
auto[3758096384:3892314111]	10	1			T109	1		T149	1		T151	1
auto[3892314112:4026531839]	12	1			T109	1		T149	1		T150	1
auto[4026531840:4160749567]	7	1			T149	1		T150	1		T139	1
auto[4160749568:4294967295]	18	1			T109	2		T101	1		T149	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30981	1			T1	29		T2	31		T3	351
auto[0:134217727]	auto[1]	7	1			T150	1		T151	1		T319	2
auto[134217728:268435455]	auto[1]	7	1			T101	1		T151	1		T137	1
auto[268435456:402653183]	auto[1]	5	1			T310	1		T293	1		T389	2
auto[402653184:536870911]	auto[1]	7	1			T254	1		T357	1		T390	1
auto[536870912:671088639]	auto[1]	10	1			T151	1		T137	1		T261	1
auto[671088640:805306367]	auto[1]	8	1			T149	1		T138	1		T261	1
auto[805306368:939524095]	auto[1]	3	1			T149	1		T265	1		T391	1
auto[939524096:1073741823]	auto[1]	8	1			T109	1		T151	1		T141	1
auto[1073741824:1207959551]	auto[1]	11	1			T151	2		T378	1		T391	1
auto[1207959552:1342177279]	auto[1]	8	1			T109	1		T150	1		T139	1
auto[1342177280:1476395007]	auto[1]	8	1			T109	1		T139	1		T261	1
auto[1476395008:1610612735]	auto[1]	7	1			T151	1		T319	1		T392	1
auto[1610612736:1744830463]	auto[1]	8	1			T139	1		T244	1		T379	1
auto[1744830464:1879048191]	auto[1]	10	1			T150	1		T357	2		T292	1
auto[1879048192:2013265919]	auto[1]	7	1			T150	1		T151	1		T139	1
auto[2013265920:2147483647]	auto[1]	6	1			T109	1		T151	1		T292	1
auto[2147483648:2281701375]	auto[1]	12	1			T101	1		T292	1		T390	1
auto[2281701376:2415919103]	auto[1]	11	1			T109	1		T151	1		T139	2
auto[2415919104:2550136831]	auto[1]	4	1			T357	1		T292	1		T272	1
auto[2550136832:2684354559]	auto[1]	9	1			T151	2		T139	1		T310	1
auto[2684354560:2818572287]	auto[1]	17	1			T149	1		T265	2		T141	1
auto[2818572288:2952790015]	auto[1]	6	1			T150	1		T244	1		T288	1
auto[2952790016:3087007743]	auto[1]	8	1			T149	1		T151	2		T393	1
auto[3087007744:3221225471]	auto[1]	9	1			T377	1		T319	1		T394	1
auto[3221225472:3355443199]	auto[1]	5	1			T151	1		T357	1		T244	1
auto[3355443200:3489660927]	auto[1]	8	1			T109	1		T150	1		T151	1
auto[3489660928:3623878655]	auto[1]	7	1			T261	1		T392	1		T379	1
auto[3623878656:3758096383]	auto[1]	8	1			T109	1		T149	1		T151	1
auto[3758096384:3892314111]	auto[1]	10	1			T109	1		T149	1		T151	1
auto[3892314112:4026531839]	auto[1]	12	1			T109	1		T149	1		T150	1
auto[4026531840:4160749567]	auto[1]	7	1			T149	1		T150	1		T139	1
auto[4160749568:4294967295]	auto[1]	18	1			T109	2		T101	1		T149	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1601

1

T3

34

T4

17

T5

1

auto[1]

1657

1

T3

30

T4

13

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T3	1		T4	1		T44	1
auto[134217728:268435455]	99	1			T3	3		T36	1		T127	1
auto[268435456:402653183]	81	1			T4	1		T127	1		T55	1
auto[402653184:536870911]	110	1			T3	3		T4	1		T39	1
auto[536870912:671088639]	81	1			T3	1		T4	1		T55	2
auto[671088640:805306367]	102	1			T3	2		T4	1		T38	2
auto[805306368:939524095]	121	1			T3	4		T4	2		T22	1
auto[939524096:1073741823]	99	1			T4	1		T5	1		T208	1
auto[1073741824:1207959551]	104	1			T3	4		T4	1		T55	2
auto[1207959552:1342177279]	114	1			T3	3		T4	2		T36	1
auto[1342177280:1476395007]	110	1			T3	3		T4	2		T16	1
auto[1476395008:1610612735]	103	1			T3	1		T39	1		T22	1
auto[1610612736:1744830463]	109	1			T3	3		T25	1		T44	1
auto[1744830464:1879048191]	105	1			T3	4		T44	1		T127	1
auto[1879048192:2013265919]	100	1			T3	1		T4	1		T55	2
auto[2013265920:2147483647]	78	1			T4	1		T55	1		T71	1
auto[2147483648:2281701375]	93	1			T3	3		T25	1		T55	1
auto[2281701376:2415919103]	102	1			T3	1		T4	1		T16	1
auto[2415919104:2550136831]	106	1			T3	2		T55	2		T47	4
auto[2550136832:2684354559]	100	1			T3	3		T4	1		T55	2
auto[2684354560:2818572287]	119	1			T3	1		T4	2		T55	1
auto[2818572288:2952790015]	117	1			T3	2		T4	3		T36	1
auto[2952790016:3087007743]	91	1			T16	1		T211	1		T55	1
auto[3087007744:3221225471]	97	1			T3	5		T4	2		T39	1
auto[3221225472:3355443199]	114	1			T3	1		T4	2		T50	1
auto[3355443200:3489660927]	89	1			T3	2		T25	1		T55	2
auto[3489660928:3623878655]	114	1			T3	1		T44	1		T55	2
auto[3623878656:3758096383]	79	1			T3	1		T4	1		T5	1
auto[3758096384:3892314111]	104	1			T3	2		T4	2		T54	1
auto[3892314112:4026531839]	100	1			T3	2		T4	1		T16	1
auto[4026531840:4160749567]	114	1			T3	3		T39	1		T38	1
auto[4160749568:4294967295]	112	1			T3	2		T36	1		T38	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T4	1		T55	2		T149	1
auto[0:134217727]	auto[1]	43	1			T3	1		T44	1		T55	1
auto[134217728:268435455]	auto[0]	53	1			T3	2		T36	1		T55	1
auto[134217728:268435455]	auto[1]	46	1			T3	1		T127	1		T55	1
auto[268435456:402653183]	auto[0]	38	1			T4	1		T55	1		T109	1
auto[268435456:402653183]	auto[1]	43	1			T127	1		T102	1		T48	1
auto[402653184:536870911]	auto[0]	48	1			T3	1		T4	1		T39	1
auto[402653184:536870911]	auto[1]	62	1			T3	2		T205	1		T250	1
auto[536870912:671088639]	auto[0]	38	1			T3	1		T4	1		T55	1
auto[536870912:671088639]	auto[1]	43	1			T55	1		T47	1		T90	1
auto[671088640:805306367]	auto[0]	50	1			T4	1		T38	2		T55	1
auto[671088640:805306367]	auto[1]	52	1			T3	2		T22	1		T87	1
auto[805306368:939524095]	auto[0]	58	1			T3	3		T22	1		T44	1
auto[805306368:939524095]	auto[1]	63	1			T3	1		T4	2		T41	1
auto[939524096:1073741823]	auto[0]	48	1			T4	1		T5	1		T50	1
auto[939524096:1073741823]	auto[1]	51	1			T208	1		T47	1		T131	1
auto[1073741824:1207959551]	auto[0]	55	1			T3	3		T55	2		T208	1
auto[1073741824:1207959551]	auto[1]	49	1			T3	1		T4	1		T215	1
auto[1207959552:1342177279]	auto[0]	59	1			T3	2		T36	1		T38	1
auto[1207959552:1342177279]	auto[1]	55	1			T3	1		T4	2		T208	1
auto[1342177280:1476395007]	auto[0]	62	1			T3	1		T4	1		T16	1
auto[1342177280:1476395007]	auto[1]	48	1			T3	2		T4	1		T128	1
auto[1476395008:1610612735]	auto[0]	55	1			T3	1		T39	1		T55	1
auto[1476395008:1610612735]	auto[1]	48	1			T22	1		T55	1		T47	1
auto[1610612736:1744830463]	auto[0]	54	1			T3	2		T44	1		T211	1
auto[1610612736:1744830463]	auto[1]	55	1			T3	1		T25	1		T55	3
auto[1744830464:1879048191]	auto[0]	50	1			T3	3		T47	1		T89	1
auto[1744830464:1879048191]	auto[1]	55	1			T3	1		T44	1		T127	1
auto[1879048192:2013265919]	auto[0]	43	1			T3	1		T4	1		T55	1
auto[1879048192:2013265919]	auto[1]	57	1			T55	1		T208	1		T47	2
auto[2013265920:2147483647]	auto[0]	25	1			T71	1		T23	1		T295	1
auto[2013265920:2147483647]	auto[1]	53	1			T4	1		T55	1		T121	1
auto[2147483648:2281701375]	auto[0]	44	1			T3	2		T301	1		T57	1
auto[2147483648:2281701375]	auto[1]	49	1			T3	1		T25	1		T55	1
auto[2281701376:2415919103]	auto[0]	52	1			T4	1		T16	1		T39	1
auto[2281701376:2415919103]	auto[1]	50	1			T3	1		T47	1		T121	1
auto[2415919104:2550136831]	auto[0]	50	1			T3	1		T55	2		T47	2
auto[2415919104:2550136831]	auto[1]	56	1			T3	1		T47	2		T64	2
auto[2550136832:2684354559]	auto[0]	48	1			T3	1		T4	1		T55	1
auto[2550136832:2684354559]	auto[1]	52	1			T3	2		T55	1		T111	1
auto[2684354560:2818572287]	auto[0]	50	1			T4	1		T47	1		T102	1
auto[2684354560:2818572287]	auto[1]	69	1			T3	1		T4	1		T55	1
auto[2818572288:2952790015]	auto[0]	63	1			T3	1		T4	3		T36	1
auto[2818572288:2952790015]	auto[1]	54	1			T3	1		T55	2		T131	1
auto[2952790016:3087007743]	auto[0]	51	1			T16	1		T211	1		T215	1
auto[2952790016:3087007743]	auto[1]	40	1			T55	1		T47	1		T27	1
auto[3087007744:3221225471]	auto[0]	57	1			T3	3		T4	1		T39	1
auto[3087007744:3221225471]	auto[1]	40	1			T3	2		T4	1		T55	1
auto[3221225472:3355443199]	auto[0]	59	1			T3	1		T4	1		T50	1
auto[3221225472:3355443199]	auto[1]	55	1			T4	1		T47	2		T131	1
auto[3355443200:3489660927]	auto[0]	46	1			T55	1		T50	1		T47	1
auto[3355443200:3489660927]	auto[1]	43	1			T3	2		T25	1		T55	1
auto[3489660928:3623878655]	auto[0]	54	1			T44	1		T47	1		T249	1
auto[3489660928:3623878655]	auto[1]	60	1			T3	1		T55	2		T121	1
auto[3623878656:3758096383]	auto[0]	35	1			T3	1		T208	1		T50	1
auto[3623878656:3758096383]	auto[1]	44	1			T4	1		T5	1		T22	1
auto[3758096384:3892314111]	auto[0]	50	1			T3	1		T4	1		T44	1
auto[3758096384:3892314111]	auto[1]	54	1			T3	1		T4	1		T54	1
auto[3892314112:4026531839]	auto[0]	43	1			T3	1		T16	1		T36	1
auto[3892314112:4026531839]	auto[1]	57	1			T3	1		T4	1		T55	1
auto[4026531840:4160749567]	auto[0]	56	1			T3	1		T39	1		T38	1
auto[4026531840:4160749567]	auto[1]	58	1			T3	2		T208	1		T47	2
auto[4160749568:4294967295]	auto[0]	59	1			T3	1		T36	1		T38	1
auto[4160749568:4294967295]	auto[1]	53	1			T3	1		T47	1		T103	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1596

1

T3

34

T4

16

T5

1

auto[1]

1662

1

T3

30

T4

14

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T4	2		T22	1		T55	1
auto[134217728:268435455]	97	1			T3	1		T16	3		T39	1
auto[268435456:402653183]	107	1			T3	1		T4	1		T44	1
auto[402653184:536870911]	100	1			T3	2		T47	3		T269	1
auto[536870912:671088639]	99	1			T3	1		T4	3		T127	1
auto[671088640:805306367]	111	1			T3	2		T4	1		T71	1
auto[805306368:939524095]	108	1			T3	4		T4	2		T5	1
auto[939524096:1073741823]	103	1			T3	4		T38	1		T127	1
auto[1073741824:1207959551]	101	1			T3	1		T87	1		T55	1
auto[1207959552:1342177279]	96	1			T3	2		T55	1		T208	1
auto[1342177280:1476395007]	101	1			T4	1		T36	1		T22	1
auto[1476395008:1610612735]	104	1			T3	4		T4	1		T44	1
auto[1610612736:1744830463]	106	1			T3	1		T4	1		T39	1
auto[1744830464:1879048191]	92	1			T3	2		T4	1		T44	1
auto[1879048192:2013265919]	95	1			T3	4		T38	1		T54	1
auto[2013265920:2147483647]	79	1			T3	2		T206	1		T55	1
auto[2147483648:2281701375]	104	1			T3	2		T4	2		T44	1
auto[2281701376:2415919103]	118	1			T3	6		T4	2		T25	1
auto[2415919104:2550136831]	109	1			T3	2		T39	1		T22	1
auto[2550136832:2684354559]	108	1			T3	1		T4	2		T36	2
auto[2684354560:2818572287]	99	1			T3	1		T25	1		T208	1
auto[2818572288:2952790015]	104	1			T3	1		T4	3		T55	3
auto[2952790016:3087007743]	107	1			T3	2		T4	1		T128	1
auto[3087007744:3221225471]	116	1			T3	6		T4	1		T25	1
auto[3221225472:3355443199]	108	1			T3	3		T16	1		T55	1
auto[3355443200:3489660927]	98	1			T3	2		T4	1		T39	1
auto[3489660928:3623878655]	100	1			T3	1		T4	1		T87	1
auto[3623878656:3758096383]	112	1			T3	1		T4	3		T5	1
auto[3758096384:3892314111]	94	1			T3	1		T4	1		T36	2
auto[3892314112:4026531839]	93	1			T3	1		T38	1		T127	1
auto[4026531840:4160749567]	101	1			T3	2		T55	3		T47	3
auto[4160749568:4294967295]	95	1			T3	1		T87	1		T64	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T4	1		T55	1		T47	2
auto[0:134217727]	auto[1]	53	1			T4	1		T22	1		T47	1
auto[134217728:268435455]	auto[0]	51	1			T3	1		T16	3		T39	1
auto[134217728:268435455]	auto[1]	46	1			T55	2		T47	1		T28	1
auto[268435456:402653183]	auto[0]	65	1			T44	1		T55	1		T47	1
auto[268435456:402653183]	auto[1]	42	1			T3	1		T4	1		T205	1
auto[402653184:536870911]	auto[0]	45	1			T3	1		T47	3		T269	1
auto[402653184:536870911]	auto[1]	55	1			T3	1		T102	1		T150	2
auto[536870912:671088639]	auto[0]	48	1			T3	1		T4	3		T55	1
auto[536870912:671088639]	auto[1]	51	1			T127	1		T64	1		T102	1
auto[671088640:805306367]	auto[0]	51	1			T3	1		T4	1		T71	1
auto[671088640:805306367]	auto[1]	60	1			T3	1		T47	2		T136	1
auto[805306368:939524095]	auto[0]	59	1			T3	3		T4	1		T55	2
auto[805306368:939524095]	auto[1]	49	1			T3	1		T4	1		T5	1
auto[939524096:1073741823]	auto[0]	42	1			T3	1		T38	1		T47	1
auto[939524096:1073741823]	auto[1]	61	1			T3	3		T127	1		T55	1
auto[1073741824:1207959551]	auto[0]	49	1			T3	1		T55	1		T47	2
auto[1073741824:1207959551]	auto[1]	52	1			T87	1		T56	1		T215	1
auto[1207959552:1342177279]	auto[0]	43	1			T3	1		T269	1		T72	1
auto[1207959552:1342177279]	auto[1]	53	1			T3	1		T55	1		T208	1
auto[1342177280:1476395007]	auto[0]	43	1			T36	1		T44	1		T47	1
auto[1342177280:1476395007]	auto[1]	58	1			T4	1		T22	1		T44	1
auto[1476395008:1610612735]	auto[0]	48	1			T3	2		T44	1		T55	1
auto[1476395008:1610612735]	auto[1]	56	1			T3	2		T4	1		T55	3
auto[1610612736:1744830463]	auto[0]	53	1			T4	1		T39	1		T55	1
auto[1610612736:1744830463]	auto[1]	53	1			T3	1		T215	1		T47	1
auto[1744830464:1879048191]	auto[0]	51	1			T3	2		T208	1		T47	2
auto[1744830464:1879048191]	auto[1]	41	1			T4	1		T44	1		T47	2
auto[1879048192:2013265919]	auto[0]	56	1			T3	2		T38	1		T47	1
auto[1879048192:2013265919]	auto[1]	39	1			T3	2		T54	1		T47	2
auto[2013265920:2147483647]	auto[0]	33	1			T206	1		T55	1		T71	1
auto[2013265920:2147483647]	auto[1]	46	1			T3	2		T208	1		T56	1
auto[2147483648:2281701375]	auto[0]	54	1			T3	1		T4	2		T44	1
auto[2147483648:2281701375]	auto[1]	50	1			T3	1		T215	1		T47	2
auto[2281701376:2415919103]	auto[0]	56	1			T3	3		T4	1		T38	1
auto[2281701376:2415919103]	auto[1]	62	1			T3	3		T4	1		T25	1
auto[2415919104:2550136831]	auto[0]	53	1			T3	1		T39	1		T211	1
auto[2415919104:2550136831]	auto[1]	56	1			T3	1		T22	1		T55	1
auto[2550136832:2684354559]	auto[0]	55	1			T3	1		T4	1		T36	2
auto[2550136832:2684354559]	auto[1]	53	1			T4	1		T47	2		T121	1
auto[2684354560:2818572287]	auto[0]	50	1			T25	1		T208	1		T136	1
auto[2684354560:2818572287]	auto[1]	49	1			T3	1		T47	1		T64	1
auto[2818572288:2952790015]	auto[0]	55	1			T4	3		T55	2		T96	1
auto[2818572288:2952790015]	auto[1]	49	1			T3	1		T55	1		T47	1
auto[2952790016:3087007743]	auto[0]	51	1			T3	1		T55	1		T47	3
auto[2952790016:3087007743]	auto[1]	56	1			T3	1		T4	1		T128	1
auto[3087007744:3221225471]	auto[0]	54	1			T3	3		T205	1		T47	3
auto[3087007744:3221225471]	auto[1]	62	1			T3	3		T4	1		T25	1
auto[3221225472:3355443199]	auto[0]	46	1			T3	2		T16	1		T50	1
auto[3221225472:3355443199]	auto[1]	62	1			T3	1		T55	1		T208	1
auto[3355443200:3489660927]	auto[0]	48	1			T3	2		T4	1		T39	1
auto[3355443200:3489660927]	auto[1]	50	1			T55	1		T47	1		T131	2
auto[3489660928:3623878655]	auto[0]	48	1			T3	1		T55	1		T23	1
auto[3489660928:3623878655]	auto[1]	52	1			T4	1		T87	1		T55	2
auto[3623878656:3758096383]	auto[0]	49	1			T4	1		T5	1		T47	3
auto[3623878656:3758096383]	auto[1]	63	1			T3	1		T4	2		T55	3
auto[3758096384:3892314111]	auto[0]	53	1			T3	1		T36	2		T39	2
auto[3758096384:3892314111]	auto[1]	41	1			T4	1		T120	1		T48	1
auto[3892314112:4026531839]	auto[0]	46	1			T38	1		T211	1		T208	2
auto[3892314112:4026531839]	auto[1]	47	1			T3	1		T127	1		T55	1
auto[4026531840:4160749567]	auto[0]	53	1			T3	2		T55	1		T47	3
auto[4026531840:4160749567]	auto[1]	48	1			T55	2		T88	1		T240	1
auto[4160749568:4294967295]	auto[0]	48	1			T87	1		T64	1		T120	1
auto[4160749568:4294967295]	auto[1]	47	1			T3	1		T249	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1568

1

T3

34

T4

17

T5

1

auto[1]

1690

1

T3

30

T4

13

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T3	1		T4	2		T87	1
auto[134217728:268435455]	105	1			T3	2		T4	1		T127	1
auto[268435456:402653183]	117	1			T3	1		T36	2		T38	1
auto[402653184:536870911]	106	1			T3	3		T39	1		T44	2
auto[536870912:671088639]	107	1			T3	1		T4	1		T55	4
auto[671088640:805306367]	105	1			T3	2		T22	1		T44	1
auto[805306368:939524095]	104	1			T3	2		T4	3		T55	1
auto[939524096:1073741823]	86	1			T3	3		T22	1		T211	1
auto[1073741824:1207959551]	99	1			T3	4		T4	3		T38	1
auto[1207959552:1342177279]	77	1			T4	2		T36	1		T47	2
auto[1342177280:1476395007]	98	1			T3	3		T4	1		T38	1
auto[1476395008:1610612735]	115	1			T4	1		T25	1		T55	2
auto[1610612736:1744830463]	108	1			T3	1		T4	1		T39	1
auto[1744830464:1879048191]	98	1			T3	2		T4	1		T208	1
auto[1879048192:2013265919]	93	1			T3	3		T4	2		T39	1
auto[2013265920:2147483647]	105	1			T3	1		T4	1		T5	1
auto[2147483648:2281701375]	131	1			T3	1		T4	1		T16	1
auto[2281701376:2415919103]	97	1			T3	3		T4	1		T47	3
auto[2415919104:2550136831]	95	1			T3	5		T16	1		T25	1
auto[2550136832:2684354559]	96	1			T3	3		T4	1		T36	1
auto[2684354560:2818572287]	104	1			T3	2		T55	1		T47	5
auto[2818572288:2952790015]	103	1			T3	1		T5	1		T25	1
auto[2952790016:3087007743]	97	1			T3	3		T4	2		T208	1
auto[3087007744:3221225471]	95	1			T3	2		T4	3		T47	2
auto[3221225472:3355443199]	103	1			T3	2		T4	1		T16	1
auto[3355443200:3489660927]	117	1			T3	5		T4	1		T36	1
auto[3489660928:3623878655]	85	1			T38	1		T44	1		T55	3
auto[3623878656:3758096383]	117	1			T3	2		T22	1		T55	1
auto[3758096384:3892314111]	97	1			T3	2		T16	1		T39	1
auto[3892314112:4026531839]	95	1			T44	1		T55	1		T208	1
auto[4026531840:4160749567]	101	1			T3	2		T55	2		T208	1
auto[4160749568:4294967295]	104	1			T3	2		T4	1		T87	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T4	1		T87	1		T208	1
auto[0:134217727]	auto[1]	50	1			T3	1		T4	1		T55	1
auto[134217728:268435455]	auto[0]	44	1			T3	1		T71	1		T131	1
auto[134217728:268435455]	auto[1]	61	1			T3	1		T4	1		T127	1
auto[268435456:402653183]	auto[0]	66	1			T3	1		T36	2		T38	1
auto[268435456:402653183]	auto[1]	51	1			T54	1		T55	1		T47	1
auto[402653184:536870911]	auto[0]	48	1			T3	2		T39	1		T44	2
auto[402653184:536870911]	auto[1]	58	1			T3	1		T87	1		T55	2
auto[536870912:671088639]	auto[0]	59	1			T4	1		T55	2		T47	1
auto[536870912:671088639]	auto[1]	48	1			T3	1		T55	2		T47	2
auto[671088640:805306367]	auto[0]	46	1			T3	1		T55	2		T208	1
auto[671088640:805306367]	auto[1]	59	1			T3	1		T22	1		T44	1
auto[805306368:939524095]	auto[0]	45	1			T3	1		T4	1		T55	1
auto[805306368:939524095]	auto[1]	59	1			T3	1		T4	2		T56	1
auto[939524096:1073741823]	auto[0]	34	1			T3	2		T211	1		T55	2
auto[939524096:1073741823]	auto[1]	52	1			T3	1		T22	1		T87	1
auto[1073741824:1207959551]	auto[0]	52	1			T3	2		T4	2		T38	1
auto[1073741824:1207959551]	auto[1]	47	1			T3	2		T4	1		T47	1
auto[1207959552:1342177279]	auto[0]	38	1			T4	2		T36	1		T47	1
auto[1207959552:1342177279]	auto[1]	39	1			T47	1		T131	1		T64	1
auto[1342177280:1476395007]	auto[0]	54	1			T3	2		T4	1		T38	1
auto[1342177280:1476395007]	auto[1]	44	1			T3	1		T55	1		T47	1
auto[1476395008:1610612735]	auto[0]	47	1			T50	1		T47	4		T64	1
auto[1476395008:1610612735]	auto[1]	68	1			T4	1		T25	1		T55	2
auto[1610612736:1744830463]	auto[0]	52	1			T3	1		T4	1		T39	1
auto[1610612736:1744830463]	auto[1]	56	1			T55	2		T215	1		T64	1
auto[1744830464:1879048191]	auto[0]	56	1			T3	1		T4	1		T47	1
auto[1744830464:1879048191]	auto[1]	42	1			T3	1		T208	1		T47	1
auto[1879048192:2013265919]	auto[0]	44	1			T3	2		T4	1		T47	1
auto[1879048192:2013265919]	auto[1]	49	1			T3	1		T4	1		T39	1
auto[2013265920:2147483647]	auto[0]	53	1			T3	1		T5	1		T55	2
auto[2013265920:2147483647]	auto[1]	52	1			T4	1		T127	1		T55	1
auto[2147483648:2281701375]	auto[0]	56	1			T16	1		T211	1		T136	1
auto[2147483648:2281701375]	auto[1]	75	1			T3	1		T4	1		T55	1
auto[2281701376:2415919103]	auto[0]	50	1			T3	3		T4	1		T47	1
auto[2281701376:2415919103]	auto[1]	47	1			T47	2		T120	1		T89	1
auto[2415919104:2550136831]	auto[0]	37	1			T3	2		T16	1		T55	1
auto[2415919104:2550136831]	auto[1]	58	1			T3	3		T25	1		T128	1
auto[2550136832:2684354559]	auto[0]	44	1			T3	2		T4	1		T36	1
auto[2550136832:2684354559]	auto[1]	52	1			T3	1		T47	1		T28	1
auto[2684354560:2818572287]	auto[0]	54	1			T55	1		T47	4		T133	1
auto[2684354560:2818572287]	auto[1]	50	1			T3	2		T47	1		T26	1
auto[2818572288:2952790015]	auto[0]	52	1			T39	1		T55	2		T71	1
auto[2818572288:2952790015]	auto[1]	51	1			T3	1		T5	1		T25	1
auto[2952790016:3087007743]	auto[0]	45	1			T3	1		T71	1		T47	1
auto[2952790016:3087007743]	auto[1]	52	1			T3	2		T4	2		T208	1
auto[3087007744:3221225471]	auto[0]	48	1			T3	2		T4	1		T47	1
auto[3087007744:3221225471]	auto[1]	47	1			T4	2		T47	1		T136	1
auto[3221225472:3355443199]	auto[0]	53	1			T3	1		T4	1		T16	1
auto[3221225472:3355443199]	auto[1]	50	1			T3	1		T22	1		T206	1
auto[3355443200:3489660927]	auto[0]	57	1			T3	3		T4	1		T36	1
auto[3355443200:3489660927]	auto[1]	60	1			T3	2		T247	1		T47	5
auto[3489660928:3623878655]	auto[0]	33	1			T38	1		T55	2		T249	1
auto[3489660928:3623878655]	auto[1]	52	1			T44	1		T55	1		T47	1
auto[3623878656:3758096383]	auto[0]	49	1			T3	2		T22	1		T208	1
auto[3623878656:3758096383]	auto[1]	68	1			T55	1		T208	1		T47	2
auto[3758096384:3892314111]	auto[0]	50	1			T3	1		T16	1		T39	1
auto[3758096384:3892314111]	auto[1]	47	1			T3	1		T111	1		T395	1
auto[3892314112:4026531839]	auto[0]	49	1			T44	1		T50	1		T47	2
auto[3892314112:4026531839]	auto[1]	46	1			T55	1		T208	1		T47	1
auto[4026531840:4160749567]	auto[0]	51	1			T55	2		T50	1		T47	2
auto[4026531840:4160749567]	auto[1]	50	1			T3	2		T208	1		T47	1
auto[4160749568:4294967295]	auto[0]	54	1			T4	1		T205	1		T47	1
auto[4160749568:4294967295]	auto[1]	50	1			T3	2		T87	1		T55	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1587

1

T3

34

T4

17

T5

1

auto[1]

1671

1

T3

30

T4

13

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T3	1		T4	2		T55	2
auto[134217728:268435455]	103	1			T4	1		T5	1		T16	1
auto[268435456:402653183]	82	1			T3	1		T39	1		T44	2
auto[402653184:536870911]	94	1			T3	2		T55	1		T208	1
auto[536870912:671088639]	108	1			T3	4		T4	2		T39	1
auto[671088640:805306367]	82	1			T3	4		T4	1		T5	1
auto[805306368:939524095]	101	1			T4	1		T36	1		T38	1
auto[939524096:1073741823]	97	1			T3	2		T25	1		T211	1
auto[1073741824:1207959551]	115	1			T3	2		T25	1		T55	3
auto[1207959552:1342177279]	98	1			T3	3		T16	1		T39	1
auto[1342177280:1476395007]	94	1			T3	3		T4	1		T215	1
auto[1476395008:1610612735]	94	1			T3	1		T4	1		T16	1
auto[1610612736:1744830463]	115	1			T3	3		T4	2		T55	1
auto[1744830464:1879048191]	102	1			T3	1		T4	1		T87	1
auto[1879048192:2013265919]	107	1			T3	3		T16	1		T71	1
auto[2013265920:2147483647]	98	1			T3	1		T87	1		T208	2
auto[2147483648:2281701375]	86	1			T3	1		T39	1		T71	1
auto[2281701376:2415919103]	90	1			T3	1		T22	1		T127	1
auto[2415919104:2550136831]	97	1			T3	4		T55	1		T208	1
auto[2550136832:2684354559]	99	1			T3	3		T4	1		T39	1
auto[2684354560:2818572287]	114	1			T3	2		T4	3		T36	1
auto[2818572288:2952790015]	104	1			T3	3		T36	1		T39	1
auto[2952790016:3087007743]	118	1			T4	2		T127	1		T55	3
auto[3087007744:3221225471]	116	1			T3	2		T4	2		T38	1
auto[3221225472:3355443199]	101	1			T3	4		T4	1		T25	1
auto[3355443200:3489660927]	110	1			T3	2		T4	1		T38	1
auto[3489660928:3623878655]	96	1			T4	1		T47	4		T269	1
auto[3623878656:3758096383]	115	1			T3	2		T4	1		T22	1
auto[3758096384:3892314111]	113	1			T3	2		T206	1		T55	1
auto[3892314112:4026531839]	114	1			T3	5		T4	4		T44	1
auto[4026531840:4160749567]	102	1			T4	1		T36	1		T55	1
auto[4160749568:4294967295]	104	1			T3	2		T4	1		T36	1