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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2876 1 T3 42 T4 30 T5 2
auto[1] 289 1 T109 8 T101 3 T149 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 95 1 T3 1 T4 1 T44 2
auto[134217728:268435455] 107 1 T3 2 T36 1 T54 1
auto[268435456:402653183] 98 1 T3 5 T4 1 T208 1
auto[402653184:536870911] 111 1 T3 1 T22 1 T127 1
auto[536870912:671088639] 106 1 T3 2 T55 1 T47 1
auto[671088640:805306367] 89 1 T3 1 T39 1 T38 1
auto[805306368:939524095] 95 1 T3 1 T38 1 T206 1
auto[939524096:1073741823] 84 1 T3 1 T4 2 T36 1
auto[1073741824:1207959551] 92 1 T3 1 T22 1 T55 2
auto[1207959552:1342177279] 110 1 T3 1 T55 2 T208 1
auto[1342177280:1476395007] 99 1 T4 1 T16 1 T55 3
auto[1476395008:1610612735] 126 1 T3 1 T4 1 T16 1
auto[1610612736:1744830463] 89 1 T3 1 T39 1 T55 2
auto[1744830464:1879048191] 100 1 T3 1 T4 1 T127 1
auto[1879048192:2013265919] 99 1 T3 2 T44 1 T55 1
auto[2013265920:2147483647] 95 1 T3 1 T4 3 T36 1
auto[2147483648:2281701375] 102 1 T3 1 T4 1 T5 1
auto[2281701376:2415919103] 119 1 T3 2 T4 1 T38 1
auto[2415919104:2550136831] 94 1 T3 1 T4 1 T22 1
auto[2550136832:2684354559] 84 1 T3 1 T55 1 T208 1
auto[2684354560:2818572287] 73 1 T3 1 T4 2 T5 1
auto[2818572288:2952790015] 109 1 T4 1 T55 2 T208 1
auto[2952790016:3087007743] 94 1 T3 1 T4 1 T127 1
auto[3087007744:3221225471] 92 1 T4 3 T208 3 T47 1
auto[3221225472:3355443199] 100 1 T3 3 T36 1 T25 1
auto[3355443200:3489660927] 96 1 T3 3 T4 1 T16 1
auto[3489660928:3623878655] 103 1 T3 2 T4 2 T55 5
auto[3623878656:3758096383] 101 1 T3 1 T4 2 T39 1
auto[3758096384:3892314111] 104 1 T3 2 T25 1 T87 1
auto[3892314112:4026531839] 99 1 T71 1 T47 1 T64 1
auto[4026531840:4160749567] 95 1 T3 1 T4 2 T16 1
auto[4160749568:4294967295] 105 1 T3 1 T4 3 T47 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 83 1 T3 1 T4 1 T44 2
auto[0:134217727] auto[1] 12 1 T109 1 T149 1 T150 3
auto[134217728:268435455] auto[0] 97 1 T3 2 T36 1 T54 1
auto[134217728:268435455] auto[1] 10 1 T150 1 T357 1 T292 2
auto[268435456:402653183] auto[0] 92 1 T3 5 T4 1 T208 1
auto[268435456:402653183] auto[1] 6 1 T151 1 T265 1 T261 2
auto[402653184:536870911] auto[0] 99 1 T3 1 T22 1 T127 1
auto[402653184:536870911] auto[1] 12 1 T149 1 T150 2 T151 1
auto[536870912:671088639] auto[0] 93 1 T3 2 T55 1 T47 1
auto[536870912:671088639] auto[1] 13 1 T109 1 T151 2 T265 1
auto[671088640:805306367] auto[0] 88 1 T3 1 T39 1 T38 1
auto[671088640:805306367] auto[1] 1 1 T238 1 - - - -
auto[805306368:939524095] auto[0] 90 1 T3 1 T38 1 T206 1
auto[805306368:939524095] auto[1] 5 1 T150 1 T254 1 T293 1
auto[939524096:1073741823] auto[0] 74 1 T3 1 T4 2 T36 1
auto[939524096:1073741823] auto[1] 10 1 T109 1 T357 1 T244 1
auto[1073741824:1207959551] auto[0] 77 1 T3 1 T22 1 T55 2
auto[1073741824:1207959551] auto[1] 15 1 T137 1 T139 4 T288 1
auto[1207959552:1342177279] auto[0] 103 1 T3 1 T55 2 T208 1
auto[1207959552:1342177279] auto[1] 7 1 T150 2 T357 1 T390 1
auto[1342177280:1476395007] auto[0] 91 1 T4 1 T16 1 T55 3
auto[1342177280:1476395007] auto[1] 8 1 T138 1 T139 1 T244 1
auto[1476395008:1610612735] auto[0] 114 1 T3 1 T4 1 T16 1
auto[1476395008:1610612735] auto[1] 12 1 T319 1 T244 2 T292 1
auto[1610612736:1744830463] auto[0] 76 1 T3 1 T39 1 T55 2
auto[1610612736:1744830463] auto[1] 13 1 T101 1 T151 1 T139 1
auto[1744830464:1879048191] auto[0] 92 1 T3 1 T4 1 T127 1
auto[1744830464:1879048191] auto[1] 8 1 T151 2 T331 1 T399 1
auto[1879048192:2013265919] auto[0] 91 1 T3 2 T44 1 T55 1
auto[1879048192:2013265919] auto[1] 8 1 T149 1 T151 1 T319 1
auto[2013265920:2147483647] auto[0] 89 1 T3 1 T4 3 T36 1
auto[2013265920:2147483647] auto[1] 6 1 T151 1 T292 1 T406 1
auto[2147483648:2281701375] auto[0] 93 1 T3 1 T4 1 T5 1
auto[2147483648:2281701375] auto[1] 9 1 T109 2 T288 1 T310 1
auto[2281701376:2415919103] auto[0] 112 1 T3 2 T4 1 T38 1
auto[2281701376:2415919103] auto[1] 7 1 T357 1 T405 1 T389 1
auto[2415919104:2550136831] auto[0] 83 1 T3 1 T4 1 T22 1
auto[2415919104:2550136831] auto[1] 11 1 T109 1 T149 1 T150 1
auto[2550136832:2684354559] auto[0] 75 1 T3 1 T55 1 T208 1
auto[2550136832:2684354559] auto[1] 9 1 T151 1 T292 2 T331 1
auto[2684354560:2818572287] auto[0] 65 1 T3 1 T4 2 T5 1
auto[2684354560:2818572287] auto[1] 8 1 T109 1 T150 1 T151 1
auto[2818572288:2952790015] auto[0] 95 1 T4 1 T55 2 T208 1
auto[2818572288:2952790015] auto[1] 14 1 T150 1 T138 1 T139 2
auto[2952790016:3087007743] auto[0] 84 1 T3 1 T4 1 T127 1
auto[2952790016:3087007743] auto[1] 10 1 T101 1 T150 1 T151 2
auto[3087007744:3221225471] auto[0] 83 1 T4 3 T208 3 T47 1
auto[3087007744:3221225471] auto[1] 9 1 T101 1 T254 1 T288 1
auto[3221225472:3355443199] auto[0] 96 1 T3 3 T36 1 T25 1
auto[3221225472:3355443199] auto[1] 4 1 T109 1 T151 1 T403 1
auto[3355443200:3489660927] auto[0] 89 1 T3 3 T4 1 T16 1
auto[3355443200:3489660927] auto[1] 7 1 T139 1 T292 1 T390 1
auto[3489660928:3623878655] auto[0] 92 1 T3 2 T4 2 T55 5
auto[3489660928:3623878655] auto[1] 11 1 T150 1 T151 2 T139 1
auto[3623878656:3758096383] auto[0] 93 1 T3 1 T4 2 T39 1
auto[3623878656:3758096383] auto[1] 8 1 T254 1 T138 1 T244 1
auto[3758096384:3892314111] auto[0] 97 1 T3 2 T25 1 T87 1
auto[3758096384:3892314111] auto[1] 7 1 T150 1 T137 1 T288 1
auto[3892314112:4026531839] auto[0] 88 1 T71 1 T47 1 T64 1
auto[3892314112:4026531839] auto[1] 11 1 T265 1 T292 1 T272 1
auto[4026531840:4160749567] auto[0] 86 1 T3 1 T4 2 T16 1
auto[4026531840:4160749567] auto[1] 9 1 T150 1 T392 1 T331 1
auto[4160749568:4294967295] auto[0] 96 1 T3 1 T4 3 T47 2
auto[4160749568:4294967295] auto[1] 9 1 T254 2 T265 1 T138 1

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