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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2878 1 T3 42 T4 30 T5 2
auto[1] 258 1 T109 6 T101 5 T149 10


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 85 1 T3 2 T211 1 T55 1
auto[134217728:268435455] 101 1 T3 4 T4 2 T55 2
auto[268435456:402653183] 97 1 T3 1 T55 1 T50 1
auto[402653184:536870911] 87 1 T3 1 T4 2 T55 1
auto[536870912:671088639] 100 1 T3 1 T87 1 T47 3
auto[671088640:805306367] 103 1 T3 2 T4 2 T36 1
auto[805306368:939524095] 96 1 T3 1 T4 1 T87 2
auto[939524096:1073741823] 92 1 T3 2 T4 5 T39 1
auto[1073741824:1207959551] 89 1 T25 1 T38 1 T127 1
auto[1207959552:1342177279] 95 1 T3 1 T4 1 T5 1
auto[1342177280:1476395007] 89 1 T55 1 T47 2 T120 2
auto[1476395008:1610612735] 115 1 T3 1 T4 3 T16 1
auto[1610612736:1744830463] 103 1 T3 1 T39 1 T208 1
auto[1744830464:1879048191] 94 1 T3 2 T39 2 T127 1
auto[1879048192:2013265919] 95 1 T3 1 T4 1 T55 2
auto[2013265920:2147483647] 92 1 T3 2 T36 1 T55 1
auto[2147483648:2281701375] 90 1 T16 2 T36 1 T55 6
auto[2281701376:2415919103] 98 1 T3 1 T4 1 T55 1
auto[2415919104:2550136831] 116 1 T3 4 T4 1 T22 1
auto[2550136832:2684354559] 107 1 T3 1 T208 1 T215 1
auto[2684354560:2818572287] 116 1 T3 3 T36 1 T44 1
auto[2818572288:2952790015] 106 1 T4 2 T38 1 T22 1
auto[2952790016:3087007743] 103 1 T3 1 T5 1 T206 1
auto[3087007744:3221225471] 85 1 T4 1 T36 1 T54 1
auto[3221225472:3355443199] 101 1 T3 1 T4 1 T44 1
auto[3355443200:3489660927] 117 1 T3 1 T4 2 T38 1
auto[3489660928:3623878655] 105 1 T3 1 T211 1 T55 3
auto[3623878656:3758096383] 94 1 T3 1 T4 1 T44 1
auto[3758096384:3892314111] 91 1 T4 1 T55 1 T47 2
auto[3892314112:4026531839] 97 1 T3 3 T39 1 T55 1
auto[4026531840:4160749567] 96 1 T3 3 T4 2 T16 1
auto[4160749568:4294967295] 81 1 T4 1 T25 2 T39 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 79 1 T3 2 T211 1 T55 1
auto[0:134217727] auto[1] 6 1 T109 1 T151 1 T244 2
auto[134217728:268435455] auto[0] 85 1 T3 4 T4 2 T55 2
auto[134217728:268435455] auto[1] 16 1 T101 1 T151 1 T377 1
auto[268435456:402653183] auto[0] 88 1 T3 1 T55 1 T50 1
auto[268435456:402653183] auto[1] 9 1 T109 1 T149 1 T141 1
auto[402653184:536870911] auto[0] 78 1 T3 1 T4 2 T55 1
auto[402653184:536870911] auto[1] 9 1 T149 1 T150 1 T151 1
auto[536870912:671088639] auto[0] 93 1 T3 1 T87 1 T47 3
auto[536870912:671088639] auto[1] 7 1 T109 1 T101 1 T149 1
auto[671088640:805306367] auto[0] 98 1 T3 2 T4 2 T36 1
auto[671088640:805306367] auto[1] 5 1 T392 1 T310 1 T405 1
auto[805306368:939524095] auto[0] 90 1 T3 1 T4 1 T87 2
auto[805306368:939524095] auto[1] 6 1 T137 1 T141 1 T377 1
auto[939524096:1073741823] auto[0] 89 1 T3 2 T4 5 T39 1
auto[939524096:1073741823] auto[1] 3 1 T139 1 T406 1 T306 1
auto[1073741824:1207959551] auto[0] 83 1 T25 1 T38 1 T127 1
auto[1073741824:1207959551] auto[1] 6 1 T149 1 T141 1 T378 1
auto[1207959552:1342177279] auto[0] 86 1 T3 1 T4 1 T5 1
auto[1207959552:1342177279] auto[1] 9 1 T319 1 T357 1 T292 1
auto[1342177280:1476395007] auto[0] 80 1 T55 1 T47 2 T120 2
auto[1342177280:1476395007] auto[1] 9 1 T150 1 T319 2 T292 1
auto[1476395008:1610612735] auto[0] 102 1 T3 1 T4 3 T16 1
auto[1476395008:1610612735] auto[1] 13 1 T150 2 T319 1 T244 2
auto[1610612736:1744830463] auto[0] 93 1 T3 1 T39 1 T208 1
auto[1610612736:1744830463] auto[1] 10 1 T292 1 T394 1 T399 2
auto[1744830464:1879048191] auto[0] 81 1 T3 2 T39 2 T127 1
auto[1744830464:1879048191] auto[1] 13 1 T149 1 T150 1 T151 1
auto[1879048192:2013265919] auto[0] 88 1 T3 1 T4 1 T55 2
auto[1879048192:2013265919] auto[1] 7 1 T109 1 T149 1 T150 1
auto[2013265920:2147483647] auto[0] 89 1 T3 2 T36 1 T55 1
auto[2013265920:2147483647] auto[1] 3 1 T151 1 T265 1 T396 1
auto[2147483648:2281701375] auto[0] 86 1 T16 2 T36 1 T55 6
auto[2147483648:2281701375] auto[1] 4 1 T149 1 T151 1 T292 1
auto[2281701376:2415919103] auto[0] 93 1 T3 1 T4 1 T55 1
auto[2281701376:2415919103] auto[1] 5 1 T265 1 T392 1 T293 1
auto[2415919104:2550136831] auto[0] 109 1 T3 4 T4 1 T22 1
auto[2415919104:2550136831] auto[1] 7 1 T149 1 T151 1 T319 1
auto[2550136832:2684354559] auto[0] 95 1 T3 1 T208 1 T215 1
auto[2550136832:2684354559] auto[1] 12 1 T109 1 T101 1 T149 1
auto[2684354560:2818572287] auto[0] 109 1 T3 3 T36 1 T44 1
auto[2684354560:2818572287] auto[1] 7 1 T137 1 T139 1 T319 1
auto[2818572288:2952790015] auto[0] 96 1 T4 2 T38 1 T22 1
auto[2818572288:2952790015] auto[1] 10 1 T101 1 T139 1 T244 1
auto[2952790016:3087007743] auto[0] 96 1 T3 1 T5 1 T206 1
auto[2952790016:3087007743] auto[1] 7 1 T151 1 T265 1 T394 1
auto[3087007744:3221225471] auto[0] 78 1 T4 1 T36 1 T54 1
auto[3087007744:3221225471] auto[1] 7 1 T151 2 T139 1 T261 1
auto[3221225472:3355443199] auto[0] 96 1 T3 1 T4 1 T44 1
auto[3221225472:3355443199] auto[1] 5 1 T150 1 T319 2 T288 1
auto[3355443200:3489660927] auto[0] 105 1 T3 1 T4 2 T38 1
auto[3355443200:3489660927] auto[1] 12 1 T101 1 T151 1 T138 1
auto[3489660928:3623878655] auto[0] 92 1 T3 1 T211 1 T55 3
auto[3489660928:3623878655] auto[1] 13 1 T149 1 T150 1 T138 1
auto[3623878656:3758096383] auto[0] 88 1 T3 1 T4 1 T44 1
auto[3623878656:3758096383] auto[1] 6 1 T139 1 T288 1 T261 1
auto[3758096384:3892314111] auto[0] 82 1 T4 1 T55 1 T47 2
auto[3758096384:3892314111] auto[1] 9 1 T150 1 T151 1 T357 1
auto[3892314112:4026531839] auto[0] 87 1 T3 3 T39 1 T55 1
auto[3892314112:4026531839] auto[1] 10 1 T150 1 T139 1 T357 2
auto[4026531840:4160749567] auto[0] 87 1 T3 3 T4 2 T16 1
auto[4026531840:4160749567] auto[1] 9 1 T109 1 T138 1 T357 1
auto[4160749568:4294967295] auto[0] 77 1 T4 1 T25 2 T39 1
auto[4160749568:4294967295] auto[1] 4 1 T139 1 T357 1 T405 1

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