Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1571

1

T3

36

T4

17

T5

1

auto[1]

1687

1

T3

28

T4

13

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T3	4		T4	1		T44	1
auto[134217728:268435455]	113	1			T4	2		T208	1		T47	2
auto[268435456:402653183]	98	1			T3	4		T5	1		T16	1
auto[402653184:536870911]	106	1			T3	1		T4	6		T36	1
auto[536870912:671088639]	102	1			T3	5		T4	1		T38	1
auto[671088640:805306367]	101	1			T3	2		T4	1		T39	1
auto[805306368:939524095]	100	1			T3	1		T87	1		T55	1
auto[939524096:1073741823]	87	1			T3	2		T4	1		T55	3
auto[1073741824:1207959551]	101	1			T3	1		T16	1		T55	4
auto[1207959552:1342177279]	109	1			T3	2		T55	1		T47	7
auto[1342177280:1476395007]	107	1			T3	5		T4	2		T36	1
auto[1476395008:1610612735]	93	1			T3	2		T4	1		T39	1
auto[1610612736:1744830463]	94	1			T36	1		T55	1		T47	1
auto[1744830464:1879048191]	113	1			T3	3		T39	1		T44	1
auto[1879048192:2013265919]	100	1			T3	2		T4	1		T16	1
auto[2013265920:2147483647]	90	1			T4	1		T55	2		T208	1
auto[2147483648:2281701375]	81	1			T3	2		T4	1		T5	1
auto[2281701376:2415919103]	108	1			T3	1		T25	1		T55	1
auto[2415919104:2550136831]	107	1			T38	1		T55	2		T208	1
auto[2550136832:2684354559]	95	1			T3	3		T208	1		T50	1
auto[2684354560:2818572287]	106	1			T3	4		T4	2		T36	1
auto[2818572288:2952790015]	108	1			T3	2		T4	3		T47	1
auto[2952790016:3087007743]	104	1			T3	1		T25	1		T39	1
auto[3087007744:3221225471]	115	1			T3	2		T39	1		T38	1
auto[3221225472:3355443199]	95	1			T3	2		T4	3		T38	1
auto[3355443200:3489660927]	111	1			T3	2		T55	1		T47	2
auto[3489660928:3623878655]	109	1			T3	2		T4	2		T55	3
auto[3623878656:3758096383]	98	1			T4	1		T39	1		T22	1
auto[3758096384:3892314111]	97	1			T3	3		T44	1		T127	1
auto[3892314112:4026531839]	88	1			T3	1		T44	1		T55	3
auto[4026531840:4160749567]	102	1			T3	4		T4	1		T36	1
auto[4160749568:4294967295]	112	1			T3	1		T16	1		T50	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T3	1		T4	1		T44	1
auto[0:134217727]	auto[1]	50	1			T3	3		T208	1		T47	1
auto[134217728:268435455]	auto[0]	50	1			T208	1		T47	1		T59	1
auto[134217728:268435455]	auto[1]	63	1			T4	2		T47	1		T120	1
auto[268435456:402653183]	auto[0]	47	1			T3	2		T16	1		T47	2
auto[268435456:402653183]	auto[1]	51	1			T3	2		T5	1		T44	1
auto[402653184:536870911]	auto[0]	57	1			T4	4		T36	1		T38	1
auto[402653184:536870911]	auto[1]	49	1			T3	1		T4	2		T87	1
auto[536870912:671088639]	auto[0]	52	1			T3	4		T4	1		T38	1
auto[536870912:671088639]	auto[1]	50	1			T3	1		T54	1		T22	1
auto[671088640:805306367]	auto[0]	49	1			T3	1		T39	1		T55	1
auto[671088640:805306367]	auto[1]	52	1			T3	1		T4	1		T128	1
auto[805306368:939524095]	auto[0]	47	1			T47	1		T102	1		T57	1
auto[805306368:939524095]	auto[1]	53	1			T3	1		T87	1		T55	1
auto[939524096:1073741823]	auto[0]	39	1			T3	1		T4	1		T55	2
auto[939524096:1073741823]	auto[1]	48	1			T3	1		T55	1		T205	1
auto[1073741824:1207959551]	auto[0]	54	1			T3	1		T16	1		T55	3
auto[1073741824:1207959551]	auto[1]	47	1			T55	1		T195	1		T329	1
auto[1207959552:1342177279]	auto[0]	45	1			T3	1		T47	3		T133	1
auto[1207959552:1342177279]	auto[1]	64	1			T3	1		T55	1		T47	4
auto[1342177280:1476395007]	auto[0]	50	1			T3	4		T36	1		T87	1
auto[1342177280:1476395007]	auto[1]	57	1			T3	1		T4	2		T55	3
auto[1476395008:1610612735]	auto[0]	47	1			T39	1		T50	2		T47	2
auto[1476395008:1610612735]	auto[1]	46	1			T3	2		T4	1		T55	1
auto[1610612736:1744830463]	auto[0]	41	1			T36	1		T55	1		T47	1
auto[1610612736:1744830463]	auto[1]	53	1			T120	1		T301	1		T75	1
auto[1744830464:1879048191]	auto[0]	51	1			T3	1		T39	1		T211	1
auto[1744830464:1879048191]	auto[1]	62	1			T3	2		T44	1		T90	1
auto[1879048192:2013265919]	auto[0]	47	1			T3	1		T16	1		T87	1
auto[1879048192:2013265919]	auto[1]	53	1			T3	1		T4	1		T127	1
auto[2013265920:2147483647]	auto[0]	38	1			T4	1		T55	1		T47	1
auto[2013265920:2147483647]	auto[1]	52	1			T55	1		T208	1		T7	1
auto[2147483648:2281701375]	auto[0]	36	1			T3	1		T4	1		T5	1
auto[2147483648:2281701375]	auto[1]	45	1			T3	1		T22	1		T56	1
auto[2281701376:2415919103]	auto[0]	50	1			T3	1		T136	1		T120	1
auto[2281701376:2415919103]	auto[1]	58	1			T25	1		T55	1		T47	2
auto[2415919104:2550136831]	auto[0]	56	1			T38	1		T55	1		T71	1
auto[2415919104:2550136831]	auto[1]	51	1			T55	1		T208	1		T136	1
auto[2550136832:2684354559]	auto[0]	42	1			T3	2		T50	1		T59	1
auto[2550136832:2684354559]	auto[1]	53	1			T3	1		T208	1		T215	1
auto[2684354560:2818572287]	auto[0]	59	1			T3	3		T4	1		T36	1
auto[2684354560:2818572287]	auto[1]	47	1			T3	1		T4	1		T55	2
auto[2818572288:2952790015]	auto[0]	56	1			T4	2		T47	1		T269	1
auto[2818572288:2952790015]	auto[1]	52	1			T3	2		T4	1		T64	1
auto[2952790016:3087007743]	auto[0]	44	1			T3	1		T55	1		T47	3
auto[2952790016:3087007743]	auto[1]	60	1			T25	1		T39	1		T206	1
auto[3087007744:3221225471]	auto[0]	44	1			T3	1		T38	1		T47	2
auto[3087007744:3221225471]	auto[1]	71	1			T3	1		T39	1		T44	1
auto[3221225472:3355443199]	auto[0]	47	1			T3	2		T4	2		T38	1
auto[3221225472:3355443199]	auto[1]	48	1			T4	1		T22	1		T55	2
auto[3355443200:3489660927]	auto[0]	60	1			T3	2		T55	1		T65	1
auto[3355443200:3489660927]	auto[1]	51	1			T47	2		T136	1		T102	1
auto[3489660928:3623878655]	auto[0]	45	1			T4	1		T55	3		T301	1
auto[3489660928:3623878655]	auto[1]	64	1			T3	2		T4	1		T208	1
auto[3623878656:3758096383]	auto[0]	53	1			T4	1		T39	1		T22	1
auto[3623878656:3758096383]	auto[1]	45	1			T47	1		T268	1		T48	1
auto[3758096384:3892314111]	auto[0]	50	1			T3	1		T44	1		T127	1
auto[3758096384:3892314111]	auto[1]	47	1			T3	2		T121	1		T103	1
auto[3892314112:4026531839]	auto[0]	42	1			T3	1		T44	1		T55	2
auto[3892314112:4026531839]	auto[1]	46	1			T55	1		T131	1		T249	1
auto[4026531840:4160749567]	auto[0]	57	1			T3	3		T4	1		T55	1
auto[4026531840:4160749567]	auto[1]	45	1			T3	1		T36	1		T25	1
auto[4160749568:4294967295]	auto[0]	58	1			T3	1		T16	1		T50	1
auto[4160749568:4294967295]	auto[1]	54	1			T64	1		T90	1		T102	1