Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1569

1

T3

34

T4

20

T5

1

auto[1]

1689

1

T3

30

T4

10

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T3	1		T127	1		T55	3
auto[134217728:268435455]	100	1			T3	5		T38	1		T211	1
auto[268435456:402653183]	105	1			T3	3		T4	1		T44	1
auto[402653184:536870911]	120	1			T3	4		T39	1		T55	1
auto[536870912:671088639]	100	1			T3	4		T4	1		T38	1
auto[671088640:805306367]	94	1			T3	1		T4	1		T16	1
auto[805306368:939524095]	97	1			T3	3		T4	1		T16	1
auto[939524096:1073741823]	112	1			T3	2		T36	1		T44	1
auto[1073741824:1207959551]	90	1			T3	4		T39	1		T38	1
auto[1207959552:1342177279]	101	1			T25	1		T39	1		T208	1
auto[1342177280:1476395007]	113	1			T3	5		T4	1		T36	1
auto[1476395008:1610612735]	96	1			T3	2		T4	1		T128	1
auto[1610612736:1744830463]	97	1			T3	2		T4	1		T87	1
auto[1744830464:1879048191]	109	1			T3	6		T4	2		T55	1
auto[1879048192:2013265919]	91	1			T3	1		T4	1		T44	2
auto[2013265920:2147483647]	90	1			T3	2		T4	1		T47	3
auto[2147483648:2281701375]	100	1			T3	1		T5	1		T44	1
auto[2281701376:2415919103]	104	1			T4	2		T55	2		T205	1
auto[2415919104:2550136831]	90	1			T3	2		T4	3		T5	1
auto[2550136832:2684354559]	109	1			T3	2		T4	3		T55	2
auto[2684354560:2818572287]	113	1			T4	3		T16	1		T208	1
auto[2818572288:2952790015]	100	1			T3	1		T4	1		T47	1
auto[2952790016:3087007743]	116	1			T3	2		T127	1		T55	2
auto[3087007744:3221225471]	98	1			T3	1		T36	1		T55	3
auto[3221225472:3355443199]	94	1			T3	1		T4	1		T16	1
auto[3355443200:3489660927]	101	1			T3	1		T55	2		T71	1
auto[3489660928:3623878655]	112	1			T3	1		T36	1		T25	1
auto[3623878656:3758096383]	84	1			T3	3		T25	1		T22	2
auto[3758096384:3892314111]	101	1			T3	2		T36	1		T127	1
auto[3892314112:4026531839]	114	1			T3	1		T4	2		T39	1
auto[4026531840:4160749567]	106	1			T4	3		T38	1		T87	1
auto[4160749568:4294967295]	102	1			T3	1		T4	1		T22	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T3	1		T55	1		T96	1
auto[0:134217727]	auto[1]	53	1			T127	1		T55	2		T208	3
auto[134217728:268435455]	auto[0]	50	1			T3	5		T38	1		T211	1
auto[134217728:268435455]	auto[1]	50	1			T55	1		T47	1		T27	1
auto[268435456:402653183]	auto[0]	56	1			T3	1		T4	1		T44	1
auto[268435456:402653183]	auto[1]	49	1			T3	2		T47	2		T249	1
auto[402653184:536870911]	auto[0]	59	1			T3	1		T39	1		T208	1
auto[402653184:536870911]	auto[1]	61	1			T3	3		T55	1		T208	1
auto[536870912:671088639]	auto[0]	49	1			T3	2		T4	1		T38	1
auto[536870912:671088639]	auto[1]	51	1			T3	2		T71	1		T47	1
auto[671088640:805306367]	auto[0]	38	1			T16	1		T47	3		T52	1
auto[671088640:805306367]	auto[1]	56	1			T3	1		T4	1		T127	1
auto[805306368:939524095]	auto[0]	52	1			T3	3		T38	1		T55	2
auto[805306368:939524095]	auto[1]	45	1			T4	1		T16	1		T208	1
auto[939524096:1073741823]	auto[0]	49	1			T3	1		T36	1		T44	1
auto[939524096:1073741823]	auto[1]	63	1			T3	1		T55	1		T208	1
auto[1073741824:1207959551]	auto[0]	48	1			T3	1		T39	1		T38	1
auto[1073741824:1207959551]	auto[1]	42	1			T3	3		T55	1		T215	1
auto[1207959552:1342177279]	auto[0]	44	1			T208	1		T50	1		T47	1
auto[1207959552:1342177279]	auto[1]	57	1			T25	1		T39	1		T47	1
auto[1342177280:1476395007]	auto[0]	56	1			T4	1		T39	1		T133	1
auto[1342177280:1476395007]	auto[1]	57	1			T3	5		T36	1		T55	2
auto[1476395008:1610612735]	auto[0]	50	1			T3	1		T4	1		T55	1
auto[1476395008:1610612735]	auto[1]	46	1			T3	1		T128	1		T55	1
auto[1610612736:1744830463]	auto[0]	42	1			T4	1		T87	1		T55	1
auto[1610612736:1744830463]	auto[1]	55	1			T3	2		T55	3		T64	2
auto[1744830464:1879048191]	auto[0]	52	1			T3	4		T4	1		T55	1
auto[1744830464:1879048191]	auto[1]	57	1			T3	2		T4	1		T215	1
auto[1879048192:2013265919]	auto[0]	44	1			T3	1		T4	1		T44	1
auto[1879048192:2013265919]	auto[1]	47	1			T44	1		T55	1		T47	2
auto[2013265920:2147483647]	auto[0]	42	1			T4	1		T47	2		T58	1
auto[2013265920:2147483647]	auto[1]	48	1			T3	2		T47	1		T195	1
auto[2147483648:2281701375]	auto[0]	42	1			T47	1		T249	1		T90	1
auto[2147483648:2281701375]	auto[1]	58	1			T3	1		T5	1		T44	1
auto[2281701376:2415919103]	auto[0]	52	1			T4	1		T205	1		T47	2
auto[2281701376:2415919103]	auto[1]	52	1			T4	1		T55	2		T47	1
auto[2415919104:2550136831]	auto[0]	45	1			T3	1		T4	3		T5	1
auto[2415919104:2550136831]	auto[1]	45	1			T3	1		T54	1		T55	1
auto[2550136832:2684354559]	auto[0]	48	1			T3	2		T4	1		T55	2
auto[2550136832:2684354559]	auto[1]	61	1			T4	2		T47	1		T249	1
auto[2684354560:2818572287]	auto[0]	56	1			T4	2		T16	1		T71	1
auto[2684354560:2818572287]	auto[1]	57	1			T4	1		T208	1		T47	1
auto[2818572288:2952790015]	auto[0]	43	1			T3	1		T64	1		T26	1
auto[2818572288:2952790015]	auto[1]	57	1			T4	1		T47	1		T269	1
auto[2952790016:3087007743]	auto[0]	55	1			T3	1		T127	1		T47	1
auto[2952790016:3087007743]	auto[1]	61	1			T3	1		T55	2		T47	1
auto[3087007744:3221225471]	auto[0]	47	1			T36	1		T55	1		T47	2
auto[3087007744:3221225471]	auto[1]	51	1			T3	1		T55	2		T205	1
auto[3221225472:3355443199]	auto[0]	55	1			T3	1		T4	1		T16	1
auto[3221225472:3355443199]	auto[1]	39	1			T22	1		T47	1		T51	1
auto[3355443200:3489660927]	auto[0]	46	1			T3	1		T55	1		T71	1
auto[3355443200:3489660927]	auto[1]	55	1			T55	1		T47	2		T131	1
auto[3489660928:3623878655]	auto[0]	50	1			T3	1		T36	1		T25	1
auto[3489660928:3623878655]	auto[1]	62	1			T87	1		T55	2		T134	1
auto[3623878656:3758096383]	auto[0]	37	1			T3	2		T47	1		T133	1
auto[3623878656:3758096383]	auto[1]	47	1			T3	1		T25	1		T22	2
auto[3758096384:3892314111]	auto[0]	57	1			T3	2		T36	1		T55	1
auto[3758096384:3892314111]	auto[1]	44	1			T127	1		T247	1		T47	2
auto[3892314112:4026531839]	auto[0]	55	1			T3	1		T4	2		T39	1
auto[3892314112:4026531839]	auto[1]	59	1			T121	1		T268	1		T48	1
auto[4026531840:4160749567]	auto[0]	54	1			T4	2		T38	1		T55	1
auto[4026531840:4160749567]	auto[1]	52	1			T4	1		T87	1		T131	1
auto[4160749568:4294967295]	auto[0]	50	1			T22	1		T55	1		T208	1
auto[4160749568:4294967295]	auto[1]	52	1			T3	1		T4	1		T55	1