Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.04 98.11 98.53 100.00 99.02 98.41 91.22


Total test records in report: 1085
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T1007 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2408351738 Jun 22 04:47:17 PM PDT 24 Jun 22 04:47:19 PM PDT 24 37741925 ps
T176 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2243544855 Jun 22 04:47:10 PM PDT 24 Jun 22 04:47:17 PM PDT 24 142236227 ps
T1008 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3517297302 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:05 PM PDT 24 313205543 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.202232971 Jun 22 04:46:53 PM PDT 24 Jun 22 04:46:56 PM PDT 24 175299349 ps
T180 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2719060418 Jun 22 04:46:56 PM PDT 24 Jun 22 04:47:02 PM PDT 24 515337006 ps
T1010 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1336505122 Jun 22 04:46:54 PM PDT 24 Jun 22 04:46:56 PM PDT 24 113376517 ps
T1011 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3329370461 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:04 PM PDT 24 42030440 ps
T1012 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4061753292 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:05 PM PDT 24 364310589 ps
T1013 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2531990174 Jun 22 04:47:15 PM PDT 24 Jun 22 04:47:16 PM PDT 24 22928691 ps
T181 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3167685511 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:52 PM PDT 24 215680849 ps
T1014 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.809671798 Jun 22 04:47:00 PM PDT 24 Jun 22 04:47:03 PM PDT 24 74734603 ps
T1015 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3212337885 Jun 22 04:47:08 PM PDT 24 Jun 22 04:47:13 PM PDT 24 168453280 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3731378101 Jun 22 04:46:52 PM PDT 24 Jun 22 04:47:01 PM PDT 24 831758147 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2604703744 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:04 PM PDT 24 51933858 ps
T1018 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1049743602 Jun 22 04:47:15 PM PDT 24 Jun 22 04:47:17 PM PDT 24 84125334 ps
T1019 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2462542150 Jun 22 04:47:13 PM PDT 24 Jun 22 04:47:15 PM PDT 24 13778174 ps
T1020 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1503864130 Jun 22 04:46:52 PM PDT 24 Jun 22 04:46:56 PM PDT 24 117525010 ps
T1021 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1894684648 Jun 22 04:47:10 PM PDT 24 Jun 22 04:47:12 PM PDT 24 58211913 ps
T1022 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3203068696 Jun 22 04:47:10 PM PDT 24 Jun 22 04:47:13 PM PDT 24 140107000 ps
T170 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2197938669 Jun 22 04:46:59 PM PDT 24 Jun 22 04:47:04 PM PDT 24 114698566 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.428683559 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:11 PM PDT 24 442821469 ps
T1024 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1678001143 Jun 22 04:46:56 PM PDT 24 Jun 22 04:46:58 PM PDT 24 79562404 ps
T1025 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2185156960 Jun 22 04:47:08 PM PDT 24 Jun 22 04:47:10 PM PDT 24 21400178 ps
T1026 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1825404514 Jun 22 04:47:09 PM PDT 24 Jun 22 04:47:16 PM PDT 24 147023542 ps
T1027 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3701061464 Jun 22 04:47:14 PM PDT 24 Jun 22 04:47:15 PM PDT 24 12357053 ps
T1028 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1267091442 Jun 22 04:47:12 PM PDT 24 Jun 22 04:47:15 PM PDT 24 297542078 ps
T172 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2904893067 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:09 PM PDT 24 343116007 ps
T1029 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2396682126 Jun 22 04:46:49 PM PDT 24 Jun 22 04:46:52 PM PDT 24 317790267 ps
T1030 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4007537181 Jun 22 04:46:59 PM PDT 24 Jun 22 04:47:03 PM PDT 24 157836109 ps
T1031 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1849662778 Jun 22 04:47:07 PM PDT 24 Jun 22 04:47:08 PM PDT 24 12529657 ps
T1032 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3597655092 Jun 22 04:47:14 PM PDT 24 Jun 22 04:47:15 PM PDT 24 18604411 ps
T1033 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1564574365 Jun 22 04:46:59 PM PDT 24 Jun 22 04:47:01 PM PDT 24 14117015 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.978881775 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:04 PM PDT 24 49373209 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.998068906 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:47 PM PDT 24 136969130 ps
T1036 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.380556794 Jun 22 04:46:46 PM PDT 24 Jun 22 04:46:49 PM PDT 24 210257518 ps
T1037 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.723597347 Jun 22 04:47:10 PM PDT 24 Jun 22 04:47:12 PM PDT 24 110013163 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.547487452 Jun 22 04:46:59 PM PDT 24 Jun 22 04:47:04 PM PDT 24 148549931 ps
T1039 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1013755545 Jun 22 04:46:57 PM PDT 24 Jun 22 04:46:59 PM PDT 24 46835113 ps
T1040 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.563080860 Jun 22 04:46:58 PM PDT 24 Jun 22 04:47:00 PM PDT 24 43126260 ps
T1041 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1308741241 Jun 22 04:46:54 PM PDT 24 Jun 22 04:46:57 PM PDT 24 19982530 ps
T1042 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.492796182 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:04 PM PDT 24 71000996 ps
T1043 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2227592619 Jun 22 04:46:59 PM PDT 24 Jun 22 04:47:01 PM PDT 24 16419188 ps
T1044 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.32108953 Jun 22 04:46:53 PM PDT 24 Jun 22 04:47:09 PM PDT 24 1550127045 ps
T1045 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.177199393 Jun 22 04:47:15 PM PDT 24 Jun 22 04:47:17 PM PDT 24 44766804 ps
T1046 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1456584062 Jun 22 04:46:48 PM PDT 24 Jun 22 04:46:50 PM PDT 24 122325348 ps
T1047 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2964692066 Jun 22 04:47:30 PM PDT 24 Jun 22 04:47:31 PM PDT 24 10151517 ps
T1048 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3312057440 Jun 22 04:46:57 PM PDT 24 Jun 22 04:47:01 PM PDT 24 682371765 ps
T1049 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3722733717 Jun 22 04:47:01 PM PDT 24 Jun 22 04:47:08 PM PDT 24 795375171 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3491624928 Jun 22 04:47:11 PM PDT 24 Jun 22 04:47:14 PM PDT 24 120665714 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.935983370 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:59 PM PDT 24 629870180 ps
T1052 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3749747302 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:56 PM PDT 24 2289694731 ps
T1053 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3970454971 Jun 22 04:46:51 PM PDT 24 Jun 22 04:46:56 PM PDT 24 451258307 ps
T1054 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3715412479 Jun 22 04:47:04 PM PDT 24 Jun 22 04:47:08 PM PDT 24 943535088 ps
T1055 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2957925479 Jun 22 04:47:10 PM PDT 24 Jun 22 04:47:12 PM PDT 24 111015509 ps
T1056 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.551700448 Jun 22 04:46:52 PM PDT 24 Jun 22 04:46:54 PM PDT 24 20585843 ps
T1057 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3446021416 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:47 PM PDT 24 44649022 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.838974571 Jun 22 04:46:44 PM PDT 24 Jun 22 04:46:48 PM PDT 24 71308776 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1041172524 Jun 22 04:46:54 PM PDT 24 Jun 22 04:47:14 PM PDT 24 3477332662 ps
T1060 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3763560214 Jun 22 04:47:08 PM PDT 24 Jun 22 04:47:09 PM PDT 24 75239157 ps
T1061 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1198230389 Jun 22 04:46:54 PM PDT 24 Jun 22 04:47:03 PM PDT 24 518553743 ps
T1062 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.488906727 Jun 22 04:47:09 PM PDT 24 Jun 22 04:47:11 PM PDT 24 19226574 ps
T1063 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1494868734 Jun 22 04:47:13 PM PDT 24 Jun 22 04:47:14 PM PDT 24 41074957 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.49303901 Jun 22 04:47:07 PM PDT 24 Jun 22 04:47:13 PM PDT 24 313322365 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3430793526 Jun 22 04:46:48 PM PDT 24 Jun 22 04:46:50 PM PDT 24 19809486 ps
T1066 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.38801595 Jun 22 04:47:07 PM PDT 24 Jun 22 04:47:09 PM PDT 24 55779683 ps
T1067 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1667488838 Jun 22 04:47:00 PM PDT 24 Jun 22 04:47:02 PM PDT 24 986876024 ps
T1068 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3523113558 Jun 22 04:47:08 PM PDT 24 Jun 22 04:47:10 PM PDT 24 44839614 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3613719450 Jun 22 04:46:59 PM PDT 24 Jun 22 04:47:02 PM PDT 24 231409789 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.496296440 Jun 22 04:46:55 PM PDT 24 Jun 22 04:46:57 PM PDT 24 111083883 ps
T1071 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2850907155 Jun 22 04:47:04 PM PDT 24 Jun 22 04:47:09 PM PDT 24 150385641 ps
T1072 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1704370950 Jun 22 04:47:06 PM PDT 24 Jun 22 04:47:22 PM PDT 24 511231922 ps
T1073 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2474315990 Jun 22 04:46:57 PM PDT 24 Jun 22 04:47:01 PM PDT 24 186170505 ps
T1074 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.670911732 Jun 22 04:47:09 PM PDT 24 Jun 22 04:47:11 PM PDT 24 92426263 ps
T1075 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.933479469 Jun 22 04:46:54 PM PDT 24 Jun 22 04:46:57 PM PDT 24 90910468 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.918024984 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:49 PM PDT 24 127365173 ps
T1077 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2497505091 Jun 22 04:47:14 PM PDT 24 Jun 22 04:47:15 PM PDT 24 12420461 ps
T1078 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1728717969 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:48 PM PDT 24 84123946 ps
T1079 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1839807590 Jun 22 04:46:57 PM PDT 24 Jun 22 04:46:59 PM PDT 24 17152776 ps
T1080 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2820052934 Jun 22 04:46:54 PM PDT 24 Jun 22 04:46:58 PM PDT 24 68954575 ps
T1081 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2566923178 Jun 22 04:46:45 PM PDT 24 Jun 22 04:46:47 PM PDT 24 41509763 ps
T1082 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3891448899 Jun 22 04:46:54 PM PDT 24 Jun 22 04:46:56 PM PDT 24 31140705 ps
T1083 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1916901450 Jun 22 04:46:39 PM PDT 24 Jun 22 04:46:41 PM PDT 24 21891309 ps
T1084 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2779209385 Jun 22 04:46:48 PM PDT 24 Jun 22 04:46:50 PM PDT 24 20796894 ps
T1085 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3316228580 Jun 22 04:47:17 PM PDT 24 Jun 22 04:47:19 PM PDT 24 11725680 ps
T162 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3825844490 Jun 22 04:47:10 PM PDT 24 Jun 22 04:47:21 PM PDT 24 1059724109 ps

Test location /workspace/coverage/default/16.keymgr_stress_all.733154921
Short name T3
Test name
Test status
Simulation time 6295204676 ps
CPU time 79.74 seconds
Started Jun 22 06:04:17 PM PDT 24
Finished Jun 22 06:05:37 PM PDT 24
Peak memory 222120 kb
Host smart-8d8c4a11-48c3-436c-b212-7e3da3995194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733154921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.733154921
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.235797776
Short name T47
Test name
Test status
Simulation time 6487040843 ps
CPU time 46.69 seconds
Started Jun 22 06:03:06 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 215744 kb
Host smart-e30d2a6a-b9f2-454a-a1d5-274d21739d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235797776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.235797776
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.519848837
Short name T102
Test name
Test status
Simulation time 347447138 ps
CPU time 13.48 seconds
Started Jun 22 06:06:36 PM PDT 24
Finished Jun 22 06:06:50 PM PDT 24
Peak memory 222624 kb
Host smart-9c7e6fc8-0c34-4c94-9219-6c5ca039ad4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519848837 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.519848837
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2976065845
Short name T11
Test name
Test status
Simulation time 890602042 ps
CPU time 10.41 seconds
Started Jun 22 06:02:22 PM PDT 24
Finished Jun 22 06:02:33 PM PDT 24
Peak memory 238048 kb
Host smart-e6e6de4b-5df1-4009-b7a9-a26e739d16b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976065845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2976065845
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3928713271
Short name T25
Test name
Test status
Simulation time 133261408 ps
CPU time 3.5 seconds
Started Jun 22 06:04:59 PM PDT 24
Finished Jun 22 06:05:03 PM PDT 24
Peak memory 214680 kb
Host smart-7d0c1b14-5ae9-46d4-9606-6ff9a59f7f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928713271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3928713271
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.66557247
Short name T55
Test name
Test status
Simulation time 16245713997 ps
CPU time 257.42 seconds
Started Jun 22 06:05:32 PM PDT 24
Finished Jun 22 06:09:50 PM PDT 24
Peak memory 222612 kb
Host smart-ad76a798-42b8-418a-b352-a4124426b087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66557247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.66557247
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1955834923
Short name T104
Test name
Test status
Simulation time 351474134 ps
CPU time 9.42 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 214524 kb
Host smart-6d0513b3-8d1b-484a-bf98-a9121316e517
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955834923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1955834923
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.113679912
Short name T8
Test name
Test status
Simulation time 21741291447 ps
CPU time 469.7 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:11:09 PM PDT 24
Peak memory 222688 kb
Host smart-e3f8faa7-0e67-45aa-8ae6-6f4fa070b1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113679912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.113679912
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1237018730
Short name T151
Test name
Test status
Simulation time 9302195183 ps
CPU time 126.64 seconds
Started Jun 22 06:06:22 PM PDT 24
Finished Jun 22 06:08:29 PM PDT 24
Peak memory 215912 kb
Host smart-10bbf1a3-728c-4860-a0de-3ff35de910f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237018730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1237018730
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2612842614
Short name T37
Test name
Test status
Simulation time 96145942 ps
CPU time 2.51 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:04:57 PM PDT 24
Peak memory 210088 kb
Host smart-cb64d8cb-01a7-48ee-aa63-f004c1005f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612842614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2612842614
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1750307190
Short name T269
Test name
Test status
Simulation time 140828563 ps
CPU time 2.81 seconds
Started Jun 22 06:03:38 PM PDT 24
Finished Jun 22 06:03:42 PM PDT 24
Peak memory 214296 kb
Host smart-815054cc-1c25-4751-a356-8d1d9e5a917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750307190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1750307190
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2386426544
Short name T9
Test name
Test status
Simulation time 66800564 ps
CPU time 2.01 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:53 PM PDT 24
Peak memory 210256 kb
Host smart-fb01d898-0642-4e48-a5a8-fd8288a15356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386426544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2386426544
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3134280569
Short name T139
Test name
Test status
Simulation time 2260238193 ps
CPU time 118.2 seconds
Started Jun 22 06:03:25 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 215336 kb
Host smart-9084a545-c308-433c-b4cf-a4bad1ef83b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134280569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3134280569
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2362224008
Short name T103
Test name
Test status
Simulation time 524244826 ps
CPU time 22.89 seconds
Started Jun 22 06:03:18 PM PDT 24
Finished Jun 22 06:03:41 PM PDT 24
Peak memory 222660 kb
Host smart-bbd8db9a-a5f7-4896-8fe7-bba59ffb79ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362224008 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2362224008
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1947765465
Short name T91
Test name
Test status
Simulation time 366443326 ps
CPU time 3.92 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:51 PM PDT 24
Peak memory 214252 kb
Host smart-a780810b-d5c6-484d-b4df-f68c1eab37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947765465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1947765465
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1484724319
Short name T292
Test name
Test status
Simulation time 462790575 ps
CPU time 12.94 seconds
Started Jun 22 06:03:10 PM PDT 24
Finished Jun 22 06:03:23 PM PDT 24
Peak memory 215524 kb
Host smart-29823ef4-22f0-40ea-b480-8189c6959eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484724319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1484724319
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.253550362
Short name T396
Test name
Test status
Simulation time 1148013211 ps
CPU time 15 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:53 PM PDT 24
Peak memory 214316 kb
Host smart-000324c3-949f-435f-8e0e-b99dffe3f0d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253550362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.253550362
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3621336755
Short name T244
Test name
Test status
Simulation time 161730725 ps
CPU time 9.29 seconds
Started Jun 22 06:02:15 PM PDT 24
Finished Jun 22 06:02:25 PM PDT 24
Peak memory 214320 kb
Host smart-8563a2df-14db-43ed-9804-7205a63c9f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621336755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3621336755
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.934329440
Short name T4
Test name
Test status
Simulation time 25469686793 ps
CPU time 352.24 seconds
Started Jun 22 06:03:10 PM PDT 24
Finished Jun 22 06:09:03 PM PDT 24
Peak memory 221076 kb
Host smart-63316b94-35f3-4a05-bdeb-83d266045197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934329440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.934329440
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3842946047
Short name T218
Test name
Test status
Simulation time 243710125 ps
CPU time 6.42 seconds
Started Jun 22 06:03:20 PM PDT 24
Finished Jun 22 06:03:26 PM PDT 24
Peak memory 214252 kb
Host smart-5ef2a875-2055-4a4f-bba4-8d7169ec482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842946047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3842946047
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3093027551
Short name T56
Test name
Test status
Simulation time 179348012 ps
CPU time 2.84 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 217708 kb
Host smart-e25725f7-f797-4cc5-aed7-ac64cd2fdb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093027551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3093027551
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2754707800
Short name T22
Test name
Test status
Simulation time 331634442 ps
CPU time 5.15 seconds
Started Jun 22 06:05:22 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 214292 kb
Host smart-ffef4c15-c520-4c52-9cff-fb7a0460228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754707800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2754707800
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.675393106
Short name T20
Test name
Test status
Simulation time 86658675 ps
CPU time 2.93 seconds
Started Jun 22 06:05:09 PM PDT 24
Finished Jun 22 06:05:13 PM PDT 24
Peak memory 217168 kb
Host smart-068fde6c-ecf0-4bad-8bcb-296ee515c448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675393106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.675393106
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3870170843
Short name T31
Test name
Test status
Simulation time 259750334 ps
CPU time 3.45 seconds
Started Jun 22 06:04:04 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 220600 kb
Host smart-0b397301-e381-47d3-8a67-ecad092cd142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870170843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3870170843
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3373265598
Short name T357
Test name
Test status
Simulation time 572269091 ps
CPU time 15.32 seconds
Started Jun 22 06:06:07 PM PDT 24
Finished Jun 22 06:06:22 PM PDT 24
Peak memory 215240 kb
Host smart-352b04a2-f6c4-49ed-b93b-e90a083b5132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373265598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3373265598
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3887200270
Short name T961
Test name
Test status
Simulation time 349793091 ps
CPU time 1.91 seconds
Started Jun 22 04:46:41 PM PDT 24
Finished Jun 22 04:46:43 PM PDT 24
Peak memory 214512 kb
Host smart-48202a53-df6b-4909-a09c-d3f107ac1c2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887200270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3887200270
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.946811593
Short name T97
Test name
Test status
Simulation time 11820400 ps
CPU time 0.77 seconds
Started Jun 22 06:06:11 PM PDT 24
Finished Jun 22 06:06:13 PM PDT 24
Peak memory 205912 kb
Host smart-80a43bbd-b5dd-4bea-b245-975221367004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946811593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.946811593
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2000040009
Short name T69
Test name
Test status
Simulation time 31291665215 ps
CPU time 58 seconds
Started Jun 22 06:03:51 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 222692 kb
Host smart-d02f9a2c-f81b-4d25-9ebe-86c3f02389b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000040009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2000040009
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1228711943
Short name T149
Test name
Test status
Simulation time 2622481895 ps
CPU time 34.23 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:53 PM PDT 24
Peak memory 215832 kb
Host smart-688d03da-9d55-45b5-b1cc-6afaf72ab0e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228711943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1228711943
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.549249093
Short name T165
Test name
Test status
Simulation time 1071299232 ps
CPU time 10.09 seconds
Started Jun 22 04:46:58 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 205940 kb
Host smart-fd4d175c-636b-42c9-b98b-781dd3a17dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549249093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
549249093
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2487996291
Short name T63
Test name
Test status
Simulation time 59638517686 ps
CPU time 561.51 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:14:46 PM PDT 24
Peak memory 223988 kb
Host smart-bba3b53d-7c66-4f14-8fbf-bcc520f2a606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487996291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2487996291
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4124067632
Short name T306
Test name
Test status
Simulation time 645846405 ps
CPU time 8.14 seconds
Started Jun 22 06:05:35 PM PDT 24
Finished Jun 22 06:05:44 PM PDT 24
Peak memory 215472 kb
Host smart-6b45f459-94c2-4a3a-8cec-92ae3050ccfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124067632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4124067632
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.713017891
Short name T319
Test name
Test status
Simulation time 855508000 ps
CPU time 12.7 seconds
Started Jun 22 06:06:01 PM PDT 24
Finished Jun 22 06:06:14 PM PDT 24
Peak memory 214312 kb
Host smart-6a41d6ae-78b9-469e-9b4d-4e1409425809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713017891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.713017891
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3977636150
Short name T353
Test name
Test status
Simulation time 581182749 ps
CPU time 19.02 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:35 PM PDT 24
Peak memory 220992 kb
Host smart-15b1938a-a975-42f2-9151-eb7d056e2d0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977636150 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3977636150
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2444457911
Short name T26
Test name
Test status
Simulation time 1755540333 ps
CPU time 9.88 seconds
Started Jun 22 06:06:04 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 209764 kb
Host smart-d11f981a-ae69-4866-a77c-b55b1076d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444457911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2444457911
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1127259288
Short name T89
Test name
Test status
Simulation time 135951199 ps
CPU time 5.69 seconds
Started Jun 22 06:03:56 PM PDT 24
Finished Jun 22 06:04:03 PM PDT 24
Peak memory 222416 kb
Host smart-d91d2e53-0835-40f3-b3e4-3e61d5663855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127259288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1127259288
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3969234217
Short name T392
Test name
Test status
Simulation time 94924308 ps
CPU time 5.68 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 214260 kb
Host smart-1d2fb18e-bc5d-424d-a26c-4caf8dd12c77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969234217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3969234217
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.922680236
Short name T96
Test name
Test status
Simulation time 121469762 ps
CPU time 6.16 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 222440 kb
Host smart-fefd1960-6513-45d1-bbc0-5aee39faaf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922680236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.922680236
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.754796945
Short name T40
Test name
Test status
Simulation time 81777871 ps
CPU time 1.16 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:47 PM PDT 24
Peak memory 209720 kb
Host smart-bfbe25a4-1b50-4325-bf44-de2347b0aa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754796945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.754796945
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3760376211
Short name T85
Test name
Test status
Simulation time 292295432 ps
CPU time 3.77 seconds
Started Jun 22 06:02:48 PM PDT 24
Finished Jun 22 06:02:52 PM PDT 24
Peak memory 209732 kb
Host smart-da35d088-cf6e-4222-87d1-e3bd8fc20931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760376211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3760376211
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3987383862
Short name T156
Test name
Test status
Simulation time 477696074 ps
CPU time 3.01 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 222564 kb
Host smart-fbec68cc-2fa3-4ab9-b5cd-6086a261d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987383862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3987383862
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4087769200
Short name T330
Test name
Test status
Simulation time 143626330 ps
CPU time 2.44 seconds
Started Jun 22 06:03:38 PM PDT 24
Finished Jun 22 06:03:42 PM PDT 24
Peak memory 222368 kb
Host smart-306903b8-f41b-4c7f-8930-0e4cb0ca4aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087769200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4087769200
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.578795437
Short name T310
Test name
Test status
Simulation time 69661136 ps
CPU time 4.29 seconds
Started Jun 22 06:03:52 PM PDT 24
Finished Jun 22 06:03:57 PM PDT 24
Peak memory 214436 kb
Host smart-30617a6e-13fa-426c-b858-c8169c97d937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578795437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.578795437
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.847042951
Short name T229
Test name
Test status
Simulation time 55624130507 ps
CPU time 380.72 seconds
Started Jun 22 06:04:07 PM PDT 24
Finished Jun 22 06:10:28 PM PDT 24
Peak memory 222528 kb
Host smart-adba870d-927f-4eb3-b740-70aabf2bdc74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847042951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.847042951
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1675765945
Short name T70
Test name
Test status
Simulation time 1253769233 ps
CPU time 30.71 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:05:12 PM PDT 24
Peak memory 216740 kb
Host smart-b9a6efb3-60fe-4fd5-b87e-59d257f67681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675765945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1675765945
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1709218507
Short name T174
Test name
Test status
Simulation time 3607945221 ps
CPU time 11.12 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 217272 kb
Host smart-b641eb66-2e7d-4b5f-9f82-cd9bf0e0551c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709218507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1709218507
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2904893067
Short name T172
Test name
Test status
Simulation time 343116007 ps
CPU time 6.27 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 214112 kb
Host smart-1322ec5d-377f-48a4-8cc5-db175021c0db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904893067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2904893067
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.98154771
Short name T155
Test name
Test status
Simulation time 75525252 ps
CPU time 4.05 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:03:01 PM PDT 24
Peak memory 222612 kb
Host smart-1084f4a6-2668-41af-8126-b496ec7695dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98154771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.98154771
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.409250082
Short name T260
Test name
Test status
Simulation time 166008588 ps
CPU time 4 seconds
Started Jun 22 06:03:51 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 208612 kb
Host smart-0acf6467-92c4-4e18-8493-732ef51be1d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409250082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.409250082
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.697672916
Short name T275
Test name
Test status
Simulation time 1011140839 ps
CPU time 5.23 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 215068 kb
Host smart-e68fd01c-49b6-4c60-a4a5-fe7aa6b15b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697672916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.697672916
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3135866679
Short name T169
Test name
Test status
Simulation time 1371333539 ps
CPU time 4.25 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 206324 kb
Host smart-9bd731d9-9db4-4a3e-8565-73fb95446780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135866679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3135866679
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1920115614
Short name T173
Test name
Test status
Simulation time 218581376 ps
CPU time 2.58 seconds
Started Jun 22 04:46:46 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 205992 kb
Host smart-9ab01e15-d967-4aed-90ad-f26156f02a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920115614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1920115614
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1693627742
Short name T52
Test name
Test status
Simulation time 118962655 ps
CPU time 4.25 seconds
Started Jun 22 06:04:23 PM PDT 24
Finished Jun 22 06:04:27 PM PDT 24
Peak memory 207304 kb
Host smart-141582ec-c673-4816-a9f6-cc334e672fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693627742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1693627742
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2435794605
Short name T45
Test name
Test status
Simulation time 877374473 ps
CPU time 10.05 seconds
Started Jun 22 06:02:57 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 231300 kb
Host smart-ea3d9eb7-4f6b-4566-92b4-1d357df769f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435794605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2435794605
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2989364291
Short name T134
Test name
Test status
Simulation time 223190395 ps
CPU time 2.3 seconds
Started Jun 22 06:03:49 PM PDT 24
Finished Jun 22 06:03:52 PM PDT 24
Peak memory 218032 kb
Host smart-e88e3e84-32c0-42db-9f36-c33e9b16e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989364291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2989364291
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.627205049
Short name T153
Test name
Test status
Simulation time 340817322 ps
CPU time 4.4 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:07 PM PDT 24
Peak memory 218800 kb
Host smart-6562b5f7-396d-40a2-931a-f767622e275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627205049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.627205049
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.861286014
Short name T288
Test name
Test status
Simulation time 123841722 ps
CPU time 6.73 seconds
Started Jun 22 06:02:21 PM PDT 24
Finished Jun 22 06:02:28 PM PDT 24
Peak memory 215652 kb
Host smart-cb5a0454-b1f9-4e95-bc22-72e1049edf7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861286014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.861286014
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3818228550
Short name T323
Test name
Test status
Simulation time 265150395 ps
CPU time 3.66 seconds
Started Jun 22 06:03:41 PM PDT 24
Finished Jun 22 06:03:45 PM PDT 24
Peak memory 208932 kb
Host smart-dc54f65a-d2bb-433d-8d08-fe0005af4ea6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818228550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3818228550
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.376363254
Short name T48
Test name
Test status
Simulation time 1631354205 ps
CPU time 16.99 seconds
Started Jun 22 06:03:39 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 215072 kb
Host smart-20d08811-6be8-4621-b2ed-5451a80db392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376363254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.376363254
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1592447493
Short name T267
Test name
Test status
Simulation time 97446385 ps
CPU time 3.87 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:55 PM PDT 24
Peak memory 222328 kb
Host smart-df214b2f-fae6-4439-bcf3-a3556f0b6061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592447493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1592447493
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3987932021
Short name T281
Test name
Test status
Simulation time 314530585 ps
CPU time 2.78 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:51 PM PDT 24
Peak memory 214272 kb
Host smart-90f0d9ba-49e9-41c5-ab16-051643d8e2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987932021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3987932021
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1924599204
Short name T38
Test name
Test status
Simulation time 113595441 ps
CPU time 2.43 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:18 PM PDT 24
Peak memory 214248 kb
Host smart-570b6a9e-5fbf-47ea-a5ad-98c5d4ceb0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924599204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1924599204
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2118638761
Short name T6
Test name
Test status
Simulation time 258935865 ps
CPU time 5.08 seconds
Started Jun 22 06:06:27 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 209108 kb
Host smart-25dc78e1-da5b-4ff2-a57c-cd2ec7e4d06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118638761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2118638761
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1337144028
Short name T238
Test name
Test status
Simulation time 64578710 ps
CPU time 2.68 seconds
Started Jun 22 06:03:02 PM PDT 24
Finished Jun 22 06:03:05 PM PDT 24
Peak memory 214320 kb
Host smart-5c00d1b8-7c68-4abd-ab8d-f02e46ef4e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1337144028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1337144028
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2496531011
Short name T331
Test name
Test status
Simulation time 321752088 ps
CPU time 4.12 seconds
Started Jun 22 06:03:32 PM PDT 24
Finished Jun 22 06:03:37 PM PDT 24
Peak memory 215616 kb
Host smart-023c38f2-88ad-410e-a695-16bde3adc02e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496531011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2496531011
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1867412709
Short name T177
Test name
Test status
Simulation time 437557275 ps
CPU time 3.49 seconds
Started Jun 22 04:47:02 PM PDT 24
Finished Jun 22 04:47:06 PM PDT 24
Peak memory 214064 kb
Host smart-afb93a7e-1be4-446c-b5c4-82ae2092b702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867412709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1867412709
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.963553602
Short name T179
Test name
Test status
Simulation time 81820067 ps
CPU time 2.16 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:30 PM PDT 24
Peak memory 210056 kb
Host smart-a14496ed-6c32-4b68-9b1d-539b70693e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963553602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.963553602
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3407128942
Short name T154
Test name
Test status
Simulation time 62283259 ps
CPU time 3.71 seconds
Started Jun 22 06:04:19 PM PDT 24
Finished Jun 22 06:04:23 PM PDT 24
Peak memory 218036 kb
Host smart-28ea1d92-b8ea-44e3-8196-63f6a451bc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407128942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3407128942
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.180778279
Short name T341
Test name
Test status
Simulation time 140791898 ps
CPU time 5.62 seconds
Started Jun 22 06:02:28 PM PDT 24
Finished Jun 22 06:02:34 PM PDT 24
Peak memory 214312 kb
Host smart-0033bd36-0e3d-42e9-9cf8-96b8f5018e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180778279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.180778279
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.388259548
Short name T188
Test name
Test status
Simulation time 440858782 ps
CPU time 8.96 seconds
Started Jun 22 06:03:54 PM PDT 24
Finished Jun 22 06:04:04 PM PDT 24
Peak memory 222608 kb
Host smart-c3d8d9f0-4aec-43cf-93a0-c1779cdb6deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388259548 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.388259548
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3009811720
Short name T219
Test name
Test status
Simulation time 257184062 ps
CPU time 6.86 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:44 PM PDT 24
Peak memory 214688 kb
Host smart-e36b5195-22df-4573-bb70-b6f7d040b7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009811720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3009811720
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2818336554
Short name T328
Test name
Test status
Simulation time 710580791 ps
CPU time 5.85 seconds
Started Jun 22 06:04:45 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 222356 kb
Host smart-3c054df2-66eb-4340-adee-d282b51b259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818336554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2818336554
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3804249556
Short name T217
Test name
Test status
Simulation time 1026231227 ps
CPU time 4.35 seconds
Started Jun 22 06:05:16 PM PDT 24
Finished Jun 22 06:05:21 PM PDT 24
Peak memory 220216 kb
Host smart-3a3d2564-2084-4906-a8ce-d2243c1df9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804249556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3804249556
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2592309603
Short name T199
Test name
Test status
Simulation time 656420944 ps
CPU time 9.83 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 214248 kb
Host smart-233a265e-d05d-4f48-9048-a72469ebe89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592309603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2592309603
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2698403877
Short name T633
Test name
Test status
Simulation time 93068136 ps
CPU time 3.89 seconds
Started Jun 22 06:02:51 PM PDT 24
Finished Jun 22 06:02:56 PM PDT 24
Peak memory 218156 kb
Host smart-d2a872f4-aeb4-46f0-8e91-58cf1ea1592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698403877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2698403877
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1052117600
Short name T339
Test name
Test status
Simulation time 506379586 ps
CPU time 5.27 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 214204 kb
Host smart-c57c3ac4-dffc-45ca-ae84-9827ad0523e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052117600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1052117600
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3759022551
Short name T865
Test name
Test status
Simulation time 636222415 ps
CPU time 17.8 seconds
Started Jun 22 06:05:53 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 222540 kb
Host smart-bd9a81a0-c04f-4ad4-871e-06372b8eb5c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759022551 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3759022551
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4054196195
Short name T233
Test name
Test status
Simulation time 366069598 ps
CPU time 17.7 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:46 PM PDT 24
Peak memory 221044 kb
Host smart-49309890-6bd3-40c0-af9c-4f03ad40aa6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054196195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4054196195
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3825844490
Short name T162
Test name
Test status
Simulation time 1059724109 ps
CPU time 9.69 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:21 PM PDT 24
Peak memory 214088 kb
Host smart-ff94f6ab-af12-4ffc-93eb-19648d602cc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825844490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3825844490
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.525416269
Short name T163
Test name
Test status
Simulation time 145743732 ps
CPU time 4.95 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 214180 kb
Host smart-f3106e2e-c537-4ce4-ac2d-337f79b2ee5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525416269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.525416269
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3626230042
Short name T158
Test name
Test status
Simulation time 795514295 ps
CPU time 4.4 seconds
Started Jun 22 06:03:33 PM PDT 24
Finished Jun 22 06:03:38 PM PDT 24
Peak memory 217972 kb
Host smart-006586cc-740e-4e4c-83b0-941a5d594142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626230042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3626230042
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1850075619
Short name T157
Test name
Test status
Simulation time 211293784 ps
CPU time 3.11 seconds
Started Jun 22 06:05:47 PM PDT 24
Finished Jun 22 06:05:50 PM PDT 24
Peak memory 217180 kb
Host smart-1fa19fed-fb9e-43c8-b467-3dec3b62b712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850075619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1850075619
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_random.4179544741
Short name T325
Test name
Test status
Simulation time 111906507 ps
CPU time 5.02 seconds
Started Jun 22 06:03:54 PM PDT 24
Finished Jun 22 06:04:00 PM PDT 24
Peak memory 218456 kb
Host smart-b70f8733-5819-4389-a685-fb13fe33e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179544741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4179544741
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2978713342
Short name T279
Test name
Test status
Simulation time 590507318 ps
CPU time 7.61 seconds
Started Jun 22 06:03:59 PM PDT 24
Finished Jun 22 06:04:07 PM PDT 24
Peak memory 222260 kb
Host smart-e961ffdd-fef1-4343-bc0d-f93451e3d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978713342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2978713342
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1141591367
Short name T141
Test name
Test status
Simulation time 519704993 ps
CPU time 7.97 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:12 PM PDT 24
Peak memory 222456 kb
Host smart-276e918b-bb76-4caf-99b5-28dd195c9a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141591367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1141591367
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3938852788
Short name T871
Test name
Test status
Simulation time 4539990807 ps
CPU time 26.51 seconds
Started Jun 22 06:04:11 PM PDT 24
Finished Jun 22 06:04:39 PM PDT 24
Peak memory 222720 kb
Host smart-792749ce-2d64-4eff-a322-1894fa88269c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938852788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3938852788
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3507848126
Short name T314
Test name
Test status
Simulation time 186790439 ps
CPU time 2.51 seconds
Started Jun 22 06:04:10 PM PDT 24
Finished Jun 22 06:04:13 PM PDT 24
Peak memory 214316 kb
Host smart-527efa1d-1780-429e-a8fb-d64806cea1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507848126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3507848126
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3690036416
Short name T274
Test name
Test status
Simulation time 298543425 ps
CPU time 4.71 seconds
Started Jun 22 06:04:24 PM PDT 24
Finished Jun 22 06:04:29 PM PDT 24
Peak memory 214368 kb
Host smart-560ca6c8-427c-46e6-94e8-43c1690c5276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690036416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3690036416
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_random.384688171
Short name T290
Test name
Test status
Simulation time 188003615 ps
CPU time 6.53 seconds
Started Jun 22 06:05:03 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 207724 kb
Host smart-69938a43-3da3-4d3f-ab1c-2c79ccb649d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384688171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.384688171
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2385154231
Short name T232
Test name
Test status
Simulation time 888601729 ps
CPU time 15.46 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 222348 kb
Host smart-6c26078d-535f-4be9-b2fe-4b94647c7598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385154231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2385154231
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_random.96999461
Short name T891
Test name
Test status
Simulation time 488165752 ps
CPU time 7.94 seconds
Started Jun 22 06:05:20 PM PDT 24
Finished Jun 22 06:05:29 PM PDT 24
Peak memory 214376 kb
Host smart-70fdfca7-c41d-4198-8ffa-aae9bae46409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96999461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.96999461
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.4276512793
Short name T363
Test name
Test status
Simulation time 482738399 ps
CPU time 13.78 seconds
Started Jun 22 06:05:26 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 222692 kb
Host smart-8b11b02d-917e-4cde-833a-71f72564322d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276512793 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.4276512793
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2144376165
Short name T315
Test name
Test status
Simulation time 127101750 ps
CPU time 2.28 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 214324 kb
Host smart-9e0614a1-f7af-4f65-a500-7dc2a0653b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144376165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2144376165
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1511403630
Short name T228
Test name
Test status
Simulation time 196453018 ps
CPU time 4.61 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 209880 kb
Host smart-45d280ef-f703-44c2-b912-3c1b5272b0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511403630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1511403630
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2029810607
Short name T220
Test name
Test status
Simulation time 3153704965 ps
CPU time 45.49 seconds
Started Jun 22 06:06:19 PM PDT 24
Finished Jun 22 06:07:05 PM PDT 24
Peak memory 222856 kb
Host smart-afa6c159-0162-4d2a-bb23-d08086b9b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029810607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2029810607
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2950519281
Short name T231
Test name
Test status
Simulation time 143477610 ps
CPU time 2.51 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:29 PM PDT 24
Peak memory 218052 kb
Host smart-dded70b2-253c-45cf-9221-698d2cf30f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950519281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2950519281
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1694328950
Short name T316
Test name
Test status
Simulation time 59376958 ps
CPU time 4.11 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:30 PM PDT 24
Peak memory 215248 kb
Host smart-5f3dec99-ac70-496f-8362-a34718b6cdc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694328950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1694328950
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3749747302
Short name T1052
Test name
Test status
Simulation time 2289694731 ps
CPU time 10.36 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 206000 kb
Host smart-1164d190-339e-4138-bbf4-2e373d340ed1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749747302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
749747302
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3936091958
Short name T943
Test name
Test status
Simulation time 1299731059 ps
CPU time 17.09 seconds
Started Jun 22 04:46:40 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 205968 kb
Host smart-02cc746c-b4b0-452b-a68a-db38db4eedc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936091958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
936091958
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1916901450
Short name T1083
Test name
Test status
Simulation time 21891309 ps
CPU time 0.92 seconds
Started Jun 22 04:46:39 PM PDT 24
Finished Jun 22 04:46:41 PM PDT 24
Peak memory 205720 kb
Host smart-05d16780-0c9a-4aac-aa56-813f56e1cd3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916901450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
916901450
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.238653848
Short name T981
Test name
Test status
Simulation time 27475977 ps
CPU time 1.73 seconds
Started Jun 22 04:46:50 PM PDT 24
Finished Jun 22 04:46:52 PM PDT 24
Peak memory 214144 kb
Host smart-139e0df1-d8bd-4ae8-a83c-fa94b8b45483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238653848 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.238653848
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.43129265
Short name T954
Test name
Test status
Simulation time 18774155 ps
CPU time 1.12 seconds
Started Jun 22 04:46:40 PM PDT 24
Finished Jun 22 04:46:42 PM PDT 24
Peak memory 206004 kb
Host smart-2862178c-fc54-478a-85e9-117a7b037831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43129265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.43129265
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2432966742
Short name T971
Test name
Test status
Simulation time 11519007 ps
CPU time 0.82 seconds
Started Jun 22 04:46:43 PM PDT 24
Finished Jun 22 04:46:44 PM PDT 24
Peak memory 205620 kb
Host smart-fad75523-0845-406e-a363-55d0a73b6147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432966742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2432966742
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1456584062
Short name T1046
Test name
Test status
Simulation time 122325348 ps
CPU time 1.46 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:50 PM PDT 24
Peak memory 205884 kb
Host smart-2ccc9b5a-6b8c-437d-9847-03470268701d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456584062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1456584062
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.855488977
Short name T964
Test name
Test status
Simulation time 166315231 ps
CPU time 4.56 seconds
Started Jun 22 04:46:38 PM PDT 24
Finished Jun 22 04:46:44 PM PDT 24
Peak memory 214432 kb
Host smart-654935e8-b911-4743-bfd5-89ea68e0676a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855488977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.855488977
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2179417501
Short name T983
Test name
Test status
Simulation time 366169323 ps
CPU time 2.15 seconds
Started Jun 22 04:46:39 PM PDT 24
Finished Jun 22 04:46:42 PM PDT 24
Peak memory 214112 kb
Host smart-4f84283c-61ff-42e0-aaf1-76abc9bf6daa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179417501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2179417501
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2653463819
Short name T168
Test name
Test status
Simulation time 216891683 ps
CPU time 2.51 seconds
Started Jun 22 04:46:39 PM PDT 24
Finished Jun 22 04:46:42 PM PDT 24
Peak memory 206016 kb
Host smart-6f30c5f0-619e-4557-b2c5-99857e15e04a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653463819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2653463819
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.838974571
Short name T1058
Test name
Test status
Simulation time 71308776 ps
CPU time 3.9 seconds
Started Jun 22 04:46:44 PM PDT 24
Finished Jun 22 04:46:48 PM PDT 24
Peak memory 205980 kb
Host smart-b21b73e7-2108-40da-8498-b211b13cdb93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838974571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.838974571
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1195548984
Short name T941
Test name
Test status
Simulation time 695538115 ps
CPU time 7.85 seconds
Started Jun 22 04:46:46 PM PDT 24
Finished Jun 22 04:46:55 PM PDT 24
Peak memory 205828 kb
Host smart-fc773e5b-cc73-41cf-a0a6-a55a644be9b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195548984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
195548984
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3446021416
Short name T1057
Test name
Test status
Simulation time 44649022 ps
CPU time 1.15 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:47 PM PDT 24
Peak memory 205908 kb
Host smart-226a68e8-1259-424a-b0f6-3b8446a3a8ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446021416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
446021416
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3611496797
Short name T996
Test name
Test status
Simulation time 50911010 ps
CPU time 2.26 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:48 PM PDT 24
Peak memory 218520 kb
Host smart-b4af6e20-ea39-4a2d-a609-1dd0cb258d77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611496797 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3611496797
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.22324622
Short name T990
Test name
Test status
Simulation time 42030477 ps
CPU time 0.86 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 205760 kb
Host smart-0618a8c5-5213-4af6-81bc-abf7963a16ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22324622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.22324622
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2779209385
Short name T1084
Test name
Test status
Simulation time 20796894 ps
CPU time 0.74 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:50 PM PDT 24
Peak memory 205660 kb
Host smart-94793127-1e83-4ce8-b085-f65dce4b494d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779209385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2779209385
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2396682126
Short name T1029
Test name
Test status
Simulation time 317790267 ps
CPU time 2.6 seconds
Started Jun 22 04:46:49 PM PDT 24
Finished Jun 22 04:46:52 PM PDT 24
Peak memory 206008 kb
Host smart-8bce320d-7b0f-4c15-b490-231a0b0691b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396682126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2396682126
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1728717969
Short name T1078
Test name
Test status
Simulation time 84123946 ps
CPU time 2.7 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:48 PM PDT 24
Peak memory 214464 kb
Host smart-6733e91c-33ce-4335-83f6-02b5fc640617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728717969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1728717969
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1433716004
Short name T106
Test name
Test status
Simulation time 778620078 ps
CPU time 4.51 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:53 PM PDT 24
Peak memory 214408 kb
Host smart-a08f4bdc-98d6-44cf-bc18-9eab6501854e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433716004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1433716004
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.380556794
Short name T1036
Test name
Test status
Simulation time 210257518 ps
CPU time 2.89 seconds
Started Jun 22 04:46:46 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 214164 kb
Host smart-dc719f31-beb8-4586-9379-6abadd2202d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380556794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.380556794
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3167685511
Short name T181
Test name
Test status
Simulation time 215680849 ps
CPU time 6.1 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:52 PM PDT 24
Peak memory 214248 kb
Host smart-eb5105e4-5a30-4436-b465-0b7a9c64013f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167685511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3167685511
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.75548316
Short name T944
Test name
Test status
Simulation time 39667155 ps
CPU time 1.07 seconds
Started Jun 22 04:47:00 PM PDT 24
Finished Jun 22 04:47:03 PM PDT 24
Peak memory 205864 kb
Host smart-b3ea12fc-e1d1-498b-9f28-0f238f6f9904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75548316 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.75548316
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3542688744
Short name T946
Test name
Test status
Simulation time 127078053 ps
CPU time 1.1 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 205984 kb
Host smart-5c419f6c-ed14-4136-a753-6fe74ce6b4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542688744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3542688744
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3590629617
Short name T918
Test name
Test status
Simulation time 17986502 ps
CPU time 0.83 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 205652 kb
Host smart-c02791bf-9b48-457d-aff3-a38ba9cc142d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590629617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3590629617
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1979167572
Short name T147
Test name
Test status
Simulation time 187738518 ps
CPU time 3.57 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:06 PM PDT 24
Peak memory 205980 kb
Host smart-27a69a2d-a28a-4d15-8de0-b0dba8c91201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979167572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1979167572
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1179666060
Short name T1001
Test name
Test status
Simulation time 131886494 ps
CPU time 2.52 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:05 PM PDT 24
Peak memory 214548 kb
Host smart-007219f8-af0a-4229-8ffc-79543b14273c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179666060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1179666060
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1704370950
Short name T1072
Test name
Test status
Simulation time 511231922 ps
CPU time 15.62 seconds
Started Jun 22 04:47:06 PM PDT 24
Finished Jun 22 04:47:22 PM PDT 24
Peak memory 214416 kb
Host smart-2e2c3e7d-21eb-4c17-b34c-dd1991ecdf04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704370950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1704370950
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.978881775
Short name T1034
Test name
Test status
Simulation time 49373209 ps
CPU time 1.88 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 214068 kb
Host smart-93aacf6e-42e3-44d2-847e-fbf57df78be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978881775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.978881775
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3153259621
Short name T175
Test name
Test status
Simulation time 559866598 ps
CPU time 5.17 seconds
Started Jun 22 04:47:00 PM PDT 24
Finished Jun 22 04:47:06 PM PDT 24
Peak memory 215684 kb
Host smart-dae992bb-70b6-4609-ba34-7a22af70388f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153259621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3153259621
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3240519334
Short name T159
Test name
Test status
Simulation time 57637608 ps
CPU time 1.19 seconds
Started Jun 22 04:47:00 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 206000 kb
Host smart-ca9f73aa-e181-4297-96cd-6660a67fb8c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240519334 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3240519334
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.563080860
Short name T1040
Test name
Test status
Simulation time 43126260 ps
CPU time 1.11 seconds
Started Jun 22 04:46:58 PM PDT 24
Finished Jun 22 04:47:00 PM PDT 24
Peak memory 206012 kb
Host smart-2a361bd6-6d15-4f6b-a559-0d37a38d18d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563080860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.563080860
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2227592619
Short name T1043
Test name
Test status
Simulation time 16419188 ps
CPU time 0.74 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 205616 kb
Host smart-e4fe22d5-ec36-4376-b569-e2feaa77bfe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227592619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2227592619
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1667488838
Short name T1067
Test name
Test status
Simulation time 986876024 ps
CPU time 1.55 seconds
Started Jun 22 04:47:00 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 205980 kb
Host smart-f56fdc52-0d16-42d8-a67f-c04b99058214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667488838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1667488838
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3517297302
Short name T1008
Test name
Test status
Simulation time 313205543 ps
CPU time 2.77 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:05 PM PDT 24
Peak memory 214436 kb
Host smart-a44be02d-8e6b-4456-b8dc-a30141cbdf6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517297302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3517297302
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.547487452
Short name T1038
Test name
Test status
Simulation time 148549931 ps
CPU time 3.49 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 214524 kb
Host smart-503f0487-1b50-4f8c-829d-ca68828584c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547487452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.547487452
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1822920039
Short name T929
Test name
Test status
Simulation time 156365663 ps
CPU time 2.87 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:05 PM PDT 24
Peak memory 217300 kb
Host smart-d3ae6bdb-909d-44d7-8ab6-49ba0fd2a9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822920039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1822920039
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2898510617
Short name T984
Test name
Test status
Simulation time 17782473 ps
CPU time 1.32 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 214260 kb
Host smart-81cba031-7223-4fdc-83da-76cfe0012520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898510617 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2898510617
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4041418605
Short name T962
Test name
Test status
Simulation time 51620910 ps
CPU time 1.54 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 205976 kb
Host smart-e58b87dd-8313-4708-88ac-2e526a5394db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041418605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4041418605
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2146096059
Short name T935
Test name
Test status
Simulation time 19629256 ps
CPU time 0.79 seconds
Started Jun 22 04:46:58 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 205704 kb
Host smart-25f8c468-352a-47ca-b36f-be1095d4b07f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146096059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2146096059
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2827407183
Short name T993
Test name
Test status
Simulation time 39312470 ps
CPU time 2.43 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:05 PM PDT 24
Peak memory 206080 kb
Host smart-81f76ea1-00ad-4711-89f2-a502b474cd05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827407183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2827407183
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1086104915
Short name T959
Test name
Test status
Simulation time 205405181 ps
CPU time 1.98 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 214412 kb
Host smart-0a6c36e0-796b-4021-8aed-f642a0de37ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086104915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1086104915
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3722733717
Short name T1049
Test name
Test status
Simulation time 795375171 ps
CPU time 4.9 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 214476 kb
Host smart-cf4006cc-1167-4370-9e9c-490a050e75d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722733717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3722733717
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2943299589
Short name T951
Test name
Test status
Simulation time 631953072 ps
CPU time 3.5 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:06 PM PDT 24
Peak memory 214160 kb
Host smart-a8c04076-bd0b-42d8-a087-6535afafae68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943299589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2943299589
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2850907155
Short name T1071
Test name
Test status
Simulation time 150385641 ps
CPU time 4.46 seconds
Started Jun 22 04:47:04 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 214148 kb
Host smart-70985639-9af9-452a-ac21-4088197a1018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850907155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2850907155
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3329370461
Short name T1011
Test name
Test status
Simulation time 42030440 ps
CPU time 1.5 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 214164 kb
Host smart-c0adb7a6-b82f-4f0e-b9d6-1142ad07a7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329370461 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3329370461
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.492796182
Short name T1042
Test name
Test status
Simulation time 71000996 ps
CPU time 1.22 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 205832 kb
Host smart-f42c86a3-e63a-4fe3-861b-e6c904765a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492796182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.492796182
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3372285282
Short name T920
Test name
Test status
Simulation time 14018372 ps
CPU time 0.81 seconds
Started Jun 22 04:47:06 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 205700 kb
Host smart-b8447d10-3b7f-4faa-98ba-6e111bb3423c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372285282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3372285282
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3659501034
Short name T145
Test name
Test status
Simulation time 129177429 ps
CPU time 1.93 seconds
Started Jun 22 04:47:04 PM PDT 24
Finished Jun 22 04:47:07 PM PDT 24
Peak memory 205972 kb
Host smart-4e539d09-163e-462f-801c-fe4f9ed1c591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659501034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3659501034
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.18908679
Short name T110
Test name
Test status
Simulation time 779081027 ps
CPU time 4.91 seconds
Started Jun 22 04:47:03 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 214448 kb
Host smart-27629c09-7b6d-47a5-a630-5a17d1d34327
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18908679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow
_reg_errors.18908679
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4007537181
Short name T1030
Test name
Test status
Simulation time 157836109 ps
CPU time 3.42 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:03 PM PDT 24
Peak memory 214488 kb
Host smart-6e93484b-ddcc-44ad-b063-e4511265f43f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007537181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4007537181
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3715412479
Short name T1054
Test name
Test status
Simulation time 943535088 ps
CPU time 3.86 seconds
Started Jun 22 04:47:04 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 217272 kb
Host smart-b6e9067d-9d65-4fd6-915c-2901d9248d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715412479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3715412479
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2197938669
Short name T170
Test name
Test status
Simulation time 114698566 ps
CPU time 3.43 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 214188 kb
Host smart-f50b8e91-5444-4338-a487-494fe3e672df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197938669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2197938669
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.809671798
Short name T1014
Test name
Test status
Simulation time 74734603 ps
CPU time 1.13 seconds
Started Jun 22 04:47:00 PM PDT 24
Finished Jun 22 04:47:03 PM PDT 24
Peak memory 205796 kb
Host smart-13f4a654-ed4a-4966-863f-e5fe01081e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809671798 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.809671798
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.506488567
Short name T1000
Test name
Test status
Simulation time 24802224 ps
CPU time 0.97 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 205740 kb
Host smart-b0e0b612-58c7-41d6-b30d-f6fc436b150a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506488567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.506488567
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1564574365
Short name T1033
Test name
Test status
Simulation time 14117015 ps
CPU time 0.9 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 205876 kb
Host smart-a4667cc5-c139-4819-8747-1181178e8cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564574365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1564574365
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.746832603
Short name T972
Test name
Test status
Simulation time 512587105 ps
CPU time 1.82 seconds
Started Jun 22 04:47:03 PM PDT 24
Finished Jun 22 04:47:06 PM PDT 24
Peak memory 205856 kb
Host smart-2b4a40e1-a921-49f4-8636-f40fbe88ae66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746832603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.746832603
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2343702182
Short name T980
Test name
Test status
Simulation time 263757863 ps
CPU time 6.05 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 219136 kb
Host smart-771b6718-e27e-45b2-945f-db1389273846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343702182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2343702182
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.428683559
Short name T1023
Test name
Test status
Simulation time 442821469 ps
CPU time 8.65 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 214420 kb
Host smart-8da63eca-020d-4f0e-97b4-80da4508ebf4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428683559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.428683559
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.24735742
Short name T925
Test name
Test status
Simulation time 128110933 ps
CPU time 4.51 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:07 PM PDT 24
Peak memory 214100 kb
Host smart-afa57633-a207-4d09-b70a-fb4574f4a6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24735742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.24735742
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1889880833
Short name T967
Test name
Test status
Simulation time 399679193 ps
CPU time 7.55 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 214104 kb
Host smart-d0023eab-c8db-4784-b4f2-44f593476a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889880833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1889880833
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3491624928
Short name T1050
Test name
Test status
Simulation time 120665714 ps
CPU time 1.58 seconds
Started Jun 22 04:47:11 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 214240 kb
Host smart-e8f239cc-ebea-446c-b505-2f1891cd5c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491624928 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3491624928
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1849662778
Short name T1031
Test name
Test status
Simulation time 12529657 ps
CPU time 0.83 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 205816 kb
Host smart-a0d2ce71-30d9-462f-bb73-aa3c69e7b258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849662778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1849662778
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1094809820
Short name T938
Test name
Test status
Simulation time 12733415 ps
CPU time 0.88 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 205596 kb
Host smart-d818ddf8-f951-4f2d-980d-0a41c675faf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094809820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1094809820
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2074199798
Short name T958
Test name
Test status
Simulation time 99286094 ps
CPU time 3.3 seconds
Started Jun 22 04:47:06 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 205984 kb
Host smart-d482d2c0-fe41-47c8-8328-0f290a8c0043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074199798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2074199798
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4061753292
Short name T1012
Test name
Test status
Simulation time 364310589 ps
CPU time 2.64 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:05 PM PDT 24
Peak memory 214588 kb
Host smart-c27e8aaf-452c-415c-8283-241f9cda816c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061753292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4061753292
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2198138989
Short name T976
Test name
Test status
Simulation time 428831932 ps
CPU time 10.88 seconds
Started Jun 22 04:47:05 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 214492 kb
Host smart-a1d30418-661f-4e02-bef4-f10088aacf7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198138989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2198138989
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3613719450
Short name T1069
Test name
Test status
Simulation time 231409789 ps
CPU time 1.97 seconds
Started Jun 22 04:46:59 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 214124 kb
Host smart-486e3fe1-abcf-43ce-9584-40c4054a2050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613719450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3613719450
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2583248296
Short name T1002
Test name
Test status
Simulation time 81451003 ps
CPU time 1.44 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 214272 kb
Host smart-72a0854b-9d02-4131-927c-312efc1ac49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583248296 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2583248296
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1894684648
Short name T1021
Test name
Test status
Simulation time 58211913 ps
CPU time 1.21 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 205872 kb
Host smart-5eea0f5a-e460-4100-a3d9-9c4e1c20da02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894684648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1894684648
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1111890429
Short name T945
Test name
Test status
Simulation time 12140293 ps
CPU time 0.86 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 205700 kb
Host smart-878cceef-1bae-431e-baf8-f88bfdd9693f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111890429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1111890429
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.406203628
Short name T969
Test name
Test status
Simulation time 91149744 ps
CPU time 2.65 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 206268 kb
Host smart-3358fdd0-a33d-40ba-b9df-b209bffb0738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406203628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.406203628
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3212337885
Short name T1015
Test name
Test status
Simulation time 168453280 ps
CPU time 3.5 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:13 PM PDT 24
Peak memory 214380 kb
Host smart-6d2a883e-1b3d-4ba4-9198-2e23b9de33d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212337885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3212337885
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1267091442
Short name T1028
Test name
Test status
Simulation time 297542078 ps
CPU time 2.91 seconds
Started Jun 22 04:47:12 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 214156 kb
Host smart-8f8e2edd-a750-40e2-9871-8bfec7389d25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267091442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1267091442
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3523113558
Short name T1068
Test name
Test status
Simulation time 44839614 ps
CPU time 1.62 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 214192 kb
Host smart-76a18380-a973-45ab-936f-e9cf7ee38d36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523113558 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3523113558
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3763560214
Short name T1060
Test name
Test status
Simulation time 75239157 ps
CPU time 1.08 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 205996 kb
Host smart-8e57ed89-410c-4b0a-9a46-e920be1c4167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763560214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3763560214
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.488906727
Short name T1062
Test name
Test status
Simulation time 19226574 ps
CPU time 0.82 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 205700 kb
Host smart-30a2471f-7852-4b82-b79a-58b2e02d245d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488906727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.488906727
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4103435470
Short name T992
Test name
Test status
Simulation time 351036858 ps
CPU time 2.02 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 205912 kb
Host smart-9a1dc37b-33ee-4424-8623-68d7b02b8488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103435470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4103435470
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2105689862
Short name T107
Test name
Test status
Simulation time 485536031 ps
CPU time 2.47 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 214472 kb
Host smart-9d3ec8a3-a400-494f-a32d-0db8120e9ff8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105689862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2105689862
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.49303901
Short name T1064
Test name
Test status
Simulation time 313322365 ps
CPU time 5.84 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:13 PM PDT 24
Peak memory 214468 kb
Host smart-8b3c3ad9-55ee-4215-965b-223acf657dbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49303901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.k
eymgr_shadow_reg_errors_with_csr_rw.49303901
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4111102412
Short name T991
Test name
Test status
Simulation time 257307368 ps
CPU time 4.29 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 214108 kb
Host smart-d1cf266c-5197-4367-8f1b-2f3b5d3f9db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111102412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4111102412
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2957925479
Short name T1055
Test name
Test status
Simulation time 111015509 ps
CPU time 1.35 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 214316 kb
Host smart-b26c7c66-8da5-4552-828b-fb26ae4e4a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957925479 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2957925479
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1275928994
Short name T997
Test name
Test status
Simulation time 39490048 ps
CPU time 1.12 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 205844 kb
Host smart-ba155e12-b824-4a5f-ba63-33e9ec4cd017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275928994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1275928994
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1964660768
Short name T979
Test name
Test status
Simulation time 59826434 ps
CPU time 0.78 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:08 PM PDT 24
Peak memory 205692 kb
Host smart-8a4093d0-678c-442b-8c2a-277d8db20814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964660768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1964660768
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.958000704
Short name T146
Test name
Test status
Simulation time 56930501 ps
CPU time 1.43 seconds
Started Jun 22 04:47:12 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 205932 kb
Host smart-1c3969d6-e09e-4be6-a422-3b43a0270568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958000704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.958000704
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.622576501
Short name T955
Test name
Test status
Simulation time 306284430 ps
CPU time 4.41 seconds
Started Jun 22 04:47:12 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 214492 kb
Host smart-11ebc9e1-2f56-46bd-b80e-0276052164ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622576501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.622576501
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.436977880
Short name T957
Test name
Test status
Simulation time 622732567 ps
CPU time 7.26 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 214720 kb
Host smart-079c8fbe-5c0b-48c0-8a32-344fff321f3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436977880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.436977880
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3203068696
Short name T1022
Test name
Test status
Simulation time 140107000 ps
CPU time 2.01 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:13 PM PDT 24
Peak memory 214132 kb
Host smart-5e948903-f5b1-40fb-944e-6e8878f8c40a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203068696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3203068696
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3643312842
Short name T166
Test name
Test status
Simulation time 53263793 ps
CPU time 1.47 seconds
Started Jun 22 04:47:12 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 217148 kb
Host smart-3737d3d2-d020-42b4-a18c-0f99c497ba88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643312842 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3643312842
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.38801595
Short name T1066
Test name
Test status
Simulation time 55779683 ps
CPU time 1.18 seconds
Started Jun 22 04:47:07 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 206048 kb
Host smart-a30c65c0-0dca-4a87-8049-49be2b1e47de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.38801595
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.416388386
Short name T933
Test name
Test status
Simulation time 42224247 ps
CPU time 0.88 seconds
Started Jun 22 04:48:13 PM PDT 24
Finished Jun 22 04:48:15 PM PDT 24
Peak memory 205696 kb
Host smart-2251f39e-1fe2-4d55-b546-b9709064ec2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416388386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.416388386
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1853409555
Short name T968
Test name
Test status
Simulation time 1076125727 ps
CPU time 3.11 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 206004 kb
Host smart-3b9c052b-32f4-43f5-a590-ec39a414fb56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853409555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1853409555
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1941997336
Short name T995
Test name
Test status
Simulation time 64770240 ps
CPU time 2.47 seconds
Started Jun 22 04:47:11 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 214416 kb
Host smart-d5a2d861-75ab-4fea-8981-17577d1d381b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941997336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1941997336
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1825404514
Short name T1026
Test name
Test status
Simulation time 147023542 ps
CPU time 6.15 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:16 PM PDT 24
Peak memory 214500 kb
Host smart-911015b5-2df0-425e-b18f-4e512850e2ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825404514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1825404514
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4223113127
Short name T1006
Test name
Test status
Simulation time 160388508 ps
CPU time 2.74 seconds
Started Jun 22 04:47:11 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 217220 kb
Host smart-f0526017-7aa1-46f8-a51c-3cf919eb0031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223113127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4223113127
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2243544855
Short name T176
Test name
Test status
Simulation time 142236227 ps
CPU time 5.79 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 213976 kb
Host smart-eb3a8ebc-fb74-427d-8a25-e9f09d19f043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243544855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2243544855
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1579428789
Short name T143
Test name
Test status
Simulation time 757469151 ps
CPU time 7.08 seconds
Started Jun 22 04:46:47 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 206004 kb
Host smart-39f7e393-c18e-4f56-9eea-69907d3068a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579428789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
579428789
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.935983370
Short name T1051
Test name
Test status
Simulation time 629870180 ps
CPU time 13.22 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 205992 kb
Host smart-a0982671-965f-420a-919e-dd07ac2cae71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935983370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.935983370
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2560780208
Short name T160
Test name
Test status
Simulation time 112193300 ps
CPU time 1.08 seconds
Started Jun 22 04:46:44 PM PDT 24
Finished Jun 22 04:46:45 PM PDT 24
Peak memory 205884 kb
Host smart-7ae0cec3-9c0a-4ebb-b358-92465c627bee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560780208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
560780208
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1503864130
Short name T1020
Test name
Test status
Simulation time 117525010 ps
CPU time 2.34 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 214112 kb
Host smart-d8bd62a8-d0cd-4adf-a2e1-c33aab872b36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503864130 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1503864130
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2461646981
Short name T966
Test name
Test status
Simulation time 113107931 ps
CPU time 1.21 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:50 PM PDT 24
Peak memory 205940 kb
Host smart-5e775c47-262b-4b57-9e86-c465f6cb8e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461646981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2461646981
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3430793526
Short name T1065
Test name
Test status
Simulation time 19809486 ps
CPU time 0.74 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:50 PM PDT 24
Peak memory 205692 kb
Host smart-cb11eb6c-25df-4fea-a4fb-094deddac082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430793526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3430793526
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2566923178
Short name T1081
Test name
Test status
Simulation time 41509763 ps
CPU time 1.35 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:47 PM PDT 24
Peak memory 206012 kb
Host smart-0b3e4d8b-1725-419d-b64c-36478091edd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566923178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2566923178
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.998068906
Short name T1035
Test name
Test status
Simulation time 136969130 ps
CPU time 1.42 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:47 PM PDT 24
Peak memory 214552 kb
Host smart-ede8dd77-d6a1-4659-9e9c-a07e898d85ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998068906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.998068906
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3564594495
Short name T963
Test name
Test status
Simulation time 247200186 ps
CPU time 5.31 seconds
Started Jun 22 04:46:46 PM PDT 24
Finished Jun 22 04:46:51 PM PDT 24
Peak memory 220540 kb
Host smart-a17c3f0f-938b-47dc-962d-f4a345ea7ab7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564594495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3564594495
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2545326806
Short name T940
Test name
Test status
Simulation time 316121656 ps
CPU time 2.98 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:52 PM PDT 24
Peak memory 214124 kb
Host smart-906e1515-b782-4b6e-829a-4dd39a6b3396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545326806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2545326806
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3329558913
Short name T937
Test name
Test status
Simulation time 21696278 ps
CPU time 0.67 seconds
Started Jun 22 04:47:12 PM PDT 24
Finished Jun 22 04:47:13 PM PDT 24
Peak memory 205624 kb
Host smart-386d2a3b-a589-45b1-ad2b-45b0f18a9bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329558913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3329558913
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1859422666
Short name T924
Test name
Test status
Simulation time 20889306 ps
CPU time 0.72 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 205544 kb
Host smart-ca6bd96e-edef-4845-8733-97546c6f1ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859422666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1859422666
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.97110234
Short name T928
Test name
Test status
Simulation time 30634910 ps
CPU time 0.92 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 205744 kb
Host smart-6e59304a-a7d6-43ab-8f82-0034e7c2d282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97110234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.97110234
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.875645053
Short name T994
Test name
Test status
Simulation time 30288143 ps
CPU time 0.72 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 205552 kb
Host smart-c70bfdc0-3e60-4458-bbe8-0956fd7e1659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875645053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.875645053
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2185156960
Short name T1025
Test name
Test status
Simulation time 21400178 ps
CPU time 0.76 seconds
Started Jun 22 04:47:08 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 205564 kb
Host smart-da7bd4e2-b52c-415b-ba93-cb86c774fdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185156960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2185156960
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.723597347
Short name T1037
Test name
Test status
Simulation time 110013163 ps
CPU time 0.79 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 205700 kb
Host smart-ae13efa5-8e68-44ac-89a3-000e99b4592b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723597347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.723597347
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2096829536
Short name T923
Test name
Test status
Simulation time 62595236 ps
CPU time 0.71 seconds
Started Jun 22 04:47:10 PM PDT 24
Finished Jun 22 04:47:12 PM PDT 24
Peak memory 205436 kb
Host smart-f3961be0-ffb8-4696-8d67-fead18d01526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096829536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2096829536
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3147462693
Short name T1004
Test name
Test status
Simulation time 42434044 ps
CPU time 0.77 seconds
Started Jun 22 04:47:30 PM PDT 24
Finished Jun 22 04:47:31 PM PDT 24
Peak memory 205616 kb
Host smart-432ad86a-04dc-4496-a90a-6a9147ef7635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147462693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3147462693
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2531990174
Short name T1013
Test name
Test status
Simulation time 22928691 ps
CPU time 0.84 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:16 PM PDT 24
Peak memory 205700 kb
Host smart-2fc482bf-5a59-461f-a89e-cca440764006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531990174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2531990174
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3132893004
Short name T953
Test name
Test status
Simulation time 28820924 ps
CPU time 0.75 seconds
Started Jun 22 04:47:29 PM PDT 24
Finished Jun 22 04:47:30 PM PDT 24
Peak memory 205692 kb
Host smart-73118004-9621-4f75-82d3-c5897b6734f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132893004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3132893004
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3731378101
Short name T1016
Test name
Test status
Simulation time 831758147 ps
CPU time 8 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 206040 kb
Host smart-4a64991b-1b52-4934-821c-09fa5a463553
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731378101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
731378101
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1041172524
Short name T1059
Test name
Test status
Simulation time 3477332662 ps
CPU time 18.04 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 205980 kb
Host smart-d441a1db-7af1-4d5a-8b4a-b323cc51f9ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041172524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
041172524
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4258796032
Short name T942
Test name
Test status
Simulation time 15768770 ps
CPU time 0.86 seconds
Started Jun 22 04:46:49 PM PDT 24
Finished Jun 22 04:46:50 PM PDT 24
Peak memory 205800 kb
Host smart-01276cd7-5b93-4296-8728-7b9a783d7fe3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258796032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
258796032
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3262992861
Short name T939
Test name
Test status
Simulation time 38278125 ps
CPU time 1.79 seconds
Started Jun 22 04:46:51 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 214428 kb
Host smart-1d8a273a-8cbe-45b4-931e-d0f3eeae78bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262992861 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3262992861
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1331097303
Short name T987
Test name
Test status
Simulation time 19158444 ps
CPU time 1 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 205964 kb
Host smart-6fae4133-3c95-4bf7-96c3-78b24a8ecd46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331097303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1331097303
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1312461354
Short name T978
Test name
Test status
Simulation time 8960751 ps
CPU time 0.7 seconds
Started Jun 22 04:46:48 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 205692 kb
Host smart-77029841-6f06-43a6-b897-2ef6ce86279a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312461354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1312461354
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2278922453
Short name T999
Test name
Test status
Simulation time 84595326 ps
CPU time 2.57 seconds
Started Jun 22 04:46:51 PM PDT 24
Finished Jun 22 04:46:55 PM PDT 24
Peak memory 205928 kb
Host smart-bca466c8-874e-4ee7-93d9-41f8d4083bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278922453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2278922453
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.918024984
Short name T1076
Test name
Test status
Simulation time 127365173 ps
CPU time 4 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 214492 kb
Host smart-2aece3f2-739c-4fba-88e9-7d997712d146
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918024984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.918024984
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1435544930
Short name T1003
Test name
Test status
Simulation time 802715162 ps
CPU time 7.69 seconds
Started Jun 22 04:46:45 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 214484 kb
Host smart-02123fb6-4185-4f85-befa-a7e22959199f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435544930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1435544930
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.794888315
Short name T931
Test name
Test status
Simulation time 86953284 ps
CPU time 1.5 seconds
Started Jun 22 04:46:47 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 215140 kb
Host smart-178df19f-acff-43fe-ad00-3afef83a888c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794888315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.794888315
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3295413412
Short name T178
Test name
Test status
Simulation time 473567856 ps
CPU time 6.08 seconds
Started Jun 22 04:46:47 PM PDT 24
Finished Jun 22 04:46:53 PM PDT 24
Peak memory 214032 kb
Host smart-e6241b54-9f2a-4463-a9cb-0bf4dfa5670b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295413412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3295413412
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.639717803
Short name T921
Test name
Test status
Simulation time 12661944 ps
CPU time 0.88 seconds
Started Jun 22 04:47:29 PM PDT 24
Finished Jun 22 04:47:31 PM PDT 24
Peak memory 205616 kb
Host smart-07817632-6674-443e-beff-e47d98fdedae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639717803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.639717803
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3215603055
Short name T1005
Test name
Test status
Simulation time 9321085 ps
CPU time 0.83 seconds
Started Jun 22 04:47:29 PM PDT 24
Finished Jun 22 04:47:30 PM PDT 24
Peak memory 205692 kb
Host smart-cc864ad8-34f2-475b-9834-d35c37ac77da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215603055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3215603055
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2726685457
Short name T960
Test name
Test status
Simulation time 9609836 ps
CPU time 0.74 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:16 PM PDT 24
Peak memory 205708 kb
Host smart-48c9adca-fb93-4b8b-8290-2c069406ed70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726685457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2726685457
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3316228580
Short name T1085
Test name
Test status
Simulation time 11725680 ps
CPU time 0.75 seconds
Started Jun 22 04:47:17 PM PDT 24
Finished Jun 22 04:47:19 PM PDT 24
Peak memory 205684 kb
Host smart-ef2dcccf-0550-4041-84a1-232b8bfe2a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316228580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3316228580
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2497505091
Short name T1077
Test name
Test status
Simulation time 12420461 ps
CPU time 0.72 seconds
Started Jun 22 04:47:14 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 205648 kb
Host smart-742e6e36-2a34-4d3d-a11a-af66ed69a66e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497505091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2497505091
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2462542150
Short name T1019
Test name
Test status
Simulation time 13778174 ps
CPU time 0.69 seconds
Started Jun 22 04:47:13 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 205692 kb
Host smart-0d37ced5-e0a2-4d36-8913-1980606061a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462542150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2462542150
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.177199393
Short name T1045
Test name
Test status
Simulation time 44766804 ps
CPU time 0.73 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 205704 kb
Host smart-b2bbd8ec-5ddb-4afe-8a76-f0f004c5da0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177199393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.177199393
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3701061464
Short name T1027
Test name
Test status
Simulation time 12357053 ps
CPU time 0.73 seconds
Started Jun 22 04:47:14 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 205700 kb
Host smart-ac4f2ee2-ae24-422d-92b6-634f4441100a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701061464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3701061464
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1003567901
Short name T919
Test name
Test status
Simulation time 32929665 ps
CPU time 0.77 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 205924 kb
Host smart-917c88da-6169-4aa4-bee2-2f5e70e5d0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003567901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1003567901
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3994267780
Short name T927
Test name
Test status
Simulation time 32241076 ps
CPU time 0.72 seconds
Started Jun 22 04:47:29 PM PDT 24
Finished Jun 22 04:47:30 PM PDT 24
Peak memory 205688 kb
Host smart-ca2f8919-176a-4826-814f-6cd9fab43cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994267780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3994267780
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1198230389
Short name T1061
Test name
Test status
Simulation time 518553743 ps
CPU time 8.11 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:47:03 PM PDT 24
Peak memory 206284 kb
Host smart-b8ad3d63-0397-4044-9a58-d8e16d95e54c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198230389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
198230389
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2280797110
Short name T374
Test name
Test status
Simulation time 1123781352 ps
CPU time 15.77 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:47:10 PM PDT 24
Peak memory 205900 kb
Host smart-0c3b5290-8f05-4725-9bf7-cdfd1d161494
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280797110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
280797110
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.551700448
Short name T1056
Test name
Test status
Simulation time 20585843 ps
CPU time 1.13 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 206044 kb
Host smart-7cbb9f92-4fbb-490b-9b4d-5f8d09942411
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551700448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.551700448
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3505727977
Short name T947
Test name
Test status
Simulation time 59959689 ps
CPU time 1.08 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:53 PM PDT 24
Peak memory 205856 kb
Host smart-d8c2eef9-08b2-4176-9e29-246a4fad015b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505727977 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3505727977
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.496296440
Short name T1070
Test name
Test status
Simulation time 111083883 ps
CPU time 1.13 seconds
Started Jun 22 04:46:55 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 206044 kb
Host smart-5887948d-90d4-422d-9954-c62ce03c52cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496296440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.496296440
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2462233167
Short name T922
Test name
Test status
Simulation time 22106515 ps
CPU time 0.73 seconds
Started Jun 22 04:46:55 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 205700 kb
Host smart-db921712-138f-4503-9c3e-deccd6539c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462233167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2462233167
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2202845951
Short name T974
Test name
Test status
Simulation time 136816328 ps
CPU time 2.45 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 205900 kb
Host smart-5d92d1d4-7624-4060-b897-9859b74bf0be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202845951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2202845951
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3970454971
Short name T1053
Test name
Test status
Simulation time 451258307 ps
CPU time 3.66 seconds
Started Jun 22 04:46:51 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 214496 kb
Host smart-ce6b2261-7ea4-405f-936f-7d43c5de8418
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970454971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3970454971
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4006417317
Short name T970
Test name
Test status
Simulation time 887062478 ps
CPU time 8.2 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 214408 kb
Host smart-d3929a71-7b68-4413-b556-ed58ebd33909
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006417317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4006417317
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2330085044
Short name T950
Test name
Test status
Simulation time 100843033 ps
CPU time 2.22 seconds
Started Jun 22 04:46:58 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 214080 kb
Host smart-d87f89bb-59bb-4912-b001-b7a7208a82d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330085044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2330085044
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3419156581
Short name T167
Test name
Test status
Simulation time 98215567 ps
CPU time 5.1 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 214172 kb
Host smart-a747d4c6-e354-4cd0-90a3-75babbb3d1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419156581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3419156581
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1927117668
Short name T965
Test name
Test status
Simulation time 30628477 ps
CPU time 0.76 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:16 PM PDT 24
Peak memory 205584 kb
Host smart-ac186b97-b84c-4c39-b2e1-85f7083c1d6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927117668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1927117668
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.474608740
Short name T973
Test name
Test status
Simulation time 50000480 ps
CPU time 0.73 seconds
Started Jun 22 04:47:16 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 205624 kb
Host smart-ae990afc-e8a5-4888-b228-2b979079e5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474608740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.474608740
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1885114710
Short name T936
Test name
Test status
Simulation time 9564489 ps
CPU time 0.77 seconds
Started Jun 22 04:47:12 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 205692 kb
Host smart-3fc51ae9-c895-4814-9c44-ecf11a2056ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885114710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1885114710
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.183262575
Short name T986
Test name
Test status
Simulation time 18668646 ps
CPU time 0.89 seconds
Started Jun 22 04:47:14 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 205684 kb
Host smart-40c66604-725c-4c23-bd75-87d6e09b407a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183262575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.183262575
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2964692066
Short name T1047
Test name
Test status
Simulation time 10151517 ps
CPU time 0.83 seconds
Started Jun 22 04:47:30 PM PDT 24
Finished Jun 22 04:47:31 PM PDT 24
Peak memory 205616 kb
Host smart-3a07802d-7af8-4700-86ab-5694e03206de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964692066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2964692066
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3597655092
Short name T1032
Test name
Test status
Simulation time 18604411 ps
CPU time 0.85 seconds
Started Jun 22 04:47:14 PM PDT 24
Finished Jun 22 04:47:15 PM PDT 24
Peak memory 205620 kb
Host smart-945789fa-2f05-40ef-9855-798ca8a7a5ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597655092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3597655092
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1049743602
Short name T1018
Test name
Test status
Simulation time 84125334 ps
CPU time 0.81 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 205568 kb
Host smart-c9c1c9ca-9540-45b7-a674-66dfd360a709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049743602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1049743602
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1494868734
Short name T1063
Test name
Test status
Simulation time 41074957 ps
CPU time 0.85 seconds
Started Jun 22 04:47:13 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 205700 kb
Host smart-608c1a94-57ac-4e84-99db-ebe800b7fff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494868734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1494868734
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.105030953
Short name T932
Test name
Test status
Simulation time 25609389 ps
CPU time 0.76 seconds
Started Jun 22 04:47:15 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 205928 kb
Host smart-2292f8de-e82c-4913-9143-d04082758986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105030953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.105030953
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2408351738
Short name T1007
Test name
Test status
Simulation time 37741925 ps
CPU time 0.82 seconds
Started Jun 22 04:47:17 PM PDT 24
Finished Jun 22 04:47:19 PM PDT 24
Peak memory 205684 kb
Host smart-d29766bd-2552-41db-92ac-df19114478e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408351738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2408351738
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4267987445
Short name T375
Test name
Test status
Simulation time 60447143 ps
CPU time 1.47 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:55 PM PDT 24
Peak memory 216992 kb
Host smart-7ce00425-3903-4ef0-8fe8-83f09fee623e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267987445 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.4267987445
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.228019206
Short name T956
Test name
Test status
Simulation time 13593762 ps
CPU time 1.09 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 205848 kb
Host smart-1361a2e1-df2f-481a-afad-3f225fe58115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228019206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.228019206
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1336505122
Short name T1010
Test name
Test status
Simulation time 113376517 ps
CPU time 0.89 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 205588 kb
Host smart-a549b747-ae64-45e2-81f0-d9ab701b19c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336505122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1336505122
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.933479469
Short name T1075
Test name
Test status
Simulation time 90910468 ps
CPU time 1.51 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 205956 kb
Host smart-4193a4dc-db9f-40e8-9799-712b3ae09f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933479469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.933479469
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1803530088
Short name T949
Test name
Test status
Simulation time 96489652 ps
CPU time 2.48 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 219452 kb
Host smart-3052d366-6814-46cb-a4dd-b14ed2bc27ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803530088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1803530088
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2683952586
Short name T975
Test name
Test status
Simulation time 773028069 ps
CPU time 5.03 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 214520 kb
Host smart-7d04598f-4ec0-4c3f-bb56-a2e0eaf10b96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683952586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2683952586
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.4232351548
Short name T952
Test name
Test status
Simulation time 243452625 ps
CPU time 3.14 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 214156 kb
Host smart-9611bf92-1ee2-460a-aa28-c24687a27973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232351548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.4232351548
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.473752841
Short name T164
Test name
Test status
Simulation time 2406042483 ps
CPU time 9.43 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 206052 kb
Host smart-a340f07f-7e47-4122-bef8-f24d38133ade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473752841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
473752841
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3721951365
Short name T985
Test name
Test status
Simulation time 171364544 ps
CPU time 1.96 seconds
Started Jun 22 04:46:57 PM PDT 24
Finished Jun 22 04:47:00 PM PDT 24
Peak memory 214240 kb
Host smart-35778c21-a52d-4251-876c-8584f8e43501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721951365 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3721951365
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1839807590
Short name T1079
Test name
Test status
Simulation time 17152776 ps
CPU time 1.06 seconds
Started Jun 22 04:46:57 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 205912 kb
Host smart-3f0097e6-32c2-4ac6-936a-b281e0b9bd7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839807590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1839807590
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1308741241
Short name T1041
Test name
Test status
Simulation time 19982530 ps
CPU time 0.93 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 205824 kb
Host smart-803ba3ee-d17b-48a0-bcad-d770e3c4232f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308741241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1308741241
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1623263029
Short name T144
Test name
Test status
Simulation time 106707340 ps
CPU time 1.3 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:55 PM PDT 24
Peak memory 205924 kb
Host smart-b4879729-ed79-4089-9b28-7c3326970c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623263029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1623263029
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3312057440
Short name T1048
Test name
Test status
Simulation time 682371765 ps
CPU time 2.83 seconds
Started Jun 22 04:46:57 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 214472 kb
Host smart-cb9910ea-088b-41a3-9dbe-787f0a5ce7a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312057440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3312057440
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3935141582
Short name T982
Test name
Test status
Simulation time 350554387 ps
CPU time 8.64 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 214484 kb
Host smart-13925cc0-e682-4165-b815-6afa4f898e80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935141582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3935141582
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2820052934
Short name T1080
Test name
Test status
Simulation time 68954575 ps
CPU time 2.51 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 217184 kb
Host smart-05de9da4-ae28-4adb-8091-814fe13025c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820052934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2820052934
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3891448899
Short name T1082
Test name
Test status
Simulation time 31140705 ps
CPU time 1.21 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 214164 kb
Host smart-4cfb31c4-0601-405a-805e-261d4d24d75a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891448899 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3891448899
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2880678102
Short name T376
Test name
Test status
Simulation time 105438269 ps
CPU time 0.93 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:54 PM PDT 24
Peak memory 205752 kb
Host smart-0aa85dfb-4118-40b5-ad15-5e56cfac95a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880678102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2880678102
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2221258348
Short name T930
Test name
Test status
Simulation time 21025329 ps
CPU time 0.73 seconds
Started Jun 22 04:46:57 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 205576 kb
Host smart-91eb6edb-a5f4-420d-a795-63fe939b4039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221258348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2221258348
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2474315990
Short name T1073
Test name
Test status
Simulation time 186170505 ps
CPU time 2.65 seconds
Started Jun 22 04:46:57 PM PDT 24
Finished Jun 22 04:47:01 PM PDT 24
Peak memory 205960 kb
Host smart-f346ce8d-7313-4628-83da-3fca1a4e29d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474315990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2474315990
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.328047168
Short name T998
Test name
Test status
Simulation time 153763771 ps
CPU time 1.93 seconds
Started Jun 22 04:46:56 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 214468 kb
Host smart-07d33383-103e-4c62-8c64-14ac822eed30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328047168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.328047168
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3577352063
Short name T105
Test name
Test status
Simulation time 282545106 ps
CPU time 4.81 seconds
Started Jun 22 04:46:56 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 214408 kb
Host smart-4f30be4e-ec94-4a5d-bc2d-17d4bd8eeaa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577352063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3577352063
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.202232971
Short name T1009
Test name
Test status
Simulation time 175299349 ps
CPU time 2.02 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 213976 kb
Host smart-7628016c-3fc7-4c6b-85d0-a108bcc38357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202232971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.202232971
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2719060418
Short name T180
Test name
Test status
Simulation time 515337006 ps
CPU time 4.84 seconds
Started Jun 22 04:46:56 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 205836 kb
Host smart-318b41dd-c33e-4fca-9290-e8bf82ca97ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719060418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2719060418
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2180161705
Short name T948
Test name
Test status
Simulation time 198267314 ps
CPU time 1.24 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 206136 kb
Host smart-d31e5626-b054-4d40-a495-94cc67ff6441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180161705 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2180161705
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1013755545
Short name T1039
Test name
Test status
Simulation time 46835113 ps
CPU time 1.06 seconds
Started Jun 22 04:46:57 PM PDT 24
Finished Jun 22 04:46:59 PM PDT 24
Peak memory 205984 kb
Host smart-844e5caa-ba9a-438a-9f78-d6adc9811808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013755545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1013755545
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3731425855
Short name T989
Test name
Test status
Simulation time 35675761 ps
CPU time 0.8 seconds
Started Jun 22 04:46:51 PM PDT 24
Finished Jun 22 04:46:53 PM PDT 24
Peak memory 205596 kb
Host smart-985ef742-3bc1-4e3e-bcc1-492766fc1ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731425855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3731425855
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3171942657
Short name T142
Test name
Test status
Simulation time 213033117 ps
CPU time 3.61 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 205904 kb
Host smart-ae83c0de-9aa7-4656-8370-5ad6b194fe4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171942657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3171942657
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1799339572
Short name T108
Test name
Test status
Simulation time 87428440 ps
CPU time 2.75 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 214412 kb
Host smart-578e99a1-83cd-487b-ab57-23c3e535f361
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799339572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1799339572
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.32108953
Short name T1044
Test name
Test status
Simulation time 1550127045 ps
CPU time 14.67 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 221748 kb
Host smart-a13a58de-1de3-4247-9900-c0adb229c86e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32108953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.32108953
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3308536158
Short name T926
Test name
Test status
Simulation time 88505611 ps
CPU time 3.32 seconds
Started Jun 22 04:46:52 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 214168 kb
Host smart-430fca4a-15b0-49b9-820e-cecadd47dbce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308536158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3308536158
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2967462636
Short name T182
Test name
Test status
Simulation time 437753082 ps
CPU time 2.58 seconds
Started Jun 22 04:46:55 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 214164 kb
Host smart-d61dd089-420d-45f4-b0d9-8fca1604e98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967462636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2967462636
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2604703744
Short name T1017
Test name
Test status
Simulation time 51933858 ps
CPU time 1.64 seconds
Started Jun 22 04:47:01 PM PDT 24
Finished Jun 22 04:47:04 PM PDT 24
Peak memory 214216 kb
Host smart-bdf2dfaa-41b1-43a7-a4c2-cf011a5d68bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604703744 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2604703744
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.670911732
Short name T1074
Test name
Test status
Simulation time 92426263 ps
CPU time 1.35 seconds
Started Jun 22 04:47:09 PM PDT 24
Finished Jun 22 04:47:11 PM PDT 24
Peak memory 205928 kb
Host smart-49dea550-127d-4aa6-b91f-ecaa0f1ceace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670911732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.670911732
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1678001143
Short name T1024
Test name
Test status
Simulation time 79562404 ps
CPU time 0.72 seconds
Started Jun 22 04:46:56 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 205728 kb
Host smart-30ca7fcb-c789-40f6-b49a-cd02cd861990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678001143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1678001143
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2569770418
Short name T148
Test name
Test status
Simulation time 65427555 ps
CPU time 2.38 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 206132 kb
Host smart-27436fbe-b3de-45a8-8f78-c7a9e272d501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569770418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2569770418
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.210452113
Short name T988
Test name
Test status
Simulation time 105288010 ps
CPU time 3.03 seconds
Started Jun 22 04:46:54 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 214488 kb
Host smart-dcf770c9-227f-4f69-a967-0dfc458c3210
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210452113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.210452113
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2603836336
Short name T977
Test name
Test status
Simulation time 78462522 ps
CPU time 3.32 seconds
Started Jun 22 04:46:53 PM PDT 24
Finished Jun 22 04:46:57 PM PDT 24
Peak memory 214480 kb
Host smart-3fe43f58-5e98-4709-8c1c-bb9a204b75c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603836336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2603836336
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3114572937
Short name T934
Test name
Test status
Simulation time 346571053 ps
CPU time 3.19 seconds
Started Jun 22 04:46:58 PM PDT 24
Finished Jun 22 04:47:02 PM PDT 24
Peak memory 214080 kb
Host smart-e857b805-4869-489d-ba49-94158fa42cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114572937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3114572937
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1769521136
Short name T639
Test name
Test status
Simulation time 36630269 ps
CPU time 0.82 seconds
Started Jun 22 06:02:22 PM PDT 24
Finished Jun 22 06:02:23 PM PDT 24
Peak memory 205928 kb
Host smart-5e8dafbb-434a-4296-9745-110b7ce87e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769521136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1769521136
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.553760276
Short name T236
Test name
Test status
Simulation time 90290421 ps
CPU time 3.71 seconds
Started Jun 22 06:02:22 PM PDT 24
Finished Jun 22 06:02:26 PM PDT 24
Peak memory 209084 kb
Host smart-91a28722-9eba-4e29-8e95-cdd435b9c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553760276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.553760276
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4043188093
Short name T902
Test name
Test status
Simulation time 31417522 ps
CPU time 2.05 seconds
Started Jun 22 06:02:14 PM PDT 24
Finished Jun 22 06:02:16 PM PDT 24
Peak memory 207980 kb
Host smart-8ddf4166-bac5-412d-b3d7-87046e1f872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043188093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4043188093
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.189090776
Short name T92
Test name
Test status
Simulation time 3075663078 ps
CPU time 11.35 seconds
Started Jun 22 06:02:14 PM PDT 24
Finished Jun 22 06:02:26 PM PDT 24
Peak memory 214424 kb
Host smart-ada51a44-198d-4a3c-8656-8bea1beecd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189090776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.189090776
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.786860360
Short name T90
Test name
Test status
Simulation time 66347672 ps
CPU time 2.36 seconds
Started Jun 22 06:02:17 PM PDT 24
Finished Jun 22 06:02:20 PM PDT 24
Peak memory 214248 kb
Host smart-18202e2f-78bf-4b9c-a36c-30f28e846e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786860360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.786860360
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2048677331
Short name T651
Test name
Test status
Simulation time 44587001 ps
CPU time 1.93 seconds
Started Jun 22 06:02:15 PM PDT 24
Finished Jun 22 06:02:17 PM PDT 24
Peak memory 219940 kb
Host smart-8775f81b-0847-40e6-9781-611a181595e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048677331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2048677331
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2178886683
Short name T544
Test name
Test status
Simulation time 158613641 ps
CPU time 3.04 seconds
Started Jun 22 06:02:15 PM PDT 24
Finished Jun 22 06:02:18 PM PDT 24
Peak memory 209884 kb
Host smart-e4c36c06-1a81-4d31-aada-f79d16b6c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178886683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2178886683
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2157825206
Short name T216
Test name
Test status
Simulation time 257313809 ps
CPU time 3.05 seconds
Started Jun 22 06:02:13 PM PDT 24
Finished Jun 22 06:02:17 PM PDT 24
Peak memory 206892 kb
Host smart-b45d07b5-faee-4d9e-a5e8-61302ba51505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157825206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2157825206
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2199231130
Short name T429
Test name
Test status
Simulation time 402281329 ps
CPU time 8.28 seconds
Started Jun 22 06:02:13 PM PDT 24
Finished Jun 22 06:02:21 PM PDT 24
Peak memory 208488 kb
Host smart-21fd821f-9dfc-4fd9-9ad5-a4035a704e6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199231130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2199231130
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3537420941
Short name T440
Test name
Test status
Simulation time 1078652484 ps
CPU time 6.24 seconds
Started Jun 22 06:02:14 PM PDT 24
Finished Jun 22 06:02:21 PM PDT 24
Peak memory 207812 kb
Host smart-274d80c4-f709-49d0-b1a4-d8a6bfcd883f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537420941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3537420941
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.95440461
Short name T515
Test name
Test status
Simulation time 266321631 ps
CPU time 4.99 seconds
Started Jun 22 06:02:14 PM PDT 24
Finished Jun 22 06:02:20 PM PDT 24
Peak memory 206976 kb
Host smart-b305d72b-3613-49f8-b1ba-fc25d883c363
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95440461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.95440461
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1511154996
Short name T627
Test name
Test status
Simulation time 46750673 ps
CPU time 1.4 seconds
Started Jun 22 06:02:20 PM PDT 24
Finished Jun 22 06:02:22 PM PDT 24
Peak memory 207660 kb
Host smart-520d30aa-63d6-4596-bc38-c611540deae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511154996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1511154996
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3704422386
Short name T575
Test name
Test status
Simulation time 142351229 ps
CPU time 3.49 seconds
Started Jun 22 06:02:14 PM PDT 24
Finished Jun 22 06:02:18 PM PDT 24
Peak memory 206800 kb
Host smart-d2c17d17-51ce-4942-a03e-fde1ed6c5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704422386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3704422386
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3489030115
Short name T643
Test name
Test status
Simulation time 2679865774 ps
CPU time 17.27 seconds
Started Jun 22 06:02:22 PM PDT 24
Finished Jun 22 06:02:40 PM PDT 24
Peak memory 208100 kb
Host smart-2d9630cb-1ef3-403a-98db-9ad7f0871880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489030115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3489030115
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.802037275
Short name T187
Test name
Test status
Simulation time 681015603 ps
CPU time 18.01 seconds
Started Jun 22 06:02:24 PM PDT 24
Finished Jun 22 06:02:42 PM PDT 24
Peak memory 222548 kb
Host smart-bf90fb9b-beae-40be-acc0-acba8e44fdb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802037275 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.802037275
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3057513835
Short name T297
Test name
Test status
Simulation time 1594336393 ps
CPU time 10.1 seconds
Started Jun 22 06:02:13 PM PDT 24
Finished Jun 22 06:02:23 PM PDT 24
Peak memory 219656 kb
Host smart-16c61e1b-52ee-46f2-9a94-c8c03cd0bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057513835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3057513835
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.385992810
Short name T904
Test name
Test status
Simulation time 60942816 ps
CPU time 3.04 seconds
Started Jun 22 06:02:19 PM PDT 24
Finished Jun 22 06:02:23 PM PDT 24
Peak memory 210436 kb
Host smart-57777550-22e7-4a9f-8065-d62b119744ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385992810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.385992810
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2491973245
Short name T118
Test name
Test status
Simulation time 40832486 ps
CPU time 0.76 seconds
Started Jun 22 06:02:33 PM PDT 24
Finished Jun 22 06:02:34 PM PDT 24
Peak memory 205928 kb
Host smart-77de025f-53ff-453c-b09d-0359da33b82d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491973245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2491973245
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.754806369
Short name T542
Test name
Test status
Simulation time 137338783 ps
CPU time 3.8 seconds
Started Jun 22 06:02:29 PM PDT 24
Finished Jun 22 06:02:33 PM PDT 24
Peak memory 222760 kb
Host smart-32046e74-7308-4fe7-84f9-11bf187ed356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754806369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.754806369
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2002686335
Short name T326
Test name
Test status
Simulation time 2733026878 ps
CPU time 30.06 seconds
Started Jun 22 06:02:31 PM PDT 24
Finished Jun 22 06:03:02 PM PDT 24
Peak memory 222504 kb
Host smart-c2436b48-a771-467f-a552-4c991d16875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002686335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2002686335
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1337664954
Short name T250
Test name
Test status
Simulation time 91550779 ps
CPU time 2.72 seconds
Started Jun 22 06:02:27 PM PDT 24
Finished Jun 22 06:02:30 PM PDT 24
Peak memory 222424 kb
Host smart-5daef4fc-ed13-4b92-bd30-f3c37acb6aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337664954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1337664954
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1552283363
Short name T466
Test name
Test status
Simulation time 244414795 ps
CPU time 3.2 seconds
Started Jun 22 06:02:27 PM PDT 24
Finished Jun 22 06:02:30 PM PDT 24
Peak memory 207588 kb
Host smart-5c104501-e56c-4a9a-8f8b-3a954a3ecdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552283363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1552283363
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2509886795
Short name T886
Test name
Test status
Simulation time 1505078688 ps
CPU time 10.7 seconds
Started Jun 22 06:02:24 PM PDT 24
Finished Jun 22 06:02:35 PM PDT 24
Peak memory 208436 kb
Host smart-2e259311-b1ab-4476-bed3-9cc396ce4c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509886795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2509886795
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2698134567
Short name T13
Test name
Test status
Simulation time 610229685 ps
CPU time 12.41 seconds
Started Jun 22 06:02:36 PM PDT 24
Finished Jun 22 06:02:49 PM PDT 24
Peak memory 235748 kb
Host smart-f8f5478c-6166-4e2a-8d8b-266cf6b65166
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698134567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2698134567
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1002283015
Short name T809
Test name
Test status
Simulation time 158092523 ps
CPU time 2.96 seconds
Started Jun 22 06:02:21 PM PDT 24
Finished Jun 22 06:02:24 PM PDT 24
Peak memory 206972 kb
Host smart-069689e0-0abb-42fc-83d0-fafbf8358444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002283015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1002283015
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3225496434
Short name T862
Test name
Test status
Simulation time 63402731 ps
CPU time 3.54 seconds
Started Jun 22 06:02:22 PM PDT 24
Finished Jun 22 06:02:26 PM PDT 24
Peak memory 208796 kb
Host smart-e10cba26-bed9-4fb2-8158-59bf2d455955
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225496434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3225496434
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1704735025
Short name T432
Test name
Test status
Simulation time 3305188098 ps
CPU time 48.82 seconds
Started Jun 22 06:02:23 PM PDT 24
Finished Jun 22 06:03:13 PM PDT 24
Peak memory 209156 kb
Host smart-53a275c3-59e7-4652-8f81-6cdd129ecd22
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704735025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1704735025
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3945892489
Short name T477
Test name
Test status
Simulation time 171189469 ps
CPU time 4.32 seconds
Started Jun 22 06:02:20 PM PDT 24
Finished Jun 22 06:02:24 PM PDT 24
Peak memory 208200 kb
Host smart-7d541b50-a134-4459-ae28-15e0259961bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945892489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3945892489
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3161070089
Short name T783
Test name
Test status
Simulation time 546997707 ps
CPU time 3.81 seconds
Started Jun 22 06:02:29 PM PDT 24
Finished Jun 22 06:02:33 PM PDT 24
Peak memory 218436 kb
Host smart-10c208b6-aa1c-4205-918e-5ed535ede22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161070089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3161070089
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1429000401
Short name T385
Test name
Test status
Simulation time 3065262552 ps
CPU time 19.41 seconds
Started Jun 22 06:02:21 PM PDT 24
Finished Jun 22 06:02:40 PM PDT 24
Peak memory 208152 kb
Host smart-a327dd95-3b97-47ad-bea6-badbb662556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429000401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1429000401
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2677193107
Short name T796
Test name
Test status
Simulation time 2118268054 ps
CPU time 17.38 seconds
Started Jun 22 06:02:31 PM PDT 24
Finished Jun 22 06:02:49 PM PDT 24
Peak memory 216180 kb
Host smart-677f180f-0318-4f85-943c-70d6b70ab290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677193107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2677193107
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.381857100
Short name T191
Test name
Test status
Simulation time 321310375 ps
CPU time 12.98 seconds
Started Jun 22 06:02:35 PM PDT 24
Finished Jun 22 06:02:48 PM PDT 24
Peak memory 219356 kb
Host smart-c58c6d3d-ce7f-4307-b01c-4bd6a2057be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381857100 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.381857100
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1989245786
Short name T435
Test name
Test status
Simulation time 207902541 ps
CPU time 2.64 seconds
Started Jun 22 06:02:28 PM PDT 24
Finished Jun 22 06:02:31 PM PDT 24
Peak memory 207504 kb
Host smart-5f0a1195-bd62-4ad7-b48c-50234db892b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989245786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1989245786
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3746283698
Short name T373
Test name
Test status
Simulation time 60775740 ps
CPU time 2.98 seconds
Started Jun 22 06:02:28 PM PDT 24
Finished Jun 22 06:02:31 PM PDT 24
Peak memory 210576 kb
Host smart-168cf32e-f531-40e7-bd56-e04a14b201b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746283698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3746283698
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3774283115
Short name T410
Test name
Test status
Simulation time 31093765 ps
CPU time 0.77 seconds
Started Jun 22 06:03:54 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 205940 kb
Host smart-6bf763d9-458d-4475-acbd-22c087b030f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774283115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3774283115
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.408957573
Short name T757
Test name
Test status
Simulation time 124617498 ps
CPU time 2.83 seconds
Started Jun 22 06:03:39 PM PDT 24
Finished Jun 22 06:03:43 PM PDT 24
Peak memory 214312 kb
Host smart-c8a2307d-dc6e-45f2-800e-28273c336010
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408957573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.408957573
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3526447284
Short name T754
Test name
Test status
Simulation time 266354493 ps
CPU time 3.09 seconds
Started Jun 22 06:03:43 PM PDT 24
Finished Jun 22 06:03:46 PM PDT 24
Peak memory 222788 kb
Host smart-3d746ac1-6f87-44ea-93eb-2bc458494641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526447284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3526447284
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2426090492
Short name T79
Test name
Test status
Simulation time 411972514 ps
CPU time 8.8 seconds
Started Jun 22 06:03:43 PM PDT 24
Finished Jun 22 06:03:52 PM PDT 24
Peak memory 208124 kb
Host smart-3c9e7849-1a2d-4add-9153-791ab8db62c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426090492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2426090492
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1329707390
Short name T57
Test name
Test status
Simulation time 60011725 ps
CPU time 3.17 seconds
Started Jun 22 06:03:41 PM PDT 24
Finished Jun 22 06:03:45 PM PDT 24
Peak memory 215728 kb
Host smart-d070ff12-a11b-4633-ae90-272cef2a82be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329707390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1329707390
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4051728123
Short name T702
Test name
Test status
Simulation time 203769014 ps
CPU time 7.82 seconds
Started Jun 22 06:03:39 PM PDT 24
Finished Jun 22 06:03:47 PM PDT 24
Peak memory 218216 kb
Host smart-212db237-e0d3-4a78-b324-6f0f5818e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051728123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4051728123
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.662487991
Short name T598
Test name
Test status
Simulation time 5357671634 ps
CPU time 21.31 seconds
Started Jun 22 06:03:38 PM PDT 24
Finished Jun 22 06:04:00 PM PDT 24
Peak memory 208452 kb
Host smart-73c43b05-4c1f-4c8c-b0e3-ebf0f77b1f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662487991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.662487991
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3200392259
Short name T490
Test name
Test status
Simulation time 296169852 ps
CPU time 2.25 seconds
Started Jun 22 06:03:41 PM PDT 24
Finished Jun 22 06:03:44 PM PDT 24
Peak memory 206928 kb
Host smart-d4f3d258-7f95-468f-8fbb-b733c1119e2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200392259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3200392259
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1424102280
Short name T333
Test name
Test status
Simulation time 103176921 ps
CPU time 4.27 seconds
Started Jun 22 06:03:37 PM PDT 24
Finished Jun 22 06:03:42 PM PDT 24
Peak memory 208652 kb
Host smart-ff12931b-93dc-470c-a813-cc12638f12df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424102280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1424102280
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.57056314
Short name T763
Test name
Test status
Simulation time 145670443 ps
CPU time 4.09 seconds
Started Jun 22 06:03:40 PM PDT 24
Finished Jun 22 06:03:45 PM PDT 24
Peak memory 208020 kb
Host smart-c838726a-d245-4059-a1d8-c85a75cb2b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57056314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.57056314
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.885277295
Short name T695
Test name
Test status
Simulation time 57279720 ps
CPU time 2.32 seconds
Started Jun 22 06:03:39 PM PDT 24
Finished Jun 22 06:03:42 PM PDT 24
Peak memory 206896 kb
Host smart-f17d5806-03a2-4947-9ede-0be3d31dc0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885277295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.885277295
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2588943232
Short name T113
Test name
Test status
Simulation time 77537302 ps
CPU time 5.65 seconds
Started Jun 22 06:03:39 PM PDT 24
Finished Jun 22 06:03:45 PM PDT 24
Peak memory 219224 kb
Host smart-632a1070-7e65-419b-a05a-399c870f7284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588943232 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2588943232
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1727762879
Short name T729
Test name
Test status
Simulation time 1298853018 ps
CPU time 29.38 seconds
Started Jun 22 06:03:38 PM PDT 24
Finished Jun 22 06:04:09 PM PDT 24
Peak memory 209340 kb
Host smart-f9d0b067-d936-4fb5-9e12-d6c5e90d0c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727762879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1727762879
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2093690297
Short name T371
Test name
Test status
Simulation time 77704260 ps
CPU time 3.35 seconds
Started Jun 22 06:03:42 PM PDT 24
Finished Jun 22 06:03:46 PM PDT 24
Peak memory 210116 kb
Host smart-765ef6da-9b75-4596-a6ef-3b57242d0da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093690297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2093690297
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1692540189
Short name T648
Test name
Test status
Simulation time 35074256 ps
CPU time 0.74 seconds
Started Jun 22 06:03:48 PM PDT 24
Finished Jun 22 06:03:50 PM PDT 24
Peak memory 205920 kb
Host smart-6f5ad638-cc03-4347-a6ca-5f4985d458ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692540189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1692540189
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.358556655
Short name T720
Test name
Test status
Simulation time 93497916 ps
CPU time 3.18 seconds
Started Jun 22 06:03:53 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 222800 kb
Host smart-2758cc5b-fcaa-41df-934b-f8a760cd9508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358556655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.358556655
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.339587415
Short name T677
Test name
Test status
Simulation time 82320613 ps
CPU time 1.66 seconds
Started Jun 22 06:03:48 PM PDT 24
Finished Jun 22 06:03:51 PM PDT 24
Peak memory 207676 kb
Host smart-7818320e-c226-4c70-acf4-f48df2023386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339587415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.339587415
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.134516786
Short name T907
Test name
Test status
Simulation time 486530060 ps
CPU time 7.3 seconds
Started Jun 22 06:03:52 PM PDT 24
Finished Jun 22 06:04:00 PM PDT 24
Peak memory 222452 kb
Host smart-b7105076-3404-4637-bd84-34e24badf995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134516786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.134516786
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1135939422
Short name T225
Test name
Test status
Simulation time 412630618 ps
CPU time 3.81 seconds
Started Jun 22 06:03:49 PM PDT 24
Finished Jun 22 06:03:54 PM PDT 24
Peak memory 214408 kb
Host smart-aaef418e-4ef8-497e-862c-84328eefde76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135939422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1135939422
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3936007372
Short name T572
Test name
Test status
Simulation time 301701651 ps
CPU time 4.57 seconds
Started Jun 22 06:03:51 PM PDT 24
Finished Jun 22 06:03:57 PM PDT 24
Peak memory 216104 kb
Host smart-0b27202a-f340-4b7a-afe6-0bd15658752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936007372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3936007372
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.322577638
Short name T541
Test name
Test status
Simulation time 69778937 ps
CPU time 3.48 seconds
Started Jun 22 06:03:54 PM PDT 24
Finished Jun 22 06:03:58 PM PDT 24
Peak memory 208608 kb
Host smart-8f273576-ca04-422f-87ca-092ef5c37e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322577638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.322577638
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.815931411
Short name T474
Test name
Test status
Simulation time 96014222 ps
CPU time 3.55 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:54 PM PDT 24
Peak memory 206852 kb
Host smart-f7b74f01-7f28-4a12-9cbb-37005b5500a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815931411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.815931411
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.677447404
Short name T772
Test name
Test status
Simulation time 41654817 ps
CPU time 2.38 seconds
Started Jun 22 06:03:48 PM PDT 24
Finished Jun 22 06:03:51 PM PDT 24
Peak memory 206944 kb
Host smart-1741a152-112f-415f-a291-b6086453adf3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677447404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.677447404
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.332045994
Short name T527
Test name
Test status
Simulation time 211043953 ps
CPU time 4.49 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:55 PM PDT 24
Peak memory 208456 kb
Host smart-42174b78-2fb0-40db-b928-16ed7135fe49
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332045994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.332045994
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1560366789
Short name T258
Test name
Test status
Simulation time 111790645 ps
CPU time 3.43 seconds
Started Jun 22 06:03:52 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 210248 kb
Host smart-b51c0b70-d76e-4762-9534-5ef59dd79434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560366789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1560366789
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1955982896
Short name T543
Test name
Test status
Simulation time 379447476 ps
CPU time 2.95 seconds
Started Jun 22 06:03:48 PM PDT 24
Finished Jun 22 06:03:51 PM PDT 24
Peak memory 208472 kb
Host smart-dba5f798-fc64-4b3b-ba79-10def456538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955982896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1955982896
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3376553746
Short name T587
Test name
Test status
Simulation time 314832456 ps
CPU time 8.77 seconds
Started Jun 22 06:03:52 PM PDT 24
Finished Jun 22 06:04:01 PM PDT 24
Peak memory 208800 kb
Host smart-07190ff0-65e0-498f-93a7-3967d8bdf6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376553746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3376553746
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2324294969
Short name T792
Test name
Test status
Simulation time 28969869 ps
CPU time 1.73 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 209948 kb
Host smart-d7ac3545-46c4-4a9e-92b9-e44d3dc624ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324294969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2324294969
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1433127894
Short name T433
Test name
Test status
Simulation time 15721313 ps
CPU time 0.92 seconds
Started Jun 22 06:03:58 PM PDT 24
Finished Jun 22 06:03:59 PM PDT 24
Peak memory 206096 kb
Host smart-fafe6088-f9b6-40d9-bc5f-10958917ad08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433127894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1433127894
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3393516803
Short name T777
Test name
Test status
Simulation time 175431260 ps
CPU time 3.72 seconds
Started Jun 22 06:03:51 PM PDT 24
Finished Jun 22 06:03:55 PM PDT 24
Peak memory 215532 kb
Host smart-a873b550-379c-4bda-ad21-c26c579c2b79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393516803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3393516803
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2014490330
Short name T782
Test name
Test status
Simulation time 391531788 ps
CPU time 3.28 seconds
Started Jun 22 06:03:49 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 208032 kb
Host smart-3e3b9d33-f24e-44f8-9e30-038401834863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014490330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2014490330
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3977887656
Short name T87
Test name
Test status
Simulation time 55760722 ps
CPU time 2.82 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:54 PM PDT 24
Peak memory 209344 kb
Host smart-27411781-40cd-4bde-8d1a-80deea379742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977887656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3977887656
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3718551569
Short name T285
Test name
Test status
Simulation time 29010153 ps
CPU time 1.9 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 214348 kb
Host smart-d8df087c-008b-4b89-bf00-eebb422f9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718551569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3718551569
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1648554337
Short name T235
Test name
Test status
Simulation time 70369279 ps
CPU time 3.12 seconds
Started Jun 22 06:03:51 PM PDT 24
Finished Jun 22 06:03:55 PM PDT 24
Peak memory 214312 kb
Host smart-5de1a213-ee8c-4009-a8af-21ae9d6199e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648554337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1648554337
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1318005176
Short name T877
Test name
Test status
Simulation time 121748009 ps
CPU time 2.47 seconds
Started Jun 22 06:03:50 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 206944 kb
Host smart-2b341b24-b103-4e8a-a5cd-9deb81481f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318005176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1318005176
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2111483051
Short name T569
Test name
Test status
Simulation time 192443982 ps
CPU time 6.69 seconds
Started Jun 22 06:03:49 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 208884 kb
Host smart-6fe35cf0-02f8-49a4-a5a7-efd63ce8e999
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111483051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2111483051
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1009725547
Short name T135
Test name
Test status
Simulation time 2210674166 ps
CPU time 5.58 seconds
Started Jun 22 06:03:52 PM PDT 24
Finished Jun 22 06:03:58 PM PDT 24
Peak memory 208056 kb
Host smart-b396d92b-f38b-4a39-9a7b-df055f3b4d74
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009725547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1009725547
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.62281279
Short name T745
Test name
Test status
Simulation time 454468573 ps
CPU time 3.29 seconds
Started Jun 22 06:03:48 PM PDT 24
Finished Jun 22 06:03:52 PM PDT 24
Peak memory 215104 kb
Host smart-96861ba5-f91f-426b-a511-561d88c9dc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62281279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.62281279
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.579094141
Short name T488
Test name
Test status
Simulation time 162053081 ps
CPU time 3.11 seconds
Started Jun 22 06:03:49 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 208024 kb
Host smart-3954b6d1-504c-489a-86f3-5619893fc0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579094141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.579094141
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3799314327
Short name T856
Test name
Test status
Simulation time 193041370 ps
CPU time 7.67 seconds
Started Jun 22 06:03:56 PM PDT 24
Finished Jun 22 06:04:04 PM PDT 24
Peak memory 218172 kb
Host smart-eca1c011-3f64-4683-9773-a034a8a7f814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799314327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3799314327
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.835163948
Short name T634
Test name
Test status
Simulation time 1026819989 ps
CPU time 34.57 seconds
Started Jun 22 06:03:49 PM PDT 24
Finished Jun 22 06:04:24 PM PDT 24
Peak memory 214304 kb
Host smart-d9e42fb5-7e3c-45c6-a7da-7637119a1ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835163948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.835163948
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4050215325
Short name T547
Test name
Test status
Simulation time 129879656 ps
CPU time 2.53 seconds
Started Jun 22 06:03:48 PM PDT 24
Finished Jun 22 06:03:50 PM PDT 24
Peak memory 210040 kb
Host smart-8ac1944f-f4f2-4b1c-8b31-655ea548376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050215325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4050215325
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1611521683
Short name T750
Test name
Test status
Simulation time 36191711 ps
CPU time 0.79 seconds
Started Jun 22 06:03:57 PM PDT 24
Finished Jun 22 06:03:58 PM PDT 24
Peak memory 205928 kb
Host smart-a514d583-62cb-4707-8ca1-da84f717c079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611521683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1611521683
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.949677633
Short name T150
Test name
Test status
Simulation time 4480978299 ps
CPU time 61.52 seconds
Started Jun 22 06:03:57 PM PDT 24
Finished Jun 22 06:04:59 PM PDT 24
Peak memory 222060 kb
Host smart-06e1b7fa-0dbf-4dd6-ae91-f3a04e23048c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949677633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.949677633
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3510795046
Short name T468
Test name
Test status
Simulation time 157440072 ps
CPU time 1.5 seconds
Started Jun 22 06:03:54 PM PDT 24
Finished Jun 22 06:03:56 PM PDT 24
Peak memory 222780 kb
Host smart-fc6e9cfa-e82f-4bd2-a5c3-57291bc6a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510795046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3510795046
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1177587681
Short name T626
Test name
Test status
Simulation time 1022726888 ps
CPU time 6.04 seconds
Started Jun 22 06:03:53 PM PDT 24
Finished Jun 22 06:04:00 PM PDT 24
Peak memory 218288 kb
Host smart-075c4e8e-e220-45e4-917e-2db564235d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177587681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1177587681
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2908530719
Short name T309
Test name
Test status
Simulation time 81767927 ps
CPU time 4.41 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 209628 kb
Host smart-2fdbaf4b-df43-41d7-a20c-e509130139aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908530719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2908530719
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3311748715
Short name T237
Test name
Test status
Simulation time 67706133 ps
CPU time 4.58 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 222384 kb
Host smart-0970cd7f-7cd2-4bc1-855c-f4bcf6b6a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311748715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3311748715
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3014840944
Short name T744
Test name
Test status
Simulation time 1053233808 ps
CPU time 12.35 seconds
Started Jun 22 06:03:56 PM PDT 24
Finished Jun 22 06:04:09 PM PDT 24
Peak memory 208776 kb
Host smart-c7ce5bec-3aa2-487b-88ef-3756521602e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014840944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3014840944
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3481246359
Short name T320
Test name
Test status
Simulation time 37444980 ps
CPU time 2.65 seconds
Started Jun 22 06:03:56 PM PDT 24
Finished Jun 22 06:04:00 PM PDT 24
Peak memory 208628 kb
Host smart-c0996305-6f43-4ec9-9f2b-d2b78edc91de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481246359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3481246359
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2134097533
Short name T641
Test name
Test status
Simulation time 269918120 ps
CPU time 3.33 seconds
Started Jun 22 06:03:56 PM PDT 24
Finished Jun 22 06:04:00 PM PDT 24
Peak memory 208644 kb
Host smart-a7c4d5a3-4796-44e0-937f-30e73bbc21d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134097533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2134097533
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.378878528
Short name T632
Test name
Test status
Simulation time 71879050 ps
CPU time 3.35 seconds
Started Jun 22 06:03:59 PM PDT 24
Finished Jun 22 06:04:02 PM PDT 24
Peak memory 206596 kb
Host smart-ae4fac6f-10c0-4fc8-ba94-d3fbe0e5f646
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378878528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.378878528
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1246479924
Short name T457
Test name
Test status
Simulation time 1862896625 ps
CPU time 23.91 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:27 PM PDT 24
Peak memory 208024 kb
Host smart-ab0cf83e-ce8d-4b59-af90-d89dce520a5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246479924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1246479924
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3709142338
Short name T778
Test name
Test status
Simulation time 128637768 ps
CPU time 1.95 seconds
Started Jun 22 06:04:05 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 207744 kb
Host smart-f19fe622-1b3d-48aa-ac92-ed625f7635fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709142338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3709142338
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.28930798
Short name T675
Test name
Test status
Simulation time 2499232407 ps
CPU time 23.21 seconds
Started Jun 22 06:03:57 PM PDT 24
Finished Jun 22 06:04:20 PM PDT 24
Peak memory 207964 kb
Host smart-7f222582-e1cd-483d-8de8-2f1d80709c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28930798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.28930798
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4121194398
Short name T829
Test name
Test status
Simulation time 1579617477 ps
CPU time 14.47 seconds
Started Jun 22 06:03:55 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 216436 kb
Host smart-865e4c03-d989-44b0-bd0c-26c4f80bfdf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121194398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4121194398
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2272172458
Short name T517
Test name
Test status
Simulation time 615055826 ps
CPU time 1.74 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:06 PM PDT 24
Peak memory 209732 kb
Host smart-b2d64f0b-ab56-461e-9e79-f3aa47233efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272172458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2272172458
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3207920132
Short name T17
Test name
Test status
Simulation time 45873368 ps
CPU time 0.78 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:05 PM PDT 24
Peak memory 205920 kb
Host smart-60422398-b978-482f-9cde-289a5a6503b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207920132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3207920132
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3996213332
Short name T507
Test name
Test status
Simulation time 45019696 ps
CPU time 2.33 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:07 PM PDT 24
Peak memory 207424 kb
Host smart-d99b4d26-2d05-4396-93cf-157894b8f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996213332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3996213332
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3383804978
Short name T885
Test name
Test status
Simulation time 135707903 ps
CPU time 2.37 seconds
Started Jun 22 06:04:02 PM PDT 24
Finished Jun 22 06:04:04 PM PDT 24
Peak memory 214332 kb
Host smart-38413fe0-882d-4ee3-962f-68b4a290778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383804978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3383804978
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.487369167
Short name T296
Test name
Test status
Simulation time 375982462 ps
CPU time 3.16 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:07 PM PDT 24
Peak memory 214208 kb
Host smart-eebb00d8-6754-4d1f-8a13-e489620826eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487369167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.487369167
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2016372631
Short name T583
Test name
Test status
Simulation time 721348414 ps
CPU time 4.13 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 208740 kb
Host smart-df0b1052-244d-4707-8c26-0eeda6284e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016372631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2016372631
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.801774938
Short name T276
Test name
Test status
Simulation time 124812321 ps
CPU time 5.35 seconds
Started Jun 22 06:04:05 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 214548 kb
Host smart-d7c790b9-0235-423b-a8ef-513797216731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801774938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.801774938
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4094816572
Short name T637
Test name
Test status
Simulation time 112595333 ps
CPU time 3.81 seconds
Started Jun 22 06:04:06 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 208220 kb
Host smart-eb0d7e87-f11a-4c5c-b7ec-23cb298e00ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094816572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4094816572
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.333300557
Short name T441
Test name
Test status
Simulation time 7226332399 ps
CPU time 53.15 seconds
Started Jun 22 06:04:05 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 208112 kb
Host smart-344b85db-6a4a-453f-a7cf-8d9c67cf25d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333300557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.333300557
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.588926381
Short name T690
Test name
Test status
Simulation time 99048419 ps
CPU time 3.23 seconds
Started Jun 22 06:04:06 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 207868 kb
Host smart-d6bf6b43-514d-4587-9273-50a3e51c3c26
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588926381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.588926381
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1319209777
Short name T130
Test name
Test status
Simulation time 677247954 ps
CPU time 6.63 seconds
Started Jun 22 06:04:05 PM PDT 24
Finished Jun 22 06:04:12 PM PDT 24
Peak memory 207868 kb
Host smart-ae4671d3-15a1-4baa-9b78-22ac13ea47f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319209777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1319209777
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2328807375
Short name T194
Test name
Test status
Simulation time 74167209 ps
CPU time 3.27 seconds
Started Jun 22 06:04:06 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 215996 kb
Host smart-e682af47-815f-4dfa-8305-b6cfdb4f08e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328807375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2328807375
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.100093230
Short name T635
Test name
Test status
Simulation time 1170056903 ps
CPU time 3.29 seconds
Started Jun 22 06:04:04 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 208572 kb
Host smart-6b57db47-04d4-4e42-868c-e2df9b88544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100093230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.100093230
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.796491729
Short name T794
Test name
Test status
Simulation time 184924430 ps
CPU time 6.85 seconds
Started Jun 22 06:04:06 PM PDT 24
Finished Jun 22 06:04:13 PM PDT 24
Peak memory 207588 kb
Host smart-f9099e4f-c45b-45be-8dac-a0792467982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796491729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.796491729
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.773979716
Short name T367
Test name
Test status
Simulation time 77687266 ps
CPU time 2.69 seconds
Started Jun 22 06:04:02 PM PDT 24
Finished Jun 22 06:04:05 PM PDT 24
Peak memory 209916 kb
Host smart-e4e78f3c-9bf6-4944-99c5-1448732c28f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773979716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.773979716
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4221422490
Short name T582
Test name
Test status
Simulation time 32215129 ps
CPU time 0.73 seconds
Started Jun 22 06:04:15 PM PDT 24
Finished Jun 22 06:04:16 PM PDT 24
Peak memory 205908 kb
Host smart-f2367e44-4813-4258-b3e9-96c86c453bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221422490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4221422490
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1970414837
Short name T681
Test name
Test status
Simulation time 62450900 ps
CPU time 4.52 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:09 PM PDT 24
Peak memory 214468 kb
Host smart-c706958e-8baf-4e14-b795-177016024db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970414837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1970414837
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.206040251
Short name T72
Test name
Test status
Simulation time 70602197 ps
CPU time 3.33 seconds
Started Jun 22 06:04:14 PM PDT 24
Finished Jun 22 06:04:18 PM PDT 24
Peak memory 214576 kb
Host smart-82f75716-520f-485a-ad05-b7330439be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206040251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.206040251
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.978532389
Short name T247
Test name
Test status
Simulation time 103459313 ps
CPU time 2.59 seconds
Started Jun 22 06:04:06 PM PDT 24
Finished Jun 22 06:04:09 PM PDT 24
Peak memory 208200 kb
Host smart-faf53ee2-a651-4b48-9100-2c835f5859c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978532389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.978532389
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.39739896
Short name T823
Test name
Test status
Simulation time 78232241 ps
CPU time 2.72 seconds
Started Jun 22 06:04:09 PM PDT 24
Finished Jun 22 06:04:12 PM PDT 24
Peak memory 214528 kb
Host smart-295ae28a-f879-4841-9bc9-9f15ef6448a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39739896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.39739896
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1230036415
Short name T915
Test name
Test status
Simulation time 71265463 ps
CPU time 3.27 seconds
Started Jun 22 06:04:11 PM PDT 24
Finished Jun 22 06:04:15 PM PDT 24
Peak memory 214332 kb
Host smart-04f033f0-d5f7-4513-bbef-682848863add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230036415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1230036415
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2733346642
Short name T887
Test name
Test status
Simulation time 332508068 ps
CPU time 4.36 seconds
Started Jun 22 06:04:10 PM PDT 24
Finished Jun 22 06:04:15 PM PDT 24
Peak memory 214312 kb
Host smart-1d4fed70-5729-40e1-a9ec-dd7ebfcb37ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733346642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2733346642
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2521047525
Short name T747
Test name
Test status
Simulation time 262971077 ps
CPU time 4.88 seconds
Started Jun 22 06:04:05 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 208660 kb
Host smart-ab9d4afb-7646-4402-9ef2-aeb0f1e529d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521047525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2521047525
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4135394578
Short name T903
Test name
Test status
Simulation time 440089106 ps
CPU time 3.07 seconds
Started Jun 22 06:04:04 PM PDT 24
Finished Jun 22 06:04:08 PM PDT 24
Peak memory 206956 kb
Host smart-79370086-e233-456a-9514-1c948df17be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135394578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4135394578
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2143237365
Short name T444
Test name
Test status
Simulation time 191832747 ps
CPU time 5.09 seconds
Started Jun 22 06:04:05 PM PDT 24
Finished Jun 22 06:04:10 PM PDT 24
Peak memory 209024 kb
Host smart-36dacf31-00de-4f69-9550-68d2f408a4f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143237365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2143237365
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1968936027
Short name T213
Test name
Test status
Simulation time 438543330 ps
CPU time 4.6 seconds
Started Jun 22 06:04:06 PM PDT 24
Finished Jun 22 06:04:11 PM PDT 24
Peak memory 209060 kb
Host smart-c6c73024-349f-4c8a-ab81-7a608af8ca7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968936027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1968936027
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2438656541
Short name T602
Test name
Test status
Simulation time 58566970 ps
CPU time 3.14 seconds
Started Jun 22 06:04:02 PM PDT 24
Finished Jun 22 06:04:06 PM PDT 24
Peak memory 206868 kb
Host smart-a5b9a26c-6973-47e0-8070-041c1f2879e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438656541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2438656541
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.211139937
Short name T301
Test name
Test status
Simulation time 654915230 ps
CPU time 15.64 seconds
Started Jun 22 06:04:11 PM PDT 24
Finished Jun 22 06:04:27 PM PDT 24
Peak memory 214308 kb
Host smart-8c1fd167-c7b1-4af8-9ec3-ea5b2a811a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211139937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.211139937
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.464420902
Short name T380
Test name
Test status
Simulation time 39146254 ps
CPU time 2.27 seconds
Started Jun 22 06:04:03 PM PDT 24
Finished Jun 22 06:04:07 PM PDT 24
Peak memory 206900 kb
Host smart-b85cb31e-bc8f-4308-959b-f8ee40c0f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464420902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.464420902
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.133201622
Short name T850
Test name
Test status
Simulation time 8189810270 ps
CPU time 61.77 seconds
Started Jun 22 06:04:11 PM PDT 24
Finished Jun 22 06:05:14 PM PDT 24
Peak memory 221268 kb
Host smart-ad9c4f3b-297f-48c4-b2df-96318f6b534f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133201622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.133201622
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4242138828
Short name T355
Test name
Test status
Simulation time 97236917 ps
CPU time 4.39 seconds
Started Jun 22 06:04:15 PM PDT 24
Finished Jun 22 06:04:20 PM PDT 24
Peak memory 208900 kb
Host smart-7d689183-3873-42dd-be76-881b0acb3ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242138828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4242138828
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1447702505
Short name T618
Test name
Test status
Simulation time 701216010 ps
CPU time 2.27 seconds
Started Jun 22 06:04:09 PM PDT 24
Finished Jun 22 06:04:12 PM PDT 24
Peak memory 210204 kb
Host smart-27df00e3-3cd4-44a2-9b84-59ed9994509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447702505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1447702505
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2832797949
Short name T642
Test name
Test status
Simulation time 15460224 ps
CPU time 0.87 seconds
Started Jun 22 06:04:19 PM PDT 24
Finished Jun 22 06:04:21 PM PDT 24
Peak memory 205928 kb
Host smart-1847aeb6-481a-4877-98c7-871d44018df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832797949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2832797949
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3986900856
Short name T377
Test name
Test status
Simulation time 32477300 ps
CPU time 2.95 seconds
Started Jun 22 06:04:12 PM PDT 24
Finished Jun 22 06:04:16 PM PDT 24
Peak memory 214320 kb
Host smart-8970ed2c-b9a8-48e6-9f15-6e9dba275db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986900856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3986900856
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2843674737
Short name T248
Test name
Test status
Simulation time 48178350 ps
CPU time 1.75 seconds
Started Jun 22 06:04:14 PM PDT 24
Finished Jun 22 06:04:17 PM PDT 24
Peak memory 207148 kb
Host smart-0a34ceec-17b3-4dd2-a66b-fc5d013779c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843674737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2843674737
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2757220619
Short name T462
Test name
Test status
Simulation time 45421647 ps
CPU time 2.48 seconds
Started Jun 22 06:04:12 PM PDT 24
Finished Jun 22 06:04:15 PM PDT 24
Peak memory 206048 kb
Host smart-60bb08f8-c946-4154-bdbf-009e040d3ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757220619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2757220619
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.415020845
Short name T629
Test name
Test status
Simulation time 99683762 ps
CPU time 3.31 seconds
Started Jun 22 06:04:14 PM PDT 24
Finished Jun 22 06:04:18 PM PDT 24
Peak memory 214396 kb
Host smart-58fbf536-35e3-468b-9897-6b00160ed302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415020845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.415020845
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3235083614
Short name T528
Test name
Test status
Simulation time 803071328 ps
CPU time 9.85 seconds
Started Jun 22 06:04:13 PM PDT 24
Finished Jun 22 06:04:23 PM PDT 24
Peak memory 209684 kb
Host smart-46d5e064-cbdf-4832-920d-a586f25d11be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235083614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3235083614
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1216496073
Short name T727
Test name
Test status
Simulation time 48167847 ps
CPU time 2.41 seconds
Started Jun 22 06:04:10 PM PDT 24
Finished Jun 22 06:04:13 PM PDT 24
Peak memory 208008 kb
Host smart-ba8295c8-07c4-4ae0-b949-4660cd83a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216496073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1216496073
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3892272178
Short name T610
Test name
Test status
Simulation time 381599336 ps
CPU time 3.71 seconds
Started Jun 22 06:04:11 PM PDT 24
Finished Jun 22 06:04:15 PM PDT 24
Peak memory 208740 kb
Host smart-1605faec-d70b-47cd-93d4-595a828a9e17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892272178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3892272178
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2984291583
Short name T447
Test name
Test status
Simulation time 935181496 ps
CPU time 22.22 seconds
Started Jun 22 06:04:15 PM PDT 24
Finished Jun 22 06:04:38 PM PDT 24
Peak memory 207988 kb
Host smart-f302a5c7-2035-430f-b396-55f2ac2929e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984291583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2984291583
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3122608008
Short name T561
Test name
Test status
Simulation time 179786623 ps
CPU time 5.06 seconds
Started Jun 22 06:04:13 PM PDT 24
Finished Jun 22 06:04:19 PM PDT 24
Peak memory 208520 kb
Host smart-3bc25243-be44-40da-8ccd-cfcc881dd952
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122608008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3122608008
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1432331127
Short name T401
Test name
Test status
Simulation time 323649118 ps
CPU time 3 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:21 PM PDT 24
Peak memory 214284 kb
Host smart-4ef569d1-afae-466e-9cea-84bd1e701ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432331127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1432331127
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4261073955
Short name T581
Test name
Test status
Simulation time 50721997 ps
CPU time 2.47 seconds
Started Jun 22 06:04:11 PM PDT 24
Finished Jun 22 06:04:14 PM PDT 24
Peak memory 206784 kb
Host smart-0791f5ec-f9eb-4dff-ada1-e47804fafd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261073955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4261073955
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.744010255
Short name T186
Test name
Test status
Simulation time 2178280930 ps
CPU time 23.02 seconds
Started Jun 22 06:04:20 PM PDT 24
Finished Jun 22 06:04:43 PM PDT 24
Peak memory 222620 kb
Host smart-f6c2f60e-a8a5-4f18-a9ee-2aac893adfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744010255 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.744010255
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1671712575
Short name T715
Test name
Test status
Simulation time 141586544 ps
CPU time 4.45 seconds
Started Jun 22 06:04:15 PM PDT 24
Finished Jun 22 06:04:20 PM PDT 24
Peak memory 207344 kb
Host smart-82f6dae5-7704-4960-87d3-86e7e55bdf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671712575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1671712575
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1991594964
Short name T203
Test name
Test status
Simulation time 280068119 ps
CPU time 3.18 seconds
Started Jun 22 06:04:17 PM PDT 24
Finished Jun 22 06:04:21 PM PDT 24
Peak memory 210356 kb
Host smart-d78c122c-01af-4480-82e4-8cb846ad9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991594964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1991594964
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1271788236
Short name T501
Test name
Test status
Simulation time 34860232 ps
CPU time 0.79 seconds
Started Jun 22 06:04:42 PM PDT 24
Finished Jun 22 06:04:43 PM PDT 24
Peak memory 205928 kb
Host smart-b8a6a85a-2320-41bf-afeb-f1b58c1f1625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271788236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1271788236
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.891672742
Short name T29
Test name
Test status
Simulation time 252066036 ps
CPU time 3.85 seconds
Started Jun 22 06:04:17 PM PDT 24
Finished Jun 22 06:04:21 PM PDT 24
Peak memory 218268 kb
Host smart-d54322da-fa73-4619-a782-b0af9c8fb4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891672742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.891672742
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.655620550
Short name T80
Test name
Test status
Simulation time 97125501 ps
CPU time 3.4 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:22 PM PDT 24
Peak memory 209272 kb
Host smart-a099f497-dd2a-4bc7-b70b-12c110fcf81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655620550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.655620550
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2392703741
Short name T551
Test name
Test status
Simulation time 342531840 ps
CPU time 1.97 seconds
Started Jun 22 06:04:23 PM PDT 24
Finished Jun 22 06:04:25 PM PDT 24
Peak memory 213796 kb
Host smart-43b1faea-bc6b-4b8b-977a-21cfb14b62b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392703741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2392703741
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2557597000
Short name T606
Test name
Test status
Simulation time 196166980 ps
CPU time 3.15 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:22 PM PDT 24
Peak memory 219388 kb
Host smart-e7efccb6-1134-4f1d-b0af-228529cab6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557597000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2557597000
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3970735367
Short name T686
Test name
Test status
Simulation time 127903213 ps
CPU time 3.53 seconds
Started Jun 22 06:04:17 PM PDT 24
Finished Jun 22 06:04:21 PM PDT 24
Peak memory 210084 kb
Host smart-85858694-ae1f-4593-a252-3485d131e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970735367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3970735367
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.761362339
Short name T706
Test name
Test status
Simulation time 128328012 ps
CPU time 5.1 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:24 PM PDT 24
Peak memory 207740 kb
Host smart-feee1c8a-a08a-4446-a042-f1cbe8753c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761362339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.761362339
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1756183235
Short name T207
Test name
Test status
Simulation time 3406221686 ps
CPU time 25.04 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:43 PM PDT 24
Peak memory 208144 kb
Host smart-5d440f1b-3bea-4d9c-8c5c-13f1ae85730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756183235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1756183235
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1442357721
Short name T425
Test name
Test status
Simulation time 159639988 ps
CPU time 2.39 seconds
Started Jun 22 06:04:18 PM PDT 24
Finished Jun 22 06:04:21 PM PDT 24
Peak memory 207000 kb
Host smart-f1fec2e3-1634-4459-be8d-aaffa89b2183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442357721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1442357721
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.642745052
Short name T799
Test name
Test status
Simulation time 57332031 ps
CPU time 3.12 seconds
Started Jun 22 06:04:19 PM PDT 24
Finished Jun 22 06:04:23 PM PDT 24
Peak memory 207592 kb
Host smart-be8ef5e1-7a3c-4eba-b177-615f9ca28a93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642745052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.642745052
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.16744760
Short name T743
Test name
Test status
Simulation time 27035249 ps
CPU time 1.89 seconds
Started Jun 22 06:04:17 PM PDT 24
Finished Jun 22 06:04:20 PM PDT 24
Peak memory 206828 kb
Host smart-23c5e575-cce6-4637-a3c4-f689c0ee4084
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16744760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.16744760
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2859096588
Short name T761
Test name
Test status
Simulation time 132041706 ps
CPU time 2.11 seconds
Started Jun 22 06:04:19 PM PDT 24
Finished Jun 22 06:04:22 PM PDT 24
Peak memory 218232 kb
Host smart-6c9f5a0b-65e8-411b-8550-0d4be872ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859096588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2859096588
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.436540565
Short name T209
Test name
Test status
Simulation time 374335229 ps
CPU time 7.56 seconds
Started Jun 22 06:04:23 PM PDT 24
Finished Jun 22 06:04:31 PM PDT 24
Peak memory 207552 kb
Host smart-5d29bd70-ecf9-4e08-8dda-ea7a59e74ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436540565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.436540565
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2086041692
Short name T257
Test name
Test status
Simulation time 157733535 ps
CPU time 2.99 seconds
Started Jun 22 06:04:24 PM PDT 24
Finished Jun 22 06:04:27 PM PDT 24
Peak memory 222560 kb
Host smart-89f19f30-4790-402c-aa09-4208194bd545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086041692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2086041692
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1580291451
Short name T900
Test name
Test status
Simulation time 524280429 ps
CPU time 6.37 seconds
Started Jun 22 06:04:23 PM PDT 24
Finished Jun 22 06:04:30 PM PDT 24
Peak memory 209160 kb
Host smart-4bc61610-5bbb-4c6e-b36e-182b1cd93bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580291451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1580291451
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4285930872
Short name T684
Test name
Test status
Simulation time 1025331945 ps
CPU time 8.54 seconds
Started Jun 22 06:04:19 PM PDT 24
Finished Jun 22 06:04:28 PM PDT 24
Peak memory 211012 kb
Host smart-bcd80c41-2428-43a5-a0bc-4f8db7d5950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285930872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4285930872
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2280123087
Short name T560
Test name
Test status
Simulation time 34544406 ps
CPU time 0.9 seconds
Started Jun 22 06:04:35 PM PDT 24
Finished Jun 22 06:04:36 PM PDT 24
Peak memory 205928 kb
Host smart-5858f9cb-fb24-46e6-be52-8232d8112f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280123087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2280123087
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3043743728
Short name T137
Test name
Test status
Simulation time 66468727 ps
CPU time 2.95 seconds
Started Jun 22 06:04:25 PM PDT 24
Finished Jun 22 06:04:28 PM PDT 24
Peak memory 214280 kb
Host smart-9d0d0ef1-d800-46b4-9b66-13de8cd478d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043743728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3043743728
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2480478689
Short name T73
Test name
Test status
Simulation time 256772719 ps
CPU time 5.97 seconds
Started Jun 22 06:04:28 PM PDT 24
Finished Jun 22 06:04:34 PM PDT 24
Peak memory 214328 kb
Host smart-bf9d59de-ee57-4e0f-91cd-6deab4496906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480478689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2480478689
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3750741898
Short name T252
Test name
Test status
Simulation time 38083534 ps
CPU time 2.05 seconds
Started Jun 22 06:04:32 PM PDT 24
Finished Jun 22 06:04:34 PM PDT 24
Peak memory 214248 kb
Host smart-b2fa68d5-210e-46ae-89b1-ff7a725e78dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750741898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3750741898
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.2330946203
Short name T661
Test name
Test status
Simulation time 38337391 ps
CPU time 2.85 seconds
Started Jun 22 06:04:24 PM PDT 24
Finished Jun 22 06:04:27 PM PDT 24
Peak memory 209672 kb
Host smart-5bb9a7ee-058d-476d-ad47-7b9eba8f091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330946203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2330946203
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.650050098
Short name T427
Test name
Test status
Simulation time 441992536 ps
CPU time 3.19 seconds
Started Jun 22 06:04:26 PM PDT 24
Finished Jun 22 06:04:30 PM PDT 24
Peak memory 208720 kb
Host smart-4fdbd88d-9ceb-45a1-91e4-93f4596adf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650050098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.650050098
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2583573918
Short name T746
Test name
Test status
Simulation time 763126771 ps
CPU time 8.56 seconds
Started Jun 22 06:04:25 PM PDT 24
Finished Jun 22 06:04:34 PM PDT 24
Peak memory 207156 kb
Host smart-a6c1f357-b074-49aa-9e98-b902a9e3941e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583573918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2583573918
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1904263700
Short name T604
Test name
Test status
Simulation time 431917460 ps
CPU time 3.55 seconds
Started Jun 22 06:04:26 PM PDT 24
Finished Jun 22 06:04:30 PM PDT 24
Peak memory 209088 kb
Host smart-7e82ae1a-0a06-4576-b223-076f310d02c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904263700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1904263700
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2742160120
Short name T553
Test name
Test status
Simulation time 122356742 ps
CPU time 4.12 seconds
Started Jun 22 06:04:27 PM PDT 24
Finished Jun 22 06:04:32 PM PDT 24
Peak memory 208920 kb
Host smart-82b39323-8c8a-42e9-9b2b-17e28157a783
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742160120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2742160120
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3657887438
Short name T263
Test name
Test status
Simulation time 243366066 ps
CPU time 3.71 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:41 PM PDT 24
Peak memory 218160 kb
Host smart-5224bed0-cb61-4e26-803c-42fb6d8c7328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657887438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3657887438
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.592850458
Short name T617
Test name
Test status
Simulation time 1355320030 ps
CPU time 15.03 seconds
Started Jun 22 06:04:24 PM PDT 24
Finished Jun 22 06:04:39 PM PDT 24
Peak memory 208840 kb
Host smart-7bdb82ea-927c-43d1-91d1-623b6000557d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592850458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.592850458
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3738531926
Short name T334
Test name
Test status
Simulation time 1286273580 ps
CPU time 22.07 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:55 PM PDT 24
Peak memory 222448 kb
Host smart-6fd9708e-7c73-408a-b0c7-63a405150727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738531926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3738531926
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1940201721
Short name T696
Test name
Test status
Simulation time 90726653 ps
CPU time 3.57 seconds
Started Jun 22 06:04:28 PM PDT 24
Finished Jun 22 06:04:31 PM PDT 24
Peak memory 208388 kb
Host smart-f15a2ddc-d9cf-4b15-a57e-296253b8a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940201721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1940201721
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2888850304
Short name T722
Test name
Test status
Simulation time 28328816 ps
CPU time 0.93 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:35 PM PDT 24
Peak memory 206096 kb
Host smart-12b39dd5-ac3a-46ca-be7d-474d680f2048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888850304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2888850304
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.410241037
Short name T404
Test name
Test status
Simulation time 238939341 ps
CPU time 12.04 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:46 PM PDT 24
Peak memory 214272 kb
Host smart-041b0299-d76f-471b-ac69-f428ab188fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410241037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.410241037
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.468804330
Short name T221
Test name
Test status
Simulation time 45650266 ps
CPU time 2.95 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:38 PM PDT 24
Peak memory 222780 kb
Host smart-02c83f18-b8ce-4dc0-9a41-1a016b82d3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468804330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.468804330
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.599037524
Short name T874
Test name
Test status
Simulation time 28079943 ps
CPU time 1.83 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:37 PM PDT 24
Peak memory 215056 kb
Host smart-6d4d016c-aa65-4496-ba94-864421944eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599037524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.599037524
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1162730354
Short name T908
Test name
Test status
Simulation time 1160599860 ps
CPU time 3.17 seconds
Started Jun 22 06:04:31 PM PDT 24
Finished Jun 22 06:04:34 PM PDT 24
Peak memory 221840 kb
Host smart-c71b8231-4790-4dad-bc2b-fe302b85494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162730354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1162730354
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2579302388
Short name T295
Test name
Test status
Simulation time 140921699 ps
CPU time 3.87 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:37 PM PDT 24
Peak memory 214244 kb
Host smart-92180248-589d-46e5-80a1-4c28a1a0f958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579302388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2579302388
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.928966815
Short name T71
Test name
Test status
Simulation time 47418295 ps
CPU time 3 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:36 PM PDT 24
Peak memory 219900 kb
Host smart-5a1528a5-d216-4dc9-992d-519a311dcd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928966815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.928966815
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2417285585
Short name T348
Test name
Test status
Simulation time 165386920 ps
CPU time 5.2 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 209024 kb
Host smart-efe2cf64-1e63-4980-877a-71bc4434d7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417285585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2417285585
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3691821792
Short name T83
Test name
Test status
Simulation time 623968325 ps
CPU time 4.23 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:39 PM PDT 24
Peak memory 206640 kb
Host smart-d108a4eb-78ec-402a-ab95-102129855122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691821792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3691821792
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.977095309
Short name T654
Test name
Test status
Simulation time 48384790 ps
CPU time 2.73 seconds
Started Jun 22 06:04:37 PM PDT 24
Finished Jun 22 06:04:41 PM PDT 24
Peak memory 207076 kb
Host smart-35118125-4995-4b63-bd3a-7b89840103e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977095309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.977095309
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3922616034
Short name T768
Test name
Test status
Simulation time 52016446 ps
CPU time 2.3 seconds
Started Jun 22 06:04:32 PM PDT 24
Finished Jun 22 06:04:35 PM PDT 24
Peak memory 208548 kb
Host smart-36a9f5e9-1615-4998-b806-ddb96ff07b3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922616034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3922616034
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3642606038
Short name T731
Test name
Test status
Simulation time 1187532814 ps
CPU time 19.86 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:54 PM PDT 24
Peak memory 208008 kb
Host smart-7402ceff-800d-48b8-bf53-ae05dbf7750c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642606038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3642606038
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3684977410
Short name T601
Test name
Test status
Simulation time 64950108 ps
CPU time 3.14 seconds
Started Jun 22 06:04:37 PM PDT 24
Finished Jun 22 06:04:41 PM PDT 24
Peak memory 214320 kb
Host smart-0f71f84c-c204-4ce3-bb44-85733b92c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684977410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3684977410
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3804179892
Short name T502
Test name
Test status
Simulation time 469082634 ps
CPU time 2.89 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:40 PM PDT 24
Peak memory 206700 kb
Host smart-3854478e-2038-42f4-ab3f-7286007c588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804179892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3804179892
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2874152134
Short name T53
Test name
Test status
Simulation time 562466643 ps
CPU time 14.71 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 215136 kb
Host smart-de508949-41ec-436e-8dd0-b3ebc5ebaa7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874152134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2874152134
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.473211525
Short name T730
Test name
Test status
Simulation time 526677423 ps
CPU time 5.16 seconds
Started Jun 22 06:04:31 PM PDT 24
Finished Jun 22 06:04:37 PM PDT 24
Peak memory 208040 kb
Host smart-ae709391-2c02-4b65-9986-da02282b684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473211525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.473211525
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4255222797
Short name T676
Test name
Test status
Simulation time 48154824 ps
CPU time 1.65 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:37 PM PDT 24
Peak memory 209832 kb
Host smart-e80069b7-e943-481c-9106-e5c7fd9dc54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255222797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4255222797
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3652780584
Short name T756
Test name
Test status
Simulation time 53603290 ps
CPU time 0.79 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:02:43 PM PDT 24
Peak memory 205924 kb
Host smart-db2fad8b-5842-4d99-9326-7014a88e77f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652780584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3652780584
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2508066273
Short name T876
Test name
Test status
Simulation time 36690637 ps
CPU time 2.75 seconds
Started Jun 22 06:02:41 PM PDT 24
Finished Jun 22 06:02:45 PM PDT 24
Peak memory 215284 kb
Host smart-314a3276-77ba-4ae8-a712-f771242a0755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508066273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2508066273
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3904217621
Short name T707
Test name
Test status
Simulation time 305801211 ps
CPU time 3.38 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:02:46 PM PDT 24
Peak memory 219580 kb
Host smart-d959a1c1-646e-4427-b37f-f2203fa7d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904217621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3904217621
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2351655385
Short name T78
Test name
Test status
Simulation time 122392461 ps
CPU time 1.8 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:02:44 PM PDT 24
Peak memory 207280 kb
Host smart-22d33c15-201f-4344-af03-18028927e0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351655385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2351655385
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4138929889
Short name T284
Test name
Test status
Simulation time 45428938 ps
CPU time 1.79 seconds
Started Jun 22 06:02:41 PM PDT 24
Finished Jun 22 06:02:43 PM PDT 24
Peak memory 214304 kb
Host smart-52cb3d57-1beb-4d72-8255-85d4d592d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138929889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4138929889
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1949796602
Short name T352
Test name
Test status
Simulation time 480534262 ps
CPU time 4.38 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:02:47 PM PDT 24
Peak memory 211684 kb
Host smart-18c376eb-4e73-432d-851e-7ae4702d5a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949796602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1949796602
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.380978300
Short name T62
Test name
Test status
Simulation time 600284203 ps
CPU time 5.3 seconds
Started Jun 22 06:02:44 PM PDT 24
Finished Jun 22 06:02:50 PM PDT 24
Peak memory 214316 kb
Host smart-21d8a3b9-27ff-4c6f-a0d8-26527590b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380978300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.380978300
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2483261471
Short name T243
Test name
Test status
Simulation time 48039905 ps
CPU time 3.12 seconds
Started Jun 22 06:02:36 PM PDT 24
Finished Jun 22 06:02:40 PM PDT 24
Peak memory 207064 kb
Host smart-e7e4ae8b-6fd3-4985-b71e-0d84bb8c9dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483261471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2483261471
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3625443276
Short name T46
Test name
Test status
Simulation time 1075027782 ps
CPU time 8.9 seconds
Started Jun 22 06:02:43 PM PDT 24
Finished Jun 22 06:02:52 PM PDT 24
Peak memory 233584 kb
Host smart-157435e7-2b12-4925-a82d-863d6597a759
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625443276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3625443276
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1552361627
Short name T384
Test name
Test status
Simulation time 1005987645 ps
CPU time 3.35 seconds
Started Jun 22 06:02:36 PM PDT 24
Finished Jun 22 06:02:39 PM PDT 24
Peak memory 206832 kb
Host smart-90a9d1e1-4e90-4063-a08f-f88fcbc0ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552361627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1552361627
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.4235777362
Short name T751
Test name
Test status
Simulation time 557101348 ps
CPU time 2.9 seconds
Started Jun 22 06:02:35 PM PDT 24
Finished Jun 22 06:02:38 PM PDT 24
Peak memory 208756 kb
Host smart-e35d473f-1e87-4368-af86-bb6963ba466c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235777362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.4235777362
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.732936597
Short name T540
Test name
Test status
Simulation time 139782253 ps
CPU time 5.03 seconds
Started Jun 22 06:02:38 PM PDT 24
Finished Jun 22 06:02:43 PM PDT 24
Peak memory 206960 kb
Host smart-fa17a6a7-6ab2-4b5e-9ec0-e8feef1ce630
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732936597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.732936597
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4244592130
Short name T463
Test name
Test status
Simulation time 131151328 ps
CPU time 2.52 seconds
Started Jun 22 06:02:36 PM PDT 24
Finished Jun 22 06:02:39 PM PDT 24
Peak memory 206960 kb
Host smart-a2be9773-98ca-4126-989d-be8e80d8e811
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244592130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4244592130
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4287122025
Short name T305
Test name
Test status
Simulation time 161770006 ps
CPU time 2.55 seconds
Started Jun 22 06:02:43 PM PDT 24
Finished Jun 22 06:02:46 PM PDT 24
Peak memory 218324 kb
Host smart-4ad6bacd-67b8-4d54-a085-de8a1cb0264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287122025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4287122025
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.174567645
Short name T709
Test name
Test status
Simulation time 78049065 ps
CPU time 2.6 seconds
Started Jun 22 06:02:35 PM PDT 24
Finished Jun 22 06:02:38 PM PDT 24
Peak memory 208456 kb
Host smart-af631b90-5677-4bd3-9d3b-69f60b4b5cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174567645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.174567645
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3090502536
Short name T198
Test name
Test status
Simulation time 17296069820 ps
CPU time 86.76 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:04:09 PM PDT 24
Peak memory 217244 kb
Host smart-bff84904-5125-4629-a36a-fd5ab0f87b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090502536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3090502536
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1040030081
Short name T760
Test name
Test status
Simulation time 8619843705 ps
CPU time 33.57 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:03:16 PM PDT 24
Peak memory 218364 kb
Host smart-d7870eb9-8e2b-4961-86e0-c8c63e5b40bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040030081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1040030081
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.121068760
Short name T557
Test name
Test status
Simulation time 260595900 ps
CPU time 2.84 seconds
Started Jun 22 06:02:42 PM PDT 24
Finished Jun 22 06:02:45 PM PDT 24
Peak memory 210256 kb
Host smart-40ec5951-b831-4ba1-b137-96aed5e40374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121068760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.121068760
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.260983605
Short name T442
Test name
Test status
Simulation time 23435641 ps
CPU time 0.76 seconds
Started Jun 22 06:04:37 PM PDT 24
Finished Jun 22 06:04:39 PM PDT 24
Peak memory 205928 kb
Host smart-b9c9359a-0e3b-4e71-944a-c0c4548a0105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260983605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.260983605
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1676892752
Short name T239
Test name
Test status
Simulation time 49171950 ps
CPU time 2.22 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:35 PM PDT 24
Peak memory 214320 kb
Host smart-29a35931-631d-4c63-b271-7f64d7582dc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676892752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1676892752
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2746191754
Short name T43
Test name
Test status
Simulation time 73145797 ps
CPU time 3.52 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:38 PM PDT 24
Peak memory 208752 kb
Host smart-e835ac8c-0a1d-4bae-ac11-ddf9f2ba4145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746191754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2746191754
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2435709029
Short name T313
Test name
Test status
Simulation time 898870686 ps
CPU time 3.99 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:37 PM PDT 24
Peak memory 214312 kb
Host smart-5d96f011-f903-4baa-9504-879861c738aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435709029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2435709029
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3527728501
Short name T347
Test name
Test status
Simulation time 47878395 ps
CPU time 2.67 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:39 PM PDT 24
Peak memory 214252 kb
Host smart-eaee6b71-854d-4351-a6a1-49616b18b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527728501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3527728501
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3943882429
Short name T815
Test name
Test status
Simulation time 91532346 ps
CPU time 3.39 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:37 PM PDT 24
Peak memory 214248 kb
Host smart-98392c8b-0fa1-4560-9239-637715e9bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943882429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3943882429
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4217332642
Short name T224
Test name
Test status
Simulation time 397521165 ps
CPU time 3.05 seconds
Started Jun 22 06:04:32 PM PDT 24
Finished Jun 22 06:04:36 PM PDT 24
Peak memory 209212 kb
Host smart-797ac02a-09ef-4dc4-8ccc-6e72a49c6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217332642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4217332642
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2030565977
Short name T655
Test name
Test status
Simulation time 270207848 ps
CPU time 4.03 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:41 PM PDT 24
Peak memory 207884 kb
Host smart-c0f4d5f4-8e5a-4049-8c86-1dca4a33ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030565977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2030565977
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2043018975
Short name T311
Test name
Test status
Simulation time 110558037 ps
CPU time 3.74 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:38 PM PDT 24
Peak memory 208564 kb
Host smart-72fa684f-2220-44dc-b889-775a86c92a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043018975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2043018975
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2635972377
Short name T508
Test name
Test status
Simulation time 31580889 ps
CPU time 2.3 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:35 PM PDT 24
Peak memory 206948 kb
Host smart-1eb83645-ea04-47a6-992a-c05949654899
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635972377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2635972377
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.780106739
Short name T570
Test name
Test status
Simulation time 222772623 ps
CPU time 6.2 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:40 PM PDT 24
Peak memory 208016 kb
Host smart-f98384cd-6828-4907-b41b-16d258f6c7a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780106739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.780106739
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4223301787
Short name T476
Test name
Test status
Simulation time 73132109 ps
CPU time 1.83 seconds
Started Jun 22 06:04:37 PM PDT 24
Finished Jun 22 06:04:40 PM PDT 24
Peak memory 206936 kb
Host smart-4396d413-fd93-4295-b3a7-1975486a2069
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223301787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4223301787
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1073568622
Short name T689
Test name
Test status
Simulation time 149681053 ps
CPU time 3.67 seconds
Started Jun 22 06:04:35 PM PDT 24
Finished Jun 22 06:04:39 PM PDT 24
Peak memory 214268 kb
Host smart-878822a7-a01c-42dc-8d2b-2dca98e943a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073568622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1073568622
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.4077287788
Short name T436
Test name
Test status
Simulation time 278174586 ps
CPU time 2.84 seconds
Started Jun 22 06:04:32 PM PDT 24
Finished Jun 22 06:04:36 PM PDT 24
Peak memory 206804 kb
Host smart-d8bb3d24-0455-4cd5-b791-54a24bc771a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077287788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4077287788
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3189514623
Short name T767
Test name
Test status
Simulation time 2012588280 ps
CPU time 21.54 seconds
Started Jun 22 06:04:33 PM PDT 24
Finished Jun 22 06:04:55 PM PDT 24
Peak memory 214312 kb
Host smart-ca9897b2-62a0-443e-88c7-cb988cd81fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189514623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3189514623
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2592639993
Short name T185
Test name
Test status
Simulation time 470309821 ps
CPU time 18.72 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:05:00 PM PDT 24
Peak memory 222520 kb
Host smart-9f9948d6-8328-425b-969b-6a1689221860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592639993 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2592639993
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.403948706
Short name T324
Test name
Test status
Simulation time 338540614 ps
CPU time 4.81 seconds
Started Jun 22 06:04:36 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 209192 kb
Host smart-60d94497-68a1-4eb3-8ac6-85ac82a72363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403948706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.403948706
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1848528187
Short name T116
Test name
Test status
Simulation time 49252323 ps
CPU time 2.67 seconds
Started Jun 22 06:04:34 PM PDT 24
Finished Jun 22 06:04:38 PM PDT 24
Peak memory 210440 kb
Host smart-93d88856-12f5-46f6-ae78-573f0735d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848528187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1848528187
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2618696548
Short name T421
Test name
Test status
Simulation time 57149719 ps
CPU time 0.78 seconds
Started Jun 22 06:04:42 PM PDT 24
Finished Jun 22 06:04:43 PM PDT 24
Peak memory 205928 kb
Host smart-e7798ab5-ed73-48ed-836f-7e651b389cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618696548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2618696548
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.889331941
Short name T261
Test name
Test status
Simulation time 95389281 ps
CPU time 5.26 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:04:46 PM PDT 24
Peak memory 215756 kb
Host smart-4fa4a015-6061-4826-b5f6-ec26bc7e237f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889331941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.889331941
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.474601294
Short name T21
Test name
Test status
Simulation time 340888818 ps
CPU time 3.84 seconds
Started Jun 22 06:04:41 PM PDT 24
Finished Jun 22 06:04:45 PM PDT 24
Peak memory 210420 kb
Host smart-d1c9380c-af18-4991-8dc4-c2e6656a2569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474601294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.474601294
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1696153494
Short name T65
Test name
Test status
Simulation time 4073609037 ps
CPU time 37.73 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:05:18 PM PDT 24
Peak memory 209540 kb
Host smart-7f1e4211-2220-48a9-86f0-1a22a389050f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696153494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1696153494
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3929304497
Short name T93
Test name
Test status
Simulation time 1005025402 ps
CPU time 16.98 seconds
Started Jun 22 06:04:37 PM PDT 24
Finished Jun 22 06:04:55 PM PDT 24
Peak memory 209972 kb
Host smart-fac754d7-587e-4fad-a476-14c51af953fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929304497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3929304497
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1040608182
Short name T317
Test name
Test status
Simulation time 103788759 ps
CPU time 2.9 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:04:44 PM PDT 24
Peak memory 214248 kb
Host smart-679fe744-da70-4ab9-b875-92cdf3867e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040608182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1040608182
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3090607933
Short name T49
Test name
Test status
Simulation time 77840815 ps
CPU time 3.46 seconds
Started Jun 22 06:04:38 PM PDT 24
Finished Jun 22 06:04:43 PM PDT 24
Peak memory 215312 kb
Host smart-c6abb3cc-b5b5-46f1-a79b-6099c0618b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090607933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3090607933
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.197618987
Short name T714
Test name
Test status
Simulation time 149175827 ps
CPU time 4.72 seconds
Started Jun 22 06:04:44 PM PDT 24
Finished Jun 22 06:04:49 PM PDT 24
Peak memory 214308 kb
Host smart-f2d37122-9909-4880-a016-b2172549a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197618987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.197618987
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.463371501
Short name T327
Test name
Test status
Simulation time 21822104 ps
CPU time 1.9 seconds
Started Jun 22 06:04:39 PM PDT 24
Finished Jun 22 06:04:41 PM PDT 24
Peak memory 206884 kb
Host smart-1348173c-0b81-4cb3-99bb-4e3d9d356c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463371501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.463371501
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.736921120
Short name T413
Test name
Test status
Simulation time 87457010 ps
CPU time 3.11 seconds
Started Jun 22 06:04:38 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 206928 kb
Host smart-62849dae-a4fa-4c14-ac58-3a3c7df164d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736921120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.736921120
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1410330754
Short name T214
Test name
Test status
Simulation time 191669951 ps
CPU time 2.71 seconds
Started Jun 22 06:04:39 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 206816 kb
Host smart-ddd2d0d8-5fb4-450b-aa7c-546805cc511d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410330754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1410330754
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.25601337
Short name T857
Test name
Test status
Simulation time 116532581 ps
CPU time 3.18 seconds
Started Jun 22 06:04:38 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 206912 kb
Host smart-853ac7b9-25f9-49a6-a0b0-f22c54b8ba5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25601337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.25601337
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2954658740
Short name T534
Test name
Test status
Simulation time 95223963 ps
CPU time 2.72 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:04:44 PM PDT 24
Peak memory 207468 kb
Host smart-44b5c910-9285-415d-9854-fb30318e8698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954658740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2954658740
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4283402877
Short name T573
Test name
Test status
Simulation time 277056109 ps
CPU time 2.74 seconds
Started Jun 22 06:04:44 PM PDT 24
Finished Jun 22 06:04:47 PM PDT 24
Peak memory 207424 kb
Host smart-39d94cb2-b257-43d8-9332-e859813ba2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283402877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4283402877
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.895093720
Short name T753
Test name
Test status
Simulation time 113889036 ps
CPU time 5.29 seconds
Started Jun 22 06:04:44 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 209360 kb
Host smart-fc94877b-29a6-4d97-96c1-13e5124eccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895093720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.895093720
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4209723866
Short name T638
Test name
Test status
Simulation time 211372423 ps
CPU time 2.46 seconds
Started Jun 22 06:04:42 PM PDT 24
Finished Jun 22 06:04:45 PM PDT 24
Peak memory 210292 kb
Host smart-5ba031a7-a565-4861-8dce-d83606696989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209723866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4209723866
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3515364329
Short name T424
Test name
Test status
Simulation time 133368383 ps
CPU time 0.9 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:49 PM PDT 24
Peak memory 206112 kb
Host smart-510d652b-e42f-475a-8010-737644972f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515364329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3515364329
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4225294360
Short name T893
Test name
Test status
Simulation time 80666639 ps
CPU time 2.14 seconds
Started Jun 22 06:04:41 PM PDT 24
Finished Jun 22 06:04:44 PM PDT 24
Peak memory 214316 kb
Host smart-335a265e-18a0-4b8f-bec7-04e9c5fb634d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225294360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4225294360
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1790925944
Short name T649
Test name
Test status
Simulation time 48949338 ps
CPU time 2.43 seconds
Started Jun 22 06:04:49 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 209168 kb
Host smart-1b87c115-6667-4799-b444-7d944ccbf14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790925944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1790925944
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1425394885
Short name T741
Test name
Test status
Simulation time 234023589 ps
CPU time 3.15 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:51 PM PDT 24
Peak memory 215772 kb
Host smart-cdcee921-6186-461e-b1de-54ba59cce6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425394885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1425394885
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3090616577
Short name T563
Test name
Test status
Simulation time 298225772 ps
CPU time 7.27 seconds
Started Jun 22 06:04:40 PM PDT 24
Finished Jun 22 06:04:48 PM PDT 24
Peak memory 209316 kb
Host smart-058c90be-454b-4322-9d3a-cfb68a881e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090616577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3090616577
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1761699268
Short name T812
Test name
Test status
Simulation time 76935698 ps
CPU time 3.12 seconds
Started Jun 22 06:04:45 PM PDT 24
Finished Jun 22 06:04:48 PM PDT 24
Peak memory 208556 kb
Host smart-3979bd63-caf2-4319-834f-2ec3f0e94613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761699268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1761699268
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.514325309
Short name T556
Test name
Test status
Simulation time 36372881 ps
CPU time 1.75 seconds
Started Jun 22 06:04:37 PM PDT 24
Finished Jun 22 06:04:40 PM PDT 24
Peak memory 206860 kb
Host smart-b47a99ba-d970-40e3-862d-d0a9d03e289a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514325309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.514325309
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.343179472
Short name T98
Test name
Test status
Simulation time 61429882 ps
CPU time 3.16 seconds
Started Jun 22 06:04:39 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 206836 kb
Host smart-801d1823-1e14-4c93-8516-68bf203fd654
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343179472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.343179472
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2698230171
Short name T578
Test name
Test status
Simulation time 235950720 ps
CPU time 3.4 seconds
Started Jun 22 06:04:44 PM PDT 24
Finished Jun 22 06:04:48 PM PDT 24
Peak memory 208080 kb
Host smart-95191666-05de-48b2-9e6b-b8024f5e95b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698230171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2698230171
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3970149964
Short name T494
Test name
Test status
Simulation time 168298562 ps
CPU time 5.22 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:53 PM PDT 24
Peak memory 208660 kb
Host smart-34e3d751-07ad-4866-bc1a-ed3681a73dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970149964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3970149964
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4193718752
Short name T411
Test name
Test status
Simulation time 999499460 ps
CPU time 3.79 seconds
Started Jun 22 06:04:38 PM PDT 24
Finished Jun 22 06:04:42 PM PDT 24
Peak memory 208048 kb
Host smart-9b5f802f-5c1c-44b8-bc36-ac5374a2ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193718752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4193718752
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.926874811
Short name T708
Test name
Test status
Simulation time 3825184792 ps
CPU time 39.24 seconds
Started Jun 22 06:04:49 PM PDT 24
Finished Jun 22 06:05:29 PM PDT 24
Peak memory 220104 kb
Host smart-8c989d9d-f7fc-4d3e-adf7-7946cecbc17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926874811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.926874811
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1517810885
Short name T737
Test name
Test status
Simulation time 330811050 ps
CPU time 4.18 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:51 PM PDT 24
Peak memory 209112 kb
Host smart-4b6175c9-bea3-4ab4-b434-4f084d18e8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517810885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1517810885
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1078511154
Short name T890
Test name
Test status
Simulation time 9589567 ps
CPU time 0.86 seconds
Started Jun 22 06:04:48 PM PDT 24
Finished Jun 22 06:04:49 PM PDT 24
Peak memory 205888 kb
Host smart-54777a11-b691-40cd-98ec-9a66f22fccda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078511154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1078511154
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3296965202
Short name T538
Test name
Test status
Simulation time 58424050 ps
CPU time 2.66 seconds
Started Jun 22 06:04:52 PM PDT 24
Finished Jun 22 06:04:55 PM PDT 24
Peak memory 218588 kb
Host smart-fa5f0e83-80d5-4f7a-9a66-11507cbc14fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296965202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3296965202
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3200792024
Short name T596
Test name
Test status
Simulation time 47619312 ps
CPU time 3.04 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 207668 kb
Host smart-e8ac944c-64ef-4b7b-89b4-d7c83d2e3325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200792024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3200792024
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.900389071
Short name T580
Test name
Test status
Simulation time 98705009 ps
CPU time 4.85 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:53 PM PDT 24
Peak memory 208880 kb
Host smart-d194ced6-d9e3-4888-ba16-949095cffeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900389071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.900389071
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.135379139
Short name T273
Test name
Test status
Simulation time 1125953626 ps
CPU time 6.78 seconds
Started Jun 22 06:04:48 PM PDT 24
Finished Jun 22 06:04:55 PM PDT 24
Peak memory 209404 kb
Host smart-c40a1072-3f17-4c46-966c-3ecb66c4b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135379139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.135379139
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2599932561
Short name T513
Test name
Test status
Simulation time 895161886 ps
CPU time 9.17 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:57 PM PDT 24
Peak memory 206916 kb
Host smart-8d8891ec-22e5-4b8f-a33e-cac4eb18d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599932561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2599932561
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1502478797
Short name T453
Test name
Test status
Simulation time 371516409 ps
CPU time 5.5 seconds
Started Jun 22 06:04:48 PM PDT 24
Finished Jun 22 06:04:54 PM PDT 24
Peak memory 208672 kb
Host smart-b84e0aeb-bff2-4093-9cfc-de1a7979ab69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502478797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1502478797
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2995574809
Short name T779
Test name
Test status
Simulation time 963381758 ps
CPU time 6.93 seconds
Started Jun 22 06:04:50 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 206980 kb
Host smart-1b20690e-a7f1-4749-b9bc-ef3da4391af7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995574809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2995574809
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3983181867
Short name T802
Test name
Test status
Simulation time 42631103 ps
CPU time 2.62 seconds
Started Jun 22 06:04:49 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 206908 kb
Host smart-7fbcba34-a531-429a-a388-895e5bbfef6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983181867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3983181867
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2300408411
Short name T241
Test name
Test status
Simulation time 46799669 ps
CPU time 2.51 seconds
Started Jun 22 06:04:45 PM PDT 24
Finished Jun 22 06:04:48 PM PDT 24
Peak memory 207880 kb
Host smart-4a6ca7f6-3d7d-4e80-85e0-4152d4ce6607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300408411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2300408411
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3644782972
Short name T710
Test name
Test status
Simulation time 1303647961 ps
CPU time 22.78 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:05:11 PM PDT 24
Peak memory 208088 kb
Host smart-b4832d5d-c59b-4ffc-970a-4c77d83398f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644782972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3644782972
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2949573482
Short name T382
Test name
Test status
Simulation time 1502682639 ps
CPU time 10.46 seconds
Started Jun 22 06:04:49 PM PDT 24
Finished Jun 22 06:05:00 PM PDT 24
Peak memory 220224 kb
Host smart-90541c8e-194b-4e11-b838-a20cd77b3c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949573482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2949573482
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2972435376
Short name T798
Test name
Test status
Simulation time 414272150 ps
CPU time 5.6 seconds
Started Jun 22 06:04:53 PM PDT 24
Finished Jun 22 06:04:59 PM PDT 24
Peak memory 208200 kb
Host smart-f181d1e1-812e-46f9-9f6e-5677e5f3cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972435376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2972435376
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1025963930
Short name T669
Test name
Test status
Simulation time 220820469 ps
CPU time 2.78 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 209948 kb
Host smart-ff0d9520-8651-434a-9a89-3f17fcf4ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025963930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1025963930
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.379060787
Short name T818
Test name
Test status
Simulation time 19685929 ps
CPU time 0.79 seconds
Started Jun 22 06:04:53 PM PDT 24
Finished Jun 22 06:04:54 PM PDT 24
Peak memory 205908 kb
Host smart-eee66547-0400-4ae2-9a91-3abd41a4237b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379060787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.379060787
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1232069238
Short name T265
Test name
Test status
Simulation time 203296071 ps
CPU time 4.05 seconds
Started Jun 22 06:04:47 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 214316 kb
Host smart-7b7b3392-c9e0-4a54-bb06-1ef31096abf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232069238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1232069238
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3715882466
Short name T32
Test name
Test status
Simulation time 235208123 ps
CPU time 3.88 seconds
Started Jun 22 06:04:53 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 209792 kb
Host smart-a60616ee-f652-49ca-b70b-518d0f292b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715882466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3715882466
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2066884176
Short name T863
Test name
Test status
Simulation time 219761892 ps
CPU time 5.14 seconds
Started Jun 22 06:04:50 PM PDT 24
Finished Jun 22 06:04:56 PM PDT 24
Peak memory 218480 kb
Host smart-5808cff8-72ea-478f-9064-7319db252a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066884176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2066884176
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.247250947
Short name T608
Test name
Test status
Simulation time 136789012 ps
CPU time 3.57 seconds
Started Jun 22 06:04:52 PM PDT 24
Finished Jun 22 06:04:56 PM PDT 24
Peak memory 214312 kb
Host smart-77ebc665-5f18-4437-8ad9-1c7cc7c5ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247250947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.247250947
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.754742101
Short name T50
Test name
Test status
Simulation time 102345384 ps
CPU time 2.84 seconds
Started Jun 22 06:04:56 PM PDT 24
Finished Jun 22 06:04:59 PM PDT 24
Peak memory 214244 kb
Host smart-ec0eb452-f625-4007-945e-fe0e5325b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754742101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.754742101
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2032373263
Short name T647
Test name
Test status
Simulation time 123987390 ps
CPU time 2.54 seconds
Started Jun 22 06:04:55 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 214404 kb
Host smart-4efb78f6-829b-40ba-9943-b8715500027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032373263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2032373263
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3547687878
Short name T308
Test name
Test status
Simulation time 657391169 ps
CPU time 5 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:52 PM PDT 24
Peak memory 210044 kb
Host smart-e885f714-f44b-4169-855c-b1f948926a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547687878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3547687878
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1751727109
Short name T242
Test name
Test status
Simulation time 106661185 ps
CPU time 4.27 seconds
Started Jun 22 06:04:49 PM PDT 24
Finished Jun 22 06:04:53 PM PDT 24
Peak memory 208748 kb
Host smart-58012a6a-992f-47b3-aabf-5f34d047d7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751727109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1751727109
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3073277252
Short name T663
Test name
Test status
Simulation time 131058461 ps
CPU time 2.57 seconds
Started Jun 22 06:04:50 PM PDT 24
Finished Jun 22 06:04:53 PM PDT 24
Peak memory 207396 kb
Host smart-9a1ffdc1-d4f8-4eea-8d75-e2d7f6afdcb9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073277252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3073277252
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3988567126
Short name T472
Test name
Test status
Simulation time 202445415 ps
CPU time 6.92 seconds
Started Jun 22 06:04:50 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 208248 kb
Host smart-163fe497-da7e-4978-a61f-5f04b4ed8ef9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988567126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3988567126
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4103455386
Short name T322
Test name
Test status
Simulation time 153599657 ps
CPU time 4.91 seconds
Started Jun 22 06:04:53 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 208536 kb
Host smart-b6c2ca34-727d-4017-b69d-546e15c0c792
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103455386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4103455386
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3736190150
Short name T522
Test name
Test status
Simulation time 112978695 ps
CPU time 1.64 seconds
Started Jun 22 06:04:56 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 207168 kb
Host smart-65ef0fdd-6173-4c4f-adb5-b4b84037dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736190150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3736190150
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3862883199
Short name T830
Test name
Test status
Simulation time 388429471 ps
CPU time 2.65 seconds
Started Jun 22 06:04:46 PM PDT 24
Finished Jun 22 06:04:50 PM PDT 24
Peak memory 208296 kb
Host smart-5421985a-86dd-4f34-a030-8f15078506b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862883199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3862883199
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2895370771
Short name T75
Test name
Test status
Simulation time 1323098778 ps
CPU time 38.49 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:05:33 PM PDT 24
Peak memory 214316 kb
Host smart-2f1cbe59-e45b-4f10-8c3b-bd6ea728da6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895370771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2895370771
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2983776586
Short name T430
Test name
Test status
Simulation time 1354617916 ps
CPU time 4.72 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:04:59 PM PDT 24
Peak memory 207308 kb
Host smart-436e216f-603a-4d7e-8e29-c592cfa93662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983776586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2983776586
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1560228377
Short name T624
Test name
Test status
Simulation time 11569127 ps
CPU time 0.74 seconds
Started Jun 22 06:04:59 PM PDT 24
Finished Jun 22 06:05:00 PM PDT 24
Peak memory 205924 kb
Host smart-6897ceee-e1b7-4696-8985-9317da6b5442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560228377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1560228377
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2429989528
Short name T391
Test name
Test status
Simulation time 129803600 ps
CPU time 4.57 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:04:59 PM PDT 24
Peak memory 215436 kb
Host smart-6706fcee-906f-4906-8dc6-140f611ba599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429989528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2429989528
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1859366332
Short name T16
Test name
Test status
Simulation time 114774870 ps
CPU time 3.36 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 214308 kb
Host smart-523204a6-8e63-4888-a38f-9ca92275f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859366332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1859366332
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.303580888
Short name T251
Test name
Test status
Simulation time 214344821 ps
CPU time 3.4 seconds
Started Jun 22 06:05:02 PM PDT 24
Finished Jun 22 06:05:05 PM PDT 24
Peak memory 206176 kb
Host smart-583f40c8-817d-4704-ad43-3e877f054b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303580888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.303580888
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.519524280
Short name T588
Test name
Test status
Simulation time 45650396 ps
CPU time 2.76 seconds
Started Jun 22 06:05:01 PM PDT 24
Finished Jun 22 06:05:04 PM PDT 24
Peak memory 222444 kb
Host smart-539511b3-93c9-4876-b207-948d23415e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519524280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.519524280
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.486750184
Short name T136
Test name
Test status
Simulation time 288621235 ps
CPU time 3.96 seconds
Started Jun 22 06:04:53 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 208780 kb
Host smart-f18c2b7a-9e58-40e2-915c-49fd0c93e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486750184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.486750184
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.897775951
Short name T609
Test name
Test status
Simulation time 242474707 ps
CPU time 3.68 seconds
Started Jun 22 06:04:53 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 206812 kb
Host smart-e6725b0d-7207-4e98-82b6-0ed9f3994b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897775951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.897775951
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.707831953
Short name T805
Test name
Test status
Simulation time 392287364 ps
CPU time 4.58 seconds
Started Jun 22 06:04:52 PM PDT 24
Finished Jun 22 06:04:57 PM PDT 24
Peak memory 208524 kb
Host smart-64957ccd-e81d-40e3-8d06-dee0ea4785c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707831953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.707831953
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2446195817
Short name T439
Test name
Test status
Simulation time 156046957 ps
CPU time 2.43 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:04:57 PM PDT 24
Peak memory 207212 kb
Host smart-04237ec3-855a-4064-ac2f-f2961241b832
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446195817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2446195817
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1727986404
Short name T591
Test name
Test status
Simulation time 45450546 ps
CPU time 2.72 seconds
Started Jun 22 06:04:54 PM PDT 24
Finished Jun 22 06:04:57 PM PDT 24
Peak memory 208776 kb
Host smart-467604dd-7c15-4cd3-bbc2-483f84971677
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727986404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1727986404
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2633839202
Short name T828
Test name
Test status
Simulation time 45595111 ps
CPU time 2.13 seconds
Started Jun 22 06:04:59 PM PDT 24
Finished Jun 22 06:05:02 PM PDT 24
Peak memory 208100 kb
Host smart-26befda5-1ba8-404b-ade7-7e43d61c9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633839202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2633839202
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.345462383
Short name T693
Test name
Test status
Simulation time 127567461 ps
CPU time 2.34 seconds
Started Jun 22 06:04:55 PM PDT 24
Finished Jun 22 06:04:58 PM PDT 24
Peak memory 206816 kb
Host smart-8d08d64c-517a-4e08-a31b-8c627224dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345462383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.345462383
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2413389348
Short name T362
Test name
Test status
Simulation time 609198728 ps
CPU time 6.08 seconds
Started Jun 22 06:05:01 PM PDT 24
Finished Jun 22 06:05:07 PM PDT 24
Peak memory 219496 kb
Host smart-43181e48-f00c-4d28-b2d6-c201114a0ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413389348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2413389348
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1434410602
Short name T128
Test name
Test status
Simulation time 174643938 ps
CPU time 3.48 seconds
Started Jun 22 06:05:00 PM PDT 24
Finished Jun 22 06:05:04 PM PDT 24
Peak memory 207424 kb
Host smart-95ffb193-9a69-453d-8a15-ab86216bad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434410602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1434410602
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.108379151
Short name T202
Test name
Test status
Simulation time 64320560 ps
CPU time 2.2 seconds
Started Jun 22 06:04:59 PM PDT 24
Finished Jun 22 06:05:02 PM PDT 24
Peak memory 209700 kb
Host smart-0071516f-b382-4bc5-839d-2e527620875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108379151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.108379151
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2932174983
Short name T577
Test name
Test status
Simulation time 23752967 ps
CPU time 0.81 seconds
Started Jun 22 06:05:09 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 205932 kb
Host smart-c18e4af1-0110-4f15-9856-cc267a30b016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932174983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2932174983
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3865218327
Short name T390
Test name
Test status
Simulation time 61496245 ps
CPU time 2.57 seconds
Started Jun 22 06:04:59 PM PDT 24
Finished Jun 22 06:05:02 PM PDT 24
Peak memory 214320 kb
Host smart-caef8085-31b7-40a0-b0af-b7a5f2d3a854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865218327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3865218327
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2772224068
Short name T495
Test name
Test status
Simulation time 89310302 ps
CPU time 2.1 seconds
Started Jun 22 06:05:00 PM PDT 24
Finished Jun 22 06:05:03 PM PDT 24
Peak memory 214264 kb
Host smart-6eb409fe-83d4-431d-b21a-f4acc7abd380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772224068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2772224068
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4073836942
Short name T537
Test name
Test status
Simulation time 293360528 ps
CPU time 3.34 seconds
Started Jun 22 06:05:03 PM PDT 24
Finished Jun 22 06:05:06 PM PDT 24
Peak memory 207996 kb
Host smart-dd8576ac-f4b0-44ce-a606-629225e3157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073836942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4073836942
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.531914624
Short name T44
Test name
Test status
Simulation time 547718146 ps
CPU time 4.7 seconds
Started Jun 22 06:05:08 PM PDT 24
Finished Jun 22 06:05:13 PM PDT 24
Peak memory 222412 kb
Host smart-702e5d28-e706-422f-8ce4-ea104bc59dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531914624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.531914624
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.618894903
Short name T520
Test name
Test status
Simulation time 135173052 ps
CPU time 2.44 seconds
Started Jun 22 06:04:58 PM PDT 24
Finished Jun 22 06:05:01 PM PDT 24
Peak memory 220000 kb
Host smart-1850a069-4fd1-4927-9515-003ffa68daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618894903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.618894903
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_sideload.4011601960
Short name T600
Test name
Test status
Simulation time 185645657 ps
CPU time 3.8 seconds
Started Jun 22 06:05:00 PM PDT 24
Finished Jun 22 06:05:04 PM PDT 24
Peak memory 207196 kb
Host smart-5c11243b-9f10-4ce2-ae5a-b7ba61d505bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011601960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.4011601960
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3105494671
Short name T786
Test name
Test status
Simulation time 42360317 ps
CPU time 1.93 seconds
Started Jun 22 06:05:00 PM PDT 24
Finished Jun 22 06:05:02 PM PDT 24
Peak memory 208516 kb
Host smart-a91adc50-1265-4b24-b512-474604454e14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105494671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3105494671
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1362236915
Short name T437
Test name
Test status
Simulation time 313521639 ps
CPU time 3.55 seconds
Started Jun 22 06:05:01 PM PDT 24
Finished Jun 22 06:05:04 PM PDT 24
Peak memory 208680 kb
Host smart-ee7cd1d0-9f44-4648-94a0-e3c6519698ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362236915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1362236915
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2716669104
Short name T487
Test name
Test status
Simulation time 34743713 ps
CPU time 2.5 seconds
Started Jun 22 06:05:03 PM PDT 24
Finished Jun 22 06:05:05 PM PDT 24
Peak memory 206912 kb
Host smart-314366f4-2bfd-4b77-bad1-cf8d58398be8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716669104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2716669104
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4117972329
Short name T426
Test name
Test status
Simulation time 324054318 ps
CPU time 4.53 seconds
Started Jun 22 06:05:06 PM PDT 24
Finished Jun 22 06:05:11 PM PDT 24
Peak memory 214312 kb
Host smart-7a3c9837-3baa-47a3-a03a-78f9392710b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117972329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4117972329
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.861980104
Short name T771
Test name
Test status
Simulation time 1449140120 ps
CPU time 9.57 seconds
Started Jun 22 06:05:00 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 208224 kb
Host smart-3a8cc23d-8017-4b44-b221-d56399c4f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861980104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.861980104
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4035186821
Short name T861
Test name
Test status
Simulation time 65421242 ps
CPU time 3.36 seconds
Started Jun 22 06:05:09 PM PDT 24
Finished Jun 22 06:05:13 PM PDT 24
Peak memory 220420 kb
Host smart-c07ea0e9-53fa-4142-99aa-7e4f0fa26fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035186821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4035186821
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.28244363
Short name T190
Test name
Test status
Simulation time 2661875165 ps
CPU time 25.38 seconds
Started Jun 22 06:05:05 PM PDT 24
Finished Jun 22 06:05:31 PM PDT 24
Peak memory 222816 kb
Host smart-53c5b381-07c2-4b99-bf90-6e43f46cea46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244363 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.28244363
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1286450955
Short name T549
Test name
Test status
Simulation time 13191765932 ps
CPU time 23.63 seconds
Started Jun 22 06:05:00 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 214424 kb
Host smart-8cb3457e-28a5-4566-a521-071597a8cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286450955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1286450955
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1589624507
Short name T450
Test name
Test status
Simulation time 201086294 ps
CPU time 2.19 seconds
Started Jun 22 06:05:08 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 209952 kb
Host smart-872e690e-c8fa-4730-a1be-cf0810730b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589624507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1589624507
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3858745407
Short name T623
Test name
Test status
Simulation time 9736078 ps
CPU time 0.87 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:16 PM PDT 24
Peak memory 205936 kb
Host smart-e901559e-7354-48a5-b2af-4c55b175c7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858745407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3858745407
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1009555666
Short name T350
Test name
Test status
Simulation time 39272292 ps
CPU time 2.78 seconds
Started Jun 22 06:05:05 PM PDT 24
Finished Jun 22 06:05:08 PM PDT 24
Peak memory 222452 kb
Host smart-774c018a-e88e-48cb-ab03-daf1440996a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009555666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1009555666
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1577952657
Short name T34
Test name
Test status
Simulation time 260148420 ps
CPU time 3.59 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 214916 kb
Host smart-900f5155-7883-455f-af21-010522601595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577952657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1577952657
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3942790987
Short name T724
Test name
Test status
Simulation time 162086185 ps
CPU time 2.64 seconds
Started Jun 22 06:05:09 PM PDT 24
Finished Jun 22 06:05:12 PM PDT 24
Peak memory 208124 kb
Host smart-6aaabaf8-3fa1-476c-bf65-4f71ef159cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942790987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3942790987
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4208552156
Short name T127
Test name
Test status
Simulation time 322804509 ps
CPU time 4.65 seconds
Started Jun 22 06:05:17 PM PDT 24
Finished Jun 22 06:05:22 PM PDT 24
Peak memory 208896 kb
Host smart-6fb26b87-75fb-48ac-8982-572b4fa7452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208552156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4208552156
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3684755649
Short name T896
Test name
Test status
Simulation time 38618082 ps
CPU time 2.58 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 222472 kb
Host smart-8d4e5e84-9464-4436-a8c1-5a17c737a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684755649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3684755649
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4234329770
Short name T705
Test name
Test status
Simulation time 37454100 ps
CPU time 2.34 seconds
Started Jun 22 06:05:08 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 219036 kb
Host smart-727030ce-3df5-43ad-9605-47e8c33423aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234329770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4234329770
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3064015223
Short name T400
Test name
Test status
Simulation time 251892542 ps
CPU time 6.27 seconds
Started Jun 22 06:05:08 PM PDT 24
Finished Jun 22 06:05:15 PM PDT 24
Peak memory 207488 kb
Host smart-760df384-36f1-422c-a537-c9d21f9d85cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064015223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3064015223
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3257891712
Short name T358
Test name
Test status
Simulation time 162989141 ps
CPU time 7.11 seconds
Started Jun 22 06:05:08 PM PDT 24
Finished Jun 22 06:05:15 PM PDT 24
Peak memory 208656 kb
Host smart-eb4f26b7-56ea-483f-b9f3-a424ca2786a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257891712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3257891712
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3753528914
Short name T611
Test name
Test status
Simulation time 243222429 ps
CPU time 2.95 seconds
Started Jun 22 06:05:08 PM PDT 24
Finished Jun 22 06:05:12 PM PDT 24
Peak memory 206932 kb
Host smart-04f527a6-6b8a-47ba-ac35-0833e05bf388
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753528914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3753528914
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1446330089
Short name T132
Test name
Test status
Simulation time 4519669574 ps
CPU time 28.31 seconds
Started Jun 22 06:05:07 PM PDT 24
Finished Jun 22 06:05:36 PM PDT 24
Peak memory 208004 kb
Host smart-696e69e0-137f-46e2-a8b0-8da56e3653fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446330089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1446330089
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1466670567
Short name T270
Test name
Test status
Simulation time 1535875444 ps
CPU time 4.5 seconds
Started Jun 22 06:05:09 PM PDT 24
Finished Jun 22 06:05:14 PM PDT 24
Peak memory 208888 kb
Host smart-b3dd6c31-ecec-49be-82d3-b6e299a8ebfa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466670567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1466670567
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.122822568
Short name T585
Test name
Test status
Simulation time 68923315 ps
CPU time 3.2 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 214308 kb
Host smart-f80b197e-8c46-4f7f-acf2-78304f556d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122822568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.122822568
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2448441658
Short name T894
Test name
Test status
Simulation time 57819455 ps
CPU time 2.97 seconds
Started Jun 22 06:05:07 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 208348 kb
Host smart-5f86832b-9496-4a2e-8a48-ba446e463d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448441658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2448441658
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2916027954
Short name T115
Test name
Test status
Simulation time 965505196 ps
CPU time 16.99 seconds
Started Jun 22 06:05:13 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 220080 kb
Host smart-59817521-f13a-4147-b2e8-31e3fec94803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916027954 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2916027954
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.969468303
Short name T576
Test name
Test status
Simulation time 750581346 ps
CPU time 4.91 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 208124 kb
Host smart-420dd5a0-9fce-4258-8a30-394438237468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969468303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.969468303
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3893811776
Short name T372
Test name
Test status
Simulation time 27415465 ps
CPU time 1.26 seconds
Started Jun 22 06:05:12 PM PDT 24
Finished Jun 22 06:05:14 PM PDT 24
Peak memory 209604 kb
Host smart-065402bb-5462-4c46-9f62-32443ffea622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893811776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3893811776
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3410479284
Short name T788
Test name
Test status
Simulation time 26000892 ps
CPU time 0.77 seconds
Started Jun 22 06:05:13 PM PDT 24
Finished Jun 22 06:05:14 PM PDT 24
Peak memory 205928 kb
Host smart-336585ba-0f89-4996-85cf-c7533c0940ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410479284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3410479284
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3412907822
Short name T406
Test name
Test status
Simulation time 24194040 ps
CPU time 2.01 seconds
Started Jun 22 06:05:16 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 214428 kb
Host smart-39980099-f23e-4e19-8c3c-6ae90aab8ed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412907822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3412907822
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2245652879
Short name T28
Test name
Test status
Simulation time 670588499 ps
CPU time 7.79 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 222748 kb
Host smart-3e4831ee-9c1b-424b-a4b5-a7311790bb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245652879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2245652879
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3698162095
Short name T584
Test name
Test status
Simulation time 1126772474 ps
CPU time 8 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:23 PM PDT 24
Peak memory 219588 kb
Host smart-6acc8eb3-1b14-4e59-b9f0-ae6255db99e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698162095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3698162095
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.244599887
Short name T723
Test name
Test status
Simulation time 2783210887 ps
CPU time 48.22 seconds
Started Jun 22 06:05:16 PM PDT 24
Finished Jun 22 06:06:05 PM PDT 24
Peak memory 214428 kb
Host smart-285f660c-82fb-49d1-a866-6bf3daf15890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244599887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.244599887
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_random.2268249777
Short name T691
Test name
Test status
Simulation time 216729012 ps
CPU time 4.94 seconds
Started Jun 22 06:05:16 PM PDT 24
Finished Jun 22 06:05:22 PM PDT 24
Peak memory 209660 kb
Host smart-fee7b911-c317-46bb-b988-03f538df7b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268249777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2268249777
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2415375153
Short name T539
Test name
Test status
Simulation time 85229451 ps
CPU time 3.83 seconds
Started Jun 22 06:05:12 PM PDT 24
Finished Jun 22 06:05:16 PM PDT 24
Peak memory 208464 kb
Host smart-fa1dea3f-0a19-41a3-b131-8e297daa8815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415375153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2415375153
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2117356709
Short name T1
Test name
Test status
Simulation time 112789201 ps
CPU time 3.74 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:18 PM PDT 24
Peak memory 208928 kb
Host smart-1fcf8b52-52ea-4958-92d5-ceee3cda6764
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117356709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2117356709
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4163287392
Short name T448
Test name
Test status
Simulation time 20638448 ps
CPU time 1.87 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:17 PM PDT 24
Peak memory 206880 kb
Host smart-e2e483a6-15a2-44af-a23c-94b6d717f345
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163287392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4163287392
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2620225272
Short name T388
Test name
Test status
Simulation time 595581749 ps
CPU time 15.6 seconds
Started Jun 22 06:05:13 PM PDT 24
Finished Jun 22 06:05:29 PM PDT 24
Peak memory 208020 kb
Host smart-381ba7e8-e12f-4457-ae21-3f0af43f5324
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620225272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2620225272
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.522606261
Short name T303
Test name
Test status
Simulation time 139572986 ps
CPU time 3.5 seconds
Started Jun 22 06:05:11 PM PDT 24
Finished Jun 22 06:05:15 PM PDT 24
Peak memory 208864 kb
Host smart-d501cd88-e044-4c66-97ae-192eb72f5996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522606261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.522606261
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3663277721
Short name T526
Test name
Test status
Simulation time 69058117 ps
CPU time 2.35 seconds
Started Jun 22 06:05:19 PM PDT 24
Finished Jun 22 06:05:22 PM PDT 24
Peak memory 206808 kb
Host smart-c7f9e68b-7ad7-4598-9e60-c5988b770a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663277721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3663277721
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3580076146
Short name T111
Test name
Test status
Simulation time 2163819621 ps
CPU time 22.45 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:38 PM PDT 24
Peak memory 222728 kb
Host smart-acdf3b2a-fc2b-4fc2-ae6b-123fb9790a49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580076146 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3580076146
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.712289425
Short name T831
Test name
Test status
Simulation time 154434271 ps
CPU time 5.66 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:21 PM PDT 24
Peak memory 214304 kb
Host smart-b9268485-d941-4280-8109-81c38978ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712289425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.712289425
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2490673410
Short name T66
Test name
Test status
Simulation time 42071925 ps
CPU time 2.35 seconds
Started Jun 22 06:05:17 PM PDT 24
Finished Jun 22 06:05:20 PM PDT 24
Peak memory 210260 kb
Host smart-c39ff5fa-c42d-40fa-839a-9534b89cb32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490673410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2490673410
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1298030723
Short name T550
Test name
Test status
Simulation time 73583794 ps
CPU time 0.81 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:15 PM PDT 24
Peak memory 205928 kb
Host smart-3a390d03-b65e-49a3-8755-48d4ccf6521a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298030723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1298030723
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3381687359
Short name T272
Test name
Test status
Simulation time 33957156 ps
CPU time 2.65 seconds
Started Jun 22 06:05:13 PM PDT 24
Finished Jun 22 06:05:16 PM PDT 24
Peak memory 215452 kb
Host smart-e7fff919-ba4e-40d7-9eab-b1c0d34a1a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381687359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3381687359
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2073861403
Short name T579
Test name
Test status
Simulation time 2637164744 ps
CPU time 6.94 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:21 PM PDT 24
Peak memory 222792 kb
Host smart-52b6800f-681e-4721-bfbe-92a9f7ed125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073861403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2073861403
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2777176629
Short name T748
Test name
Test status
Simulation time 521446910 ps
CPU time 3.67 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:18 PM PDT 24
Peak memory 207540 kb
Host smart-220410a2-60fd-4e2b-a286-8ce4a847dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777176629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2777176629
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1324058454
Short name T94
Test name
Test status
Simulation time 4212164191 ps
CPU time 29.69 seconds
Started Jun 22 06:05:17 PM PDT 24
Finished Jun 22 06:05:47 PM PDT 24
Peak memory 214412 kb
Host smart-b64ea4ad-3711-429c-836f-d48525084d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324058454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1324058454
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1706733482
Short name T249
Test name
Test status
Simulation time 86943757 ps
CPU time 1.91 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:18 PM PDT 24
Peak memory 214228 kb
Host smart-fee1003c-9080-421e-a2d7-9adcb083fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706733482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1706733482
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3432873141
Short name T853
Test name
Test status
Simulation time 61586161 ps
CPU time 1.63 seconds
Started Jun 22 06:05:12 PM PDT 24
Finished Jun 22 06:05:14 PM PDT 24
Peak memory 206132 kb
Host smart-ef612f2c-4ad3-4466-aa9c-4cbd4bfe5227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432873141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3432873141
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3858008123
Short name T808
Test name
Test status
Simulation time 503279377 ps
CPU time 9.65 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 207188 kb
Host smart-6bdcec70-d3af-478b-b501-e66fe58cfdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858008123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3858008123
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2496588700
Short name T694
Test name
Test status
Simulation time 84101623 ps
CPU time 3.22 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 208516 kb
Host smart-b342aec5-fb52-4b8b-b5be-3a155530a7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496588700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2496588700
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.589771050
Short name T35
Test name
Test status
Simulation time 364195813 ps
CPU time 5.47 seconds
Started Jun 22 06:05:17 PM PDT 24
Finished Jun 22 06:05:23 PM PDT 24
Peak memory 208524 kb
Host smart-1d41ca14-97aa-4360-bc57-6961ef024efa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589771050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.589771050
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1066408596
Short name T500
Test name
Test status
Simulation time 165393996 ps
CPU time 4.51 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:21 PM PDT 24
Peak memory 208768 kb
Host smart-1fb1f669-b7ec-40ae-831b-de68cdec7bab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066408596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1066408596
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1343738896
Short name T2
Test name
Test status
Simulation time 375859416 ps
CPU time 4.26 seconds
Started Jun 22 06:05:17 PM PDT 24
Finished Jun 22 06:05:22 PM PDT 24
Peak memory 208880 kb
Host smart-876170a0-35d1-4f54-be39-66de4e280692
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343738896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1343738896
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3176914875
Short name T888
Test name
Test status
Simulation time 97073322 ps
CPU time 2.08 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:17 PM PDT 24
Peak memory 214328 kb
Host smart-e484c953-c59b-4c53-bbad-6ed0109200d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176914875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3176914875
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1049935151
Short name T419
Test name
Test status
Simulation time 211219583 ps
CPU time 2.25 seconds
Started Jun 22 06:05:16 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 206816 kb
Host smart-e3e0bd03-6781-426a-9741-7986b9710311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049935151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1049935151
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.49753440
Short name T880
Test name
Test status
Simulation time 6758837267 ps
CPU time 30.84 seconds
Started Jun 22 06:05:14 PM PDT 24
Finished Jun 22 06:05:45 PM PDT 24
Peak memory 208972 kb
Host smart-56efd3e5-4a79-4235-9029-5faf7dcb63a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49753440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.49753440
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3515322829
Short name T735
Test name
Test status
Simulation time 72202223 ps
CPU time 2.94 seconds
Started Jun 22 06:05:19 PM PDT 24
Finished Jun 22 06:05:22 PM PDT 24
Peak memory 210260 kb
Host smart-a261fb55-818b-4f6c-b537-939675e6c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515322829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3515322829
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2140860309
Short name T14
Test name
Test status
Simulation time 39967619 ps
CPU time 0.82 seconds
Started Jun 22 06:02:58 PM PDT 24
Finished Jun 22 06:02:59 PM PDT 24
Peak memory 205904 kb
Host smart-b934080a-7b59-46fd-beb2-6a1734d3a80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140860309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2140860309
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.372123625
Short name T389
Test name
Test status
Simulation time 72715382 ps
CPU time 3.91 seconds
Started Jun 22 06:02:51 PM PDT 24
Finished Jun 22 06:02:56 PM PDT 24
Peak memory 214544 kb
Host smart-2c9b5d5b-d5a1-4368-a5c6-910dfe4e2bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372123625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.372123625
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4287094067
Short name T718
Test name
Test status
Simulation time 133426232 ps
CPU time 3.23 seconds
Started Jun 22 06:02:49 PM PDT 24
Finished Jun 22 06:02:53 PM PDT 24
Peak memory 220360 kb
Host smart-b159fddf-fc78-4e5b-a067-6ae9fbfedb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287094067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4287094067
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1161131246
Short name T834
Test name
Test status
Simulation time 351405167 ps
CPU time 2.44 seconds
Started Jun 22 06:02:51 PM PDT 24
Finished Jun 22 06:02:54 PM PDT 24
Peak memory 214348 kb
Host smart-cddc6add-3a41-40d0-97ef-d948a6b13ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161131246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1161131246
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1342835117
Short name T364
Test name
Test status
Simulation time 121588826 ps
CPU time 3.34 seconds
Started Jun 22 06:02:48 PM PDT 24
Finished Jun 22 06:02:52 PM PDT 24
Peak memory 211276 kb
Host smart-dd3d9ea5-2359-497b-93b5-5b66c109aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342835117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1342835117
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2286388505
Short name T230
Test name
Test status
Simulation time 136369231 ps
CPU time 7.58 seconds
Started Jun 22 06:02:51 PM PDT 24
Finished Jun 22 06:02:59 PM PDT 24
Peak memory 222548 kb
Host smart-4d019b41-54a9-45f1-bc59-79c0a6c0b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286388505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2286388505
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2938619677
Short name T475
Test name
Test status
Simulation time 796138349 ps
CPU time 9.21 seconds
Started Jun 22 06:02:48 PM PDT 24
Finished Jun 22 06:02:58 PM PDT 24
Peak memory 209200 kb
Host smart-96d91bb1-06ca-4e32-9c53-929214c0383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938619677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2938619677
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3691869969
Short name T758
Test name
Test status
Simulation time 635158145 ps
CPU time 17.94 seconds
Started Jun 22 06:02:43 PM PDT 24
Finished Jun 22 06:03:01 PM PDT 24
Peak memory 208904 kb
Host smart-11bb20b5-f58f-4898-a408-4af3d10d0cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691869969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3691869969
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4104617271
Short name T565
Test name
Test status
Simulation time 987813951 ps
CPU time 7.43 seconds
Started Jun 22 06:02:49 PM PDT 24
Finished Jun 22 06:02:57 PM PDT 24
Peak memory 208312 kb
Host smart-6374709e-62a9-40bf-b67f-fbc62d91e7bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104617271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4104617271
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.386658443
Short name T422
Test name
Test status
Simulation time 192570730 ps
CPU time 5.68 seconds
Started Jun 22 06:02:50 PM PDT 24
Finished Jun 22 06:02:56 PM PDT 24
Peak memory 207968 kb
Host smart-77e9d13a-8951-4400-b4e4-676a5dd7e6d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386658443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.386658443
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1604436120
Short name T672
Test name
Test status
Simulation time 359414357 ps
CPU time 8.34 seconds
Started Jun 22 06:02:51 PM PDT 24
Finished Jun 22 06:02:59 PM PDT 24
Peak memory 208992 kb
Host smart-f2275b45-dfa3-4751-a957-35c521cd0efd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604436120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1604436120
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1869487632
Short name T497
Test name
Test status
Simulation time 158735443 ps
CPU time 3.04 seconds
Started Jun 22 06:02:43 PM PDT 24
Finished Jun 22 06:02:46 PM PDT 24
Peak memory 208116 kb
Host smart-5d3a7371-f6fd-4ded-8e16-a8b176f34059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869487632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1869487632
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3975628487
Short name T117
Test name
Test status
Simulation time 561473007 ps
CPU time 11.76 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 222616 kb
Host smart-a2134842-b1bd-475c-bd8a-d56f44b00ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975628487 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3975628487
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.805871737
Short name T434
Test name
Test status
Simulation time 153280538 ps
CPU time 6.8 seconds
Started Jun 22 06:02:49 PM PDT 24
Finished Jun 22 06:02:56 PM PDT 24
Peak memory 209976 kb
Host smart-c552d248-32be-419e-835a-0b2d0674c652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805871737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.805871737
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.184557227
Short name T161
Test name
Test status
Simulation time 91803518 ps
CPU time 1.77 seconds
Started Jun 22 06:02:49 PM PDT 24
Finished Jun 22 06:02:51 PM PDT 24
Peak memory 209552 kb
Host smart-95f00e83-125a-45c0-a3ca-8df0b5041f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184557227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.184557227
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2768594607
Short name T781
Test name
Test status
Simulation time 33564241 ps
CPU time 0.96 seconds
Started Jun 22 06:05:19 PM PDT 24
Finished Jun 22 06:05:21 PM PDT 24
Peak memory 206076 kb
Host smart-179429ef-84c5-4b10-89a9-854651c5aa5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768594607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2768594607
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2893380038
Short name T393
Test name
Test status
Simulation time 74628452 ps
CPU time 3.09 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:27 PM PDT 24
Peak memory 215044 kb
Host smart-90be417e-aded-42eb-aec9-33f54d8df3b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893380038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2893380038
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1225955798
Short name T19
Test name
Test status
Simulation time 67401952 ps
CPU time 1.5 seconds
Started Jun 22 06:05:22 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 215720 kb
Host smart-e7554350-565e-4735-bbc7-615e43909cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225955798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1225955798
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.221794578
Short name T465
Test name
Test status
Simulation time 38327476 ps
CPU time 1.99 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:25 PM PDT 24
Peak memory 209444 kb
Host smart-8e4044d6-e120-420a-bc13-6894c203bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221794578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.221794578
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1957675358
Short name T804
Test name
Test status
Simulation time 91332841 ps
CPU time 4.77 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 215784 kb
Host smart-da592745-d1b5-4c8f-9b56-1f474689aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957675358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1957675358
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3706811456
Short name T832
Test name
Test status
Simulation time 39366903 ps
CPU time 2.33 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:25 PM PDT 24
Peak memory 214392 kb
Host smart-972e7752-26a1-4f49-89f6-418748485a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706811456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3706811456
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3046034009
Short name T849
Test name
Test status
Simulation time 350836729 ps
CPU time 4.27 seconds
Started Jun 22 06:05:24 PM PDT 24
Finished Jun 22 06:05:29 PM PDT 24
Peak memory 208268 kb
Host smart-70c53c0b-bafe-4cd3-89ad-d440575a20c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046034009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3046034009
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1531111025
Short name T345
Test name
Test status
Simulation time 202579837 ps
CPU time 3.77 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 208368 kb
Host smart-39a94f6d-902c-47ed-bf9b-ae221405532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531111025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1531111025
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3007620466
Short name T479
Test name
Test status
Simulation time 610846094 ps
CPU time 6.98 seconds
Started Jun 22 06:05:18 PM PDT 24
Finished Jun 22 06:05:25 PM PDT 24
Peak memory 208508 kb
Host smart-8336c344-a523-46a3-95d0-c6bc811f96dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007620466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3007620466
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.126406490
Short name T332
Test name
Test status
Simulation time 176608765 ps
CPU time 3.3 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 208812 kb
Host smart-b91715bf-44d1-4215-82fc-9a975eaf8234
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126406490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.126406490
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.703637500
Short name T559
Test name
Test status
Simulation time 108213090 ps
CPU time 2.67 seconds
Started Jun 22 06:05:20 PM PDT 24
Finished Jun 22 06:05:23 PM PDT 24
Peak memory 206912 kb
Host smart-42b03f18-3d8a-4539-a00a-66ccb05fd6fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703637500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.703637500
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2947213677
Short name T395
Test name
Test status
Simulation time 55896304 ps
CPU time 1.84 seconds
Started Jun 22 06:05:24 PM PDT 24
Finished Jun 22 06:05:26 PM PDT 24
Peak memory 209360 kb
Host smart-3bcab789-8b70-4bc1-aea0-477e6a1d4ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947213677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2947213677
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2633486945
Short name T884
Test name
Test status
Simulation time 12796518517 ps
CPU time 21.83 seconds
Started Jun 22 06:05:15 PM PDT 24
Finished Jun 22 06:05:38 PM PDT 24
Peak memory 208632 kb
Host smart-bd9d22c8-3c65-4d95-be85-23374dc00855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633486945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2633486945
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3121412083
Short name T897
Test name
Test status
Simulation time 1196664756 ps
CPU time 15.76 seconds
Started Jun 22 06:05:20 PM PDT 24
Finished Jun 22 06:05:36 PM PDT 24
Peak memory 220536 kb
Host smart-1a97f230-38b8-4a78-97ac-35a5a1f65d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121412083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3121412083
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.82866903
Short name T701
Test name
Test status
Simulation time 222798989 ps
CPU time 7.81 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:31 PM PDT 24
Peak memory 222556 kb
Host smart-36c91e01-6f24-4962-8cb0-aba9ddbd447b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82866903 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.82866903
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4276466007
Short name T446
Test name
Test status
Simulation time 95091086 ps
CPU time 4.51 seconds
Started Jun 22 06:05:25 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 207716 kb
Host smart-7e83513c-ef1f-4eb6-a793-9411ad1ccc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276466007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4276466007
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.634980440
Short name T171
Test name
Test status
Simulation time 885080113 ps
CPU time 10.17 seconds
Started Jun 22 06:05:19 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 210324 kb
Host smart-4764ab28-1516-461c-97b7-e70cd6fc240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634980440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.634980440
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3232346482
Short name T431
Test name
Test status
Simulation time 13863324 ps
CPU time 0.77 seconds
Started Jun 22 06:05:27 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 205932 kb
Host smart-34ad84e9-d90a-4f36-8fb8-2bd610522e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232346482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3232346482
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4266161382
Short name T138
Test name
Test status
Simulation time 195951084 ps
CPU time 4.18 seconds
Started Jun 22 06:05:22 PM PDT 24
Finished Jun 22 06:05:27 PM PDT 24
Peak memory 222552 kb
Host smart-0a997c76-a992-4f65-8cb9-127d9970bc58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266161382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4266161382
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3581866962
Short name T509
Test name
Test status
Simulation time 181397098 ps
CPU time 4.56 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:43 PM PDT 24
Peak memory 214616 kb
Host smart-17faf970-9402-4072-9e9f-77323fe65d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581866962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3581866962
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1523407644
Short name T77
Test name
Test status
Simulation time 37115054 ps
CPU time 2.3 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:26 PM PDT 24
Peak memory 218604 kb
Host smart-b900d5c4-138a-4f14-b45e-23490f06d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523407644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1523407644
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.905386711
Short name T568
Test name
Test status
Simulation time 148543768 ps
CPU time 6.06 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 215204 kb
Host smart-e7e8acf5-ff0a-4313-af5e-e7339b6ddea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905386711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.905386711
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.925281480
Short name T140
Test name
Test status
Simulation time 981223090 ps
CPU time 6.2 seconds
Started Jun 22 06:05:21 PM PDT 24
Finished Jun 22 06:05:28 PM PDT 24
Peak memory 219840 kb
Host smart-e114099f-112a-4072-a4ae-9c9f49cbd25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925281480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.925281480
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1002538664
Short name T879
Test name
Test status
Simulation time 322626137 ps
CPU time 3.2 seconds
Started Jun 22 06:05:20 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 206772 kb
Host smart-32c66908-31c2-4b2e-9065-2cc7502f494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002538664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1002538664
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.509651256
Short name T493
Test name
Test status
Simulation time 74608490 ps
CPU time 3.77 seconds
Started Jun 22 06:05:22 PM PDT 24
Finished Jun 22 06:05:26 PM PDT 24
Peak memory 208980 kb
Host smart-92b211bc-bcdc-4d88-a1c8-1a519fcce2fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509651256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.509651256
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2413025011
Short name T736
Test name
Test status
Simulation time 169608822 ps
CPU time 4.8 seconds
Started Jun 22 06:05:25 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 208464 kb
Host smart-a51c4eca-aedc-442a-8353-786a3ec7ff4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413025011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2413025011
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2545952000
Short name T806
Test name
Test status
Simulation time 69518768 ps
CPU time 1.81 seconds
Started Jun 22 06:05:21 PM PDT 24
Finished Jun 22 06:05:24 PM PDT 24
Peak memory 206892 kb
Host smart-a829e1f7-181c-4b21-b7ac-9ff4827cf6a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545952000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2545952000
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.447266904
Short name T700
Test name
Test status
Simulation time 161335166 ps
CPU time 2.09 seconds
Started Jun 22 06:05:31 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 208500 kb
Host smart-13e0e613-32ea-4ddf-a366-d8e8978d9244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447266904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.447266904
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2296776832
Short name T678
Test name
Test status
Simulation time 91286328 ps
CPU time 2.62 seconds
Started Jun 22 06:05:22 PM PDT 24
Finished Jun 22 06:05:25 PM PDT 24
Peak memory 208552 kb
Host smart-d4529874-d92c-4032-8111-a4db684cff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296776832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2296776832
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2980053294
Short name T255
Test name
Test status
Simulation time 458568775 ps
CPU time 11.4 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 215016 kb
Host smart-4c45cb57-ee4f-4283-be24-b08242649225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980053294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2980053294
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.446872954
Short name T670
Test name
Test status
Simulation time 301057637 ps
CPU time 5.12 seconds
Started Jun 22 06:05:23 PM PDT 24
Finished Jun 22 06:05:29 PM PDT 24
Peak memory 214304 kb
Host smart-90fb3292-9c6f-44c2-b01b-6ef1a92e1124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446872954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.446872954
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1126031892
Short name T824
Test name
Test status
Simulation time 149016157 ps
CPU time 2.26 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:33 PM PDT 24
Peak memory 210648 kb
Host smart-9ed3bb07-6c29-420b-8ebb-d2659e82bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126031892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1126031892
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3112448428
Short name T533
Test name
Test status
Simulation time 43005837 ps
CPU time 0.76 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 205908 kb
Host smart-0e8633a1-44d7-4e73-a559-5be4404ea56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112448428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3112448428
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2025805424
Short name T378
Test name
Test status
Simulation time 30343518 ps
CPU time 2.34 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:33 PM PDT 24
Peak memory 214312 kb
Host smart-204c4e8c-a547-48bf-bd0d-e7a94ef45ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025805424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2025805424
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3232136622
Short name T41
Test name
Test status
Simulation time 133575887 ps
CPU time 3.62 seconds
Started Jun 22 06:05:27 PM PDT 24
Finished Jun 22 06:05:31 PM PDT 24
Peak memory 220364 kb
Host smart-30208a2d-90d5-4b10-b208-45546c042ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232136622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3232136622
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1006548255
Short name T5
Test name
Test status
Simulation time 95340583 ps
CPU time 2.09 seconds
Started Jun 22 06:05:25 PM PDT 24
Finished Jun 22 06:05:27 PM PDT 24
Peak memory 209804 kb
Host smart-e5fd2f58-96ab-4d4d-8463-acf78320d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006548255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1006548255
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1309819144
Short name T807
Test name
Test status
Simulation time 6522382703 ps
CPU time 12.23 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 214636 kb
Host smart-b9d1cf3d-386c-41c5-bd1e-8324c238d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309819144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1309819144
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3307959116
Short name T644
Test name
Test status
Simulation time 82432597 ps
CPU time 2.58 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:31 PM PDT 24
Peak memory 214308 kb
Host smart-533dc8d4-b31f-4bb8-8788-98da96a209e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307959116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3307959116
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3742932119
Short name T7
Test name
Test status
Simulation time 155889760 ps
CPU time 3.34 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 222460 kb
Host smart-7379fd96-da5c-4f1d-98bb-6008424c7878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742932119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3742932119
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3212625763
Short name T653
Test name
Test status
Simulation time 4552997515 ps
CPU time 21.46 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:50 PM PDT 24
Peak memory 209080 kb
Host smart-d606b4e9-3ef5-48e9-87ec-6cd6493e0b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212625763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3212625763
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3444514927
Short name T631
Test name
Test status
Simulation time 214909338 ps
CPU time 2.82 seconds
Started Jun 22 06:05:31 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 206732 kb
Host smart-37c2ff3b-b724-41f7-8b11-5ddbc0490ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444514927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3444514927
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3092125160
Short name T454
Test name
Test status
Simulation time 870268620 ps
CPU time 5.6 seconds
Started Jun 22 06:05:32 PM PDT 24
Finished Jun 22 06:05:38 PM PDT 24
Peak memory 207936 kb
Host smart-663b8dc3-e0db-4c17-8f47-6ebe8469f25f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092125160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3092125160
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.393377653
Short name T704
Test name
Test status
Simulation time 155492749 ps
CPU time 2.24 seconds
Started Jun 22 06:05:29 PM PDT 24
Finished Jun 22 06:05:32 PM PDT 24
Peak memory 206908 kb
Host smart-ddc25c7f-b78b-4286-bd15-5a6193a934eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393377653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.393377653
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3645742491
Short name T622
Test name
Test status
Simulation time 380434260 ps
CPU time 4.34 seconds
Started Jun 22 06:05:35 PM PDT 24
Finished Jun 22 06:05:39 PM PDT 24
Peak memory 208592 kb
Host smart-eac5585f-2e81-4c7c-b86b-167813cfab8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645742491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3645742491
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2605371458
Short name T592
Test name
Test status
Simulation time 134998196 ps
CPU time 4.37 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 209920 kb
Host smart-830e6b42-7aaf-4a5b-bf23-9a08360b9e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605371458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2605371458
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.214580182
Short name T590
Test name
Test status
Simulation time 835397887 ps
CPU time 6.02 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:36 PM PDT 24
Peak memory 206808 kb
Host smart-e0ec7b68-725a-4d93-b0f2-17f9b30a541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214580182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.214580182
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3570084491
Short name T76
Test name
Test status
Simulation time 4126377500 ps
CPU time 50.92 seconds
Started Jun 22 06:05:29 PM PDT 24
Finished Jun 22 06:06:20 PM PDT 24
Peak memory 221892 kb
Host smart-fe29268b-3a24-498f-b575-99581279a60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570084491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3570084491
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1744690346
Short name T82
Test name
Test status
Simulation time 2667804437 ps
CPU time 21.58 seconds
Started Jun 22 06:05:32 PM PDT 24
Finished Jun 22 06:05:54 PM PDT 24
Peak memory 222684 kb
Host smart-fd78628b-b8aa-49ec-bf43-eff66294a312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744690346 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1744690346
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2283329
Short name T245
Test name
Test status
Simulation time 139157127 ps
CPU time 3.59 seconds
Started Jun 22 06:05:33 PM PDT 24
Finished Jun 22 06:05:37 PM PDT 24
Peak memory 209388 kb
Host smart-78c93834-b53c-401b-9ec8-66373a943345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2283329
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2228173468
Short name T370
Test name
Test status
Simulation time 241676025 ps
CPU time 1.61 seconds
Started Jun 22 06:05:32 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 209788 kb
Host smart-a5b5340a-67a7-4464-b41e-1414c813a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228173468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2228173468
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2858680991
Short name T506
Test name
Test status
Simulation time 48862794 ps
CPU time 0.73 seconds
Started Jun 22 06:05:39 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 205872 kb
Host smart-83d0f5ba-9547-4121-842c-7124d013e5ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858680991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2858680991
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.713286361
Short name T184
Test name
Test status
Simulation time 899345140 ps
CPU time 3.92 seconds
Started Jun 22 06:05:30 PM PDT 24
Finished Jun 22 06:05:35 PM PDT 24
Peak memory 219652 kb
Host smart-1bfed76a-785c-40f5-9dd6-242525e7ad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713286361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.713286361
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1036424145
Short name T889
Test name
Test status
Simulation time 160779403 ps
CPU time 3.67 seconds
Started Jun 22 06:05:29 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 218512 kb
Host smart-650c6ff0-8139-4e4a-98e8-d0f94555fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036424145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1036424145
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4002953553
Short name T516
Test name
Test status
Simulation time 507179558 ps
CPU time 4.07 seconds
Started Jun 22 06:05:29 PM PDT 24
Finished Jun 22 06:05:34 PM PDT 24
Peak memory 222020 kb
Host smart-901312d5-738a-45f8-a809-df59fca57ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002953553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4002953553
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2889885254
Short name T680
Test name
Test status
Simulation time 91890792 ps
CPU time 2.77 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 206088 kb
Host smart-5ec04e9e-4c65-4607-bd89-cc06a0086efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889885254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2889885254
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1194131582
Short name T795
Test name
Test status
Simulation time 40456855 ps
CPU time 2.34 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:30 PM PDT 24
Peak memory 214288 kb
Host smart-1cce3445-95f5-4e69-98e6-1198c8b00687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194131582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1194131582
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1179304469
Short name T535
Test name
Test status
Simulation time 293128798 ps
CPU time 3.54 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 214236 kb
Host smart-53e2db58-0574-4166-8a72-b42f69cb3021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179304469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1179304469
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1646084274
Short name T100
Test name
Test status
Simulation time 302119624 ps
CPU time 4.44 seconds
Started Jun 22 06:05:35 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 206964 kb
Host smart-c29f745f-de60-45ae-8688-567ec5119436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646084274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1646084274
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3224804959
Short name T613
Test name
Test status
Simulation time 393532698 ps
CPU time 4.66 seconds
Started Jun 22 06:05:27 PM PDT 24
Finished Jun 22 06:05:33 PM PDT 24
Peak memory 207072 kb
Host smart-3c6661a7-5412-4e63-9838-bcf957ee1ec0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224804959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3224804959
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3029188811
Short name T650
Test name
Test status
Simulation time 50931288 ps
CPU time 2.73 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:32 PM PDT 24
Peak memory 206920 kb
Host smart-47101848-b938-4d7a-bcf1-7b2f0b7e1bb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029188811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3029188811
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2911164842
Short name T119
Test name
Test status
Simulation time 40721414 ps
CPU time 1.81 seconds
Started Jun 22 06:05:31 PM PDT 24
Finished Jun 22 06:05:33 PM PDT 24
Peak memory 206808 kb
Host smart-50d6fdf1-9ec4-4a25-8255-06dab2e3c291
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911164842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2911164842
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2800685133
Short name T481
Test name
Test status
Simulation time 56492704 ps
CPU time 2.36 seconds
Started Jun 22 06:05:29 PM PDT 24
Finished Jun 22 06:05:32 PM PDT 24
Peak memory 214336 kb
Host smart-fe5ef460-3db0-4c7c-9eb4-d7de30483baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800685133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2800685133
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1059091229
Short name T712
Test name
Test status
Simulation time 317904551 ps
CPU time 3.76 seconds
Started Jun 22 06:05:31 PM PDT 24
Finished Jun 22 06:05:35 PM PDT 24
Peak memory 207304 kb
Host smart-b99d2afa-b4ba-4b91-ba7c-ba81e36770e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059091229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1059091229
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.211332877
Short name T668
Test name
Test status
Simulation time 1179166570 ps
CPU time 18.89 seconds
Started Jun 22 06:05:38 PM PDT 24
Finished Jun 22 06:05:58 PM PDT 24
Peak memory 220744 kb
Host smart-0583698d-9489-4654-9f0a-479aabb41234
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211332877 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.211332877
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1017984131
Short name T671
Test name
Test status
Simulation time 644649060 ps
CPU time 6.15 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:35 PM PDT 24
Peak memory 208212 kb
Host smart-e6618363-927d-4a9f-b792-ddee8cda775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017984131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1017984131
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1738049491
Short name T204
Test name
Test status
Simulation time 156801438 ps
CPU time 3.23 seconds
Started Jun 22 06:05:28 PM PDT 24
Finished Jun 22 06:05:32 PM PDT 24
Peak memory 210208 kb
Host smart-918aa29b-07da-4461-b3f3-4b4ac36e01c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738049491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1738049491
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1778852409
Short name T845
Test name
Test status
Simulation time 72192799 ps
CPU time 0.74 seconds
Started Jun 22 06:05:35 PM PDT 24
Finished Jun 22 06:05:36 PM PDT 24
Peak memory 205936 kb
Host smart-c81e47d5-3e8a-4b80-a5da-768bbd6a470d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778852409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1778852409
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3234505662
Short name T394
Test name
Test status
Simulation time 259091200 ps
CPU time 7.06 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:45 PM PDT 24
Peak memory 214916 kb
Host smart-b69672ac-138d-4169-bd39-f97ef3f451d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234505662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3234505662
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2591796734
Short name T10
Test name
Test status
Simulation time 4039717652 ps
CPU time 40.85 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:06:18 PM PDT 24
Peak memory 223004 kb
Host smart-1a4770c5-0810-4ec3-848b-218ccbead406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591796734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2591796734
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3773603176
Short name T662
Test name
Test status
Simulation time 196517727 ps
CPU time 2.59 seconds
Started Jun 22 06:05:41 PM PDT 24
Finished Jun 22 06:05:44 PM PDT 24
Peak memory 207884 kb
Host smart-02ce9918-43ed-4b38-8c91-f93c3c4dcc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773603176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3773603176
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1815890878
Short name T271
Test name
Test status
Simulation time 387319962 ps
CPU time 5.14 seconds
Started Jun 22 06:05:38 PM PDT 24
Finished Jun 22 06:05:44 PM PDT 24
Peak memory 222460 kb
Host smart-01151e37-0acc-490c-aba3-37deecac03c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815890878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1815890878
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4090641970
Short name T911
Test name
Test status
Simulation time 137144930 ps
CPU time 4.54 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 222528 kb
Host smart-be5a5526-a38d-48c0-9ef7-9eab0cfa0a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090641970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4090641970
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.575538441
Short name T304
Test name
Test status
Simulation time 54355020 ps
CPU time 3.41 seconds
Started Jun 22 06:05:34 PM PDT 24
Finished Jun 22 06:05:38 PM PDT 24
Peak memory 214324 kb
Host smart-0be09464-581a-467d-838b-6bc3e92a4afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575538441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.575538441
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3181031047
Short name T445
Test name
Test status
Simulation time 1065114335 ps
CPU time 9.81 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 208024 kb
Host smart-5514667a-5108-4d63-a6ae-5a4b68367a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181031047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3181031047
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.628429079
Short name T492
Test name
Test status
Simulation time 879419864 ps
CPU time 14.16 seconds
Started Jun 22 06:05:34 PM PDT 24
Finished Jun 22 06:05:49 PM PDT 24
Peak memory 208856 kb
Host smart-8359ad78-771e-45c8-95bd-f7ce4c6c9b14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628429079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.628429079
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3231938047
Short name T870
Test name
Test status
Simulation time 72669070 ps
CPU time 3.81 seconds
Started Jun 22 06:05:45 PM PDT 24
Finished Jun 22 06:05:50 PM PDT 24
Peak memory 208448 kb
Host smart-1f7f61f1-3798-434d-9f60-443e80ab90e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231938047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3231938047
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1289710926
Short name T742
Test name
Test status
Simulation time 82341077 ps
CPU time 3.32 seconds
Started Jun 22 06:05:42 PM PDT 24
Finished Jun 22 06:05:46 PM PDT 24
Peak memory 209092 kb
Host smart-f8a62939-40ad-4e30-b4ee-77a8dcf6cd26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289710926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1289710926
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.879077244
Short name T264
Test name
Test status
Simulation time 106060829 ps
CPU time 1.98 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 209616 kb
Host smart-fadefca2-e962-4e6c-ba6e-7f9e6733fe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879077244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.879077244
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3352631561
Short name T574
Test name
Test status
Simulation time 211217783 ps
CPU time 4.39 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 208704 kb
Host smart-8228b4ae-fe91-43d7-8e2f-8de38424fc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352631561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3352631561
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3778099563
Short name T685
Test name
Test status
Simulation time 110082463 ps
CPU time 3.06 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 219668 kb
Host smart-80829f1d-ae5f-4366-876f-5f4ce14832dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778099563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3778099563
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.585797648
Short name T39
Test name
Test status
Simulation time 143706732 ps
CPU time 3.59 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 218284 kb
Host smart-19a4a99c-a7f7-4389-89d6-c85c7923bc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585797648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.585797648
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1415759552
Short name T594
Test name
Test status
Simulation time 330755309 ps
CPU time 2.65 seconds
Started Jun 22 06:05:38 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 209932 kb
Host smart-a17262ef-524f-4043-b717-a28dc0b7f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415759552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1415759552
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1618679819
Short name T917
Test name
Test status
Simulation time 12586217 ps
CPU time 0.73 seconds
Started Jun 22 06:05:35 PM PDT 24
Finished Jun 22 06:05:36 PM PDT 24
Peak memory 205936 kb
Host smart-cc451d37-192a-4164-9b2d-a02049d68031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618679819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1618679819
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.428964597
Short name T356
Test name
Test status
Simulation time 845208801 ps
CPU time 4.71 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:43 PM PDT 24
Peak memory 207792 kb
Host smart-aa49945e-b73d-4ed7-a149-7d82e31fbba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428964597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.428964597
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1163745833
Short name T23
Test name
Test status
Simulation time 444102973 ps
CPU time 6.95 seconds
Started Jun 22 06:05:38 PM PDT 24
Finished Jun 22 06:05:45 PM PDT 24
Peak memory 220960 kb
Host smart-ecf217df-7095-4f62-8145-77f615cb8eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163745833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1163745833
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1762423243
Short name T614
Test name
Test status
Simulation time 541491010 ps
CPU time 3.53 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 220816 kb
Host smart-c7827489-04da-4acd-a4e0-f1fe6051b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762423243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1762423243
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2857699862
Short name T278
Test name
Test status
Simulation time 177967779 ps
CPU time 3.52 seconds
Started Jun 22 06:05:38 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 210048 kb
Host smart-e7f7fa23-d4d1-4463-a71e-22e4ebe93dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857699862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2857699862
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3286436682
Short name T120
Test name
Test status
Simulation time 183349334 ps
CPU time 5.71 seconds
Started Jun 22 06:05:39 PM PDT 24
Finished Jun 22 06:05:46 PM PDT 24
Peak memory 208112 kb
Host smart-255c82fe-ca92-49dd-bb7a-2ed658a2ec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286436682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3286436682
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3444145673
Short name T773
Test name
Test status
Simulation time 200669674 ps
CPU time 3.07 seconds
Started Jun 22 06:05:35 PM PDT 24
Finished Jun 22 06:05:38 PM PDT 24
Peak memory 206896 kb
Host smart-b6181a87-6b65-47c9-a0c2-d81c29c532c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444145673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3444145673
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3410742846
Short name T759
Test name
Test status
Simulation time 85641380 ps
CPU time 3.37 seconds
Started Jun 22 06:05:39 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 208212 kb
Host smart-115924ce-e10a-4260-ae4e-3b40f3e4ace5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410742846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3410742846
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1062521147
Short name T496
Test name
Test status
Simulation time 91983731 ps
CPU time 2.74 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 206916 kb
Host smart-42098763-aecd-45b9-ba28-5071e3dc28d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062521147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1062521147
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2024055030
Short name T460
Test name
Test status
Simulation time 39107801 ps
CPU time 2.33 seconds
Started Jun 22 06:05:39 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 206792 kb
Host smart-bf9997cd-70f1-47fd-bf7a-eaeaa2463928
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024055030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2024055030
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1293062957
Short name T206
Test name
Test status
Simulation time 203275660 ps
CPU time 2.34 seconds
Started Jun 22 06:05:45 PM PDT 24
Finished Jun 22 06:05:49 PM PDT 24
Peak memory 216040 kb
Host smart-0a2031f9-e1bc-4988-8567-3050e045da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293062957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1293062957
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2241829332
Short name T820
Test name
Test status
Simulation time 22329499 ps
CPU time 1.8 seconds
Started Jun 22 06:05:41 PM PDT 24
Finished Jun 22 06:05:43 PM PDT 24
Peak memory 207260 kb
Host smart-5cf0ffef-445b-472e-b79c-2e90f2b0b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241829332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2241829332
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3611574961
Short name T858
Test name
Test status
Simulation time 506949673 ps
CPU time 19.26 seconds
Started Jun 22 06:05:43 PM PDT 24
Finished Jun 22 06:06:02 PM PDT 24
Peak memory 215132 kb
Host smart-dd1d2f21-4bbf-4f13-911e-aa4ef2e370d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611574961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3611574961
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3824699047
Short name T657
Test name
Test status
Simulation time 416105479 ps
CPU time 16.12 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:54 PM PDT 24
Peak memory 220664 kb
Host smart-9b940e65-4a9f-49ca-9268-620832ac57fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824699047 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3824699047
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.753918256
Short name T359
Test name
Test status
Simulation time 106355363 ps
CPU time 3.89 seconds
Started Jun 22 06:05:38 PM PDT 24
Finished Jun 22 06:05:42 PM PDT 24
Peak memory 218428 kb
Host smart-35e35a8b-bdec-4ff9-b781-86d8f0718328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753918256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.753918256
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2477062729
Short name T733
Test name
Test status
Simulation time 84409626 ps
CPU time 2.95 seconds
Started Jun 22 06:05:41 PM PDT 24
Finished Jun 22 06:05:44 PM PDT 24
Peak memory 210056 kb
Host smart-b2dbd529-b86d-428d-9bb4-7839f420b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477062729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2477062729
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1708249809
Short name T504
Test name
Test status
Simulation time 28867682 ps
CPU time 1.04 seconds
Started Jun 22 06:05:42 PM PDT 24
Finished Jun 22 06:05:44 PM PDT 24
Peak memory 206092 kb
Host smart-2091cc92-4de5-4586-9372-85da4afa20ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708249809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1708249809
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.272390362
Short name T379
Test name
Test status
Simulation time 87020732 ps
CPU time 5.65 seconds
Started Jun 22 06:05:46 PM PDT 24
Finished Jun 22 06:05:52 PM PDT 24
Peak memory 214392 kb
Host smart-f9373437-844b-4fc4-9393-a7c7892e1f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272390362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.272390362
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3409973066
Short name T821
Test name
Test status
Simulation time 101207936 ps
CPU time 3.89 seconds
Started Jun 22 06:05:43 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 210412 kb
Host smart-eb2134fd-0d01-4200-a997-1e55d7a62122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409973066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3409973066
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2125914361
Short name T636
Test name
Test status
Simulation time 398517179 ps
CPU time 5.19 seconds
Started Jun 22 06:05:44 PM PDT 24
Finished Jun 22 06:05:49 PM PDT 24
Peak memory 209932 kb
Host smart-b07b9412-4fa5-4deb-a892-6c5ec4555f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125914361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2125914361
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.596562560
Short name T286
Test name
Test status
Simulation time 76972297 ps
CPU time 2.2 seconds
Started Jun 22 06:05:44 PM PDT 24
Finished Jun 22 06:05:47 PM PDT 24
Peak memory 214248 kb
Host smart-fd83ec36-20f7-4be5-89a4-e92d7eaa29a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596562560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.596562560
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3299916223
Short name T673
Test name
Test status
Simulation time 48416237 ps
CPU time 2.09 seconds
Started Jun 22 06:05:46 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 220240 kb
Host smart-dc24ed67-d14b-42e3-a1c1-5705fa9e5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299916223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3299916223
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1440387413
Short name T848
Test name
Test status
Simulation time 106687759 ps
CPU time 2.73 seconds
Started Jun 22 06:05:50 PM PDT 24
Finished Jun 22 06:05:53 PM PDT 24
Peak memory 208220 kb
Host smart-ccf912ad-4862-457a-8fc1-84d7118807f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440387413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1440387413
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3457821562
Short name T123
Test name
Test status
Simulation time 320113579 ps
CPU time 2.76 seconds
Started Jun 22 06:05:36 PM PDT 24
Finished Jun 22 06:05:40 PM PDT 24
Peak memory 207464 kb
Host smart-311c7e41-f7a4-430a-a35a-9f873b8e5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457821562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3457821562
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1095618263
Short name T836
Test name
Test status
Simulation time 3034509767 ps
CPU time 7.22 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:45 PM PDT 24
Peak memory 208108 kb
Host smart-d90cce18-957f-4d38-8d32-9b4ef072a09a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095618263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1095618263
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.202868350
Short name T734
Test name
Test status
Simulation time 257746214 ps
CPU time 3.35 seconds
Started Jun 22 06:05:37 PM PDT 24
Finished Jun 22 06:05:41 PM PDT 24
Peak memory 206972 kb
Host smart-b9b3471b-41b0-488a-8f7d-0e80181627d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202868350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.202868350
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.157724150
Short name T868
Test name
Test status
Simulation time 1650515479 ps
CPU time 12.43 seconds
Started Jun 22 06:05:44 PM PDT 24
Finished Jun 22 06:05:57 PM PDT 24
Peak memory 208388 kb
Host smart-8e30f209-72a7-4940-9cc6-f35658266942
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157724150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.157724150
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2010714293
Short name T774
Test name
Test status
Simulation time 52645500 ps
CPU time 2.92 seconds
Started Jun 22 06:05:42 PM PDT 24
Finished Jun 22 06:05:45 PM PDT 24
Peak memory 214304 kb
Host smart-765452af-db9d-4aee-b62f-2f8b7af3a37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010714293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2010714293
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2868031016
Short name T586
Test name
Test status
Simulation time 411270435 ps
CPU time 3.97 seconds
Started Jun 22 06:05:43 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 208716 kb
Host smart-3ea87991-19ee-4aa7-9d50-36dfc1e756f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868031016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2868031016
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.900453742
Short name T226
Test name
Test status
Simulation time 2249208552 ps
CPU time 22.74 seconds
Started Jun 22 06:05:43 PM PDT 24
Finished Jun 22 06:06:07 PM PDT 24
Peak memory 222652 kb
Host smart-2854cabc-e2fa-45aa-b87f-549f31bccb91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900453742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.900453742
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4083275486
Short name T835
Test name
Test status
Simulation time 205798254 ps
CPU time 6.78 seconds
Started Jun 22 06:05:46 PM PDT 24
Finished Jun 22 06:05:53 PM PDT 24
Peak memory 222520 kb
Host smart-6a53ea3a-3341-4a8b-8525-8bc0167da1df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083275486 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4083275486
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1739066675
Short name T803
Test name
Test status
Simulation time 61072518 ps
CPU time 2.8 seconds
Started Jun 22 06:05:44 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 207784 kb
Host smart-5721ea12-1235-431c-bab3-d70ab7ada1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739066675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1739066675
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2222780956
Short name T369
Test name
Test status
Simulation time 1998210681 ps
CPU time 3.43 seconds
Started Jun 22 06:05:45 PM PDT 24
Finished Jun 22 06:05:49 PM PDT 24
Peak memory 210516 kb
Host smart-c779a6b9-7cf6-4907-bdfa-a41a5923145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222780956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2222780956
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2472633962
Short name T840
Test name
Test status
Simulation time 62897962 ps
CPU time 0.78 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:53 PM PDT 24
Peak memory 205924 kb
Host smart-bdb45991-f641-4faf-93d3-d5cff270cf9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472633962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2472633962
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.859817932
Short name T397
Test name
Test status
Simulation time 3277021992 ps
CPU time 16.51 seconds
Started Jun 22 06:05:42 PM PDT 24
Finished Jun 22 06:05:59 PM PDT 24
Peak memory 222580 kb
Host smart-bf0fd55c-1bb4-4a67-85f2-9b44009354d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859817932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.859817932
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1152141444
Short name T81
Test name
Test status
Simulation time 188757022 ps
CPU time 3.06 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:55 PM PDT 24
Peak memory 214292 kb
Host smart-63c75c65-89b3-4b8a-8362-428c82c7908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152141444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1152141444
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.274858121
Short name T24
Test name
Test status
Simulation time 2015527394 ps
CPU time 27.47 seconds
Started Jun 22 06:05:53 PM PDT 24
Finished Jun 22 06:06:22 PM PDT 24
Peak memory 222396 kb
Host smart-d93b93d7-3c46-4071-b897-6087ee24186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274858121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.274858121
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1129262230
Short name T287
Test name
Test status
Simulation time 45329415 ps
CPU time 2.51 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:54 PM PDT 24
Peak memory 220924 kb
Host smart-b38cdc4c-9e6b-4806-b302-f0bc9288b0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129262230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1129262230
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4081735163
Short name T234
Test name
Test status
Simulation time 222188956 ps
CPU time 5.88 seconds
Started Jun 22 06:05:49 PM PDT 24
Finished Jun 22 06:05:55 PM PDT 24
Peak memory 209688 kb
Host smart-0b7f2bc3-58e2-4dd1-80ed-845411fcedae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081735163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4081735163
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3292623129
Short name T246
Test name
Test status
Simulation time 838345099 ps
CPU time 5.34 seconds
Started Jun 22 06:05:46 PM PDT 24
Finished Jun 22 06:05:52 PM PDT 24
Peak memory 208280 kb
Host smart-ac93cbc4-e268-4fb1-9622-7b3c72f4ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292623129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3292623129
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2476619264
Short name T847
Test name
Test status
Simulation time 500569829 ps
CPU time 3.94 seconds
Started Jun 22 06:05:43 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 208708 kb
Host smart-4031ee6b-803e-4601-ba56-991fe4607d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476619264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2476619264
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2415244141
Short name T679
Test name
Test status
Simulation time 88618778 ps
CPU time 2.98 seconds
Started Jun 22 06:05:41 PM PDT 24
Finished Jun 22 06:05:45 PM PDT 24
Peak memory 206892 kb
Host smart-e48e826b-e432-4149-97f4-fd04b7aff355
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415244141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2415244141
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.4053622927
Short name T259
Test name
Test status
Simulation time 170953469 ps
CPU time 5.2 seconds
Started Jun 22 06:05:42 PM PDT 24
Finished Jun 22 06:05:48 PM PDT 24
Peak memory 208540 kb
Host smart-b71a539c-39b5-4272-8145-a017e3d465b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053622927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4053622927
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3075710966
Short name T822
Test name
Test status
Simulation time 222176943 ps
CPU time 3.03 seconds
Started Jun 22 06:05:42 PM PDT 24
Finished Jun 22 06:05:46 PM PDT 24
Peak memory 206768 kb
Host smart-e31fd16c-5b06-4d0f-a33a-9d452252f624
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075710966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3075710966
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3435229585
Short name T878
Test name
Test status
Simulation time 407683428 ps
CPU time 3.72 seconds
Started Jun 22 06:05:52 PM PDT 24
Finished Jun 22 06:05:57 PM PDT 24
Peak memory 210084 kb
Host smart-b64ba3bf-a472-4fc6-a04d-4e3974e1f1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435229585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3435229585
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3758795006
Short name T478
Test name
Test status
Simulation time 18584079313 ps
CPU time 36.93 seconds
Started Jun 22 06:05:45 PM PDT 24
Finished Jun 22 06:06:22 PM PDT 24
Peak memory 208216 kb
Host smart-e210347e-76ad-4d78-b25e-219d66a75be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758795006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3758795006
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2879875078
Short name T764
Test name
Test status
Simulation time 567485748 ps
CPU time 8.13 seconds
Started Jun 22 06:05:52 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 214316 kb
Host smart-617cdbfd-cdc4-4bc7-bd7e-6837835ef66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879875078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2879875078
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4013325642
Short name T530
Test name
Test status
Simulation time 94507621 ps
CPU time 2 seconds
Started Jun 22 06:05:54 PM PDT 24
Finished Jun 22 06:05:56 PM PDT 24
Peak memory 207736 kb
Host smart-f479b40b-484d-415c-aba2-a6cf0e7d2921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013325642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4013325642
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2862408586
Short name T365
Test name
Test status
Simulation time 88271107 ps
CPU time 1.63 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:53 PM PDT 24
Peak memory 210156 kb
Host smart-335e48f0-facf-4dd0-848f-eaff2db5f324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862408586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2862408586
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4159790076
Short name T867
Test name
Test status
Simulation time 222209256 ps
CPU time 0.9 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:03 PM PDT 24
Peak memory 206112 kb
Host smart-20828d6d-7d73-4e00-b85f-9b13cf97e401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159790076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4159790076
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3020964321
Short name T407
Test name
Test status
Simulation time 308883159 ps
CPU time 8.57 seconds
Started Jun 22 06:05:52 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 215780 kb
Host smart-dd8b0c2d-2649-43d2-b7b3-533fd7cb1e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020964321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3020964321
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4199269557
Short name T912
Test name
Test status
Simulation time 168138434 ps
CPU time 2.64 seconds
Started Jun 22 06:05:53 PM PDT 24
Finished Jun 22 06:05:56 PM PDT 24
Peak memory 207564 kb
Host smart-b0a7bbf6-4be4-43f8-9af7-c9edf228d363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199269557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4199269557
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3224794927
Short name T88
Test name
Test status
Simulation time 20106837 ps
CPU time 1.56 seconds
Started Jun 22 06:05:55 PM PDT 24
Finished Jun 22 06:05:57 PM PDT 24
Peak memory 214436 kb
Host smart-82a248d2-a994-4e13-870c-8fa416e5119d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224794927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3224794927
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3707357655
Short name T660
Test name
Test status
Simulation time 750735202 ps
CPU time 5.62 seconds
Started Jun 22 06:05:52 PM PDT 24
Finished Jun 22 06:05:58 PM PDT 24
Peak memory 214324 kb
Host smart-b4ab1740-efb8-42af-a204-72d7399e6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707357655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3707357655
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1557346446
Short name T749
Test name
Test status
Simulation time 773548677 ps
CPU time 5.12 seconds
Started Jun 22 06:05:52 PM PDT 24
Finished Jun 22 06:05:58 PM PDT 24
Peak memory 209972 kb
Host smart-b665b62f-3f56-4c6c-816b-b8d0273f9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557346446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1557346446
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2190211682
Short name T554
Test name
Test status
Simulation time 279366943 ps
CPU time 8.22 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 209868 kb
Host smart-9815fb90-fc5c-43ff-bbdd-8ee72b48f103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190211682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2190211682
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3125175357
Short name T307
Test name
Test status
Simulation time 628416622 ps
CPU time 5.33 seconds
Started Jun 22 06:05:55 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 208064 kb
Host smart-d475c678-a776-410d-aaaf-43d214ee50cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125175357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3125175357
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2323772237
Short name T895
Test name
Test status
Simulation time 412996158 ps
CPU time 5.15 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:57 PM PDT 24
Peak memory 208656 kb
Host smart-abf33e70-8d24-452f-82c2-98b62802b4ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323772237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2323772237
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1827855111
Short name T784
Test name
Test status
Simulation time 123546236 ps
CPU time 2.47 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:54 PM PDT 24
Peak memory 207012 kb
Host smart-1567e52a-7b72-4fcd-aa07-f3e4137fd548
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827855111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1827855111
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2153262292
Short name T593
Test name
Test status
Simulation time 1103491044 ps
CPU time 4.46 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:56 PM PDT 24
Peak memory 207912 kb
Host smart-97dca324-efde-4299-85b4-e25158d3101f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153262292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2153262292
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.157903048
Short name T469
Test name
Test status
Simulation time 88646555 ps
CPU time 1.95 seconds
Started Jun 22 06:05:50 PM PDT 24
Finished Jun 22 06:05:52 PM PDT 24
Peak memory 207864 kb
Host smart-65494c7e-9f8a-4ed5-b996-82d6a58b39a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157903048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.157903048
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3120623927
Short name T800
Test name
Test status
Simulation time 103422254 ps
CPU time 3.53 seconds
Started Jun 22 06:05:50 PM PDT 24
Finished Jun 22 06:05:54 PM PDT 24
Peak memory 208340 kb
Host smart-b44abdc8-b485-47c5-996c-de5a5652519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120623927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3120623927
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3484773446
Short name T838
Test name
Test status
Simulation time 852856387 ps
CPU time 5 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:57 PM PDT 24
Peak memory 208248 kb
Host smart-d7a41f27-e79c-4d77-96b9-fbe083517b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484773446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3484773446
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2822182810
Short name T814
Test name
Test status
Simulation time 245253724 ps
CPU time 16.82 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 220712 kb
Host smart-4767cb80-1cbc-47a8-b04b-29384f0e3708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822182810 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2822182810
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1550628526
Short name T883
Test name
Test status
Simulation time 59193745 ps
CPU time 2.45 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 214320 kb
Host smart-5f67296c-16e5-4d3f-b3ac-78b473c59db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550628526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1550628526
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.553748412
Short name T819
Test name
Test status
Simulation time 156695673 ps
CPU time 1.87 seconds
Started Jun 22 06:05:51 PM PDT 24
Finished Jun 22 06:05:54 PM PDT 24
Peak memory 209940 kb
Host smart-e547196a-7c0e-42c9-aa9e-e6a1df1e8fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553748412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.553748412
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4229951413
Short name T485
Test name
Test status
Simulation time 41929811 ps
CPU time 0.84 seconds
Started Jun 22 06:05:57 PM PDT 24
Finished Jun 22 06:05:59 PM PDT 24
Peak memory 205888 kb
Host smart-16cb460c-b442-4e76-ac20-b65dcd3119e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229951413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4229951413
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3795853126
Short name T564
Test name
Test status
Simulation time 242367358 ps
CPU time 6.73 seconds
Started Jun 22 06:05:58 PM PDT 24
Finished Jun 22 06:06:05 PM PDT 24
Peak memory 210824 kb
Host smart-d3b45c14-7f00-47fb-a449-2cfbd48e5a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795853126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3795853126
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2009729259
Short name T54
Test name
Test status
Simulation time 255539820 ps
CPU time 6.7 seconds
Started Jun 22 06:05:58 PM PDT 24
Finished Jun 22 06:06:05 PM PDT 24
Peak memory 208776 kb
Host smart-9c3da5af-3757-4b78-9f48-b733f2f3d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009729259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2009729259
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3904656223
Short name T95
Test name
Test status
Simulation time 234443184 ps
CPU time 9.13 seconds
Started Jun 22 06:05:57 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 209668 kb
Host smart-e75fabf2-5522-4eaa-bdaf-853803e85803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904656223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3904656223
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3635547476
Short name T343
Test name
Test status
Simulation time 299170885 ps
CPU time 4.05 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 221396 kb
Host smart-344f38e6-257c-4684-aa59-89af55334643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635547476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3635547476
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3603598341
Short name T68
Test name
Test status
Simulation time 353975101 ps
CPU time 3.29 seconds
Started Jun 22 06:05:59 PM PDT 24
Finished Jun 22 06:06:03 PM PDT 24
Peak memory 218792 kb
Host smart-86335247-2732-4b69-b61a-29a1f9fa13ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603598341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3603598341
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1028262073
Short name T844
Test name
Test status
Simulation time 300996837 ps
CPU time 5.45 seconds
Started Jun 22 06:05:59 PM PDT 24
Finished Jun 22 06:06:05 PM PDT 24
Peak memory 214304 kb
Host smart-08674107-8c92-40d0-83b5-304fa042a79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028262073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1028262073
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2578854438
Short name T15
Test name
Test status
Simulation time 24287486 ps
CPU time 2.04 seconds
Started Jun 22 06:05:53 PM PDT 24
Finished Jun 22 06:05:56 PM PDT 24
Peak memory 208636 kb
Host smart-1badc6d2-f700-4b6f-a5be-c4e4d8fe8fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578854438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2578854438
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1305964248
Short name T599
Test name
Test status
Simulation time 184545034 ps
CPU time 2.9 seconds
Started Jun 22 06:05:58 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 207400 kb
Host smart-931b4225-86b7-4556-bfb4-6130cf7dfc76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305964248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1305964248
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3119323359
Short name T826
Test name
Test status
Simulation time 154804633 ps
CPU time 2.63 seconds
Started Jun 22 06:05:58 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 206940 kb
Host smart-428a1370-1ad3-4c26-9581-61a09f9e96a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119323359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3119323359
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2352754689
Short name T451
Test name
Test status
Simulation time 199588026 ps
CPU time 2.92 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 208676 kb
Host smart-16dde143-09ac-4db7-801e-89fa43257b29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352754689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2352754689
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2743215681
Short name T211
Test name
Test status
Simulation time 103183751 ps
CPU time 1.67 seconds
Started Jun 22 06:05:56 PM PDT 24
Finished Jun 22 06:05:59 PM PDT 24
Peak memory 209796 kb
Host smart-3b987903-cc1e-4e2c-8448-f390d87f9d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743215681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2743215681
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2300627556
Short name T443
Test name
Test status
Simulation time 234689740 ps
CPU time 4.19 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 206872 kb
Host smart-b034953a-8642-4aeb-aeae-952a5e1d0080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300627556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2300627556
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.385190041
Short name T337
Test name
Test status
Simulation time 21463419539 ps
CPU time 64.19 seconds
Started Jun 22 06:05:59 PM PDT 24
Finished Jun 22 06:07:04 PM PDT 24
Peak memory 215776 kb
Host smart-b0cde0a8-39c1-4e02-add0-54173c0f6cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385190041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.385190041
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3355767203
Short name T114
Test name
Test status
Simulation time 584915687 ps
CPU time 27.49 seconds
Started Jun 22 06:05:57 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 221652 kb
Host smart-e4278d94-3cc2-48a1-b3b5-00d4c084c6d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355767203 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3355767203
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.460197809
Short name T361
Test name
Test status
Simulation time 346614522 ps
CPU time 5.86 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 214304 kb
Host smart-ec052038-c88b-4e67-9021-9ad0c0b45e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460197809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.460197809
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2138633615
Short name T833
Test name
Test status
Simulation time 50974341 ps
CPU time 1.23 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:04 PM PDT 24
Peak memory 209812 kb
Host smart-0bd6259b-84a8-49db-ae36-896bb4470da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138633615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2138633615
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1129190408
Short name T415
Test name
Test status
Simulation time 12205781 ps
CPU time 0.77 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:02:57 PM PDT 24
Peak memory 205928 kb
Host smart-3a22e2d8-6886-431d-91be-25443588c955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129190408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1129190408
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2494918895
Short name T109
Test name
Test status
Simulation time 5104505713 ps
CPU time 137.8 seconds
Started Jun 22 06:03:01 PM PDT 24
Finished Jun 22 06:05:19 PM PDT 24
Peak memory 222560 kb
Host smart-98fe632f-a11f-4cb1-8aa2-8bcdda916801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494918895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2494918895
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3926163431
Short name T839
Test name
Test status
Simulation time 174909168 ps
CPU time 5.53 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:03:01 PM PDT 24
Peak memory 209292 kb
Host smart-5fe2fc16-4e06-4e30-a676-613fd70ec92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926163431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3926163431
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2804974464
Short name T827
Test name
Test status
Simulation time 880617338 ps
CPU time 3.59 seconds
Started Jun 22 06:02:58 PM PDT 24
Finished Jun 22 06:03:02 PM PDT 24
Peak memory 214244 kb
Host smart-4743b89b-d18e-4bf6-ac14-b2f0a4b893e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804974464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2804974464
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1669033627
Short name T703
Test name
Test status
Simulation time 38705671 ps
CPU time 1.78 seconds
Started Jun 22 06:02:58 PM PDT 24
Finished Jun 22 06:03:00 PM PDT 24
Peak memory 209520 kb
Host smart-6ed1daa6-aa7e-4a28-b4e4-56fb263371e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669033627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1669033627
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.293695191
Short name T59
Test name
Test status
Simulation time 291905365 ps
CPU time 7.78 seconds
Started Jun 22 06:02:58 PM PDT 24
Finished Jun 22 06:03:06 PM PDT 24
Peak memory 218360 kb
Host smart-a997f9b1-e298-4c3d-8b57-aa1ac68f5d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293695191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.293695191
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4130984978
Short name T205
Test name
Test status
Simulation time 205099607 ps
CPU time 6.72 seconds
Started Jun 22 06:03:06 PM PDT 24
Finished Jun 22 06:03:13 PM PDT 24
Peak memory 214308 kb
Host smart-26acab78-6092-4f4b-83b3-adf957e774d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130984978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4130984978
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1985000701
Short name T12
Test name
Test status
Simulation time 544945558 ps
CPU time 6.91 seconds
Started Jun 22 06:02:58 PM PDT 24
Finished Jun 22 06:03:05 PM PDT 24
Peak memory 229064 kb
Host smart-04c8d8cf-e030-4e87-ac92-8a84d2592ec2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985000701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1985000701
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.959407812
Short name T640
Test name
Test status
Simulation time 36072531 ps
CPU time 2.32 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:02:59 PM PDT 24
Peak memory 208976 kb
Host smart-93005642-b78f-4742-89d8-d1ce5582d756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959407812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.959407812
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3601764391
Short name T126
Test name
Test status
Simulation time 1087012795 ps
CPU time 6.06 seconds
Started Jun 22 06:02:57 PM PDT 24
Finished Jun 22 06:03:04 PM PDT 24
Peak memory 208804 kb
Host smart-5e1e916b-4aea-4d0e-a838-decb1760f833
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601764391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3601764391
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3802448742
Short name T498
Test name
Test status
Simulation time 719356381 ps
CPU time 5.74 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:03:02 PM PDT 24
Peak memory 208736 kb
Host smart-90a7a70b-9a15-4739-986c-14edeb74c3a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802448742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3802448742
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2600662814
Short name T360
Test name
Test status
Simulation time 3901775711 ps
CPU time 36.42 seconds
Started Jun 22 06:02:57 PM PDT 24
Finished Jun 22 06:03:34 PM PDT 24
Peak memory 208760 kb
Host smart-34e138f4-e909-46c3-8349-a14e2b79d369
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600662814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2600662814
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4222401746
Short name T719
Test name
Test status
Simulation time 123802478 ps
CPU time 3.27 seconds
Started Jun 22 06:02:57 PM PDT 24
Finished Jun 22 06:03:01 PM PDT 24
Peak memory 209128 kb
Host smart-5e9be6c8-00e0-45c4-a8fa-6c17dac5f770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222401746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4222401746
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3045042653
Short name T408
Test name
Test status
Simulation time 187422028 ps
CPU time 1.81 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:02:58 PM PDT 24
Peak memory 207092 kb
Host smart-4c2a1d7b-d83a-49f9-8783-d7ecbd5f399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045042653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3045042653
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2013877254
Short name T227
Test name
Test status
Simulation time 585665586 ps
CPU time 4.83 seconds
Started Jun 22 06:03:06 PM PDT 24
Finished Jun 22 06:03:11 PM PDT 24
Peak memory 210068 kb
Host smart-b34fc3e0-b907-42c1-8e27-9d42c764271f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013877254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2013877254
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1385737598
Short name T473
Test name
Test status
Simulation time 111903184 ps
CPU time 3.97 seconds
Started Jun 22 06:03:06 PM PDT 24
Finished Jun 22 06:03:10 PM PDT 24
Peak memory 218160 kb
Host smart-f3117e7b-9229-41fa-b084-0c121b9e3c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385737598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1385737598
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2623841912
Short name T366
Test name
Test status
Simulation time 318223389 ps
CPU time 1.95 seconds
Started Jun 22 06:02:58 PM PDT 24
Finished Jun 22 06:03:00 PM PDT 24
Peak memory 209828 kb
Host smart-c1c38d41-e6e5-42f5-9073-4cc3a69e3358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623841912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2623841912
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3930683972
Short name T775
Test name
Test status
Simulation time 11176086 ps
CPU time 0.86 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 205908 kb
Host smart-b89b03c8-97ba-4d57-930b-5f788a95dab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930683972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3930683972
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3000244442
Short name T293
Test name
Test status
Simulation time 63772212 ps
CPU time 4.37 seconds
Started Jun 22 06:05:59 PM PDT 24
Finished Jun 22 06:06:03 PM PDT 24
Peak memory 215784 kb
Host smart-71ef725f-b852-4993-a677-044cda7b14bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000244442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3000244442
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1253355111
Short name T458
Test name
Test status
Simulation time 93256040 ps
CPU time 3.46 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:04 PM PDT 24
Peak memory 214612 kb
Host smart-05c1f538-53af-4e2a-92b7-7809850dd88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253355111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1253355111
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1589227373
Short name T846
Test name
Test status
Simulation time 1148767975 ps
CPU time 7.01 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 208028 kb
Host smart-236e6b55-a417-4e16-9479-aea6112d53ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589227373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1589227373
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3218573068
Short name T841
Test name
Test status
Simulation time 312244529 ps
CPU time 5.14 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 219620 kb
Host smart-096c108c-2a6f-4544-af26-916ae90484cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218573068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3218573068
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3465329899
Short name T266
Test name
Test status
Simulation time 330564219 ps
CPU time 2.85 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 214348 kb
Host smart-a02699a5-c894-4eff-9255-4860a6cadf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465329899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3465329899
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3136489862
Short name T842
Test name
Test status
Simulation time 48418725 ps
CPU time 3.12 seconds
Started Jun 22 06:05:57 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 214336 kb
Host smart-4fc98b55-430d-4ad4-90d1-daf910d20f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136489862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3136489862
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1714423586
Short name T740
Test name
Test status
Simulation time 102781950 ps
CPU time 4.87 seconds
Started Jun 22 06:06:01 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 208220 kb
Host smart-5128e197-6d1c-4bcc-a37c-8cc661360bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714423586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1714423586
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2139694905
Short name T99
Test name
Test status
Simulation time 22357482 ps
CPU time 1.97 seconds
Started Jun 22 06:06:01 PM PDT 24
Finished Jun 22 06:06:04 PM PDT 24
Peak memory 207056 kb
Host smart-23c09bac-5038-4f46-b96d-c4a58add3431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139694905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2139694905
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3823875614
Short name T909
Test name
Test status
Simulation time 265970234 ps
CPU time 7.2 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 208820 kb
Host smart-a2199352-d227-4f65-99ba-5c174fa8d0ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823875614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3823875614
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3643323002
Short name T589
Test name
Test status
Simulation time 81853317 ps
CPU time 1.95 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:03 PM PDT 24
Peak memory 208740 kb
Host smart-61527150-2aa7-4a59-8601-ce756edcbc4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643323002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3643323002
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1741169897
Short name T122
Test name
Test status
Simulation time 4324388780 ps
CPU time 26.43 seconds
Started Jun 22 06:06:01 PM PDT 24
Finished Jun 22 06:06:28 PM PDT 24
Peak memory 208756 kb
Host smart-5448aca7-d6b1-480f-89aa-482879235552
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741169897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1741169897
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2191008871
Short name T519
Test name
Test status
Simulation time 241133017 ps
CPU time 2.1 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:03 PM PDT 24
Peak memory 208192 kb
Host smart-dc7c451f-efa2-4eca-8633-ddc07d106d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191008871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2191008871
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2040881169
Short name T383
Test name
Test status
Simulation time 54626929 ps
CPU time 2.72 seconds
Started Jun 22 06:05:57 PM PDT 24
Finished Jun 22 06:06:01 PM PDT 24
Peak memory 206804 kb
Host smart-96e20e0f-bfa7-4034-a5c5-a9e0f95eca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040881169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2040881169
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1070051542
Short name T201
Test name
Test status
Simulation time 99836416 ps
CPU time 0.8 seconds
Started Jun 22 06:05:59 PM PDT 24
Finished Jun 22 06:06:00 PM PDT 24
Peak memory 205940 kb
Host smart-ad8257f3-7d5b-40ad-b7a1-c2990140e7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070051542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1070051542
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4272419561
Short name T423
Test name
Test status
Simulation time 100337781 ps
CPU time 5.06 seconds
Started Jun 22 06:06:04 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 214296 kb
Host smart-750c0672-5c57-42c4-9724-5e2cda572310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272419561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4272419561
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4015034411
Short name T752
Test name
Test status
Simulation time 117504477 ps
CPU time 2.51 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 209828 kb
Host smart-00b2aaad-582e-4e09-b7cc-228ab7ae0d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015034411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4015034411
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.4068280222
Short name T793
Test name
Test status
Simulation time 48832429 ps
CPU time 0.84 seconds
Started Jun 22 06:06:07 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 205920 kb
Host smart-676fd8da-1f8d-4c9d-bafb-68f8e5df7d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068280222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.4068280222
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3249513851
Short name T254
Test name
Test status
Simulation time 51424279 ps
CPU time 2.42 seconds
Started Jun 22 06:06:02 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 214320 kb
Host smart-daa0d9e0-a0b8-49d5-a97e-d58806e5c6c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249513851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3249513851
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3216021087
Short name T470
Test name
Test status
Simulation time 317555526 ps
CPU time 4.7 seconds
Started Jun 22 06:05:58 PM PDT 24
Finished Jun 22 06:06:03 PM PDT 24
Peak memory 207060 kb
Host smart-51c40cb9-f0b4-4ab6-be5b-f73cc5a0e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216021087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3216021087
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3889827893
Short name T86
Test name
Test status
Simulation time 312297836 ps
CPU time 3.94 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 214296 kb
Host smart-177288e3-b49f-48cc-aa26-f0c5ee3245cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889827893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3889827893
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.636011536
Short name T133
Test name
Test status
Simulation time 103918930 ps
CPU time 2.1 seconds
Started Jun 22 06:06:01 PM PDT 24
Finished Jun 22 06:06:04 PM PDT 24
Peak memory 206180 kb
Host smart-a15fed0c-46d2-4cd0-aa34-f08ed4ba581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636011536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.636011536
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3130559951
Short name T302
Test name
Test status
Simulation time 222444296 ps
CPU time 5.12 seconds
Started Jun 22 06:05:59 PM PDT 24
Finished Jun 22 06:06:04 PM PDT 24
Peak memory 207296 kb
Host smart-eb0667e9-9501-4856-b16d-dacfab8fc0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130559951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3130559951
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1179749502
Short name T869
Test name
Test status
Simulation time 175995842 ps
CPU time 4.89 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 208164 kb
Host smart-68932123-7f79-4da9-90c5-754c925afd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179749502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1179749502
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3137221759
Short name T692
Test name
Test status
Simulation time 833931489 ps
CPU time 2.89 seconds
Started Jun 22 06:06:06 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 206948 kb
Host smart-ed1db794-fc68-4401-bb24-d810f09c0fdd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137221759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3137221759
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3603126159
Short name T906
Test name
Test status
Simulation time 477581426 ps
CPU time 6.13 seconds
Started Jun 22 06:06:00 PM PDT 24
Finished Jun 22 06:06:07 PM PDT 24
Peak memory 207916 kb
Host smart-90aea5c3-b94b-46ac-9e8f-f839936cd2f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603126159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3603126159
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2778661354
Short name T688
Test name
Test status
Simulation time 88820545 ps
CPU time 3.41 seconds
Started Jun 22 06:06:01 PM PDT 24
Finished Jun 22 06:06:05 PM PDT 24
Peak memory 206908 kb
Host smart-b418d3d1-e5b8-4946-ab95-2491eedda5c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778661354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2778661354
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2462445367
Short name T299
Test name
Test status
Simulation time 150347109 ps
CPU time 4.74 seconds
Started Jun 22 06:06:08 PM PDT 24
Finished Jun 22 06:06:13 PM PDT 24
Peak memory 218228 kb
Host smart-99b503ef-7aaf-40d5-8809-1aaa8709151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462445367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2462445367
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1054718032
Short name T196
Test name
Test status
Simulation time 129470968 ps
CPU time 4.48 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 207940 kb
Host smart-8e560fdd-71cc-454c-a8dd-5f1086d97921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054718032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1054718032
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2263970339
Short name T860
Test name
Test status
Simulation time 6550651056 ps
CPU time 63.69 seconds
Started Jun 22 06:06:04 PM PDT 24
Finished Jun 22 06:07:09 PM PDT 24
Peak memory 215196 kb
Host smart-cef0db3c-bd11-4896-b7b6-9e758ad84c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263970339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2263970339
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3679487139
Short name T738
Test name
Test status
Simulation time 111291032 ps
CPU time 2.31 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:13 PM PDT 24
Peak memory 208716 kb
Host smart-fd1ca73a-9277-496b-90b7-6b35d5b7af98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679487139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3679487139
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.21255105
Short name T60
Test name
Test status
Simulation time 2019284369 ps
CPU time 8.95 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 210920 kb
Host smart-26096809-79b4-4fc7-9e3d-67be3397c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21255105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.21255105
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3277873819
Short name T518
Test name
Test status
Simulation time 51843298 ps
CPU time 0.8 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:06 PM PDT 24
Peak memory 205888 kb
Host smart-ecfc2295-6408-4fa5-a63e-49578fdf7352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277873819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3277873819
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2333786992
Short name T101
Test name
Test status
Simulation time 44873259 ps
CPU time 3.35 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:07 PM PDT 24
Peak memory 214260 kb
Host smart-e80c96b9-345c-4e58-9c98-f0bfc7ce39f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2333786992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2333786992
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.960716494
Short name T851
Test name
Test status
Simulation time 153332740 ps
CPU time 3.29 seconds
Started Jun 22 06:06:04 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 209552 kb
Host smart-38080b91-1131-472f-9e64-aa65bcb92fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960716494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.960716494
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.125719865
Short name T873
Test name
Test status
Simulation time 2744132145 ps
CPU time 34.48 seconds
Started Jun 22 06:06:07 PM PDT 24
Finished Jun 22 06:06:42 PM PDT 24
Peak memory 214424 kb
Host smart-d94dd0db-f84e-4055-b2a5-01d669fe1710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125719865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.125719865
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.879778957
Short name T338
Test name
Test status
Simulation time 86775474 ps
CPU time 3.2 seconds
Started Jun 22 06:06:06 PM PDT 24
Finished Jun 22 06:06:10 PM PDT 24
Peak memory 222404 kb
Host smart-384f8539-e83b-45f3-a298-96df3fa10b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879778957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.879778957
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1127927046
Short name T595
Test name
Test status
Simulation time 57657165 ps
CPU time 2.1 seconds
Started Jun 22 06:06:07 PM PDT 24
Finished Jun 22 06:06:10 PM PDT 24
Peak memory 222456 kb
Host smart-a37eb089-addd-45b6-85b0-aa3cac09a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127927046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1127927046
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2744001392
Short name T121
Test name
Test status
Simulation time 1157005006 ps
CPU time 32.15 seconds
Started Jun 22 06:06:06 PM PDT 24
Finished Jun 22 06:06:39 PM PDT 24
Peak memory 214304 kb
Host smart-24e2cdac-d062-4859-9f51-60547c415da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744001392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2744001392
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1123745519
Short name T409
Test name
Test status
Simulation time 503179316 ps
CPU time 5.36 seconds
Started Jun 22 06:06:03 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 206844 kb
Host smart-6ca697f8-73da-4112-9982-ef353eceddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123745519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1123745519
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1912472240
Short name T346
Test name
Test status
Simulation time 700851273 ps
CPU time 5.41 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 208696 kb
Host smart-468846bf-e488-4795-907f-56d5478a2954
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912472240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1912472240
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.457044042
Short name T843
Test name
Test status
Simulation time 7079969936 ps
CPU time 35.53 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:45 PM PDT 24
Peak memory 208928 kb
Host smart-61ed214f-5270-48b5-ad09-272d4900f198
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457044042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.457044042
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1655099335
Short name T620
Test name
Test status
Simulation time 108496852 ps
CPU time 3.48 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:14 PM PDT 24
Peak memory 207568 kb
Host smart-fbb36f59-e5b3-41b3-be9c-3699cfe42870
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655099335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1655099335
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3549438701
Short name T486
Test name
Test status
Simulation time 71747915 ps
CPU time 3.13 seconds
Started Jun 22 06:06:07 PM PDT 24
Finished Jun 22 06:06:10 PM PDT 24
Peak memory 209000 kb
Host smart-c34e406e-2194-4c1a-96da-e2fd38777ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549438701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3549438701
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1945646186
Short name T816
Test name
Test status
Simulation time 94941927 ps
CPU time 3.4 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 208516 kb
Host smart-1eac34e3-34d7-470b-8924-cd45d8f88161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945646186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1945646186
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1072198473
Short name T277
Test name
Test status
Simulation time 7280875407 ps
CPU time 45.39 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:51 PM PDT 24
Peak memory 216808 kb
Host smart-39a56af9-b06f-4c5e-b2d5-b18c9543f01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072198473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1072198473
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3035455152
Short name T195
Test name
Test status
Simulation time 99315040 ps
CPU time 3.82 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 214308 kb
Host smart-432f4f10-539e-4bb6-b503-74fab435e21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035455152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3035455152
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.791403020
Short name T368
Test name
Test status
Simulation time 110099589 ps
CPU time 2.17 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:08 PM PDT 24
Peak memory 209980 kb
Host smart-77f2f6f9-42e6-4a9c-bf48-6059e7e36c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791403020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.791403020
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2266416201
Short name T223
Test name
Test status
Simulation time 423666459 ps
CPU time 2.76 seconds
Started Jun 22 06:06:14 PM PDT 24
Finished Jun 22 06:06:18 PM PDT 24
Peak memory 216852 kb
Host smart-4f86848f-5505-47f0-8f16-af64d6829c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266416201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2266416201
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.12877811
Short name T801
Test name
Test status
Simulation time 121354772 ps
CPU time 3.41 seconds
Started Jun 22 06:06:08 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 218416 kb
Host smart-16aa20cf-1125-4856-9be1-5f545d0dff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12877811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.12877811
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1281094592
Short name T253
Test name
Test status
Simulation time 95731212 ps
CPU time 2.15 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:13 PM PDT 24
Peak memory 214296 kb
Host smart-3e1cb84a-f0fa-40a4-97c4-fc968018e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281094592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1281094592
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1811152191
Short name T36
Test name
Test status
Simulation time 248073608 ps
CPU time 5.09 seconds
Started Jun 22 06:06:12 PM PDT 24
Finished Jun 22 06:06:17 PM PDT 24
Peak memory 221604 kb
Host smart-da91955f-e506-4bcb-bbf5-554feb1736e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811152191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1811152191
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1982660607
Short name T152
Test name
Test status
Simulation time 34150473 ps
CPU time 2.2 seconds
Started Jun 22 06:06:08 PM PDT 24
Finished Jun 22 06:06:11 PM PDT 24
Peak memory 220704 kb
Host smart-f1583882-b70d-4b05-809f-6b1a00c4adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982660607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1982660607
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1325493249
Short name T866
Test name
Test status
Simulation time 1500484412 ps
CPU time 11.19 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:21 PM PDT 24
Peak memory 208384 kb
Host smart-ca189010-20df-49ff-b412-bdc5ac96fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325493249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1325493249
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.978695309
Short name T124
Test name
Test status
Simulation time 75042870 ps
CPU time 3.86 seconds
Started Jun 22 06:06:07 PM PDT 24
Finished Jun 22 06:06:11 PM PDT 24
Peak memory 208340 kb
Host smart-38ca30c9-eaa2-48c6-8130-c987d8fdee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978695309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.978695309
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3985430910
Short name T769
Test name
Test status
Simulation time 399408893 ps
CPU time 4.94 seconds
Started Jun 22 06:06:04 PM PDT 24
Finished Jun 22 06:06:10 PM PDT 24
Peak memory 206936 kb
Host smart-debef457-f103-410e-bccc-18a1e2fb5dc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985430910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3985430910
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2494676661
Short name T484
Test name
Test status
Simulation time 285920091 ps
CPU time 4.54 seconds
Started Jun 22 06:06:04 PM PDT 24
Finished Jun 22 06:06:10 PM PDT 24
Peak memory 208684 kb
Host smart-4567e7f7-d0b4-4f42-997e-1cda4cb6ed5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494676661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2494676661
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3380172922
Short name T597
Test name
Test status
Simulation time 115436806 ps
CPU time 4.54 seconds
Started Jun 22 06:06:06 PM PDT 24
Finished Jun 22 06:06:11 PM PDT 24
Peak memory 207004 kb
Host smart-9246fc26-8c6b-4608-82a2-3fa757f539e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380172922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3380172922
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2709538682
Short name T480
Test name
Test status
Simulation time 178388385 ps
CPU time 2.19 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 215384 kb
Host smart-2bdf14f6-4cbd-48af-b836-7bde09bfbea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709538682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2709538682
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3437980227
Short name T459
Test name
Test status
Simulation time 229617212 ps
CPU time 3.05 seconds
Started Jun 22 06:06:05 PM PDT 24
Finished Jun 22 06:06:09 PM PDT 24
Peak memory 208364 kb
Host smart-dc682966-5dc5-478c-a36f-a3de5a301a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437980227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3437980227
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1232131215
Short name T256
Test name
Test status
Simulation time 790610735 ps
CPU time 7.6 seconds
Started Jun 22 06:06:08 PM PDT 24
Finished Jun 22 06:06:16 PM PDT 24
Peak memory 210604 kb
Host smart-058142b8-471a-4e8f-bf42-79c091bc3aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232131215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1232131215
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1678959120
Short name T354
Test name
Test status
Simulation time 177708994 ps
CPU time 11.24 seconds
Started Jun 22 06:06:16 PM PDT 24
Finished Jun 22 06:06:27 PM PDT 24
Peak memory 222896 kb
Host smart-e072651a-fda9-4782-8d35-49ccbfdd9339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678959120 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1678959120
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.557711435
Short name T616
Test name
Test status
Simulation time 35661459 ps
CPU time 2.68 seconds
Started Jun 22 06:06:12 PM PDT 24
Finished Jun 22 06:06:16 PM PDT 24
Peak memory 207548 kb
Host smart-6234ddd7-6d0a-4de3-9145-6b385cb6833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557711435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.557711435
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1479086985
Short name T728
Test name
Test status
Simulation time 150397597 ps
CPU time 1.98 seconds
Started Jun 22 06:06:12 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 210072 kb
Host smart-b491a877-fbd7-45dd-9c4d-91c05c475be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479086985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1479086985
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2777183805
Short name T664
Test name
Test status
Simulation time 58724100 ps
CPU time 0.75 seconds
Started Jun 22 06:06:15 PM PDT 24
Finished Jun 22 06:06:16 PM PDT 24
Peak memory 205924 kb
Host smart-3733a67b-b541-4ca0-bdac-102f894d1860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777183805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2777183805
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1938426856
Short name T399
Test name
Test status
Simulation time 1040996526 ps
CPU time 52.47 seconds
Started Jun 22 06:06:13 PM PDT 24
Finished Jun 22 06:07:06 PM PDT 24
Peak memory 214360 kb
Host smart-e341ba47-a0e6-4b22-9578-88755d89044d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938426856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1938426856
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4011029458
Short name T30
Test name
Test status
Simulation time 68945123 ps
CPU time 1.62 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:13 PM PDT 24
Peak memory 214308 kb
Host smart-a23e0d29-a591-484e-954f-4a6b0a4c678f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011029458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4011029458
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2739548993
Short name T892
Test name
Test status
Simulation time 38080456 ps
CPU time 1.9 seconds
Started Jun 22 06:06:13 PM PDT 24
Finished Jun 22 06:06:16 PM PDT 24
Peak memory 208236 kb
Host smart-a3f837bc-a3d3-46d7-aef9-29489676c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739548993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2739548993
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.353632117
Short name T852
Test name
Test status
Simulation time 359998281 ps
CPU time 2.98 seconds
Started Jun 22 06:06:12 PM PDT 24
Finished Jun 22 06:06:16 PM PDT 24
Peak memory 214488 kb
Host smart-3026c38b-5a5e-45d1-bbad-f462d79b601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353632117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.353632117
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.657035101
Short name T882
Test name
Test status
Simulation time 81616025 ps
CPU time 2.77 seconds
Started Jun 22 06:06:12 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 213832 kb
Host smart-78c86dac-a144-42d2-ba9a-673e7258e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657035101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.657035101
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.2324190775
Short name T762
Test name
Test status
Simulation time 1183669542 ps
CPU time 3.89 seconds
Started Jun 22 06:06:12 PM PDT 24
Finished Jun 22 06:06:17 PM PDT 24
Peak memory 208836 kb
Host smart-74ce1ced-f28d-4e15-ad1e-c778ba1aa6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324190775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2324190775
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2420922298
Short name T545
Test name
Test status
Simulation time 142128150 ps
CPU time 2.74 seconds
Started Jun 22 06:06:11 PM PDT 24
Finished Jun 22 06:06:14 PM PDT 24
Peak memory 207108 kb
Host smart-252113e8-e406-4087-9759-8a8b6de6adbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420922298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2420922298
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1649877312
Short name T505
Test name
Test status
Simulation time 82187562 ps
CPU time 3.94 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 208928 kb
Host smart-8a471002-b412-4e5d-8883-d10ef71e14da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649877312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1649877312
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4199092187
Short name T387
Test name
Test status
Simulation time 234907817 ps
CPU time 5.49 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:16 PM PDT 24
Peak memory 207020 kb
Host smart-6f79878b-a13f-4479-ac79-f32487a493ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199092187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4199092187
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.186785958
Short name T193
Test name
Test status
Simulation time 1524825662 ps
CPU time 19.87 seconds
Started Jun 22 06:06:13 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 208816 kb
Host smart-d3458817-db4a-451f-b0cc-6d760fe093e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186785958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.186785958
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1069335987
Short name T711
Test name
Test status
Simulation time 95320278 ps
CPU time 1.98 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:13 PM PDT 24
Peak memory 207320 kb
Host smart-e8e2e315-8742-4c35-b8e2-025cfbf4cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069335987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1069335987
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3516570915
Short name T607
Test name
Test status
Simulation time 209021692 ps
CPU time 2.44 seconds
Started Jun 22 06:06:09 PM PDT 24
Finished Jun 22 06:06:12 PM PDT 24
Peak memory 208436 kb
Host smart-52497d0d-ba7b-4b28-b278-9eb6758e7e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516570915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3516570915
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.33905148
Short name T665
Test name
Test status
Simulation time 402584139 ps
CPU time 12.12 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:23 PM PDT 24
Peak memory 222488 kb
Host smart-73d66a52-4dd8-4c46-87ab-fe2f7b1141ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.33905148
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.777591242
Short name T628
Test name
Test status
Simulation time 226534039 ps
CPU time 8.89 seconds
Started Jun 22 06:06:11 PM PDT 24
Finished Jun 22 06:06:21 PM PDT 24
Peak memory 222516 kb
Host smart-594bd128-4ecd-4b89-b9d4-bdbc6d95a8e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777591242 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.777591242
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2902610873
Short name T511
Test name
Test status
Simulation time 91994275 ps
CPU time 4.42 seconds
Started Jun 22 06:06:15 PM PDT 24
Finished Jun 22 06:06:20 PM PDT 24
Peak memory 209588 kb
Host smart-955d858e-1f64-4df8-8acc-e5431af8fc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902610873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2902610873
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1844664243
Short name T183
Test name
Test status
Simulation time 49956188 ps
CPU time 3.03 seconds
Started Jun 22 06:06:10 PM PDT 24
Finished Jun 22 06:06:14 PM PDT 24
Peak memory 210380 kb
Host smart-e7e6c1c7-dde3-42ee-9efb-4f133173cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844664243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1844664243
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3049342589
Short name T531
Test name
Test status
Simulation time 42603342 ps
CPU time 0.76 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:24 PM PDT 24
Peak memory 205932 kb
Host smart-d3e5d06b-5367-4594-82c3-5389c98239ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049342589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3049342589
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1132397442
Short name T797
Test name
Test status
Simulation time 132014516 ps
CPU time 3.26 seconds
Started Jun 22 06:06:17 PM PDT 24
Finished Jun 22 06:06:21 PM PDT 24
Peak memory 214604 kb
Host smart-07b81488-9938-4fbb-bf95-d8807f2f02fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132397442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1132397442
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2657627695
Short name T483
Test name
Test status
Simulation time 43628438 ps
CPU time 1.64 seconds
Started Jun 22 06:06:17 PM PDT 24
Finished Jun 22 06:06:19 PM PDT 24
Peak memory 207260 kb
Host smart-c7a6bbd5-515c-40ff-bc14-9a0e2ce95813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657627695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2657627695
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3053616798
Short name T813
Test name
Test status
Simulation time 259220877 ps
CPU time 3.07 seconds
Started Jun 22 06:06:18 PM PDT 24
Finished Jun 22 06:06:22 PM PDT 24
Peak memory 214304 kb
Host smart-3f69c524-1c1f-4db4-84f1-4078320a55da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053616798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3053616798
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1359071505
Short name T340
Test name
Test status
Simulation time 971354409 ps
CPU time 5.35 seconds
Started Jun 22 06:06:19 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 222428 kb
Host smart-454ecb18-2c20-4a6c-a3d3-378c6d582360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359071505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1359071505
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.692682875
Short name T687
Test name
Test status
Simulation time 343525737 ps
CPU time 3.46 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:28 PM PDT 24
Peak memory 209444 kb
Host smart-2ee1d566-6256-4359-aed0-5d01f67033be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692682875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.692682875
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.108939007
Short name T521
Test name
Test status
Simulation time 93629566 ps
CPU time 4.67 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:31 PM PDT 24
Peak memory 209700 kb
Host smart-43bff5d6-d97d-489f-8226-daca091e18a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108939007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.108939007
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1323106498
Short name T770
Test name
Test status
Simulation time 241174907 ps
CPU time 3.86 seconds
Started Jun 22 06:06:15 PM PDT 24
Finished Jun 22 06:06:19 PM PDT 24
Peak memory 206836 kb
Host smart-699446fb-0ed3-4b25-903a-5955978a7136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323106498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1323106498
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3768775297
Short name T318
Test name
Test status
Simulation time 894074084 ps
CPU time 8.06 seconds
Started Jun 22 06:06:14 PM PDT 24
Finished Jun 22 06:06:23 PM PDT 24
Peak memory 208756 kb
Host smart-5914240d-5e61-4ee1-8ab1-0cd937822067
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768775297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3768775297
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1329836287
Short name T615
Test name
Test status
Simulation time 96722088 ps
CPU time 4.25 seconds
Started Jun 22 06:06:11 PM PDT 24
Finished Jun 22 06:06:15 PM PDT 24
Peak memory 207008 kb
Host smart-fce448bc-8140-4bfe-bb40-fa0c7a90d85d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329836287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1329836287
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.706759085
Short name T555
Test name
Test status
Simulation time 38117232 ps
CPU time 2.44 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:28 PM PDT 24
Peak memory 207380 kb
Host smart-891ad946-ab23-432f-9232-b97b2c719ff4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706759085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.706759085
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.523722604
Short name T402
Test name
Test status
Simulation time 215256886 ps
CPU time 3.27 seconds
Started Jun 22 06:06:20 PM PDT 24
Finished Jun 22 06:06:24 PM PDT 24
Peak memory 214308 kb
Host smart-7f65c351-3693-4b52-85ca-b7ff4696b50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523722604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.523722604
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1942078860
Short name T683
Test name
Test status
Simulation time 97636692 ps
CPU time 2.57 seconds
Started Jun 22 06:06:14 PM PDT 24
Finished Jun 22 06:06:17 PM PDT 24
Peak memory 206832 kb
Host smart-5fdb609c-e2da-4804-996e-626a82816669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942078860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1942078860
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1381560793
Short name T336
Test name
Test status
Simulation time 1605704430 ps
CPU time 16.49 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:40 PM PDT 24
Peak memory 208964 kb
Host smart-7ea48e2d-fb00-46cb-9024-0571432d13a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381560793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1381560793
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1077462055
Short name T67
Test name
Test status
Simulation time 636854321 ps
CPU time 3.46 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:29 PM PDT 24
Peak memory 210048 kb
Host smart-e1703f3c-5d41-4f3c-8e88-682b0cf4c632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077462055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1077462055
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3703141376
Short name T414
Test name
Test status
Simulation time 9369588 ps
CPU time 0.89 seconds
Started Jun 22 06:06:20 PM PDT 24
Finished Jun 22 06:06:22 PM PDT 24
Peak memory 205924 kb
Host smart-cf1048e9-e59d-4c75-a5e8-420a9230448c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703141376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3703141376
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4209609497
Short name T405
Test name
Test status
Simulation time 282480642 ps
CPU time 6.79 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 214696 kb
Host smart-e3f20850-4969-47c6-9d4f-9ca50aa161ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209609497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4209609497
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2481706391
Short name T452
Test name
Test status
Simulation time 296029061 ps
CPU time 1.8 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:26 PM PDT 24
Peak memory 207336 kb
Host smart-f33962cb-ad56-4a7a-a025-59f88a3d0431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481706391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2481706391
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1474732432
Short name T280
Test name
Test status
Simulation time 108961452 ps
CPU time 3.41 seconds
Started Jun 22 06:06:20 PM PDT 24
Finished Jun 22 06:06:24 PM PDT 24
Peak memory 214332 kb
Host smart-9a3c7c4f-6f8a-4f73-b149-62e2d4733814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474732432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1474732432
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2233035543
Short name T342
Test name
Test status
Simulation time 202385071 ps
CPU time 2.35 seconds
Started Jun 22 06:06:22 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 214252 kb
Host smart-4eab917c-ba05-41ee-b3fc-6719f1c0ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233035543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2233035543
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_random.937519484
Short name T532
Test name
Test status
Simulation time 129072582 ps
CPU time 5.06 seconds
Started Jun 22 06:06:20 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 214300 kb
Host smart-93c5525b-016c-4584-bc2b-0bc6beebf7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937519484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.937519484
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1104620110
Short name T567
Test name
Test status
Simulation time 215999746 ps
CPU time 6.06 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 208676 kb
Host smart-50c9878e-e99d-4298-95f7-86b13d04ab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104620110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1104620110
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3560856856
Short name T571
Test name
Test status
Simulation time 470111004 ps
CPU time 5.68 seconds
Started Jun 22 06:06:19 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 207196 kb
Host smart-cef59f5d-9423-4cd7-8906-fdbafcfc21ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560856856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3560856856
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1655933106
Short name T739
Test name
Test status
Simulation time 652372498 ps
CPU time 20.33 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:47 PM PDT 24
Peak memory 207960 kb
Host smart-7f8faf58-6fae-43a7-94d5-c354cfe3030b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655933106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1655933106
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2964646925
Short name T854
Test name
Test status
Simulation time 97136293 ps
CPU time 3.42 seconds
Started Jun 22 06:06:21 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 208364 kb
Host smart-a8dbf0d8-ce10-43c5-aa25-6c3796564057
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964646925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2964646925
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.585562346
Short name T215
Test name
Test status
Simulation time 101664153 ps
CPU time 2.09 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:29 PM PDT 24
Peak memory 214284 kb
Host smart-5b0aad58-fb4d-411a-a1d6-a73e2f1e1606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585562346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.585562346
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2025053892
Short name T417
Test name
Test status
Simulation time 182900231 ps
CPU time 3.84 seconds
Started Jun 22 06:06:24 PM PDT 24
Finished Jun 22 06:06:28 PM PDT 24
Peak memory 208804 kb
Host smart-139f1a6b-9bee-4b31-a37f-7687ce82ee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025053892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2025053892
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3286814211
Short name T200
Test name
Test status
Simulation time 6075529411 ps
CPU time 57.47 seconds
Started Jun 22 06:06:22 PM PDT 24
Finished Jun 22 06:07:20 PM PDT 24
Peak memory 222540 kb
Host smart-0c7b786c-33c4-4f1e-8255-b91f44bf38e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286814211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3286814211
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1563540746
Short name T64
Test name
Test status
Simulation time 359916829 ps
CPU time 15.14 seconds
Started Jun 22 06:06:17 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 222540 kb
Host smart-f9c925b3-3afe-4853-930e-4dde9efcbb6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563540746 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1563540746
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4041664340
Short name T461
Test name
Test status
Simulation time 58952850 ps
CPU time 3.78 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:30 PM PDT 24
Peak memory 207984 kb
Host smart-70de1e7f-d5bd-44d2-b483-880f95890a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041664340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4041664340
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1035646254
Short name T536
Test name
Test status
Simulation time 15822025 ps
CPU time 0.8 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:27 PM PDT 24
Peak memory 205928 kb
Host smart-754d98c7-e168-453d-8ea3-ca5cfb7bb22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035646254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1035646254
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1855643983
Short name T27
Test name
Test status
Simulation time 77370607 ps
CPU time 4.97 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 210136 kb
Host smart-59da3f00-7539-4fee-a7fb-b018757a9eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855643983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1855643983
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.702459096
Short name T381
Test name
Test status
Simulation time 359379822 ps
CPU time 3.72 seconds
Started Jun 22 06:06:27 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 218280 kb
Host smart-17a9c2c8-e16b-4007-be2a-466a80a45662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702459096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.702459096
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1215046028
Short name T525
Test name
Test status
Simulation time 327877469 ps
CPU time 3.91 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:28 PM PDT 24
Peak memory 209764 kb
Host smart-99485e03-459d-48c0-a4c7-5f865ef5bcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215046028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1215046028
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2163686579
Short name T51
Test name
Test status
Simulation time 2065509312 ps
CPU time 3.77 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:27 PM PDT 24
Peak memory 214252 kb
Host smart-e83ecb26-46a1-47c9-b11a-062e5cd2ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163686579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2163686579
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.638411720
Short name T300
Test name
Test status
Simulation time 233976695 ps
CPU time 3.34 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:31 PM PDT 24
Peak memory 214316 kb
Host smart-62023cd0-1d00-44bf-bd49-a34c756271bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638411720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.638411720
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1348849967
Short name T240
Test name
Test status
Simulation time 2087052820 ps
CPU time 54.71 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:07:21 PM PDT 24
Peak memory 207924 kb
Host smart-7272266a-bfa5-484d-8775-5337671476f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348849967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1348849967
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.958180594
Short name T666
Test name
Test status
Simulation time 204953201 ps
CPU time 3.1 seconds
Started Jun 22 06:06:21 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 206856 kb
Host smart-b625d7f3-1d22-484b-b5af-b6a055f72397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958180594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.958180594
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3374723653
Short name T514
Test name
Test status
Simulation time 30004202 ps
CPU time 2.12 seconds
Started Jun 22 06:06:22 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 208500 kb
Host smart-e5e4a269-c37c-4bbd-b979-c6935fd73664
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374723653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3374723653
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1829142370
Short name T455
Test name
Test status
Simulation time 3821233542 ps
CPU time 39.55 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:07:05 PM PDT 24
Peak memory 208476 kb
Host smart-217c103e-4801-46f5-946a-4592d41e40f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829142370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1829142370
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3213386708
Short name T776
Test name
Test status
Simulation time 157559916 ps
CPU time 6.18 seconds
Started Jun 22 06:06:22 PM PDT 24
Finished Jun 22 06:06:29 PM PDT 24
Peak memory 208680 kb
Host smart-552897c1-af8e-4899-be71-b78c208f35cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213386708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3213386708
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3009372496
Short name T667
Test name
Test status
Simulation time 114245966 ps
CPU time 2.37 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:29 PM PDT 24
Peak memory 208936 kb
Host smart-48622991-b373-48b4-b07d-ebbe0470bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009372496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3009372496
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.224182722
Short name T438
Test name
Test status
Simulation time 1326979463 ps
CPU time 3.83 seconds
Started Jun 22 06:06:17 PM PDT 24
Finished Jun 22 06:06:21 PM PDT 24
Peak memory 208572 kb
Host smart-2bb80669-82ec-45da-8835-00da921ba0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224182722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.224182722
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3557460344
Short name T291
Test name
Test status
Simulation time 1252076880 ps
CPU time 38.08 seconds
Started Jun 22 06:06:27 PM PDT 24
Finished Jun 22 06:07:06 PM PDT 24
Peak memory 222468 kb
Host smart-a0fc83af-2c5d-4b00-b496-6036534f21d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557460344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3557460344
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2157876718
Short name T787
Test name
Test status
Simulation time 112569396 ps
CPU time 7.7 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 219956 kb
Host smart-be8aa42a-0ecc-4a4d-b13d-8a48a6fb40f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157876718 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2157876718
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4115963833
Short name T552
Test name
Test status
Simulation time 73633629 ps
CPU time 4.08 seconds
Started Jun 22 06:06:27 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 214304 kb
Host smart-98afccae-730d-4e77-95f7-2ba8b83d9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115963833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4115963833
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1052645226
Short name T197
Test name
Test status
Simulation time 65184425 ps
CPU time 1.75 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 209908 kb
Host smart-bfcc95ac-eebb-499a-9cdc-fb685aebbaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052645226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1052645226
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.967908427
Short name T910
Test name
Test status
Simulation time 21022361 ps
CPU time 0.78 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:25 PM PDT 24
Peak memory 205928 kb
Host smart-af76db1f-e9ef-4038-b8c0-a31f483bc528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967908427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.967908427
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3571924828
Short name T732
Test name
Test status
Simulation time 198936363 ps
CPU time 2.14 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:30 PM PDT 24
Peak memory 206844 kb
Host smart-1de39e24-468a-4742-996b-5cb7b5243021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571924828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3571924828
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.620101550
Short name T289
Test name
Test status
Simulation time 65324242 ps
CPU time 3.25 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:31 PM PDT 24
Peak memory 221448 kb
Host smart-587f8181-10df-4875-ada3-e80953b9ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620101550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.620101550
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1097260915
Short name T755
Test name
Test status
Simulation time 219155206 ps
CPU time 3.63 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:30 PM PDT 24
Peak memory 214248 kb
Host smart-9c7e4648-df07-424c-b826-05ef59f9bfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097260915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1097260915
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1274119707
Short name T916
Test name
Test status
Simulation time 172852795 ps
CPU time 3.17 seconds
Started Jun 22 06:06:28 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 207624 kb
Host smart-d11baac0-f9c3-43f7-9ca6-d0bd5088f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274119707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1274119707
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2210348003
Short name T482
Test name
Test status
Simulation time 131279206 ps
CPU time 5.61 seconds
Started Jun 22 06:06:28 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 210324 kb
Host smart-f8ee87ca-7178-40d0-912e-6df6664dd39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210348003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2210348003
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4068947513
Short name T529
Test name
Test status
Simulation time 81439941 ps
CPU time 3.78 seconds
Started Jun 22 06:06:29 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 208544 kb
Host smart-f77d1c91-823e-41b9-b5ce-5e05c386f37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068947513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4068947513
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2843578024
Short name T855
Test name
Test status
Simulation time 135027965 ps
CPU time 3.49 seconds
Started Jun 22 06:06:29 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 208720 kb
Host smart-f340ce02-bf6c-4dee-b642-469d67595b89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843578024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2843578024
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1936099278
Short name T864
Test name
Test status
Simulation time 112611157 ps
CPU time 2.72 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 207896 kb
Host smart-857b098b-6c91-43b9-a980-28393cbcd953
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936099278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1936099278
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2140256796
Short name T726
Test name
Test status
Simulation time 37236234 ps
CPU time 1.79 seconds
Started Jun 22 06:06:29 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 206932 kb
Host smart-fbfc7ad9-7e9d-40f3-96e5-e98583ae399c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140256796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2140256796
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1151002805
Short name T859
Test name
Test status
Simulation time 207012062 ps
CPU time 2.74 seconds
Started Jun 22 06:06:25 PM PDT 24
Finished Jun 22 06:06:28 PM PDT 24
Peak memory 209808 kb
Host smart-5b952c7e-8971-4662-8395-b0ab516ef9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151002805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1151002805
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1066646117
Short name T212
Test name
Test status
Simulation time 668851362 ps
CPU time 11.26 seconds
Started Jun 22 06:06:23 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 208168 kb
Host smart-a237261c-e88c-4d53-8b63-5ab697ed73f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066646117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1066646117
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3296961330
Short name T548
Test name
Test status
Simulation time 344974160 ps
CPU time 3.43 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 206884 kb
Host smart-6bf61fbb-37c5-4f65-9cba-f23f1fa78154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296961330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3296961330
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2015521853
Short name T605
Test name
Test status
Simulation time 100976524 ps
CPU time 4.98 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:36 PM PDT 24
Peak memory 208132 kb
Host smart-40eff0e3-c850-446c-a5aa-98c4edd25aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015521853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2015521853
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.572487742
Short name T881
Test name
Test status
Simulation time 80411124 ps
CPU time 3.2 seconds
Started Jun 22 06:06:26 PM PDT 24
Finished Jun 22 06:06:31 PM PDT 24
Peak memory 210368 kb
Host smart-e904cc9b-a4db-4055-a6d9-b8b8a5601309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572487742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.572487742
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2721092551
Short name T811
Test name
Test status
Simulation time 30779753 ps
CPU time 0.83 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 205932 kb
Host smart-df9caad8-509d-4bd7-b08d-d4b566e30473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721092551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2721092551
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3331876334
Short name T403
Test name
Test status
Simulation time 308562921 ps
CPU time 14.92 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:46 PM PDT 24
Peak memory 222544 kb
Host smart-1383c055-c109-445f-abca-7d427e546634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331876334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3331876334
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3270088630
Short name T717
Test name
Test status
Simulation time 430785550 ps
CPU time 5.46 seconds
Started Jun 22 06:06:32 PM PDT 24
Finished Jun 22 06:06:38 PM PDT 24
Peak memory 209756 kb
Host smart-084f633c-3d2e-459c-9c8d-c7205f7cf8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270088630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3270088630
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3077676872
Short name T546
Test name
Test status
Simulation time 359018523 ps
CPU time 12.82 seconds
Started Jun 22 06:06:32 PM PDT 24
Finished Jun 22 06:06:46 PM PDT 24
Peak memory 209520 kb
Host smart-2544b1ca-cb4c-4f21-9fe1-d5422c50ade3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077676872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3077676872
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1463639684
Short name T282
Test name
Test status
Simulation time 506124769 ps
CPU time 3.77 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 214300 kb
Host smart-b764f0b3-5122-4e11-8d80-c0680041e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463639684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1463639684
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2163979454
Short name T659
Test name
Test status
Simulation time 189415832 ps
CPU time 3.38 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 214292 kb
Host smart-30d26c6e-e4f7-4ace-afc8-140bfd33fa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163979454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2163979454
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3957098476
Short name T222
Test name
Test status
Simulation time 440316390 ps
CPU time 7.06 seconds
Started Jun 22 06:06:30 PM PDT 24
Finished Jun 22 06:06:38 PM PDT 24
Peak memory 208628 kb
Host smart-702963f8-6c28-469b-bac3-8ae1acb89472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957098476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3957098476
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.689029897
Short name T725
Test name
Test status
Simulation time 147459729 ps
CPU time 4.26 seconds
Started Jun 22 06:06:29 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 207600 kb
Host smart-3e0be6a6-f778-42bc-9937-0e2d87b4d492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689029897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.689029897
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1832929235
Short name T698
Test name
Test status
Simulation time 141092283 ps
CPU time 3.25 seconds
Started Jun 22 06:06:29 PM PDT 24
Finished Jun 22 06:06:34 PM PDT 24
Peak memory 208780 kb
Host smart-33d2cef9-ab7d-4210-85a8-03a5716cb215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832929235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1832929235
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1121621275
Short name T603
Test name
Test status
Simulation time 155476521 ps
CPU time 3.26 seconds
Started Jun 22 06:06:29 PM PDT 24
Finished Jun 22 06:06:33 PM PDT 24
Peak memory 207912 kb
Host smart-c20aec80-3ab0-4a9f-8dbb-b4b48352dde9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121621275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1121621275
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2841756385
Short name T898
Test name
Test status
Simulation time 247249871 ps
CPU time 3.36 seconds
Started Jun 22 06:06:31 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 208820 kb
Host smart-3e36c157-650a-40a5-a621-9f16a9529afc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841756385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2841756385
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1973773675
Short name T875
Test name
Test status
Simulation time 44201919 ps
CPU time 2.8 seconds
Started Jun 22 06:06:33 PM PDT 24
Finished Jun 22 06:06:36 PM PDT 24
Peak memory 206948 kb
Host smart-4236d1e1-1ebb-4d44-9a67-b7e3b8b14d4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973773675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1973773675
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.695456911
Short name T656
Test name
Test status
Simulation time 498630741 ps
CPU time 3.87 seconds
Started Jun 22 06:06:36 PM PDT 24
Finished Jun 22 06:06:41 PM PDT 24
Peak memory 209188 kb
Host smart-4abae75c-e57e-4013-83e8-5337216891a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695456911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.695456911
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2199152049
Short name T412
Test name
Test status
Simulation time 120471173 ps
CPU time 2.76 seconds
Started Jun 22 06:06:28 PM PDT 24
Finished Jun 22 06:06:32 PM PDT 24
Peak memory 206836 kb
Host smart-2829af96-55bf-4029-83ce-31e1a0d5b5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199152049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2199152049
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3253717594
Short name T489
Test name
Test status
Simulation time 60766700 ps
CPU time 2.67 seconds
Started Jun 22 06:06:32 PM PDT 24
Finished Jun 22 06:06:36 PM PDT 24
Peak memory 208260 kb
Host smart-9507ec1d-9aa7-4b1e-b5c6-a2ee1aefabf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253717594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3253717594
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1054664385
Short name T872
Test name
Test status
Simulation time 178077444 ps
CPU time 4.81 seconds
Started Jun 22 06:06:34 PM PDT 24
Finished Jun 22 06:06:39 PM PDT 24
Peak memory 207552 kb
Host smart-58e085bf-b35b-45b6-aad3-43a1c45a5928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054664385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1054664385
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1290787417
Short name T129
Test name
Test status
Simulation time 296023374 ps
CPU time 2.95 seconds
Started Jun 22 06:06:31 PM PDT 24
Finished Jun 22 06:06:35 PM PDT 24
Peak memory 210956 kb
Host smart-b3b05e32-6e7f-480c-8785-b1f36ea03e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290787417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1290787417
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.157605374
Short name T491
Test name
Test status
Simulation time 26120420 ps
CPU time 0.91 seconds
Started Jun 22 06:03:05 PM PDT 24
Finished Jun 22 06:03:06 PM PDT 24
Peak memory 205928 kb
Host smart-46c9c20c-b7ea-423d-bec6-2aeeac8d0f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157605374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.157605374
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3353844558
Short name T42
Test name
Test status
Simulation time 1289139935 ps
CPU time 4.47 seconds
Started Jun 22 06:03:02 PM PDT 24
Finished Jun 22 06:03:07 PM PDT 24
Peak memory 218796 kb
Host smart-357f8dc6-24fe-4dbc-858c-9869d0a1a0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353844558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3353844558
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.805759417
Short name T645
Test name
Test status
Simulation time 134904015 ps
CPU time 3.74 seconds
Started Jun 22 06:03:04 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 218228 kb
Host smart-93567e18-4bfd-4e66-acc5-62cdbb19c147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805759417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.805759417
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2457202798
Short name T84
Test name
Test status
Simulation time 612647516 ps
CPU time 5.45 seconds
Started Jun 22 06:03:05 PM PDT 24
Finished Jun 22 06:03:11 PM PDT 24
Peak memory 214260 kb
Host smart-3d891999-2d7c-4bf0-9d62-56da3687f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457202798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2457202798
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3377087146
Short name T335
Test name
Test status
Simulation time 106220134 ps
CPU time 5.01 seconds
Started Jun 22 06:03:02 PM PDT 24
Finished Jun 22 06:03:07 PM PDT 24
Peak memory 214256 kb
Host smart-6c3a3be2-731f-450b-9ebf-884baf06a7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377087146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3377087146
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2905101655
Short name T837
Test name
Test status
Simulation time 215418076 ps
CPU time 5.04 seconds
Started Jun 22 06:03:03 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 210160 kb
Host smart-37d1dcd2-a65f-4baa-84dd-9169e86fbcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905101655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2905101655
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.749557949
Short name T524
Test name
Test status
Simulation time 1652297599 ps
CPU time 37.61 seconds
Started Jun 22 06:03:04 PM PDT 24
Finished Jun 22 06:03:42 PM PDT 24
Peak memory 208480 kb
Host smart-dec26ac2-f35f-4425-80b1-b3ad3a5564c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749557949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.749557949
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.748465207
Short name T914
Test name
Test status
Simulation time 661523804 ps
CPU time 5.36 seconds
Started Jun 22 06:03:03 PM PDT 24
Finished Jun 22 06:03:09 PM PDT 24
Peak memory 206972 kb
Host smart-a093f1f1-c852-419b-9796-95458b9726fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748465207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.748465207
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4154234388
Short name T566
Test name
Test status
Simulation time 54933296 ps
CPU time 3.08 seconds
Started Jun 22 06:03:04 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 208812 kb
Host smart-c08f4daa-b3eb-4321-9d70-cd2a1b3e1255
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154234388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4154234388
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3086453305
Short name T901
Test name
Test status
Simulation time 56965531 ps
CPU time 2.75 seconds
Started Jun 22 06:03:04 PM PDT 24
Finished Jun 22 06:03:08 PM PDT 24
Peak memory 208760 kb
Host smart-6eba1b40-fd89-49c5-a7da-ed3778fd19c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086453305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3086453305
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3911867886
Short name T456
Test name
Test status
Simulation time 439625111 ps
CPU time 3.42 seconds
Started Jun 22 06:03:05 PM PDT 24
Finished Jun 22 06:03:09 PM PDT 24
Peak memory 209024 kb
Host smart-154c241e-5fde-4516-b65f-639d58c42705
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911867886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3911867886
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1233176598
Short name T418
Test name
Test status
Simulation time 604262185 ps
CPU time 2.65 seconds
Started Jun 22 06:03:03 PM PDT 24
Finished Jun 22 06:03:06 PM PDT 24
Peak memory 218200 kb
Host smart-c2e0cccc-de4a-40a3-81a2-8f99b9ad950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233176598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1233176598
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2020281300
Short name T646
Test name
Test status
Simulation time 286668013 ps
CPU time 2.91 seconds
Started Jun 22 06:02:56 PM PDT 24
Finished Jun 22 06:03:00 PM PDT 24
Peak memory 206808 kb
Host smart-0e7c0357-d90d-4987-b67e-9a65b020c6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020281300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2020281300
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3964155110
Short name T294
Test name
Test status
Simulation time 158612729 ps
CPU time 8.41 seconds
Started Jun 22 06:03:04 PM PDT 24
Finished Jun 22 06:03:12 PM PDT 24
Peak memory 215232 kb
Host smart-2634d23a-5700-4d67-b912-dedf2b2d86af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964155110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3964155110
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.912410787
Short name T349
Test name
Test status
Simulation time 134053896 ps
CPU time 4.59 seconds
Started Jun 22 06:03:02 PM PDT 24
Finished Jun 22 06:03:07 PM PDT 24
Peak memory 207688 kb
Host smart-03bfa720-aa6f-4f13-8d31-a3089025c74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912410787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.912410787
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2252263546
Short name T61
Test name
Test status
Simulation time 156594560 ps
CPU time 2.11 seconds
Started Jun 22 06:03:04 PM PDT 24
Finished Jun 22 06:03:06 PM PDT 24
Peak memory 210036 kb
Host smart-d247a276-7a95-4675-afa0-8c92fbafaf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252263546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2252263546
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1714777784
Short name T790
Test name
Test status
Simulation time 20698409 ps
CPU time 1.03 seconds
Started Jun 22 06:03:09 PM PDT 24
Finished Jun 22 06:03:11 PM PDT 24
Peak memory 206136 kb
Host smart-69889645-aab4-4657-8139-5abb22c86a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714777784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1714777784
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4026111639
Short name T716
Test name
Test status
Simulation time 77439327 ps
CPU time 1.68 seconds
Started Jun 22 06:03:20 PM PDT 24
Finished Jun 22 06:03:22 PM PDT 24
Peak memory 214328 kb
Host smart-71d2b857-45e2-4716-a7af-a8ed118a3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026111639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4026111639
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4038295020
Short name T674
Test name
Test status
Simulation time 65454327 ps
CPU time 2.18 seconds
Started Jun 22 06:03:10 PM PDT 24
Finished Jun 22 06:03:13 PM PDT 24
Peak memory 208496 kb
Host smart-617f6a37-5d83-427f-9b52-e754ea088112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038295020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4038295020
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.801365411
Short name T344
Test name
Test status
Simulation time 208527035 ps
CPU time 2.42 seconds
Started Jun 22 06:03:11 PM PDT 24
Finished Jun 22 06:03:13 PM PDT 24
Peak memory 214304 kb
Host smart-07475e70-f8ad-465c-9fed-4b16c952430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801365411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.801365411
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.923484383
Short name T268
Test name
Test status
Simulation time 108131140 ps
CPU time 3.1 seconds
Started Jun 22 06:03:13 PM PDT 24
Finished Jun 22 06:03:16 PM PDT 24
Peak memory 214224 kb
Host smart-9491bcce-cc21-4b47-ad8d-1df7da93a1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923484383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.923484383
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3213376999
Short name T780
Test name
Test status
Simulation time 170041783 ps
CPU time 4.91 seconds
Started Jun 22 06:03:21 PM PDT 24
Finished Jun 22 06:03:26 PM PDT 24
Peak memory 222512 kb
Host smart-303998da-99d4-4f94-8ff7-f92ab2e51bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213376999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3213376999
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1309067739
Short name T131
Test name
Test status
Simulation time 507321161 ps
CPU time 5.9 seconds
Started Jun 22 06:03:21 PM PDT 24
Finished Jun 22 06:03:27 PM PDT 24
Peak memory 210528 kb
Host smart-60f7ec0d-ae3a-4e2a-82aa-499d4f4d10bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309067739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1309067739
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1157621661
Short name T512
Test name
Test status
Simulation time 40194951 ps
CPU time 2.58 seconds
Started Jun 22 06:03:12 PM PDT 24
Finished Jun 22 06:03:15 PM PDT 24
Peak memory 208700 kb
Host smart-f611549c-bad2-4fcc-a993-e9e6647fabd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157621661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1157621661
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1813926661
Short name T766
Test name
Test status
Simulation time 3426494427 ps
CPU time 27.54 seconds
Started Jun 22 06:03:11 PM PDT 24
Finished Jun 22 06:03:39 PM PDT 24
Peak memory 208136 kb
Host smart-b538c03e-b357-41a5-9ecd-15daa6d07c56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813926661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1813926661
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.968454261
Short name T789
Test name
Test status
Simulation time 197361425 ps
CPU time 2.76 seconds
Started Jun 22 06:03:12 PM PDT 24
Finished Jun 22 06:03:15 PM PDT 24
Peak memory 206948 kb
Host smart-c50f76fe-ce76-4ad0-8c38-bc7009214ba6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968454261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.968454261
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2026244904
Short name T899
Test name
Test status
Simulation time 492363421 ps
CPU time 3 seconds
Started Jun 22 06:03:13 PM PDT 24
Finished Jun 22 06:03:17 PM PDT 24
Peak memory 207000 kb
Host smart-5f0198c4-fd3f-4152-9a5b-3a4f357817b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026244904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2026244904
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1270686914
Short name T262
Test name
Test status
Simulation time 82932357 ps
CPU time 3.36 seconds
Started Jun 22 06:03:13 PM PDT 24
Finished Jun 22 06:03:17 PM PDT 24
Peak memory 218252 kb
Host smart-7a770147-7b0f-4d03-844d-8751455e0699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270686914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1270686914
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2744076402
Short name T464
Test name
Test status
Simulation time 264824636 ps
CPU time 3.29 seconds
Started Jun 22 06:03:10 PM PDT 24
Finished Jun 22 06:03:14 PM PDT 24
Peak memory 207744 kb
Host smart-6d80ea01-a16f-43e5-ba15-4360f8550337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744076402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2744076402
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2136117497
Short name T351
Test name
Test status
Simulation time 1611672054 ps
CPU time 25.7 seconds
Started Jun 22 06:03:21 PM PDT 24
Finished Jun 22 06:03:47 PM PDT 24
Peak memory 222588 kb
Host smart-13ef83fe-1dc7-44fa-9dc3-78b70ff5e45f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136117497 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2136117497
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2840507377
Short name T619
Test name
Test status
Simulation time 77629781 ps
CPU time 4.06 seconds
Started Jun 22 06:03:12 PM PDT 24
Finished Jun 22 06:03:16 PM PDT 24
Peak memory 219732 kb
Host smart-1bf38cec-01b4-4693-b796-7d5b1a69a54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840507377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2840507377
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3708650526
Short name T499
Test name
Test status
Simulation time 713847782 ps
CPU time 2.16 seconds
Started Jun 22 06:03:10 PM PDT 24
Finished Jun 22 06:03:12 PM PDT 24
Peak memory 210192 kb
Host smart-892688dd-b0e9-4df5-8fbc-4f6ea2abed80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708650526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3708650526
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2143406745
Short name T625
Test name
Test status
Simulation time 12830152 ps
CPU time 0.79 seconds
Started Jun 22 06:03:18 PM PDT 24
Finished Jun 22 06:03:19 PM PDT 24
Peak memory 205916 kb
Host smart-5ca151f3-9be4-4c92-b665-33cc2c819cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143406745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2143406745
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2205911265
Short name T398
Test name
Test status
Simulation time 1500356323 ps
CPU time 39.04 seconds
Started Jun 22 06:03:17 PM PDT 24
Finished Jun 22 06:03:57 PM PDT 24
Peak memory 214468 kb
Host smart-8716d4b1-e943-4dda-8544-e37c38296f68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205911265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2205911265
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1420363233
Short name T652
Test name
Test status
Simulation time 1314720778 ps
CPU time 7.52 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:27 PM PDT 24
Peak memory 208532 kb
Host smart-4596677a-f7b1-4e8d-be3e-3ae50f25006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420363233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1420363233
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.978591623
Short name T658
Test name
Test status
Simulation time 734501343 ps
CPU time 6.46 seconds
Started Jun 22 06:03:17 PM PDT 24
Finished Jun 22 06:03:24 PM PDT 24
Peak memory 214280 kb
Host smart-bb7a6985-e79d-499e-9354-2906b1384fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978591623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.978591623
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1917592884
Short name T785
Test name
Test status
Simulation time 71802729 ps
CPU time 2.99 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:22 PM PDT 24
Peak memory 214248 kb
Host smart-dfefe40b-9152-4e98-ac07-0efe72d47649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917592884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1917592884
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.231037750
Short name T58
Test name
Test status
Simulation time 287652032 ps
CPU time 2.51 seconds
Started Jun 22 06:03:21 PM PDT 24
Finished Jun 22 06:03:24 PM PDT 24
Peak memory 217752 kb
Host smart-45f98a56-190d-4cc9-a6b9-ef43957f54c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231037750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.231037750
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1527968017
Short name T510
Test name
Test status
Simulation time 36576688 ps
CPU time 2.8 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:23 PM PDT 24
Peak memory 214300 kb
Host smart-71a92589-750c-4e8e-a73d-27a553eca182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527968017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1527968017
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1308818004
Short name T791
Test name
Test status
Simulation time 36698244 ps
CPU time 1.72 seconds
Started Jun 22 06:03:17 PM PDT 24
Finished Jun 22 06:03:19 PM PDT 24
Peak memory 206716 kb
Host smart-0d3424e8-cba6-49fb-b835-7579474f658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308818004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1308818004
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1095589
Short name T810
Test name
Test status
Simulation time 141860860 ps
CPU time 3.71 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:23 PM PDT 24
Peak memory 208980 kb
Host smart-6e7cccac-80a6-4a7b-ace9-4d54b2794581
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1095589
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1755444975
Short name T765
Test name
Test status
Simulation time 752125074 ps
CPU time 2.76 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:22 PM PDT 24
Peak memory 206964 kb
Host smart-8f760b75-9621-410d-8533-44cac916d099
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755444975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1755444975
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.960851320
Short name T817
Test name
Test status
Simulation time 135267280 ps
CPU time 3.91 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:23 PM PDT 24
Peak memory 208684 kb
Host smart-044a3620-1496-4933-b7ac-a149b6ca306e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960851320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.960851320
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2017299731
Short name T386
Test name
Test status
Simulation time 164003144 ps
CPU time 3.16 seconds
Started Jun 22 06:03:19 PM PDT 24
Finished Jun 22 06:03:23 PM PDT 24
Peak memory 210020 kb
Host smart-9a952f7e-9d50-4111-b1d3-d263ec1fba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017299731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2017299731
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1730329693
Short name T913
Test name
Test status
Simulation time 195886405 ps
CPU time 2.35 seconds
Started Jun 22 06:03:18 PM PDT 24
Finished Jun 22 06:03:20 PM PDT 24
Peak memory 206112 kb
Host smart-876cecdb-5203-4303-8824-b9a43c161855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730329693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1730329693
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2324562052
Short name T558
Test name
Test status
Simulation time 240394027 ps
CPU time 7.69 seconds
Started Jun 22 06:03:17 PM PDT 24
Finished Jun 22 06:03:25 PM PDT 24
Peak memory 208148 kb
Host smart-d33e1c1d-eebe-453f-98b3-8a4650394db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324562052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2324562052
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3536039741
Short name T125
Test name
Test status
Simulation time 42402558 ps
CPU time 2.4 seconds
Started Jun 22 06:03:21 PM PDT 24
Finished Jun 22 06:03:24 PM PDT 24
Peak memory 210396 kb
Host smart-6ad64918-76a0-42bc-a74a-d3dda01bddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536039741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3536039741
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1619918636
Short name T721
Test name
Test status
Simulation time 59033566 ps
CPU time 0.81 seconds
Started Jun 22 06:03:30 PM PDT 24
Finished Jun 22 06:03:31 PM PDT 24
Peak memory 205924 kb
Host smart-f9e44506-cf3d-4e2c-adb7-acba6505afa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619918636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1619918636
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.4276172155
Short name T33
Test name
Test status
Simulation time 124203242 ps
CPU time 4.1 seconds
Started Jun 22 06:03:25 PM PDT 24
Finished Jun 22 06:03:30 PM PDT 24
Peak memory 214608 kb
Host smart-86f1fac5-fe50-4250-9ded-80f4a7b6be04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276172155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.4276172155
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2057906514
Short name T697
Test name
Test status
Simulation time 308490582 ps
CPU time 3.53 seconds
Started Jun 22 06:03:23 PM PDT 24
Finished Jun 22 06:03:27 PM PDT 24
Peak memory 222468 kb
Host smart-ce8638c4-7241-40d3-9814-de17823f9ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057906514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2057906514
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1098576397
Short name T905
Test name
Test status
Simulation time 242043723 ps
CPU time 4.51 seconds
Started Jun 22 06:03:23 PM PDT 24
Finished Jun 22 06:03:28 PM PDT 24
Peak memory 222432 kb
Host smart-0883912c-fe56-46bc-b26a-16c1459881b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098576397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1098576397
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.612871948
Short name T699
Test name
Test status
Simulation time 43963434 ps
CPU time 2.83 seconds
Started Jun 22 06:03:26 PM PDT 24
Finished Jun 22 06:03:30 PM PDT 24
Peak memory 214752 kb
Host smart-6a35586a-cde6-4b62-aa8c-a0f7f07dd748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612871948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.612871948
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.592447671
Short name T612
Test name
Test status
Simulation time 114158438 ps
CPU time 2.9 seconds
Started Jun 22 06:03:26 PM PDT 24
Finished Jun 22 06:03:29 PM PDT 24
Peak memory 215256 kb
Host smart-3b0a42f3-8160-40cb-92da-4bc3214ef03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592447671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.592447671
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4209949107
Short name T682
Test name
Test status
Simulation time 191146179 ps
CPU time 4.7 seconds
Started Jun 22 06:03:25 PM PDT 24
Finished Jun 22 06:03:31 PM PDT 24
Peak memory 207424 kb
Host smart-41db2763-2fbd-4687-bf34-57e4fc2769cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209949107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4209949107
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.66969711
Short name T467
Test name
Test status
Simulation time 1289268861 ps
CPU time 8.99 seconds
Started Jun 22 06:03:18 PM PDT 24
Finished Jun 22 06:03:27 PM PDT 24
Peak memory 206984 kb
Host smart-72a7e7e5-bbbc-4cb5-9640-50c796f4b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66969711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.66969711
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2487692490
Short name T449
Test name
Test status
Simulation time 215526643 ps
CPU time 4.33 seconds
Started Jun 22 06:03:23 PM PDT 24
Finished Jun 22 06:03:28 PM PDT 24
Peak memory 207040 kb
Host smart-76cde2cc-e9aa-4b18-8dfe-79ecfc6ef6b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487692490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2487692490
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2963794568
Short name T416
Test name
Test status
Simulation time 251372981 ps
CPU time 3.85 seconds
Started Jun 22 06:03:31 PM PDT 24
Finished Jun 22 06:03:35 PM PDT 24
Peak memory 208164 kb
Host smart-beea86bb-544c-4425-ade8-2a7a469d033f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963794568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2963794568
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1565293901
Short name T630
Test name
Test status
Simulation time 40305876 ps
CPU time 2.49 seconds
Started Jun 22 06:03:31 PM PDT 24
Finished Jun 22 06:03:34 PM PDT 24
Peak memory 208672 kb
Host smart-1df90036-dd7b-46e2-8d8c-ae590e32fc3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565293901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1565293901
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2214434594
Short name T713
Test name
Test status
Simulation time 449240241 ps
CPU time 5.45 seconds
Started Jun 22 06:03:24 PM PDT 24
Finished Jun 22 06:03:30 PM PDT 24
Peak memory 209100 kb
Host smart-fbb6abf2-aca2-4929-baf9-ed0b1d7861be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214434594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2214434594
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.38556
Short name T210
Test name
Test status
Simulation time 129884777 ps
CPU time 3.06 seconds
Started Jun 22 06:03:17 PM PDT 24
Finished Jun 22 06:03:20 PM PDT 24
Peak memory 208496 kb
Host smart-bf318a45-7a03-42cd-823d-bda6e469b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.38556
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.420494236
Short name T208
Test name
Test status
Simulation time 31231234028 ps
CPU time 104.58 seconds
Started Jun 22 06:03:25 PM PDT 24
Finished Jun 22 06:05:10 PM PDT 24
Peak memory 222496 kb
Host smart-b7b16e65-b0c3-4ffc-9c78-76071f6fb9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420494236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.420494236
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3938070655
Short name T112
Test name
Test status
Simulation time 1036659342 ps
CPU time 9.44 seconds
Started Jun 22 06:03:35 PM PDT 24
Finished Jun 22 06:03:45 PM PDT 24
Peak memory 218676 kb
Host smart-7e7213bc-30f6-4df5-a964-1eca00aca04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938070655 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3938070655
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4198444274
Short name T621
Test name
Test status
Simulation time 1224439863 ps
CPU time 8.09 seconds
Started Jun 22 06:03:24 PM PDT 24
Finished Jun 22 06:03:32 PM PDT 24
Peak memory 218224 kb
Host smart-5b221cd2-90ff-4565-adfe-fe4d837521a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198444274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4198444274
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3145458490
Short name T503
Test name
Test status
Simulation time 34529542 ps
CPU time 1.97 seconds
Started Jun 22 06:03:24 PM PDT 24
Finished Jun 22 06:03:26 PM PDT 24
Peak memory 210020 kb
Host smart-a1182634-dd5f-4db2-bead-11267436a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145458490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3145458490
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3853459254
Short name T428
Test name
Test status
Simulation time 11631044 ps
CPU time 0.72 seconds
Started Jun 22 06:03:40 PM PDT 24
Finished Jun 22 06:03:41 PM PDT 24
Peak memory 206068 kb
Host smart-b11e2175-dd83-485f-9659-e04875b85088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853459254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3853459254
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1290088285
Short name T74
Test name
Test status
Simulation time 80880038 ps
CPU time 3.25 seconds
Started Jun 22 06:03:36 PM PDT 24
Finished Jun 22 06:03:40 PM PDT 24
Peak memory 207368 kb
Host smart-58bd35e6-2a08-4edc-8a84-8717da8eb54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290088285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1290088285
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1718489368
Short name T329
Test name
Test status
Simulation time 93218453 ps
CPU time 3 seconds
Started Jun 22 06:03:31 PM PDT 24
Finished Jun 22 06:03:35 PM PDT 24
Peak memory 214376 kb
Host smart-258aab46-ca2d-459c-ae9f-4607595fcafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718489368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1718489368
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1948596463
Short name T283
Test name
Test status
Simulation time 1799155849 ps
CPU time 18.61 seconds
Started Jun 22 06:03:35 PM PDT 24
Finished Jun 22 06:03:54 PM PDT 24
Peak memory 214292 kb
Host smart-8f00c2cb-67d6-4340-8772-6e1f25235407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948596463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1948596463
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3356423274
Short name T825
Test name
Test status
Simulation time 266715336 ps
CPU time 3.41 seconds
Started Jun 22 06:03:36 PM PDT 24
Finished Jun 22 06:03:39 PM PDT 24
Peak memory 219884 kb
Host smart-a7af6ade-7634-4f8b-8a38-764d4c4a2efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356423274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3356423274
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1205635308
Short name T321
Test name
Test status
Simulation time 3780303601 ps
CPU time 12.42 seconds
Started Jun 22 06:03:30 PM PDT 24
Finished Jun 22 06:03:43 PM PDT 24
Peak memory 208996 kb
Host smart-5fb885f7-261e-4224-a288-141c465e981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205635308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1205635308
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1844079191
Short name T562
Test name
Test status
Simulation time 64859331 ps
CPU time 3.47 seconds
Started Jun 22 06:03:34 PM PDT 24
Finished Jun 22 06:03:38 PM PDT 24
Peak memory 208420 kb
Host smart-b62abaef-82da-46c1-ad0c-e8d1c12b0d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844079191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1844079191
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2670540140
Short name T192
Test name
Test status
Simulation time 231271566 ps
CPU time 2.68 seconds
Started Jun 22 06:03:32 PM PDT 24
Finished Jun 22 06:03:35 PM PDT 24
Peak memory 207380 kb
Host smart-41c9abb7-939b-41ac-a84c-9fccb953cb47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670540140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2670540140
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4037281903
Short name T420
Test name
Test status
Simulation time 296196480 ps
CPU time 2.58 seconds
Started Jun 22 06:03:30 PM PDT 24
Finished Jun 22 06:03:33 PM PDT 24
Peak memory 206944 kb
Host smart-b43e95f1-eb29-427d-8728-7a526067b94c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037281903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4037281903
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3162464895
Short name T312
Test name
Test status
Simulation time 1037177832 ps
CPU time 10.45 seconds
Started Jun 22 06:03:33 PM PDT 24
Finished Jun 22 06:03:44 PM PDT 24
Peak memory 208672 kb
Host smart-1ed52d6d-96f7-48dc-8dfd-338baf61e7f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162464895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3162464895
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2118842674
Short name T523
Test name
Test status
Simulation time 4348357670 ps
CPU time 22.44 seconds
Started Jun 22 06:03:30 PM PDT 24
Finished Jun 22 06:03:53 PM PDT 24
Peak memory 214432 kb
Host smart-aba5a187-11a6-4398-af40-c5e95bad25ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118842674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2118842674
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3957564776
Short name T18
Test name
Test status
Simulation time 73661007 ps
CPU time 3.18 seconds
Started Jun 22 06:03:35 PM PDT 24
Finished Jun 22 06:03:39 PM PDT 24
Peak memory 208584 kb
Host smart-3555934c-a4ec-48ac-a2e9-3f44f148cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957564776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3957564776
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1080165130
Short name T189
Test name
Test status
Simulation time 6093856655 ps
CPU time 17.02 seconds
Started Jun 22 06:03:42 PM PDT 24
Finished Jun 22 06:03:59 PM PDT 24
Peak memory 221336 kb
Host smart-e0e1618d-00d6-40e1-83b7-647b77c0a40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080165130 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1080165130
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3492582021
Short name T298
Test name
Test status
Simulation time 232572325 ps
CPU time 5.79 seconds
Started Jun 22 06:03:34 PM PDT 24
Finished Jun 22 06:03:40 PM PDT 24
Peak memory 222316 kb
Host smart-0898af6b-c566-4533-b354-f1d2cae6030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492582021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3492582021
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1443186168
Short name T471
Test name
Test status
Simulation time 23206797 ps
CPU time 1.41 seconds
Started Jun 22 06:03:33 PM PDT 24
Finished Jun 22 06:03:35 PM PDT 24
Peak memory 209568 kb
Host smart-d57a10e4-716a-414a-bb92-7717227c079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443186168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1443186168
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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