Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10652

1

T1

7

T2

5

T4

17

auto[Attestation]

7005

1

T1

6

T4

4

T5

1

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2556	1			T1	1		T2	1		T4	2
auto[Aes]	3169	1			T2	1		T4	5		T5	2
auto[Kmac]	3076	1			T1	1		T2	1		T4	6
auto[Otbn]	3255	1			T1	2		T4	3		T5	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7238	1			T1	4		T2	1		T4	8
auto[OpGenId]	5601	1			T1	9		T2	2		T4	5
auto[OpGenSwOut]	5544	1			T1	2		T2	3		T4	12
auto[OpGenHwOut]	6512	1			T1	2		T4	4		T5	8
auto[OpDisable]	139	1			T1	1		T14	1		T36	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10066

1

T1

15

T2

1

T4

8

auto[OpDoneFail]

14968

1

T1

3

T2

5

T4

21

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6206	1			T1	1		T2	6		T4	14
auto[StInit]	3573	1			T1	2		T4	2		T5	5
auto[StCreatorRootKey]	2961	1			T1	3		T4	2		T5	3
auto[StOwnerIntKey]	2630	1			T1	5		T4	2		T12	2
auto[StOwnerKey]	2353	1			T1	5		T4	2		T12	2
auto[StDisabled]	7311	1			T1	2		T4	7		T12	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	338	1			T2	1		T4	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T56	1		T57	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T14	1		T75	1		T78	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T80	1		T25	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	76	1			T1	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	177	1			T14	2		T80	2		T25	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	325	1			T2	1		T4	3		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	88	1			T5	1		T13	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	86	1			T13	1		T14	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T14	1		T81	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	65	1			T25	1		T49	1		T53	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	195	1			T13	1		T14	2		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	325	1			T2	1		T4	4		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	102	1			T5	1		T35	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T25	1		T49	1		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T1	1		T25	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	50	1			T14	1		T80	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	189	1			T4	1		T13	1		T14	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	306	1			T4	1		T14	5		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	101	1			T25	2		T21	2		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T79	1		T49	2		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T14	1		T25	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T44	1		T49	2		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	207	1			T14	1		T80	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	63	1			T49	3		T66	1		T67	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T25	2		T21	2		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T25	1		T49	1		T53	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	79	1			T4	1		T14	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	58	1			T78	2		T49	2		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	205	1			T13	2		T14	2		T80	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T25	1		T49	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	94	1			T14	3		T35	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	75	1			T25	1		T180	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T13	1		T44	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T25	1		T49	3		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	212	1			T14	2		T80	2		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	60	1			T25	1		T49	4		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	85	1			T15	1		T25	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	67	1			T14	1		T60	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T57	1		T75	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	57	1			T49	2		T126	1		T53	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	161	1			T14	1		T80	2		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T25	3		T49	2		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T14	1		T36	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	68	1			T14	1		T15	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	57	1			T14	1		T56	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	58	1			T4	1		T14	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	220	1			T13	1		T14	2		T80	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	293	1			T5	1		T14	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T35	1		T25	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T5	2		T47	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T14	1		T49	3		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T36	1		T44	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	142	1			T14	1		T36	1		T80	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	365	1			T4	1		T5	1		T14	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	115	1			T25	1		T21	3		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	107	1			T14	1		T49	1		T184	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T14	1		T75	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T14	1		T36	2		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	281	1			T4	1		T44	1		T25	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	434	1			T5	1		T14	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T5	1		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T75	1		T76	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T12	1		T81	1		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	92	1			T12	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	246	1			T4	1		T12	1		T14	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	477	1			T4	1		T14	4		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T57	1		T22	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T5	1		T57	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T1	1		T15	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	78	1			T81	1		T77	1		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	272	1			T25	3		T75	1		T77	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T25	3		T66	2		T67	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	80	1			T13	2		T25	4		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	64	1			T14	2		T47	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T25	2		T49	2		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T25	2		T185	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	137	1			T14	3		T81	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T25	2		T53	1		T66	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T13	1		T21	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	115	1			T13	1		T14	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T186	1		T185	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	81	1			T49	1		T186	1		T180	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	260	1			T14	4		T44	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	42	1			T66	1		T188	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	99	1			T14	1		T25	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T12	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T13	1		T25	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	79	1			T14	1		T78	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	276	1			T12	3		T14	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	42	1			T25	1		T53	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	121	1			T5	1		T14	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	115	1			T1	1		T15	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T190	1		T126	1		T181	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	81	1			T14	1		T80	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	251	1			T80	1		T25	2		T77	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	198	1			T1	1		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	638	1			T2	1		T4	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	204	1			T14	2		T47	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	623	1			T2	1		T4	3		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	180	1			T1	1		T14	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	626	1			T2	1		T4	5		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	212	1			T14	1		T44	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	629	1			T4	1		T14	6		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	192	1			T4	1		T14	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	382	1			T13	2		T14	2		T80	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	187	1			T13	1		T44	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	392	1			T14	5		T35	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T14	1		T57	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	322	1			T14	1		T15	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T4	1		T14	3		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	402	1			T13	1		T14	3		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T5	2		T14	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	545	1			T5	1		T14	3		T35	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	271	1			T14	3		T36	2		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	776	1			T4	2		T5	1		T14	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T12	2		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	820	1			T4	1		T5	2		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	261	1			T1	1		T5	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	880	1			T4	1		T14	4		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	162	1			T14	2		T47	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	286	1			T13	2		T14	3		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	278	1			T13	1		T14	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	438	1			T13	1		T14	4		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	255	1			T12	1		T14	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	436	1			T12	3		T13	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T1	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	433	1			T5	1		T14	1		T80	1