Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31009

1

T1

20

T2

39

T4

33

auto[1]

291

1

T44

2

T81

1

T75

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31017	1			T1	20		T2	39		T4	33
auto[134217728:268435455]	9	1			T248	1		T294	1		T300	1
auto[268435456:402653183]	9	1			T294	1		T318	1		T234	1
auto[402653184:536870911]	7	1			T318	1		T216	2		T337	1
auto[536870912:671088639]	13	1			T44	1		T294	1		T219	1
auto[671088640:805306367]	11	1			T294	1		T295	1		T218	1
auto[805306368:939524095]	8	1			T276	1		T278	1		T216	1
auto[939524096:1073741823]	15	1			T75	1		T126	2		T216	1
auto[1073741824:1207959551]	7	1			T239	1		T168	1		T226	1
auto[1207959552:1342177279]	9	1			T168	1		T216	1		T342	1
auto[1342177280:1476395007]	6	1			T276	1		T300	1		T388	1
auto[1476395008:1610612735]	8	1			T216	2		T342	1		T389	1
auto[1610612736:1744830463]	8	1			T216	1		T217	1		T219	1
auto[1744830464:1879048191]	6	1			T257	1		T354	1		T390	1
auto[1879048192:2013265919]	7	1			T75	1		T216	1		T226	1
auto[2013265920:2147483647]	10	1			T276	1		T216	1		T218	2
auto[2147483648:2281701375]	10	1			T81	1		T168	1		T388	1
auto[2281701376:2415919103]	11	1			T257	1		T300	1		T388	2
auto[2415919104:2550136831]	12	1			T248	1		T168	1		T218	1
auto[2550136832:2684354559]	3	1			T342	1		T391	1		T392	1
auto[2684354560:2818572287]	6	1			T75	1		T300	1		T389	1
auto[2818572288:2952790015]	13	1			T276	1		T294	1		T388	2
auto[2952790016:3087007743]	9	1			T294	1		T257	1		T226	1
auto[3087007744:3221225471]	4	1			T294	1		T391	1		T393	1
auto[3221225472:3355443199]	11	1			T44	1		T168	1		T216	1
auto[3355443200:3489660927]	14	1			T294	2		T216	1		T257	2
auto[3489660928:3623878655]	7	1			T168	1		T254	1		T263	2
auto[3623878656:3758096383]	14	1			T75	1		T276	1		T257	1
auto[3758096384:3892314111]	5	1			T239	3		T388	1		T394	1
auto[3892314112:4026531839]	12	1			T239	1		T294	1		T318	1
auto[4026531840:4160749567]	6	1			T248	1		T216	1		T218	1
auto[4160749568:4294967295]	13	1			T248	1		T276	1		T294	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31009	1			T1	20		T2	39		T4	33
auto[0:134217727]	auto[1]	8	1			T276	1		T216	1		T217	1
auto[134217728:268435455]	auto[1]	9	1			T248	1		T294	1		T300	1
auto[268435456:402653183]	auto[1]	9	1			T294	1		T318	1		T234	1
auto[402653184:536870911]	auto[1]	7	1			T318	1		T216	2		T337	1
auto[536870912:671088639]	auto[1]	13	1			T44	1		T294	1		T219	1
auto[671088640:805306367]	auto[1]	11	1			T294	1		T295	1		T218	1
auto[805306368:939524095]	auto[1]	8	1			T276	1		T278	1		T216	1
auto[939524096:1073741823]	auto[1]	15	1			T75	1		T126	2		T216	1
auto[1073741824:1207959551]	auto[1]	7	1			T239	1		T168	1		T226	1
auto[1207959552:1342177279]	auto[1]	9	1			T168	1		T216	1		T342	1
auto[1342177280:1476395007]	auto[1]	6	1			T276	1		T300	1		T388	1
auto[1476395008:1610612735]	auto[1]	8	1			T216	2		T342	1		T389	1
auto[1610612736:1744830463]	auto[1]	8	1			T216	1		T217	1		T219	1
auto[1744830464:1879048191]	auto[1]	6	1			T257	1		T354	1		T390	1
auto[1879048192:2013265919]	auto[1]	7	1			T75	1		T216	1		T226	1
auto[2013265920:2147483647]	auto[1]	10	1			T276	1		T216	1		T218	2
auto[2147483648:2281701375]	auto[1]	10	1			T81	1		T168	1		T388	1
auto[2281701376:2415919103]	auto[1]	11	1			T257	1		T300	1		T388	2
auto[2415919104:2550136831]	auto[1]	12	1			T248	1		T168	1		T218	1
auto[2550136832:2684354559]	auto[1]	3	1			T342	1		T391	1		T392	1
auto[2684354560:2818572287]	auto[1]	6	1			T75	1		T300	1		T389	1
auto[2818572288:2952790015]	auto[1]	13	1			T276	1		T294	1		T388	2
auto[2952790016:3087007743]	auto[1]	9	1			T294	1		T257	1		T226	1
auto[3087007744:3221225471]	auto[1]	4	1			T294	1		T391	1		T393	1
auto[3221225472:3355443199]	auto[1]	11	1			T44	1		T168	1		T216	1
auto[3355443200:3489660927]	auto[1]	14	1			T294	2		T216	1		T257	2
auto[3489660928:3623878655]	auto[1]	7	1			T168	1		T254	1		T263	2
auto[3623878656:3758096383]	auto[1]	14	1			T75	1		T276	1		T257	1
auto[3758096384:3892314111]	auto[1]	5	1			T239	3		T388	1		T394	1
auto[3892314112:4026531839]	auto[1]	12	1			T239	1		T294	1		T318	1
auto[4026531840:4160749567]	auto[1]	6	1			T248	1		T216	1		T218	1
auto[4160749568:4294967295]	auto[1]	13	1			T248	1		T276	1		T294	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1435

1

T1

1

T2

3

T13

1

auto[1]

1563

1

T1

3

T2

1

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T25	1		T49	5		T66	1
auto[134217728:268435455]	94	1			T1	1		T14	1		T25	1
auto[268435456:402653183]	83	1			T81	2		T21	1		T49	2
auto[402653184:536870911]	81	1			T46	1		T36	1		T25	2
auto[536870912:671088639]	90	1			T13	1		T6	1		T25	2
auto[671088640:805306367]	92	1			T53	1		T192	1		T66	1
auto[805306368:939524095]	107	1			T2	1		T35	1		T25	2
auto[939524096:1073741823]	81	1			T14	2		T36	1		T25	1
auto[1073741824:1207959551]	98	1			T47	1		T25	2		T75	1
auto[1207959552:1342177279]	91	1			T6	1		T80	1		T25	2
auto[1342177280:1476395007]	101	1			T25	1		T79	1		T49	1
auto[1476395008:1610612735]	95	1			T36	1		T80	1		T25	2
auto[1610612736:1744830463]	74	1			T1	1		T47	1		T25	2
auto[1744830464:1879048191]	85	1			T44	1		T57	1		T25	2
auto[1879048192:2013265919]	105	1			T1	1		T13	1		T44	1
auto[2013265920:2147483647]	95	1			T2	1		T14	2		T179	1
auto[2147483648:2281701375]	96	1			T2	1		T47	1		T25	2
auto[2281701376:2415919103]	95	1			T80	1		T44	1		T81	1
auto[2415919104:2550136831]	109	1			T35	1		T25	2		T16	1
auto[2550136832:2684354559]	109	1			T44	1		T81	1		T75	1
auto[2684354560:2818572287]	85	1			T2	1		T14	2		T25	2
auto[2818572288:2952790015]	99	1			T25	1		T49	2		T66	1
auto[2952790016:3087007743]	107	1			T1	1		T56	1		T25	3
auto[3087007744:3221225471]	84	1			T13	1		T14	2		T46	1
auto[3221225472:3355443199]	96	1			T14	1		T46	1		T25	2
auto[3355443200:3489660927]	85	1			T35	1		T47	1		T25	2
auto[3489660928:3623878655]	107	1			T78	1		T49	1		T27	1
auto[3623878656:3758096383]	94	1			T14	1		T35	1		T49	2
auto[3758096384:3892314111]	77	1			T25	1		T49	2		T66	1
auto[3892314112:4026531839]	87	1			T25	3		T189	1		T49	1
auto[4026531840:4160749567]	92	1			T80	1		T78	1		T49	4
auto[4160749568:4294967295]	109	1			T47	1		T81	1		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T25	1		T49	3		T66	1
auto[0:134217727]	auto[1]	44	1			T49	2		T68	1		T7	2
auto[134217728:268435455]	auto[0]	44	1			T14	1		T75	1		T21	1
auto[134217728:268435455]	auto[1]	50	1			T1	1		T25	1		T21	1
auto[268435456:402653183]	auto[0]	36	1			T49	2		T180	1		T53	1
auto[268435456:402653183]	auto[1]	47	1			T81	2		T21	1		T60	1
auto[402653184:536870911]	auto[0]	31	1			T25	1		T79	1		T119	1
auto[402653184:536870911]	auto[1]	50	1			T46	1		T36	1		T25	1
auto[536870912:671088639]	auto[0]	46	1			T13	1		T25	1		T27	1
auto[536870912:671088639]	auto[1]	44	1			T6	1		T25	1		T16	1
auto[671088640:805306367]	auto[0]	43	1			T53	1		T192	1		T246	1
auto[671088640:805306367]	auto[1]	49	1			T66	1		T127	1		T41	1
auto[805306368:939524095]	auto[0]	53	1			T2	1		T25	1		T75	1
auto[805306368:939524095]	auto[1]	54	1			T35	1		T25	1		T66	1
auto[939524096:1073741823]	auto[0]	45	1			T14	1		T36	1		T25	1
auto[939524096:1073741823]	auto[1]	36	1			T14	1		T49	2		T184	1
auto[1073741824:1207959551]	auto[0]	49	1			T47	1		T25	1		T49	1
auto[1073741824:1207959551]	auto[1]	49	1			T25	1		T75	1		T53	1
auto[1207959552:1342177279]	auto[0]	35	1			T79	1		T53	1		T89	1
auto[1207959552:1342177279]	auto[1]	56	1			T6	1		T80	1		T25	2
auto[1342177280:1476395007]	auto[0]	56	1			T25	1		T66	1		T61	1
auto[1342177280:1476395007]	auto[1]	45	1			T79	1		T49	1		T17	1
auto[1476395008:1610612735]	auto[0]	44	1			T25	1		T37	1		T62	1
auto[1476395008:1610612735]	auto[1]	51	1			T36	1		T80	1		T25	1
auto[1610612736:1744830463]	auto[0]	35	1			T47	1		T25	2		T79	1
auto[1610612736:1744830463]	auto[1]	39	1			T1	1		T67	1		T61	1
auto[1744830464:1879048191]	auto[0]	45	1			T57	1		T49	1		T51	1
auto[1744830464:1879048191]	auto[1]	40	1			T44	1		T25	2		T49	1
auto[1879048192:2013265919]	auto[0]	47	1			T47	1		T25	1		T49	2
auto[1879048192:2013265919]	auto[1]	58	1			T1	1		T13	1		T44	1
auto[2013265920:2147483647]	auto[0]	45	1			T2	1		T14	1		T179	1
auto[2013265920:2147483647]	auto[1]	50	1			T14	1		T126	1		T53	2
auto[2147483648:2281701375]	auto[0]	48	1			T47	1		T49	1		T37	1
auto[2147483648:2281701375]	auto[1]	48	1			T2	1		T25	2		T102	1
auto[2281701376:2415919103]	auto[0]	50	1			T44	1		T49	1		T395	1
auto[2281701376:2415919103]	auto[1]	45	1			T80	1		T81	1		T67	1
auto[2415919104:2550136831]	auto[0]	45	1			T25	1		T16	1		T53	1
auto[2415919104:2550136831]	auto[1]	64	1			T35	1		T25	1		T62	1
auto[2550136832:2684354559]	auto[0]	60	1			T81	1		T21	1		T49	3
auto[2550136832:2684354559]	auto[1]	49	1			T44	1		T75	1		T49	1
auto[2684354560:2818572287]	auto[0]	35	1			T2	1		T14	1		T53	1
auto[2684354560:2818572287]	auto[1]	50	1			T14	1		T25	2		T189	1
auto[2818572288:2952790015]	auto[0]	54	1			T49	2		T69	1		T121	1
auto[2818572288:2952790015]	auto[1]	45	1			T25	1		T66	1		T61	1
auto[2952790016:3087007743]	auto[0]	41	1			T1	1		T25	2		T26	1
auto[2952790016:3087007743]	auto[1]	66	1			T56	1		T25	1		T184	1
auto[3087007744:3221225471]	auto[0]	39	1			T46	1		T25	1		T49	1
auto[3087007744:3221225471]	auto[1]	45	1			T13	1		T14	2		T49	2
auto[3221225472:3355443199]	auto[0]	50	1			T14	1		T46	1		T25	2
auto[3221225472:3355443199]	auto[1]	46	1			T51	1		T126	1		T66	1
auto[3355443200:3489660927]	auto[0]	41	1			T47	1		T25	1		T53	1
auto[3355443200:3489660927]	auto[1]	44	1			T35	1		T25	1		T49	1
auto[3489660928:3623878655]	auto[0]	37	1			T118	1		T61	2		T240	1
auto[3489660928:3623878655]	auto[1]	70	1			T78	1		T49	1		T27	1
auto[3623878656:3758096383]	auto[0]	49	1			T49	1		T53	2		T119	1
auto[3623878656:3758096383]	auto[1]	45	1			T14	1		T35	1		T49	1
auto[3758096384:3892314111]	auto[0]	37	1			T25	1		T49	1		T66	1
auto[3758096384:3892314111]	auto[1]	40	1			T49	1		T395	1		T240	1
auto[3892314112:4026531839]	auto[0]	44	1			T25	3		T49	1		T37	1
auto[3892314112:4026531839]	auto[1]	43	1			T189	1		T183	1		T53	1
auto[4026531840:4160749567]	auto[0]	47	1			T49	3		T26	1		T70	2
auto[4026531840:4160749567]	auto[1]	45	1			T80	1		T78	1		T49	1
auto[4160749568:4294967295]	auto[0]	53	1			T47	1		T81	1		T25	2
auto[4160749568:4294967295]	auto[1]	56	1			T57	1		T25	1		T62	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1432

1

T1

1

T2

3

T14

5

auto[1]

1565

1

T1

3

T2

1

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T14	1		T81	1		T79	1
auto[134217728:268435455]	91	1			T47	1		T25	3		T49	1
auto[268435456:402653183]	87	1			T81	1		T78	1		T49	4
auto[402653184:536870911]	91	1			T47	1		T25	1		T189	1
auto[536870912:671088639]	87	1			T35	2		T47	1		T256	1
auto[671088640:805306367]	82	1			T25	3		T49	2		T66	1
auto[805306368:939524095]	106	1			T47	1		T25	1		T179	1
auto[939524096:1073741823]	88	1			T44	1		T25	3		T49	1
auto[1073741824:1207959551]	94	1			T44	1		T47	1		T56	1
auto[1207959552:1342177279]	91	1			T1	1		T25	1		T49	3
auto[1342177280:1476395007]	84	1			T14	1		T49	2		T53	1
auto[1476395008:1610612735]	103	1			T14	1		T6	1		T80	1
auto[1610612736:1744830463]	78	1			T14	1		T6	1		T25	1
auto[1744830464:1879048191]	103	1			T25	2		T49	1		T53	1
auto[1879048192:2013265919]	103	1			T13	1		T25	1		T78	1
auto[2013265920:2147483647]	88	1			T35	1		T49	2		T53	1
auto[2147483648:2281701375]	97	1			T35	1		T25	1		T22	1
auto[2281701376:2415919103]	108	1			T2	1		T80	1		T25	4
auto[2415919104:2550136831]	89	1			T80	1		T44	1		T25	1
auto[2550136832:2684354559]	101	1			T14	1		T25	1		T75	1
auto[2684354560:2818572287]	108	1			T25	2		T49	1		T66	2
auto[2818572288:2952790015]	102	1			T25	1		T53	2		T192	1
auto[2952790016:3087007743]	94	1			T1	1		T2	1		T14	1
auto[3087007744:3221225471]	83	1			T2	1		T46	2		T324	1
auto[3221225472:3355443199]	112	1			T13	1		T36	1		T25	1
auto[3355443200:3489660927]	86	1			T14	1		T81	2		T25	2
auto[3489660928:3623878655]	110	1			T13	1		T14	1		T36	2
auto[3623878656:3758096383]	81	1			T2	1		T47	1		T81	1
auto[3758096384:3892314111]	77	1			T14	1		T80	1		T25	2
auto[3892314112:4026531839]	92	1			T14	2		T46	1		T25	2
auto[4026531840:4160749567]	90	1			T1	1		T57	1		T25	2
auto[4160749568:4294967295]	98	1			T1	1		T57	1		T25	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T14	1		T81	1		T49	1
auto[0:134217727]	auto[1]	42	1			T79	1		T49	1		T126	1
auto[134217728:268435455]	auto[0]	37	1			T47	1		T25	1		T37	1
auto[134217728:268435455]	auto[1]	54	1			T25	2		T49	1		T126	1
auto[268435456:402653183]	auto[0]	39	1			T49	2		T70	1		T63	1
auto[268435456:402653183]	auto[1]	48	1			T81	1		T78	1		T49	2
auto[402653184:536870911]	auto[0]	45	1			T47	1		T49	1		T53	2
auto[402653184:536870911]	auto[1]	46	1			T25	1		T189	1		T49	1
auto[536870912:671088639]	auto[0]	45	1			T47	1		T192	1		T69	1
auto[536870912:671088639]	auto[1]	42	1			T35	2		T256	1		T39	1
auto[671088640:805306367]	auto[0]	45	1			T25	1		T49	1		T246	1
auto[671088640:805306367]	auto[1]	37	1			T25	2		T49	1		T66	1
auto[805306368:939524095]	auto[0]	57	1			T47	1		T179	1		T37	1
auto[805306368:939524095]	auto[1]	49	1			T25	1		T53	1		T67	1
auto[939524096:1073741823]	auto[0]	47	1			T25	2		T49	1		T53	1
auto[939524096:1073741823]	auto[1]	41	1			T44	1		T25	1		T53	1
auto[1073741824:1207959551]	auto[0]	40	1			T47	1		T51	1		T52	1
auto[1073741824:1207959551]	auto[1]	54	1			T44	1		T56	1		T25	1
auto[1207959552:1342177279]	auto[0]	48	1			T25	1		T49	1		T67	1
auto[1207959552:1342177279]	auto[1]	43	1			T1	1		T49	2		T62	1
auto[1342177280:1476395007]	auto[0]	45	1			T49	2		T53	1		T66	1
auto[1342177280:1476395007]	auto[1]	39	1			T14	1		T66	1		T7	1
auto[1476395008:1610612735]	auto[0]	53	1			T14	1		T49	1		T37	1
auto[1476395008:1610612735]	auto[1]	50	1			T6	1		T80	1		T21	1
auto[1610612736:1744830463]	auto[0]	28	1			T21	1		T79	1		T396	1
auto[1610612736:1744830463]	auto[1]	50	1			T14	1		T6	1		T25	1
auto[1744830464:1879048191]	auto[0]	47	1			T25	2		T66	1		T121	1
auto[1744830464:1879048191]	auto[1]	56	1			T49	1		T53	1		T68	1
auto[1879048192:2013265919]	auto[0]	44	1			T25	1		T49	1		T179	2
auto[1879048192:2013265919]	auto[1]	59	1			T13	1		T78	1		T49	2
auto[2013265920:2147483647]	auto[0]	47	1			T49	2		T53	1		T67	1
auto[2013265920:2147483647]	auto[1]	41	1			T35	1		T66	1		T7	1
auto[2147483648:2281701375]	auto[0]	41	1			T25	1		T22	1		T49	4
auto[2147483648:2281701375]	auto[1]	56	1			T35	1		T49	1		T184	1
auto[2281701376:2415919103]	auto[0]	54	1			T2	1		T25	1		T49	1
auto[2281701376:2415919103]	auto[1]	54	1			T80	1		T25	3		T75	1
auto[2415919104:2550136831]	auto[0]	41	1			T25	1		T179	1		T69	1
auto[2415919104:2550136831]	auto[1]	48	1			T80	1		T44	1		T53	1
auto[2550136832:2684354559]	auto[0]	46	1			T14	1		T25	1		T75	1
auto[2550136832:2684354559]	auto[1]	55	1			T49	1		T53	1		T66	4
auto[2684354560:2818572287]	auto[0]	54	1			T25	2		T7	1		T245	1
auto[2684354560:2818572287]	auto[1]	54	1			T49	1		T66	2		T120	1
auto[2818572288:2952790015]	auto[0]	51	1			T25	1		T53	1		T192	1
auto[2818572288:2952790015]	auto[1]	51	1			T53	1		T66	1		T70	1
auto[2952790016:3087007743]	auto[0]	47	1			T2	1		T14	1		T44	1
auto[2952790016:3087007743]	auto[1]	47	1			T1	1		T25	1		T53	1
auto[3087007744:3221225471]	auto[0]	38	1			T2	1		T46	1		T70	2
auto[3087007744:3221225471]	auto[1]	45	1			T46	1		T324	1		T68	1
auto[3221225472:3355443199]	auto[0]	50	1			T21	1		T16	1		T53	1
auto[3221225472:3355443199]	auto[1]	62	1			T13	1		T36	1		T25	1
auto[3355443200:3489660927]	auto[0]	39	1			T81	1		T25	2		T26	1
auto[3355443200:3489660927]	auto[1]	47	1			T14	1		T81	1		T53	1
auto[3489660928:3623878655]	auto[0]	48	1			T14	1		T36	1		T25	2
auto[3489660928:3623878655]	auto[1]	62	1			T13	1		T36	1		T16	1
auto[3623878656:3758096383]	auto[0]	34	1			T47	1		T81	1		T25	1
auto[3623878656:3758096383]	auto[1]	47	1			T2	1		T60	1		T66	1
auto[3758096384:3892314111]	auto[0]	32	1			T25	1		T49	1		T180	1
auto[3758096384:3892314111]	auto[1]	45	1			T14	1		T80	1		T25	1
auto[3892314112:4026531839]	auto[0]	40	1			T46	1		T25	1		T49	2
auto[3892314112:4026531839]	auto[1]	52	1			T14	2		T25	1		T16	1
auto[4026531840:4160749567]	auto[0]	52	1			T57	1		T25	1		T21	1
auto[4026531840:4160749567]	auto[1]	38	1			T1	1		T25	1		T66	1
auto[4160749568:4294967295]	auto[0]	47	1			T1	1		T25	1		T75	1
auto[4160749568:4294967295]	auto[1]	51	1			T57	1		T25	1		T75	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1396

1

T1

1

T2

2

T14

4

auto[1]

1601

1

T1

3

T2

2

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T14	1		T49	3		T53	2
auto[134217728:268435455]	102	1			T2	1		T49	1		T179	1
auto[268435456:402653183]	85	1			T2	1		T13	1		T14	1
auto[402653184:536870911]	78	1			T25	1		T22	1		T49	2
auto[536870912:671088639]	97	1			T44	1		T25	2		T49	1
auto[671088640:805306367]	93	1			T1	1		T57	1		T25	2
auto[805306368:939524095]	95	1			T57	1		T25	1		T78	1
auto[939524096:1073741823]	90	1			T35	1		T25	2		T189	1
auto[1073741824:1207959551]	86	1			T25	3		T179	1		T53	1
auto[1207959552:1342177279]	83	1			T25	3		T53	2		T62	1
auto[1342177280:1476395007]	95	1			T1	1		T36	1		T44	1
auto[1476395008:1610612735]	79	1			T47	1		T75	1		T16	1
auto[1610612736:1744830463]	118	1			T14	1		T36	1		T47	1
auto[1744830464:1879048191]	102	1			T14	1		T47	1		T25	1
auto[1879048192:2013265919]	95	1			T13	1		T46	1		T49	4
auto[2013265920:2147483647]	83	1			T14	2		T80	1		T81	1
auto[2147483648:2281701375]	99	1			T2	1		T80	1		T47	1
auto[2281701376:2415919103]	94	1			T79	1		T22	1		T49	1
auto[2415919104:2550136831]	93	1			T14	1		T46	1		T79	1
auto[2550136832:2684354559]	89	1			T35	1		T60	1		T53	1
auto[2684354560:2818572287]	91	1			T25	1		T66	2		T61	1
auto[2818572288:2952790015]	86	1			T80	1		T47	1		T78	1
auto[2952790016:3087007743]	97	1			T14	1		T6	1		T25	2
auto[3087007744:3221225471]	85	1			T56	1		T49	2		T27	1
auto[3221225472:3355443199]	85	1			T35	1		T25	3		T60	1
auto[3355443200:3489660927]	97	1			T25	2		T189	1		T49	3
auto[3489660928:3623878655]	105	1			T35	1		T36	1		T81	2
auto[3623878656:3758096383]	98	1			T25	2		T21	1		T49	2
auto[3758096384:3892314111]	105	1			T1	1		T46	1		T25	2
auto[3892314112:4026531839]	109	1			T13	1		T14	1		T25	5
auto[4026531840:4160749567]	90	1			T1	1		T2	1		T80	1
auto[4160749568:4294967295]	100	1			T14	2		T6	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T14	1		T49	2		T192	1
auto[0:134217727]	auto[1]	55	1			T49	1		T53	2		T68	2
auto[134217728:268435455]	auto[0]	51	1			T2	1		T179	1		T118	1
auto[134217728:268435455]	auto[1]	51	1			T49	1		T66	1		T67	2
auto[268435456:402653183]	auto[0]	36	1			T7	1		T127	1		T70	1
auto[268435456:402653183]	auto[1]	49	1			T2	1		T13	1		T14	1
auto[402653184:536870911]	auto[0]	38	1			T25	1		T49	2		T53	1
auto[402653184:536870911]	auto[1]	40	1			T22	1		T53	1		T120	1
auto[536870912:671088639]	auto[0]	54	1			T44	1		T25	1		T27	1
auto[536870912:671088639]	auto[1]	43	1			T25	1		T49	1		T324	1
auto[671088640:805306367]	auto[0]	42	1			T57	1		T75	1		T49	1
auto[671088640:805306367]	auto[1]	51	1			T1	1		T25	2		T49	2
auto[805306368:939524095]	auto[0]	43	1			T25	1		T181	1		T119	1
auto[805306368:939524095]	auto[1]	52	1			T57	1		T78	1		T49	1
auto[939524096:1073741823]	auto[0]	44	1			T25	2		T189	1		T49	1
auto[939524096:1073741823]	auto[1]	46	1			T35	1		T49	1		T37	1
auto[1073741824:1207959551]	auto[0]	47	1			T25	1		T179	1		T53	1
auto[1073741824:1207959551]	auto[1]	39	1			T25	2		T324	1		T192	1
auto[1207959552:1342177279]	auto[0]	50	1			T25	1		T53	1		T61	1
auto[1207959552:1342177279]	auto[1]	33	1			T25	2		T53	1		T62	1
auto[1342177280:1476395007]	auto[0]	37	1			T25	1		T21	1		T49	1
auto[1342177280:1476395007]	auto[1]	58	1			T1	1		T36	1		T44	1
auto[1476395008:1610612735]	auto[0]	42	1			T49	2		T70	3		T174	1
auto[1476395008:1610612735]	auto[1]	37	1			T47	1		T75	1		T16	1
auto[1610612736:1744830463]	auto[0]	52	1			T47	1		T25	2		T16	1
auto[1610612736:1744830463]	auto[1]	66	1			T14	1		T36	1		T25	1
auto[1744830464:1879048191]	auto[0]	52	1			T14	1		T25	1		T49	1
auto[1744830464:1879048191]	auto[1]	50	1			T47	1		T79	1		T26	1
auto[1879048192:2013265919]	auto[0]	53	1			T46	1		T49	3		T26	1
auto[1879048192:2013265919]	auto[1]	42	1			T13	1		T49	1		T69	1
auto[2013265920:2147483647]	auto[0]	33	1			T67	1		T395	1		T89	1
auto[2013265920:2147483647]	auto[1]	50	1			T14	2		T80	1		T81	1
auto[2147483648:2281701375]	auto[0]	42	1			T80	1		T47	1		T25	1
auto[2147483648:2281701375]	auto[1]	57	1			T2	1		T81	1		T25	2
auto[2281701376:2415919103]	auto[0]	36	1			T79	1		T22	1		T49	1
auto[2281701376:2415919103]	auto[1]	58	1			T183	1		T324	1		T68	1
auto[2415919104:2550136831]	auto[0]	43	1			T179	1		T126	1		T121	1
auto[2415919104:2550136831]	auto[1]	50	1			T14	1		T46	1		T79	1
auto[2550136832:2684354559]	auto[0]	38	1			T66	1		T70	1		T191	1
auto[2550136832:2684354559]	auto[1]	51	1			T35	1		T60	1		T53	1
auto[2684354560:2818572287]	auto[0]	42	1			T25	1		T61	1		T70	4
auto[2684354560:2818572287]	auto[1]	49	1			T66	2		T7	3		T41	1
auto[2818572288:2952790015]	auto[0]	41	1			T47	1		T79	1		T49	1
auto[2818572288:2952790015]	auto[1]	45	1			T80	1		T78	1		T126	1
auto[2952790016:3087007743]	auto[0]	48	1			T14	1		T25	2		T49	1
auto[2952790016:3087007743]	auto[1]	49	1			T6	1		T51	1		T184	1
auto[3087007744:3221225471]	auto[0]	42	1			T49	1		T53	2		T69	1
auto[3087007744:3221225471]	auto[1]	43	1			T56	1		T49	1		T27	1
auto[3221225472:3355443199]	auto[0]	40	1			T25	3		T52	1		T119	1
auto[3221225472:3355443199]	auto[1]	45	1			T35	1		T60	1		T7	1
auto[3355443200:3489660927]	auto[0]	46	1			T25	1		T49	2		T179	1
auto[3355443200:3489660927]	auto[1]	51	1			T25	1		T189	1		T49	1
auto[3489660928:3623878655]	auto[0]	52	1			T36	1		T81	1		T25	1
auto[3489660928:3623878655]	auto[1]	53	1			T35	1		T81	1		T25	1
auto[3623878656:3758096383]	auto[0]	43	1			T25	1		T21	1		T49	2
auto[3623878656:3758096383]	auto[1]	55	1			T25	1		T256	1		T66	1
auto[3758096384:3892314111]	auto[0]	42	1			T1	1		T46	1		T25	1
auto[3758096384:3892314111]	auto[1]	63	1			T25	1		T75	1		T49	2
auto[3892314112:4026531839]	auto[0]	41	1			T14	1		T25	3		T49	1
auto[3892314112:4026531839]	auto[1]	68	1			T13	1		T25	2		T21	1
auto[4026531840:4160749567]	auto[0]	44	1			T2	1		T25	1		T75	1
auto[4026531840:4160749567]	auto[1]	46	1			T1	1		T80	1		T25	1
auto[4160749568:4294967295]	auto[0]	44	1			T47	1		T61	1		T309	1
auto[4160749568:4294967295]	auto[1]	56	1			T14	2		T6	1		T44	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1407

1

T1

1

T2

3

T14

4

auto[1]

1590

1

T1

3

T2

1

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	85	1			T46	1		T80	2		T49	1
auto[134217728:268435455]	75	1			T35	1		T57	1		T25	1
auto[268435456:402653183]	108	1			T44	1		T25	1		T53	1
auto[402653184:536870911]	87	1			T14	2		T25	1		T49	1
auto[536870912:671088639]	120	1			T2	1		T35	1		T25	1
auto[671088640:805306367]	95	1			T1	1		T46	1		T56	1
auto[805306368:939524095]	96	1			T14	2		T44	1		T25	2
auto[939524096:1073741823]	104	1			T14	1		T47	2		T16	1
auto[1073741824:1207959551]	104	1			T47	2		T81	1		T49	2
auto[1207959552:1342177279]	78	1			T25	1		T22	1		T37	1
auto[1342177280:1476395007]	86	1			T35	1		T46	1		T25	2
auto[1476395008:1610612735]	93	1			T2	1		T49	1		T61	1
auto[1610612736:1744830463]	80	1			T53	1		T62	1		T66	1
auto[1744830464:1879048191]	93	1			T1	1		T6	1		T25	1
auto[1879048192:2013265919]	98	1			T44	1		T25	3		T16	1
auto[2013265920:2147483647]	102	1			T21	1		T49	2		T53	2
auto[2147483648:2281701375]	79	1			T81	1		T25	3		T179	2
auto[2281701376:2415919103]	96	1			T14	1		T44	1		T79	1
auto[2415919104:2550136831]	93	1			T14	2		T36	1		T75	1
auto[2550136832:2684354559]	87	1			T2	1		T25	4		T189	1
auto[2684354560:2818572287]	100	1			T14	1		T25	1		T49	2
auto[2818572288:2952790015]	93	1			T1	1		T25	3		T49	2
auto[2952790016:3087007743]	121	1			T80	1		T25	1		T49	2
auto[3087007744:3221225471]	97	1			T14	1		T36	1		T80	1
auto[3221225472:3355443199]	92	1			T14	1		T25	3		T22	1
auto[3355443200:3489660927]	85	1			T13	2		T79	1		T49	1
auto[3489660928:3623878655]	98	1			T35	1		T81	1		T25	3
auto[3623878656:3758096383]	85	1			T47	1		T25	2		T78	1
auto[3758096384:3892314111]	90	1			T6	1		T25	1		T75	1
auto[3892314112:4026531839]	90	1			T36	1		T81	1		T57	1
auto[4026531840:4160749567]	101	1			T2	1		T13	1		T47	1
auto[4160749568:4294967295]	86	1			T1	1		T25	4		T21	1