Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2627

1

T1

4

T2

4

T13

3

auto[1]

311

1

T44

2

T81

2

T75

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T81	1		T25	1		T78	1
auto[134217728:268435455]	92	1			T1	1		T44	1		T25	1
auto[268435456:402653183]	99	1			T2	1		T13	1		T14	1
auto[402653184:536870911]	107	1			T2	2		T36	1		T81	1
auto[536870912:671088639]	66	1			T81	1		T21	1		T119	1
auto[671088640:805306367]	97	1			T44	1		T47	1		T25	2
auto[805306368:939524095]	85	1			T14	1		T25	1		T75	1
auto[939524096:1073741823]	89	1			T1	1		T35	1		T36	1
auto[1073741824:1207959551]	103	1			T1	1		T14	1		T25	1
auto[1207959552:1342177279]	92	1			T81	1		T25	1		T75	1
auto[1342177280:1476395007]	83	1			T13	1		T35	1		T25	2
auto[1476395008:1610612735]	97	1			T80	1		T81	1		T79	1
auto[1610612736:1744830463]	113	1			T25	1		T189	1		T49	2
auto[1744830464:1879048191]	91	1			T80	1		T49	1		T37	1
auto[1879048192:2013265919]	92	1			T35	1		T80	1		T56	1
auto[2013265920:2147483647]	95	1			T14	1		T44	1		T47	1
auto[2147483648:2281701375]	94	1			T49	1		T66	1		T61	1
auto[2281701376:2415919103]	92	1			T14	1		T183	1		T256	1
auto[2415919104:2550136831]	99	1			T13	1		T14	1		T80	1
auto[2550136832:2684354559]	84	1			T14	1		T25	2		T79	1
auto[2684354560:2818572287]	94	1			T1	1		T14	1		T81	1
auto[2818572288:2952790015]	109	1			T36	1		T75	1		T78	1
auto[2952790016:3087007743]	76	1			T78	2		T49	1		T27	1
auto[3087007744:3221225471]	89	1			T14	1		T44	1		T81	1
auto[3221225472:3355443199]	79	1			T49	1		T51	1		T53	1
auto[3355443200:3489660927]	85	1			T14	1		T46	1		T44	1
auto[3489660928:3623878655]	74	1			T35	1		T44	1		T75	1
auto[3623878656:3758096383]	91	1			T57	1		T22	1		T49	1
auto[3758096384:3892314111]	102	1			T25	1		T49	1		T53	1
auto[3892314112:4026531839]	83	1			T25	1		T49	1		T37	1
auto[4026531840:4160749567]	75	1			T25	4		T180	1		T66	3
auto[4160749568:4294967295]	121	1			T2	1		T14	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	80	1			T81	1		T25	1		T49	2
auto[0:134217727]	auto[1]	10	1			T78	1		T300	1		T263	2
auto[134217728:268435455]	auto[0]	79	1			T1	1		T44	1		T25	1
auto[134217728:268435455]	auto[1]	13	1			T239	1		T278	2		T294	1
auto[268435456:402653183]	auto[0]	90	1			T2	1		T13	1		T14	1
auto[268435456:402653183]	auto[1]	9	1			T239	1		T257	1		T219	2
auto[402653184:536870911]	auto[0]	99	1			T2	2		T36	1		T81	1
auto[402653184:536870911]	auto[1]	8	1			T278	1		T294	1		T216	1
auto[536870912:671088639]	auto[0]	61	1			T81	1		T21	1		T119	1
auto[536870912:671088639]	auto[1]	5	1			T257	1		T254	1		T354	1
auto[671088640:805306367]	auto[0]	91	1			T44	1		T47	1		T25	2
auto[671088640:805306367]	auto[1]	6	1			T218	1		T388	1		T254	1
auto[805306368:939524095]	auto[0]	82	1			T14	1		T25	1		T49	1
auto[805306368:939524095]	auto[1]	3	1			T75	1		T276	1		T406	1
auto[939524096:1073741823]	auto[0]	75	1			T1	1		T35	1		T36	1
auto[939524096:1073741823]	auto[1]	14	1			T248	2		T294	2		T218	2
auto[1073741824:1207959551]	auto[0]	92	1			T1	1		T14	1		T25	1
auto[1073741824:1207959551]	auto[1]	11	1			T126	1		T276	1		T168	1
auto[1207959552:1342177279]	auto[0]	77	1			T25	1		T21	1		T16	1
auto[1207959552:1342177279]	auto[1]	15	1			T81	1		T75	1		T126	1
auto[1342177280:1476395007]	auto[0]	74	1			T13	1		T35	1		T25	2
auto[1342177280:1476395007]	auto[1]	9	1			T216	1		T218	2		T254	2
auto[1476395008:1610612735]	auto[0]	86	1			T80	1		T81	1		T79	1
auto[1476395008:1610612735]	auto[1]	11	1			T216	2		T300	2		T217	1
auto[1610612736:1744830463]	auto[0]	99	1			T25	1		T189	1		T49	2
auto[1610612736:1744830463]	auto[1]	14	1			T278	1		T295	1		T218	2
auto[1744830464:1879048191]	auto[0]	82	1			T80	1		T49	1		T37	1
auto[1744830464:1879048191]	auto[1]	9	1			T248	2		T278	1		T217	1
auto[1879048192:2013265919]	auto[0]	83	1			T35	1		T80	1		T56	1
auto[1879048192:2013265919]	auto[1]	9	1			T248	1		T254	1		T263	1
auto[2013265920:2147483647]	auto[0]	81	1			T14	1		T44	1		T47	1
auto[2013265920:2147483647]	auto[1]	14	1			T248	1		T276	1		T294	1
auto[2147483648:2281701375]	auto[0]	82	1			T49	1		T66	1		T61	1
auto[2147483648:2281701375]	auto[1]	12	1			T168	1		T218	1		T254	1
auto[2281701376:2415919103]	auto[0]	87	1			T14	1		T183	1		T256	1
auto[2281701376:2415919103]	auto[1]	5	1			T248	1		T254	1		T405	1
auto[2415919104:2550136831]	auto[0]	87	1			T13	1		T14	1		T80	1
auto[2415919104:2550136831]	auto[1]	12	1			T239	1		T248	1		T294	1
auto[2550136832:2684354559]	auto[0]	78	1			T14	1		T25	2		T79	1
auto[2550136832:2684354559]	auto[1]	6	1			T216	2		T218	1		T300	1
auto[2684354560:2818572287]	auto[0]	87	1			T1	1		T14	1		T81	1
auto[2684354560:2818572287]	auto[1]	7	1			T276	1		T218	1		T388	1
auto[2818572288:2952790015]	auto[0]	103	1			T36	1		T75	1		T79	1
auto[2818572288:2952790015]	auto[1]	6	1			T78	1		T276	1		T294	1
auto[2952790016:3087007743]	auto[0]	69	1			T49	1		T27	1		T66	1
auto[2952790016:3087007743]	auto[1]	7	1			T78	2		T295	1		T216	1
auto[3087007744:3221225471]	auto[0]	77	1			T14	1		T44	1		T25	3
auto[3087007744:3221225471]	auto[1]	12	1			T81	1		T75	1		T276	1
auto[3221225472:3355443199]	auto[0]	68	1			T49	1		T51	1		T53	1
auto[3221225472:3355443199]	auto[1]	11	1			T248	1		T168	1		T388	1
auto[3355443200:3489660927]	auto[0]	77	1			T14	1		T46	1		T25	2
auto[3355443200:3489660927]	auto[1]	8	1			T44	1		T216	2		T257	1
auto[3489660928:3623878655]	auto[0]	64	1			T35	1		T75	1		T21	1
auto[3489660928:3623878655]	auto[1]	10	1			T44	1		T248	2		T276	1
auto[3623878656:3758096383]	auto[0]	77	1			T57	1		T22	1		T49	1
auto[3623878656:3758096383]	auto[1]	14	1			T294	1		T168	2		T257	1
auto[3758096384:3892314111]	auto[0]	89	1			T25	1		T49	1		T53	1
auto[3758096384:3892314111]	auto[1]	13	1			T248	1		T168	1		T257	2
auto[3892314112:4026531839]	auto[0]	77	1			T25	1		T49	1		T37	1
auto[3892314112:4026531839]	auto[1]	6	1			T294	1		T168	1		T404	1
auto[4026531840:4160749567]	auto[0]	71	1			T25	4		T180	1		T66	3
auto[4026531840:4160749567]	auto[1]	4	1			T257	1		T217	1		T390	1
auto[4160749568:4294967295]	auto[0]	103	1			T2	1		T14	1		T49	1
auto[4160749568:4294967295]	auto[1]	18	1			T239	1		T294	3		T257	1