Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.34 99.00 97.99 98.26 97.67 98.93 98.41 91.14


Total test records in report: 1087
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1005 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4218035479 Jun 23 05:01:51 PM PDT 24 Jun 23 05:01:54 PM PDT 24 479478209 ps
T1006 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.205787359 Jun 23 05:01:49 PM PDT 24 Jun 23 05:01:50 PM PDT 24 14967874 ps
T1007 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2039732105 Jun 23 05:01:30 PM PDT 24 Jun 23 05:01:31 PM PDT 24 30635015 ps
T1008 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3156170379 Jun 23 05:02:06 PM PDT 24 Jun 23 05:02:07 PM PDT 24 23035396 ps
T1009 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1214763893 Jun 23 05:01:37 PM PDT 24 Jun 23 05:01:39 PM PDT 24 54940357 ps
T1010 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3772913784 Jun 23 05:01:08 PM PDT 24 Jun 23 05:01:09 PM PDT 24 17535588 ps
T1011 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1730570063 Jun 23 05:01:45 PM PDT 24 Jun 23 05:01:46 PM PDT 24 9145654 ps
T1012 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1426683323 Jun 23 05:01:59 PM PDT 24 Jun 23 05:02:01 PM PDT 24 22905338 ps
T1013 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1000072142 Jun 23 05:01:50 PM PDT 24 Jun 23 05:01:53 PM PDT 24 226962806 ps
T1014 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.845104533 Jun 23 05:02:11 PM PDT 24 Jun 23 05:02:12 PM PDT 24 17659634 ps
T1015 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3031312252 Jun 23 05:02:13 PM PDT 24 Jun 23 05:02:14 PM PDT 24 13101424 ps
T1016 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1792535470 Jun 23 05:01:51 PM PDT 24 Jun 23 05:01:52 PM PDT 24 15165027 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2144060438 Jun 23 05:01:38 PM PDT 24 Jun 23 05:01:40 PM PDT 24 27746301 ps
T1018 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1596245148 Jun 23 05:02:12 PM PDT 24 Jun 23 05:02:14 PM PDT 24 14045310 ps
T1019 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.141782836 Jun 23 05:01:46 PM PDT 24 Jun 23 05:01:47 PM PDT 24 24989001 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.287707327 Jun 23 05:01:30 PM PDT 24 Jun 23 05:01:33 PM PDT 24 30923976 ps
T1021 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1424858849 Jun 23 05:01:17 PM PDT 24 Jun 23 05:01:22 PM PDT 24 78859149 ps
T1022 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3276887195 Jun 23 05:01:36 PM PDT 24 Jun 23 05:01:40 PM PDT 24 55421592 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4173019783 Jun 23 05:01:49 PM PDT 24 Jun 23 05:01:50 PM PDT 24 123017857 ps
T1024 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2180132482 Jun 23 05:01:14 PM PDT 24 Jun 23 05:01:18 PM PDT 24 353325202 ps
T1025 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2999371362 Jun 23 05:01:43 PM PDT 24 Jun 23 05:01:45 PM PDT 24 59281743 ps
T146 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2963864244 Jun 23 05:01:32 PM PDT 24 Jun 23 05:01:37 PM PDT 24 592825941 ps
T1026 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4006211186 Jun 23 05:01:32 PM PDT 24 Jun 23 05:01:34 PM PDT 24 10338103 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1440637815 Jun 23 05:01:13 PM PDT 24 Jun 23 05:01:17 PM PDT 24 147265907 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2500712232 Jun 23 05:01:30 PM PDT 24 Jun 23 05:01:35 PM PDT 24 663468230 ps
T1029 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1639713986 Jun 23 05:01:12 PM PDT 24 Jun 23 05:01:15 PM PDT 24 1153583370 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1505532676 Jun 23 05:01:17 PM PDT 24 Jun 23 05:01:22 PM PDT 24 529861120 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2653499641 Jun 23 05:01:14 PM PDT 24 Jun 23 05:01:16 PM PDT 24 175216699 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2327548766 Jun 23 05:01:30 PM PDT 24 Jun 23 05:01:31 PM PDT 24 176636758 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3462215703 Jun 23 05:01:52 PM PDT 24 Jun 23 05:02:06 PM PDT 24 402713907 ps
T1034 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2401223967 Jun 23 05:01:58 PM PDT 24 Jun 23 05:02:00 PM PDT 24 188348553 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.297482680 Jun 23 05:01:11 PM PDT 24 Jun 23 05:01:16 PM PDT 24 296607169 ps
T1036 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4283969069 Jun 23 05:02:05 PM PDT 24 Jun 23 05:02:06 PM PDT 24 15012306 ps
T149 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1556424702 Jun 23 05:01:11 PM PDT 24 Jun 23 05:01:15 PM PDT 24 128446206 ps
T152 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.778323830 Jun 23 05:02:01 PM PDT 24 Jun 23 05:02:07 PM PDT 24 341881231 ps
T1037 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1354774078 Jun 23 05:01:42 PM PDT 24 Jun 23 05:01:43 PM PDT 24 22960876 ps
T1038 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.670052273 Jun 23 05:02:05 PM PDT 24 Jun 23 05:02:06 PM PDT 24 10924899 ps
T1039 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1444910018 Jun 23 05:01:13 PM PDT 24 Jun 23 05:01:14 PM PDT 24 149577572 ps
T1040 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1657721508 Jun 23 05:01:37 PM PDT 24 Jun 23 05:01:40 PM PDT 24 43211604 ps
T1041 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.215403400 Jun 23 05:02:13 PM PDT 24 Jun 23 05:02:14 PM PDT 24 30042841 ps
T1042 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.653204969 Jun 23 05:02:10 PM PDT 24 Jun 23 05:02:11 PM PDT 24 78145675 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4153149030 Jun 23 05:01:32 PM PDT 24 Jun 23 05:01:39 PM PDT 24 130018795 ps
T1044 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2214475706 Jun 23 05:02:11 PM PDT 24 Jun 23 05:02:12 PM PDT 24 194919618 ps
T1045 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2851408743 Jun 23 05:02:07 PM PDT 24 Jun 23 05:02:08 PM PDT 24 63348800 ps
T1046 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1523504515 Jun 23 05:01:59 PM PDT 24 Jun 23 05:02:08 PM PDT 24 574389663 ps
T1047 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3680536140 Jun 23 05:01:30 PM PDT 24 Jun 23 05:01:32 PM PDT 24 36937517 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3919500281 Jun 23 05:01:35 PM PDT 24 Jun 23 05:01:38 PM PDT 24 31389310 ps
T1049 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.308638971 Jun 23 05:01:32 PM PDT 24 Jun 23 05:01:34 PM PDT 24 400178636 ps
T1050 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2332199874 Jun 23 05:01:51 PM PDT 24 Jun 23 05:01:53 PM PDT 24 22840345 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2636464010 Jun 23 05:01:43 PM PDT 24 Jun 23 05:01:48 PM PDT 24 144622915 ps
T1052 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2223845954 Jun 23 05:01:50 PM PDT 24 Jun 23 05:01:59 PM PDT 24 146148528 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1554179368 Jun 23 05:01:59 PM PDT 24 Jun 23 05:02:01 PM PDT 24 103795320 ps
T1054 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2083041551 Jun 23 05:01:45 PM PDT 24 Jun 23 05:01:48 PM PDT 24 45188276 ps
T1055 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4104358275 Jun 23 05:02:12 PM PDT 24 Jun 23 05:02:13 PM PDT 24 45890712 ps
T1056 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2324996203 Jun 23 05:01:35 PM PDT 24 Jun 23 05:01:39 PM PDT 24 95620140 ps
T156 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.638427802 Jun 23 05:01:59 PM PDT 24 Jun 23 05:02:05 PM PDT 24 961147814 ps
T1057 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2389525845 Jun 23 05:02:06 PM PDT 24 Jun 23 05:02:08 PM PDT 24 12882669 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3803190648 Jun 23 05:01:12 PM PDT 24 Jun 23 05:01:13 PM PDT 24 14904363 ps
T1059 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2064482956 Jun 23 05:01:47 PM PDT 24 Jun 23 05:01:50 PM PDT 24 292402461 ps
T1060 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.831678705 Jun 23 05:01:13 PM PDT 24 Jun 23 05:01:21 PM PDT 24 131916930 ps
T1061 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.578260956 Jun 23 05:02:11 PM PDT 24 Jun 23 05:02:12 PM PDT 24 29817250 ps
T1062 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.486069883 Jun 23 05:01:35 PM PDT 24 Jun 23 05:01:39 PM PDT 24 215967360 ps
T1063 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3893734903 Jun 23 05:01:32 PM PDT 24 Jun 23 05:01:34 PM PDT 24 27762459 ps
T1064 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.512661676 Jun 23 05:01:55 PM PDT 24 Jun 23 05:01:58 PM PDT 24 499795701 ps
T1065 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3667795982 Jun 23 05:01:56 PM PDT 24 Jun 23 05:01:58 PM PDT 24 252421303 ps
T1066 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3756896596 Jun 23 05:01:54 PM PDT 24 Jun 23 05:01:56 PM PDT 24 37200546 ps
T1067 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1748684247 Jun 23 05:02:01 PM PDT 24 Jun 23 05:02:06 PM PDT 24 632674943 ps
T1068 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1375546637 Jun 23 05:01:12 PM PDT 24 Jun 23 05:01:14 PM PDT 24 34137074 ps
T1069 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.205334920 Jun 23 05:02:00 PM PDT 24 Jun 23 05:02:02 PM PDT 24 39389463 ps
T1070 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2395689288 Jun 23 05:01:48 PM PDT 24 Jun 23 05:01:50 PM PDT 24 30175697 ps
T1071 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1385245530 Jun 23 05:02:08 PM PDT 24 Jun 23 05:02:09 PM PDT 24 17010500 ps
T1072 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2495452445 Jun 23 05:02:11 PM PDT 24 Jun 23 05:02:12 PM PDT 24 9553186 ps
T1073 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.565093185 Jun 23 05:01:13 PM PDT 24 Jun 23 05:01:15 PM PDT 24 161339959 ps
T1074 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3400836109 Jun 23 05:01:54 PM PDT 24 Jun 23 05:01:58 PM PDT 24 109520673 ps
T1075 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4133288101 Jun 23 05:01:38 PM PDT 24 Jun 23 05:01:42 PM PDT 24 448816203 ps
T1076 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.128014746 Jun 23 05:01:36 PM PDT 24 Jun 23 05:01:38 PM PDT 24 42307121 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.473044003 Jun 23 05:01:49 PM PDT 24 Jun 23 05:01:51 PM PDT 24 180263880 ps
T1078 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.104390418 Jun 23 05:01:56 PM PDT 24 Jun 23 05:02:04 PM PDT 24 602496954 ps
T1079 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2059555745 Jun 23 05:01:31 PM PDT 24 Jun 23 05:01:34 PM PDT 24 250892104 ps
T1080 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2656528917 Jun 23 05:01:12 PM PDT 24 Jun 23 05:01:29 PM PDT 24 1288123344 ps
T1081 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.71408111 Jun 23 05:02:11 PM PDT 24 Jun 23 05:02:12 PM PDT 24 10669436 ps
T1082 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.952900659 Jun 23 05:01:50 PM PDT 24 Jun 23 05:01:51 PM PDT 24 23855078 ps
T1083 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.555235305 Jun 23 05:01:18 PM PDT 24 Jun 23 05:01:21 PM PDT 24 314475197 ps
T1084 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1061088180 Jun 23 05:01:35 PM PDT 24 Jun 23 05:01:39 PM PDT 24 191217683 ps
T1085 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1856467140 Jun 23 05:02:00 PM PDT 24 Jun 23 05:02:02 PM PDT 24 30125337 ps
T1086 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2587993204 Jun 23 05:01:34 PM PDT 24 Jun 23 05:01:36 PM PDT 24 18322622 ps
T1087 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3511708004 Jun 23 05:01:55 PM PDT 24 Jun 23 05:01:57 PM PDT 24 41965802 ps

Test location /workspace/coverage/default/0.keymgr_stress_all.152082661
Short name T14
Test name
Test status
Simulation time 1400713644 ps
CPU time 33.53 seconds
Started Jun 23 05:02:55 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 222484 kb
Host smart-45794db3-3e9b-445f-b83d-dec0815cf0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152082661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.152082661
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3915522471
Short name T49
Test name
Test status
Simulation time 8944068028 ps
CPU time 57.33 seconds
Started Jun 23 05:05:39 PM PDT 24
Finished Jun 23 05:06:37 PM PDT 24
Peak memory 221988 kb
Host smart-500ef22a-5310-40c0-8b0d-75e415d9644b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915522471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3915522471
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2427252311
Short name T7
Test name
Test status
Simulation time 21462377781 ps
CPU time 315.41 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:08:18 PM PDT 24
Peak memory 231708 kb
Host smart-ddffe552-b27e-42dc-9903-c55ee81c5d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427252311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2427252311
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.418283512
Short name T9
Test name
Test status
Simulation time 419505577 ps
CPU time 5.02 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 233488 kb
Host smart-3f939d2f-20ea-4bb6-b591-b2e8558a92ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418283512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.418283512
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.475653147
Short name T61
Test name
Test status
Simulation time 445486332 ps
CPU time 18.33 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:03:21 PM PDT 24
Peak memory 222708 kb
Host smart-26dbbfc5-1826-4329-85b3-3e0cdce7ca18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475653147 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.475653147
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1815967133
Short name T115
Test name
Test status
Simulation time 2838962108 ps
CPU time 25.32 seconds
Started Jun 23 05:03:34 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 222696 kb
Host smart-c0678f84-2a72-4bf1-b94c-9716234d3279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815967133 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1815967133
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1000567324
Short name T66
Test name
Test status
Simulation time 1458254567 ps
CPU time 17.2 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:03:20 PM PDT 24
Peak memory 217312 kb
Host smart-19e1e713-174e-4e49-8049-ece2ac875841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000567324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1000567324
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.14122106
Short name T26
Test name
Test status
Simulation time 1504921380 ps
CPU time 19.78 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 214732 kb
Host smart-0d772129-2d4a-4026-aa32-805df0b822ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14122106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.14122106
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3447673741
Short name T107
Test name
Test status
Simulation time 1538897576 ps
CPU time 7.99 seconds
Started Jun 23 05:01:45 PM PDT 24
Finished Jun 23 05:01:54 PM PDT 24
Peak memory 214544 kb
Host smart-de06c33c-b0a2-40fc-b8c9-ae89a7b21d38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447673741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3447673741
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1167024795
Short name T216
Test name
Test status
Simulation time 618554698 ps
CPU time 32.7 seconds
Started Jun 23 05:05:20 PM PDT 24
Finished Jun 23 05:05:53 PM PDT 24
Peak memory 215012 kb
Host smart-5dc6eb3e-80c1-44de-82c0-fbafb8761c01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167024795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1167024795
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1940094821
Short name T25
Test name
Test status
Simulation time 4030037810 ps
CPU time 51.37 seconds
Started Jun 23 05:03:43 PM PDT 24
Finished Jun 23 05:04:36 PM PDT 24
Peak memory 216052 kb
Host smart-efa7e22e-44b3-432c-bca1-6164e69625c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940094821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1940094821
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.768739008
Short name T294
Test name
Test status
Simulation time 268165792 ps
CPU time 14.37 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 214324 kb
Host smart-7669d00c-b3bb-4ed1-a0c3-a72e05b67612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=768739008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.768739008
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3554894017
Short name T83
Test name
Test status
Simulation time 7337116667 ps
CPU time 11.56 seconds
Started Jun 23 05:04:57 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 214408 kb
Host smart-904868d6-7117-4dab-88f6-6067e17da24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554894017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3554894017
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1108880611
Short name T389
Test name
Test status
Simulation time 3276148150 ps
CPU time 37.69 seconds
Started Jun 23 05:03:05 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 215360 kb
Host smart-98f686f8-b650-404a-b7c4-2d593a605feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108880611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1108880611
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.748515700
Short name T67
Test name
Test status
Simulation time 1664531470 ps
CPU time 16.96 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 222580 kb
Host smart-edcb8ada-b657-4cf6-a0d7-31c80b9ef65c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748515700 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.748515700
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1793993381
Short name T388
Test name
Test status
Simulation time 2187090444 ps
CPU time 17.27 seconds
Started Jun 23 05:02:58 PM PDT 24
Finished Jun 23 05:03:16 PM PDT 24
Peak memory 214368 kb
Host smart-6165713b-580f-4ada-822d-2e464df77404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793993381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1793993381
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3018117657
Short name T53
Test name
Test status
Simulation time 2698161674 ps
CPU time 20.56 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 222472 kb
Host smart-bc0e6935-cb0b-40d0-8353-f2db89562d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018117657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3018117657
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.48068389
Short name T37
Test name
Test status
Simulation time 92754823 ps
CPU time 4.67 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 214264 kb
Host smart-d484c55c-0028-4222-9e12-110d97103711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48068389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.48068389
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3081383277
Short name T18
Test name
Test status
Simulation time 143342615 ps
CPU time 2.14 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 217500 kb
Host smart-3ca3a65f-87ed-4fe8-8ea6-8dc892523373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081383277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3081383277
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.430035297
Short name T193
Test name
Test status
Simulation time 1135587672 ps
CPU time 43.81 seconds
Started Jun 23 05:03:52 PM PDT 24
Finished Jun 23 05:04:37 PM PDT 24
Peak memory 222412 kb
Host smart-521ba589-aaec-469b-be83-fc5e1854b3fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430035297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.430035297
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.81214710
Short name T257
Test name
Test status
Simulation time 707946479 ps
CPU time 4.61 seconds
Started Jun 23 05:04:39 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 215260 kb
Host smart-372c8a00-2a14-4a6f-af5a-0b0ebb225213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81214710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.81214710
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.176057749
Short name T406
Test name
Test status
Simulation time 1103186998 ps
CPU time 59.06 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 215028 kb
Host smart-8798ea22-18db-4ee2-98bd-42dfb8e5343a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176057749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.176057749
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2075269202
Short name T287
Test name
Test status
Simulation time 149692989 ps
CPU time 4.47 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 221072 kb
Host smart-7dea46f0-1004-467c-b5d3-37e55e43c4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075269202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2075269202
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2542102876
Short name T241
Test name
Test status
Simulation time 68693479 ps
CPU time 2.59 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:18 PM PDT 24
Peak memory 214316 kb
Host smart-d19e8bb2-08ae-4e8c-a8eb-44e2ea8a7c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542102876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2542102876
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.567982095
Short name T134
Test name
Test status
Simulation time 145011310 ps
CPU time 3.31 seconds
Started Jun 23 05:03:55 PM PDT 24
Finished Jun 23 05:03:59 PM PDT 24
Peak memory 218160 kb
Host smart-2e187a53-f09a-4362-a458-64df7d75b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567982095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.567982095
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3642180675
Short name T90
Test name
Test status
Simulation time 118827486 ps
CPU time 4.77 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 222360 kb
Host smart-ab269fdc-5cd3-4807-a1db-e120c48212b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642180675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3642180675
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1852747714
Short name T211
Test name
Test status
Simulation time 263323335 ps
CPU time 3.19 seconds
Started Jun 23 05:02:55 PM PDT 24
Finished Jun 23 05:02:59 PM PDT 24
Peak memory 209356 kb
Host smart-8f98a1c5-44bb-4384-ba4b-10dc6b0d2804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852747714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1852747714
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3166466917
Short name T63
Test name
Test status
Simulation time 654473148 ps
CPU time 24.26 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 215140 kb
Host smart-11c5cbbb-13d8-469d-a169-49da4e8c9054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166466917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3166466917
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.246525485
Short name T254
Test name
Test status
Simulation time 1086079431 ps
CPU time 14.63 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 214792 kb
Host smart-ef475024-c20c-4361-ad39-cbdc656c013f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246525485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.246525485
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3027274959
Short name T108
Test name
Test status
Simulation time 306675109 ps
CPU time 4.72 seconds
Started Jun 23 05:01:44 PM PDT 24
Finished Jun 23 05:01:49 PM PDT 24
Peak memory 214412 kb
Host smart-1ba8f771-1a7c-4bc9-98aa-0673c7bf216b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027274959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3027274959
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.309164186
Short name T154
Test name
Test status
Simulation time 197153163 ps
CPU time 1.51 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:53 PM PDT 24
Peak memory 209912 kb
Host smart-3b84d34d-db5e-4050-a869-415242c42b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309164186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.309164186
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2072594247
Short name T70
Test name
Test status
Simulation time 402321913 ps
CPU time 18.47 seconds
Started Jun 23 05:04:09 PM PDT 24
Finished Jun 23 05:04:27 PM PDT 24
Peak memory 222124 kb
Host smart-d2b50f1d-4357-4c00-a458-30296f5774bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072594247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2072594247
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3651149397
Short name T318
Test name
Test status
Simulation time 264320470 ps
CPU time 4.18 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 215084 kb
Host smart-b7af3c79-9dfa-417d-ad91-d84bc67028a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651149397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3651149397
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3759751545
Short name T140
Test name
Test status
Simulation time 350349076 ps
CPU time 5.25 seconds
Started Jun 23 05:01:06 PM PDT 24
Finished Jun 23 05:01:11 PM PDT 24
Peak memory 215644 kb
Host smart-e3075a45-d28d-4d49-8626-b28a772bbb40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759751545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3759751545
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1484159990
Short name T100
Test name
Test status
Simulation time 64187535 ps
CPU time 0.75 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:09 PM PDT 24
Peak memory 205772 kb
Host smart-8ff1f5e4-2d00-4d7b-a1a5-8970cafb25b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484159990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1484159990
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1753034313
Short name T391
Test name
Test status
Simulation time 97259191 ps
CPU time 5.16 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 214580 kb
Host smart-edbf47d2-c48a-4017-bb97-b8adb4c6a61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753034313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1753034313
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1987128449
Short name T48
Test name
Test status
Simulation time 1949422742 ps
CPU time 45.83 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:04:06 PM PDT 24
Peak memory 222448 kb
Host smart-8613e8e1-de3f-4aa6-bae5-f05794d4dd6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987128449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1987128449
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4043069180
Short name T127
Test name
Test status
Simulation time 13386831285 ps
CPU time 117.26 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:06:39 PM PDT 24
Peak memory 220000 kb
Host smart-b55b997e-72ad-4054-80bc-04ccaf818054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043069180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4043069180
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2146162810
Short name T299
Test name
Test status
Simulation time 318115739 ps
CPU time 5.33 seconds
Started Jun 23 05:05:28 PM PDT 24
Finished Jun 23 05:05:34 PM PDT 24
Peak memory 214244 kb
Host smart-aeec232b-4651-4a33-97e7-2dd5300f8c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146162810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2146162810
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3531722062
Short name T151
Test name
Test status
Simulation time 354513575 ps
CPU time 5.16 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:36 PM PDT 24
Peak memory 215416 kb
Host smart-35a94bff-ba8e-4b65-a32d-98c9bf9f3c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531722062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3531722062
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3671461654
Short name T203
Test name
Test status
Simulation time 1414376352 ps
CPU time 18.23 seconds
Started Jun 23 05:04:02 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 216756 kb
Host smart-6aedda21-c034-4986-82df-fa0a6326894b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671461654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3671461654
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3682385153
Short name T331
Test name
Test status
Simulation time 71819342 ps
CPU time 2.58 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:26 PM PDT 24
Peak memory 214128 kb
Host smart-e872c3db-ffa5-4266-a8ff-8cfffe1fb333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682385153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3682385153
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2617343246
Short name T255
Test name
Test status
Simulation time 987117180 ps
CPU time 40.26 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:05:33 PM PDT 24
Peak memory 220712 kb
Host smart-90eb7df7-da04-4d4a-bc76-d96c2c4a9493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617343246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2617343246
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2422154146
Short name T142
Test name
Test status
Simulation time 315094816 ps
CPU time 10.49 seconds
Started Jun 23 05:01:43 PM PDT 24
Finished Jun 23 05:01:54 PM PDT 24
Peak memory 214084 kb
Host smart-92357861-5e32-417a-ac50-06b909904f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422154146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2422154146
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1242041218
Short name T754
Test name
Test status
Simulation time 180361874 ps
CPU time 2.9 seconds
Started Jun 23 05:04:19 PM PDT 24
Finished Jun 23 05:04:23 PM PDT 24
Peak memory 222440 kb
Host smart-62a74351-843b-4618-b966-ad9cda9dce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242041218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1242041218
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1479566552
Short name T305
Test name
Test status
Simulation time 728473355 ps
CPU time 4.08 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 220672 kb
Host smart-57ba02e9-9474-4513-9755-c15b8b5b6756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479566552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1479566552
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2542048518
Short name T168
Test name
Test status
Simulation time 1323290501 ps
CPU time 62.96 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 214528 kb
Host smart-630553b3-3e29-4cbc-ae49-f806baddc420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542048518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2542048518
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3575353094
Short name T322
Test name
Test status
Simulation time 175307758 ps
CPU time 3.35 seconds
Started Jun 23 05:05:39 PM PDT 24
Finished Jun 23 05:05:42 PM PDT 24
Peak memory 208736 kb
Host smart-7e3f4f61-49da-4bcb-ac25-125e296a64c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575353094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3575353094
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3426598234
Short name T150
Test name
Test status
Simulation time 353190186 ps
CPU time 4.1 seconds
Started Jun 23 05:01:43 PM PDT 24
Finished Jun 23 05:01:48 PM PDT 24
Peak memory 215416 kb
Host smart-849e1200-e958-4058-bb55-af7a2303e3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426598234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3426598234
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.638427802
Short name T156
Test name
Test status
Simulation time 961147814 ps
CPU time 6.35 seconds
Started Jun 23 05:01:59 PM PDT 24
Finished Jun 23 05:02:05 PM PDT 24
Peak memory 214056 kb
Host smart-d096adee-1931-4f49-a548-c8b9b676887d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638427802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.638427802
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2098506536
Short name T11
Test name
Test status
Simulation time 1676973144 ps
CPU time 13.73 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:03:16 PM PDT 24
Peak memory 238964 kb
Host smart-8a20da0d-06ec-4c99-a6f6-d4040954ceed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098506536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2098506536
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.820682251
Short name T135
Test name
Test status
Simulation time 289537212 ps
CPU time 2.52 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 218292 kb
Host smart-d87ea471-0243-4ce2-8745-17d3abe34e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820682251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.820682251
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1817001969
Short name T283
Test name
Test status
Simulation time 500785924 ps
CPU time 10.56 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:03:07 PM PDT 24
Peak memory 218356 kb
Host smart-8e9b8e69-a34f-4022-b2ec-f48749389140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817001969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1817001969
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4167763173
Short name T307
Test name
Test status
Simulation time 764530371 ps
CPU time 3.56 seconds
Started Jun 23 05:03:52 PM PDT 24
Finished Jun 23 05:03:56 PM PDT 24
Peak memory 220096 kb
Host smart-02fe5039-41f3-453f-9c47-c0693daa3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167763173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4167763173
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2319498217
Short name T86
Test name
Test status
Simulation time 170607901 ps
CPU time 4.43 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:04:00 PM PDT 24
Peak memory 214212 kb
Host smart-26f007fe-7e19-4995-abad-e718a5d6664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319498217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2319498217
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3286691320
Short name T215
Test name
Test status
Simulation time 455166637 ps
CPU time 22.01 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 216464 kb
Host smart-eef7848a-399b-4b68-aa7d-e0699db3097b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286691320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3286691320
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.283932721
Short name T696
Test name
Test status
Simulation time 133578927 ps
CPU time 3.04 seconds
Started Jun 23 05:04:31 PM PDT 24
Finished Jun 23 05:04:34 PM PDT 24
Peak memory 210712 kb
Host smart-f7e13f74-82d6-4df6-9088-3a8e9eca3d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283932721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.283932721
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2326173298
Short name T834
Test name
Test status
Simulation time 471721087 ps
CPU time 9.1 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 209332 kb
Host smart-24876390-d1a6-4837-9d38-db985694537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326173298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2326173298
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.887325608
Short name T176
Test name
Test status
Simulation time 10785583464 ps
CPU time 31.99 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:05:23 PM PDT 24
Peak memory 215144 kb
Host smart-eb1c28ae-dc88-4f80-a6d1-d45c86a66dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887325608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.887325608
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2466363074
Short name T207
Test name
Test status
Simulation time 357277154 ps
CPU time 6.71 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 222532 kb
Host smart-bfb0dbf9-cd31-4c3e-be70-2f65ae6a63ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466363074 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2466363074
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3287097739
Short name T133
Test name
Test status
Simulation time 106134530 ps
CPU time 5.42 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:04 PM PDT 24
Peak memory 218248 kb
Host smart-cb262e01-ce70-4715-b228-02c0eb464b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287097739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3287097739
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.86720694
Short name T136
Test name
Test status
Simulation time 441533021 ps
CPU time 1.8 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:37 PM PDT 24
Peak memory 217224 kb
Host smart-5c769f3c-4d19-46f5-b29a-cfb3f0ec6c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86720694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.86720694
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.174582176
Short name T137
Test name
Test status
Simulation time 167402782 ps
CPU time 2.13 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 217096 kb
Host smart-5f899295-6a5c-4590-9d92-06c876755895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174582176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.174582176
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2432116557
Short name T44
Test name
Test status
Simulation time 113883692 ps
CPU time 2.4 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 215104 kb
Host smart-beb120f2-d7dd-46bb-b73e-f7992b9997d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432116557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2432116557
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2683945252
Short name T19
Test name
Test status
Simulation time 9178116989 ps
CPU time 37.73 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:04:18 PM PDT 24
Peak memory 214308 kb
Host smart-2ef003b7-bfef-4103-ac4e-25df9b9b184f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683945252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2683945252
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.603035867
Short name T404
Test name
Test status
Simulation time 102263826 ps
CPU time 5.8 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:47 PM PDT 24
Peak memory 214512 kb
Host smart-b78d10d8-2d4f-4d7d-a6d6-be4f878e7133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603035867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.603035867
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2087510605
Short name T209
Test name
Test status
Simulation time 972135399 ps
CPU time 38.67 seconds
Started Jun 23 05:04:03 PM PDT 24
Finished Jun 23 05:04:42 PM PDT 24
Peak memory 215188 kb
Host smart-c8c031fc-08c3-400d-838c-a4830980a78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087510605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2087510605
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2974178768
Short name T512
Test name
Test status
Simulation time 1226406956 ps
CPU time 6.47 seconds
Started Jun 23 05:04:09 PM PDT 24
Finished Jun 23 05:04:16 PM PDT 24
Peak memory 208512 kb
Host smart-5b4c495d-3752-45fc-9f7c-6e55f7c3303b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974178768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2974178768
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.92879638
Short name T354
Test name
Test status
Simulation time 438176612 ps
CPU time 5.09 seconds
Started Jun 23 05:05:12 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 214300 kb
Host smart-5c18ccde-d5a8-42a6-a9b0-a614a809391d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92879638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.92879638
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3664335567
Short name T21
Test name
Test status
Simulation time 294508327 ps
CPU time 10.05 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 214188 kb
Host smart-d04c78eb-b7cf-40da-8858-c58c3f30e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664335567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3664335567
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2995884935
Short name T235
Test name
Test status
Simulation time 1406431410 ps
CPU time 29.23 seconds
Started Jun 23 05:05:46 PM PDT 24
Finished Jun 23 05:06:15 PM PDT 24
Peak memory 221464 kb
Host smart-b4709cde-8a00-4d6b-9dc2-8bcfa43a9e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995884935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2995884935
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.444025507
Short name T84
Test name
Test status
Simulation time 51294330 ps
CPU time 1.87 seconds
Started Jun 23 05:03:17 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 214324 kb
Host smart-5fd9c397-805a-4ef4-9afc-3268cee4af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444025507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.444025507
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1556424702
Short name T149
Test name
Test status
Simulation time 128446206 ps
CPU time 4.07 seconds
Started Jun 23 05:01:11 PM PDT 24
Finished Jun 23 05:01:15 PM PDT 24
Peak memory 214084 kb
Host smart-1ac16fea-b59e-4695-84a0-8e289a3797c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556424702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1556424702
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.526919451
Short name T145
Test name
Test status
Simulation time 166153471 ps
CPU time 5.61 seconds
Started Jun 23 05:01:44 PM PDT 24
Finished Jun 23 05:01:50 PM PDT 24
Peak memory 214080 kb
Host smart-65ee4e66-8081-4428-830a-cb8c0713998e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526919451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.526919451
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1361027302
Short name T158
Test name
Test status
Simulation time 54143548 ps
CPU time 3.43 seconds
Started Jun 23 05:01:50 PM PDT 24
Finished Jun 23 05:01:54 PM PDT 24
Peak memory 214012 kb
Host smart-6fb2543a-cb53-4ff7-96a8-b7593dae2d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361027302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1361027302
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2622824386
Short name T191
Test name
Test status
Simulation time 208506091 ps
CPU time 4 seconds
Started Jun 23 05:04:30 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 209644 kb
Host smart-1a566884-2c18-4e2f-8e5e-78ccc6fb372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622824386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2622824386
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.994726233
Short name T185
Test name
Test status
Simulation time 73596257 ps
CPU time 2.69 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:56 PM PDT 24
Peak memory 208148 kb
Host smart-35a7bf03-041e-49e9-9885-416d54770663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994726233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.994726233
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2014836459
Short name T555
Test name
Test status
Simulation time 85726180 ps
CPU time 2.08 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:02:59 PM PDT 24
Peak memory 210144 kb
Host smart-18454057-73df-4088-a1e2-ec63825346de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014836459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2014836459
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.442366648
Short name T280
Test name
Test status
Simulation time 249495455 ps
CPU time 2.25 seconds
Started Jun 23 05:03:36 PM PDT 24
Finished Jun 23 05:03:39 PM PDT 24
Peak memory 214224 kb
Host smart-f69110cd-a254-4cb2-b91c-0283d38a9c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442366648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.442366648
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3584002110
Short name T261
Test name
Test status
Simulation time 688424242 ps
CPU time 3.19 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 214328 kb
Host smart-cfb2ffd2-8f29-4b73-9296-dafa063e7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584002110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3584002110
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3159846957
Short name T264
Test name
Test status
Simulation time 135118014 ps
CPU time 2.9 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:53 PM PDT 24
Peak memory 214244 kb
Host smart-d70423c9-e2ff-4b71-b187-46674d8012df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159846957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3159846957
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2650512638
Short name T201
Test name
Test status
Simulation time 225822519 ps
CPU time 2.88 seconds
Started Jun 23 05:03:53 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 219956 kb
Host smart-05e845ac-36f8-4263-b6c1-ad6f1c4f3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650512638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2650512638
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3009221468
Short name T267
Test name
Test status
Simulation time 475349216 ps
CPU time 5.23 seconds
Started Jun 23 05:04:09 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 209852 kb
Host smart-9ae0cafd-210a-4a61-b77e-fa34f075719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009221468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3009221468
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1851390195
Short name T138
Test name
Test status
Simulation time 234860943 ps
CPU time 2.61 seconds
Started Jun 23 05:04:18 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 215368 kb
Host smart-40c4acab-0d08-42b3-a370-b659186cd52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851390195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1851390195
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2800962000
Short name T51
Test name
Test status
Simulation time 75479991 ps
CPU time 1.63 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 214152 kb
Host smart-d30bfaa0-64db-4447-8971-ae41e3595421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800962000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2800962000
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2574444672
Short name T348
Test name
Test status
Simulation time 172043298 ps
CPU time 2.79 seconds
Started Jun 23 05:05:22 PM PDT 24
Finished Jun 23 05:05:25 PM PDT 24
Peak memory 222384 kb
Host smart-62a298f9-9f80-4a56-9ef2-bb2ff1fb7581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574444672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2574444672
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2080478586
Short name T65
Test name
Test status
Simulation time 357163731 ps
CPU time 10.62 seconds
Started Jun 23 05:05:19 PM PDT 24
Finished Jun 23 05:05:30 PM PDT 24
Peak memory 209152 kb
Host smart-281f4fef-b762-4b77-824a-e08586ae0984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080478586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2080478586
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3281573402
Short name T208
Test name
Test status
Simulation time 823118292 ps
CPU time 19.65 seconds
Started Jun 23 05:05:29 PM PDT 24
Finished Jun 23 05:05:49 PM PDT 24
Peak memory 216260 kb
Host smart-f009f243-f078-4db3-80c6-e0977817b56d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281573402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3281573402
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2349337203
Short name T351
Test name
Test status
Simulation time 99700475 ps
CPU time 4.41 seconds
Started Jun 23 05:05:32 PM PDT 24
Finished Jun 23 05:05:36 PM PDT 24
Peak memory 215352 kb
Host smart-04ee9c8e-40df-414d-8b89-990a38db8ab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349337203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2349337203
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3359805185
Short name T6
Test name
Test status
Simulation time 575670864 ps
CPU time 4.01 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 209820 kb
Host smart-d60f04a4-0095-4ab4-94de-8cdb59b1ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359805185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3359805185
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1314207964
Short name T972
Test name
Test status
Simulation time 253682412 ps
CPU time 7.57 seconds
Started Jun 23 05:01:11 PM PDT 24
Finished Jun 23 05:01:19 PM PDT 24
Peak memory 205776 kb
Host smart-73fc7561-5c2b-4adb-b31f-ce600156140a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314207964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
314207964
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.831678705
Short name T1060
Test name
Test status
Simulation time 131916930 ps
CPU time 7.8 seconds
Started Jun 23 05:01:13 PM PDT 24
Finished Jun 23 05:01:21 PM PDT 24
Peak memory 206024 kb
Host smart-0d9293fb-56bc-426c-8e26-dbac540c52ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831678705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.831678705
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2408658871
Short name T976
Test name
Test status
Simulation time 165258585 ps
CPU time 1.14 seconds
Started Jun 23 05:01:10 PM PDT 24
Finished Jun 23 05:01:11 PM PDT 24
Peak memory 205964 kb
Host smart-58f66aeb-2db7-46e0-89c7-c81498903cd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408658871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
408658871
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.565093185
Short name T1073
Test name
Test status
Simulation time 161339959 ps
CPU time 2.14 seconds
Started Jun 23 05:01:13 PM PDT 24
Finished Jun 23 05:01:15 PM PDT 24
Peak memory 214300 kb
Host smart-614f5cd6-1534-400f-9124-0466125f0fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565093185 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.565093185
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3772913784
Short name T1010
Test name
Test status
Simulation time 17535588 ps
CPU time 1.26 seconds
Started Jun 23 05:01:08 PM PDT 24
Finished Jun 23 05:01:09 PM PDT 24
Peak memory 205908 kb
Host smart-eacbfb90-74fe-48ce-960a-1ae42ef327a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772913784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3772913784
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2875570935
Short name T920
Test name
Test status
Simulation time 16851223 ps
CPU time 0.79 seconds
Started Jun 23 05:01:06 PM PDT 24
Finished Jun 23 05:01:07 PM PDT 24
Peak memory 205516 kb
Host smart-16017b71-6561-486d-b6d7-c379a0e5ace0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875570935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2875570935
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.331992895
Short name T958
Test name
Test status
Simulation time 22946280 ps
CPU time 1.54 seconds
Started Jun 23 05:01:12 PM PDT 24
Finished Jun 23 05:01:14 PM PDT 24
Peak memory 205996 kb
Host smart-fff54924-5acb-43d1-ba1b-559bf5049435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331992895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.331992895
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1749451189
Short name T952
Test name
Test status
Simulation time 269622080 ps
CPU time 2.74 seconds
Started Jun 23 05:01:06 PM PDT 24
Finished Jun 23 05:01:09 PM PDT 24
Peak memory 214312 kb
Host smart-e370b324-219e-45b8-a7cc-07c1bbb6b39e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749451189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1749451189
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1659875647
Short name T991
Test name
Test status
Simulation time 443813372 ps
CPU time 8.43 seconds
Started Jun 23 05:01:08 PM PDT 24
Finished Jun 23 05:01:17 PM PDT 24
Peak memory 214532 kb
Host smart-4a59e1bc-4059-4a0a-aa5b-9192593c827c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659875647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1659875647
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.697170462
Short name T1001
Test name
Test status
Simulation time 233645703 ps
CPU time 2.39 seconds
Started Jun 23 05:01:10 PM PDT 24
Finished Jun 23 05:01:13 PM PDT 24
Peak memory 215132 kb
Host smart-088e5cfc-90d9-4e4e-b3c0-09ee7302ca18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697170462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.697170462
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1440637815
Short name T1027
Test name
Test status
Simulation time 147265907 ps
CPU time 3.89 seconds
Started Jun 23 05:01:13 PM PDT 24
Finished Jun 23 05:01:17 PM PDT 24
Peak memory 205964 kb
Host smart-12362049-3d7e-4a76-b8d5-4e2bfe6eba7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440637815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
440637815
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2656528917
Short name T1080
Test name
Test status
Simulation time 1288123344 ps
CPU time 17.01 seconds
Started Jun 23 05:01:12 PM PDT 24
Finished Jun 23 05:01:29 PM PDT 24
Peak memory 206044 kb
Host smart-7cbf376a-8642-4293-9c0c-37fedf866b53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656528917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
656528917
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1444910018
Short name T1039
Test name
Test status
Simulation time 149577572 ps
CPU time 1.08 seconds
Started Jun 23 05:01:13 PM PDT 24
Finished Jun 23 05:01:14 PM PDT 24
Peak memory 206004 kb
Host smart-618697cf-5107-4b22-b22a-e3ba83a00f57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444910018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
444910018
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3440460882
Short name T988
Test name
Test status
Simulation time 59985243 ps
CPU time 1.51 seconds
Started Jun 23 05:01:11 PM PDT 24
Finished Jun 23 05:01:13 PM PDT 24
Peak memory 214140 kb
Host smart-86cb79ba-2e08-446d-880d-c0bede5e71be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440460882 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3440460882
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1375546637
Short name T1068
Test name
Test status
Simulation time 34137074 ps
CPU time 1.27 seconds
Started Jun 23 05:01:12 PM PDT 24
Finished Jun 23 05:01:14 PM PDT 24
Peak memory 205992 kb
Host smart-4be5f11d-513e-4fe4-96ea-d9348f11611a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375546637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1375546637
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3803190648
Short name T1058
Test name
Test status
Simulation time 14904363 ps
CPU time 0.73 seconds
Started Jun 23 05:01:12 PM PDT 24
Finished Jun 23 05:01:13 PM PDT 24
Peak memory 205680 kb
Host smart-013ef53b-8e93-4050-8f3e-16918bbecd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803190648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3803190648
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2653499641
Short name T1031
Test name
Test status
Simulation time 175216699 ps
CPU time 1.78 seconds
Started Jun 23 05:01:14 PM PDT 24
Finished Jun 23 05:01:16 PM PDT 24
Peak memory 205876 kb
Host smart-ceb2610d-a95c-43d7-9480-654a28fe16ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653499641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2653499641
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1639713986
Short name T1029
Test name
Test status
Simulation time 1153583370 ps
CPU time 3.41 seconds
Started Jun 23 05:01:12 PM PDT 24
Finished Jun 23 05:01:15 PM PDT 24
Peak memory 214532 kb
Host smart-ea532969-82ba-4877-9202-deead693109e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639713986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1639713986
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2180132482
Short name T1024
Test name
Test status
Simulation time 353325202 ps
CPU time 3.77 seconds
Started Jun 23 05:01:14 PM PDT 24
Finished Jun 23 05:01:18 PM PDT 24
Peak memory 220392 kb
Host smart-7305a962-77bb-4f91-8514-0f8d1e17ba50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180132482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2180132482
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.13006677
Short name T933
Test name
Test status
Simulation time 878678574 ps
CPU time 2.63 seconds
Started Jun 23 05:01:11 PM PDT 24
Finished Jun 23 05:01:13 PM PDT 24
Peak memory 216164 kb
Host smart-754b2489-dfd6-4aae-8841-f7cc1ef510c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13006677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.13006677
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1503760818
Short name T999
Test name
Test status
Simulation time 49200832 ps
CPU time 1.66 seconds
Started Jun 23 05:01:41 PM PDT 24
Finished Jun 23 05:01:44 PM PDT 24
Peak memory 214160 kb
Host smart-e41c193e-193c-49e8-b6aa-65d96d8b6cfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503760818 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1503760818
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1344403952
Short name T947
Test name
Test status
Simulation time 122974287 ps
CPU time 1.15 seconds
Started Jun 23 05:01:41 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 205908 kb
Host smart-3b6588b1-f9d6-485e-acfc-500000b7a315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344403952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1344403952
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1647771924
Short name T940
Test name
Test status
Simulation time 156882411 ps
CPU time 0.7 seconds
Started Jun 23 05:01:42 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 205536 kb
Host smart-0ebf4461-77a8-4f86-9108-2598704e4ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647771924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1647771924
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1963361073
Short name T943
Test name
Test status
Simulation time 37094493 ps
CPU time 2.1 seconds
Started Jun 23 05:01:42 PM PDT 24
Finished Jun 23 05:01:45 PM PDT 24
Peak memory 205812 kb
Host smart-ef07f37b-5006-4ed6-8720-ac75ced75e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963361073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1963361073
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2636464010
Short name T1051
Test name
Test status
Simulation time 144622915 ps
CPU time 4.39 seconds
Started Jun 23 05:01:43 PM PDT 24
Finished Jun 23 05:01:48 PM PDT 24
Peak memory 214304 kb
Host smart-277a5192-6d14-4fa8-ab49-f0fc6be3a631
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636464010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2636464010
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2083041551
Short name T1054
Test name
Test status
Simulation time 45188276 ps
CPU time 2.82 seconds
Started Jun 23 05:01:45 PM PDT 24
Finished Jun 23 05:01:48 PM PDT 24
Peak memory 213960 kb
Host smart-0f326f38-8da5-4249-b418-f990f817d976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083041551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2083041551
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1354774078
Short name T1037
Test name
Test status
Simulation time 22960876 ps
CPU time 1.38 seconds
Started Jun 23 05:01:42 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 214156 kb
Host smart-a0536b86-05fc-44eb-8292-c214f81eaea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354774078 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1354774078
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.141782836
Short name T1019
Test name
Test status
Simulation time 24989001 ps
CPU time 1.22 seconds
Started Jun 23 05:01:46 PM PDT 24
Finished Jun 23 05:01:47 PM PDT 24
Peak memory 205992 kb
Host smart-cad097dd-c554-4b6f-b99d-e08c9f9baff4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141782836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.141782836
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3731405624
Short name T995
Test name
Test status
Simulation time 28945928 ps
CPU time 0.69 seconds
Started Jun 23 05:01:43 PM PDT 24
Finished Jun 23 05:01:44 PM PDT 24
Peak memory 205636 kb
Host smart-7b77e9f0-5cc6-4db9-a2bd-e648dda1e64b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731405624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3731405624
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2681781015
Short name T129
Test name
Test status
Simulation time 131979433 ps
CPU time 1.92 seconds
Started Jun 23 05:01:45 PM PDT 24
Finished Jun 23 05:01:48 PM PDT 24
Peak memory 205992 kb
Host smart-130d1c85-04d5-4731-9ff4-f0e6127d5c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681781015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2681781015
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2999371362
Short name T1025
Test name
Test status
Simulation time 59281743 ps
CPU time 2.11 seconds
Started Jun 23 05:01:43 PM PDT 24
Finished Jun 23 05:01:45 PM PDT 24
Peak memory 219344 kb
Host smart-83c5c21a-6669-4d08-abf0-425a353eff58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999371362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2999371362
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.193053558
Short name T104
Test name
Test status
Simulation time 161911869 ps
CPU time 4.3 seconds
Started Jun 23 05:01:46 PM PDT 24
Finished Jun 23 05:01:50 PM PDT 24
Peak memory 214496 kb
Host smart-28029c21-74c9-4713-b1e1-6f50da59de48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193053558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.193053558
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1333717033
Short name T961
Test name
Test status
Simulation time 77706292 ps
CPU time 2.77 seconds
Started Jun 23 05:01:42 PM PDT 24
Finished Jun 23 05:01:45 PM PDT 24
Peak memory 216028 kb
Host smart-92c0c174-9a4c-411f-bcaf-d589785f7384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333717033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1333717033
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3512971411
Short name T978
Test name
Test status
Simulation time 37867816 ps
CPU time 1.52 seconds
Started Jun 23 05:01:51 PM PDT 24
Finished Jun 23 05:01:53 PM PDT 24
Peak memory 216592 kb
Host smart-eb64bb56-d345-451f-bf4c-9eaf8d429ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512971411 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3512971411
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1792535470
Short name T1016
Test name
Test status
Simulation time 15165027 ps
CPU time 1.1 seconds
Started Jun 23 05:01:51 PM PDT 24
Finished Jun 23 05:01:52 PM PDT 24
Peak memory 205908 kb
Host smart-538054bd-7242-41c9-a298-b791790225af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792535470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1792535470
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1730570063
Short name T1011
Test name
Test status
Simulation time 9145654 ps
CPU time 0.72 seconds
Started Jun 23 05:01:45 PM PDT 24
Finished Jun 23 05:01:46 PM PDT 24
Peak memory 205680 kb
Host smart-02063adc-81d5-4e78-90ed-6447b15d6845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730570063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1730570063
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.355892916
Short name T130
Test name
Test status
Simulation time 76045295 ps
CPU time 1.98 seconds
Started Jun 23 05:01:50 PM PDT 24
Finished Jun 23 05:01:53 PM PDT 24
Peak memory 206024 kb
Host smart-bda9f83a-9a13-47b6-b16b-695198fb5777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355892916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.355892916
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1652710504
Short name T110
Test name
Test status
Simulation time 1383652404 ps
CPU time 6.37 seconds
Started Jun 23 05:01:45 PM PDT 24
Finished Jun 23 05:01:51 PM PDT 24
Peak memory 222256 kb
Host smart-c4306def-50df-4bae-af76-07e366d0b2b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652710504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1652710504
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3030693453
Short name T962
Test name
Test status
Simulation time 30428194 ps
CPU time 2.16 seconds
Started Jun 23 05:01:43 PM PDT 24
Finished Jun 23 05:01:46 PM PDT 24
Peak memory 214064 kb
Host smart-e2b9b5fa-380a-45cb-960f-cb168b68612f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030693453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3030693453
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.248995833
Short name T922
Test name
Test status
Simulation time 31826362 ps
CPU time 2.47 seconds
Started Jun 23 05:01:48 PM PDT 24
Finished Jun 23 05:01:51 PM PDT 24
Peak memory 214116 kb
Host smart-80c1db58-066c-48e3-af57-052c3d2958c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248995833 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.248995833
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2332199874
Short name T1050
Test name
Test status
Simulation time 22840345 ps
CPU time 1.41 seconds
Started Jun 23 05:01:51 PM PDT 24
Finished Jun 23 05:01:53 PM PDT 24
Peak memory 206028 kb
Host smart-36f2fc5b-e9f9-4249-a721-72e6ef34bedd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332199874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2332199874
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.952900659
Short name T1082
Test name
Test status
Simulation time 23855078 ps
CPU time 0.73 seconds
Started Jun 23 05:01:50 PM PDT 24
Finished Jun 23 05:01:51 PM PDT 24
Peak memory 205600 kb
Host smart-f347b63b-b6c3-432f-b66a-173306d196da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952900659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.952900659
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.473044003
Short name T1077
Test name
Test status
Simulation time 180263880 ps
CPU time 1.51 seconds
Started Jun 23 05:01:49 PM PDT 24
Finished Jun 23 05:01:51 PM PDT 24
Peak memory 205964 kb
Host smart-ca18fc97-9856-41a6-8cfb-dbd9a3033bfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473044003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.473044003
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1000072142
Short name T1013
Test name
Test status
Simulation time 226962806 ps
CPU time 2.24 seconds
Started Jun 23 05:01:50 PM PDT 24
Finished Jun 23 05:01:53 PM PDT 24
Peak memory 214404 kb
Host smart-d6698b53-c121-47c4-b13d-e892de0ecbd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000072142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1000072142
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3462215703
Short name T1033
Test name
Test status
Simulation time 402713907 ps
CPU time 13.73 seconds
Started Jun 23 05:01:52 PM PDT 24
Finished Jun 23 05:02:06 PM PDT 24
Peak memory 220488 kb
Host smart-f4a99e7d-e66f-49e1-9327-3b3d88f99a14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462215703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3462215703
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2395689288
Short name T1070
Test name
Test status
Simulation time 30175697 ps
CPU time 1.97 seconds
Started Jun 23 05:01:48 PM PDT 24
Finished Jun 23 05:01:50 PM PDT 24
Peak memory 214092 kb
Host smart-92d74c58-9772-4856-8c8e-b388b83e3688
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395689288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2395689288
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.448911880
Short name T994
Test name
Test status
Simulation time 134166608 ps
CPU time 1.41 seconds
Started Jun 23 05:01:52 PM PDT 24
Finished Jun 23 05:01:54 PM PDT 24
Peak memory 214280 kb
Host smart-25894625-22f8-4981-a83b-58e4e1a13a24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448911880 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.448911880
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4173019783
Short name T1023
Test name
Test status
Simulation time 123017857 ps
CPU time 1.2 seconds
Started Jun 23 05:01:49 PM PDT 24
Finished Jun 23 05:01:50 PM PDT 24
Peak memory 205848 kb
Host smart-d4a076e7-1ea0-4b73-8cc1-247fc60a6877
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173019783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4173019783
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.205787359
Short name T1006
Test name
Test status
Simulation time 14967874 ps
CPU time 0.84 seconds
Started Jun 23 05:01:49 PM PDT 24
Finished Jun 23 05:01:50 PM PDT 24
Peak memory 205672 kb
Host smart-8d0b8b88-4843-4397-a076-1c084404887d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205787359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.205787359
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2064482956
Short name T1059
Test name
Test status
Simulation time 292402461 ps
CPU time 2.43 seconds
Started Jun 23 05:01:47 PM PDT 24
Finished Jun 23 05:01:50 PM PDT 24
Peak memory 205912 kb
Host smart-4e2bbe27-19c7-40af-a2cd-4bfd8a55865d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064482956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2064482956
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4218035479
Short name T1005
Test name
Test status
Simulation time 479478209 ps
CPU time 2.59 seconds
Started Jun 23 05:01:51 PM PDT 24
Finished Jun 23 05:01:54 PM PDT 24
Peak memory 214532 kb
Host smart-17f55140-8d6c-4fd5-b3a1-7ed7c77a45cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218035479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4218035479
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2223845954
Short name T1052
Test name
Test status
Simulation time 146148528 ps
CPU time 8.26 seconds
Started Jun 23 05:01:50 PM PDT 24
Finished Jun 23 05:01:59 PM PDT 24
Peak memory 214468 kb
Host smart-82b75f71-a228-4c15-9c46-90c925654561
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223845954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2223845954
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.938359788
Short name T173
Test name
Test status
Simulation time 512352445 ps
CPU time 3.39 seconds
Started Jun 23 05:01:51 PM PDT 24
Finished Jun 23 05:01:55 PM PDT 24
Peak memory 217268 kb
Host smart-a3f6576c-26ab-4d07-b9e2-78df0a058cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938359788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.938359788
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3134849072
Short name T155
Test name
Test status
Simulation time 167295070 ps
CPU time 4.1 seconds
Started Jun 23 05:01:49 PM PDT 24
Finished Jun 23 05:01:53 PM PDT 24
Peak memory 214076 kb
Host smart-dfa4acff-288e-4be9-8b8e-ec5eb54d0c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134849072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3134849072
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1881286158
Short name T928
Test name
Test status
Simulation time 48966397 ps
CPU time 1.6 seconds
Started Jun 23 05:01:53 PM PDT 24
Finished Jun 23 05:01:55 PM PDT 24
Peak memory 214148 kb
Host smart-84168fcb-7694-4a3d-95c9-a27c6555afba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881286158 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1881286158
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.778344840
Short name T1003
Test name
Test status
Simulation time 46602712 ps
CPU time 1.4 seconds
Started Jun 23 05:01:56 PM PDT 24
Finished Jun 23 05:01:57 PM PDT 24
Peak memory 206028 kb
Host smart-82d67e04-fa61-4065-9324-1295026a336b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778344840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.778344840
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.573216831
Short name T950
Test name
Test status
Simulation time 15152612 ps
CPU time 0.88 seconds
Started Jun 23 05:01:57 PM PDT 24
Finished Jun 23 05:01:58 PM PDT 24
Peak memory 205776 kb
Host smart-42b0b08a-9e12-4f99-a066-3d812869a381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573216831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.573216831
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.512661676
Short name T1064
Test name
Test status
Simulation time 499795701 ps
CPU time 2.57 seconds
Started Jun 23 05:01:55 PM PDT 24
Finished Jun 23 05:01:58 PM PDT 24
Peak memory 205896 kb
Host smart-d9e9c9b1-6b50-424a-881e-d09dc37ef232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512661676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.512661676
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2588958663
Short name T111
Test name
Test status
Simulation time 97111174 ps
CPU time 2.53 seconds
Started Jun 23 05:01:58 PM PDT 24
Finished Jun 23 05:02:01 PM PDT 24
Peak memory 214472 kb
Host smart-d74f3641-8167-4c96-808c-3c0e35d40038
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588958663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2588958663
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2119002230
Short name T975
Test name
Test status
Simulation time 1164450571 ps
CPU time 4.78 seconds
Started Jun 23 05:01:57 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 220456 kb
Host smart-a7e5a6d9-866f-419b-95a4-4616dbad0351
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119002230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2119002230
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3400836109
Short name T1074
Test name
Test status
Simulation time 109520673 ps
CPU time 2.79 seconds
Started Jun 23 05:01:54 PM PDT 24
Finished Jun 23 05:01:58 PM PDT 24
Peak memory 214136 kb
Host smart-554667f7-fcd8-4e8e-a710-44924eea3877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400836109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3400836109
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.865018967
Short name T159
Test name
Test status
Simulation time 180894005 ps
CPU time 2.5 seconds
Started Jun 23 05:01:53 PM PDT 24
Finished Jun 23 05:01:56 PM PDT 24
Peak memory 214056 kb
Host smart-5845f13d-a922-414b-86ac-89432dd066ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865018967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.865018967
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2401223967
Short name T1034
Test name
Test status
Simulation time 188348553 ps
CPU time 2.13 seconds
Started Jun 23 05:01:58 PM PDT 24
Finished Jun 23 05:02:00 PM PDT 24
Peak memory 206024 kb
Host smart-36faa082-5b97-49e4-a784-6e45bc0aa533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401223967 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2401223967
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3667795982
Short name T1065
Test name
Test status
Simulation time 252421303 ps
CPU time 1.17 seconds
Started Jun 23 05:01:56 PM PDT 24
Finished Jun 23 05:01:58 PM PDT 24
Peak memory 205904 kb
Host smart-c6b1bb5c-1fab-4672-b5a6-0862fd4d2b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667795982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3667795982
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3924144528
Short name T918
Test name
Test status
Simulation time 33636805 ps
CPU time 0.73 seconds
Started Jun 23 05:01:55 PM PDT 24
Finished Jun 23 05:01:56 PM PDT 24
Peak memory 205520 kb
Host smart-28aff16f-29d6-490a-87ed-46fdc6f91335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924144528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3924144528
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3756896596
Short name T1066
Test name
Test status
Simulation time 37200546 ps
CPU time 1.63 seconds
Started Jun 23 05:01:54 PM PDT 24
Finished Jun 23 05:01:56 PM PDT 24
Peak memory 205864 kb
Host smart-1015fb8b-e7fd-46ec-86a9-d8fea678dbdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756896596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3756896596
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3511708004
Short name T1087
Test name
Test status
Simulation time 41965802 ps
CPU time 1.9 seconds
Started Jun 23 05:01:55 PM PDT 24
Finished Jun 23 05:01:57 PM PDT 24
Peak memory 214388 kb
Host smart-9ce85c45-9041-4a19-8dc6-e31a71b184cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511708004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3511708004
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.104390418
Short name T1078
Test name
Test status
Simulation time 602496954 ps
CPU time 8.4 seconds
Started Jun 23 05:01:56 PM PDT 24
Finished Jun 23 05:02:04 PM PDT 24
Peak memory 220604 kb
Host smart-aecc6af9-05b5-43c0-bf31-85bb8c28aa6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104390418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.104390418
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2244378672
Short name T925
Test name
Test status
Simulation time 212017798 ps
CPU time 3.25 seconds
Started Jun 23 05:01:54 PM PDT 24
Finished Jun 23 05:01:58 PM PDT 24
Peak memory 214136 kb
Host smart-84e3aa6c-8eba-48d9-9af5-4879b1eabb2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244378672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2244378672
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1450545216
Short name T957
Test name
Test status
Simulation time 56660789 ps
CPU time 3.15 seconds
Started Jun 23 05:01:56 PM PDT 24
Finished Jun 23 05:02:00 PM PDT 24
Peak memory 214160 kb
Host smart-e9c1b824-ba6a-48fe-a05e-a4e5ad2f911d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450545216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1450545216
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1554179368
Short name T1053
Test name
Test status
Simulation time 103795320 ps
CPU time 1.41 seconds
Started Jun 23 05:01:59 PM PDT 24
Finished Jun 23 05:02:01 PM PDT 24
Peak memory 205932 kb
Host smart-68bd9236-6260-46d2-9ba5-2d4b0306ec74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554179368 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1554179368
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1602963391
Short name T949
Test name
Test status
Simulation time 26044170 ps
CPU time 1.16 seconds
Started Jun 23 05:02:00 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 206032 kb
Host smart-e9362618-d6c2-494d-b041-985c899b66b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602963391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1602963391
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4154586336
Short name T990
Test name
Test status
Simulation time 63957434 ps
CPU time 0.73 seconds
Started Jun 23 05:02:01 PM PDT 24
Finished Jun 23 05:02:03 PM PDT 24
Peak memory 205668 kb
Host smart-52fa9219-8dd4-483d-9272-e87ae67a4db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154586336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4154586336
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4013721364
Short name T977
Test name
Test status
Simulation time 81576691 ps
CPU time 2.06 seconds
Started Jun 23 05:01:59 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 205960 kb
Host smart-293e34af-fef5-4162-b501-036913d32179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013721364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4013721364
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1406691687
Short name T936
Test name
Test status
Simulation time 189259630 ps
CPU time 1.8 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 214496 kb
Host smart-569c4249-3b80-4d97-9366-f933f67b1e9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406691687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1406691687
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2094353858
Short name T105
Test name
Test status
Simulation time 189347768 ps
CPU time 7.56 seconds
Started Jun 23 05:01:54 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 214308 kb
Host smart-93495e04-cc26-4f76-b84e-d19664a7d28d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094353858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2094353858
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3701783720
Short name T987
Test name
Test status
Simulation time 171557848 ps
CPU time 3.32 seconds
Started Jun 23 05:01:54 PM PDT 24
Finished Jun 23 05:01:57 PM PDT 24
Peak memory 213956 kb
Host smart-0ff0afec-94c2-40b6-893f-ea82279a2cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701783720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3701783720
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2139668577
Short name T960
Test name
Test status
Simulation time 108222532 ps
CPU time 3.52 seconds
Started Jun 23 05:01:56 PM PDT 24
Finished Jun 23 05:02:00 PM PDT 24
Peak memory 215260 kb
Host smart-99193b11-48b6-4657-b568-205e097343e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139668577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2139668577
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.205334920
Short name T1069
Test name
Test status
Simulation time 39389463 ps
CPU time 1.47 seconds
Started Jun 23 05:02:00 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 214032 kb
Host smart-74397de5-f9c2-40a6-ba84-2a8a88cb708f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205334920 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.205334920
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1385542750
Short name T974
Test name
Test status
Simulation time 24252024 ps
CPU time 0.9 seconds
Started Jun 23 05:01:58 PM PDT 24
Finished Jun 23 05:02:00 PM PDT 24
Peak memory 205644 kb
Host smart-06c7a0fa-67d7-4170-89fc-618fd3476a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385542750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1385542750
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1856467140
Short name T1085
Test name
Test status
Simulation time 30125337 ps
CPU time 0.83 seconds
Started Jun 23 05:02:00 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 205596 kb
Host smart-c2b63f03-c0c7-48a3-9cd7-657b9887c8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856467140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1856467140
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3289735760
Short name T979
Test name
Test status
Simulation time 22165540 ps
CPU time 1.43 seconds
Started Jun 23 05:02:01 PM PDT 24
Finished Jun 23 05:02:03 PM PDT 24
Peak memory 205968 kb
Host smart-a6fc034e-076c-463f-aa74-e8f622688ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289735760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3289735760
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1280639229
Short name T989
Test name
Test status
Simulation time 125151955 ps
CPU time 3.86 seconds
Started Jun 23 05:02:04 PM PDT 24
Finished Jun 23 05:02:08 PM PDT 24
Peak memory 214364 kb
Host smart-473d3638-83b8-4259-bd37-359d3d50214e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280639229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1280639229
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1523504515
Short name T1046
Test name
Test status
Simulation time 574389663 ps
CPU time 7.28 seconds
Started Jun 23 05:01:59 PM PDT 24
Finished Jun 23 05:02:08 PM PDT 24
Peak memory 214468 kb
Host smart-990edd1d-06a8-431c-b044-e381ac70cfac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523504515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1523504515
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.329050391
Short name T921
Test name
Test status
Simulation time 31625764 ps
CPU time 2.29 seconds
Started Jun 23 05:02:00 PM PDT 24
Finished Jun 23 05:02:03 PM PDT 24
Peak memory 214040 kb
Host smart-8d82e78f-0425-41c7-9542-a954da551283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329050391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.329050391
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1426683323
Short name T1012
Test name
Test status
Simulation time 22905338 ps
CPU time 1.14 seconds
Started Jun 23 05:01:59 PM PDT 24
Finished Jun 23 05:02:01 PM PDT 24
Peak memory 205904 kb
Host smart-991201df-b071-4b60-b93c-03dfb14407f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426683323 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1426683323
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4191012464
Short name T144
Test name
Test status
Simulation time 31973157 ps
CPU time 1.16 seconds
Started Jun 23 05:02:00 PM PDT 24
Finished Jun 23 05:02:02 PM PDT 24
Peak memory 205896 kb
Host smart-45bfde5a-6404-437a-97d0-6674c455f7ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191012464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4191012464
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4121691023
Short name T937
Test name
Test status
Simulation time 12146873 ps
CPU time 0.78 seconds
Started Jun 23 05:01:59 PM PDT 24
Finished Jun 23 05:02:00 PM PDT 24
Peak memory 205512 kb
Host smart-22811875-77c5-4e7d-96f2-2655829e9dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121691023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4121691023
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.524592390
Short name T992
Test name
Test status
Simulation time 902532950 ps
CPU time 1.69 seconds
Started Jun 23 05:02:00 PM PDT 24
Finished Jun 23 05:02:03 PM PDT 24
Peak memory 206060 kb
Host smart-b881e442-b794-4ae6-ad1a-7013fd3cad62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524592390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.524592390
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1124041853
Short name T103
Test name
Test status
Simulation time 105220653 ps
CPU time 2.4 seconds
Started Jun 23 05:02:01 PM PDT 24
Finished Jun 23 05:02:04 PM PDT 24
Peak memory 214484 kb
Host smart-1c1445c2-d44b-4b26-b63a-751d11f4336c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124041853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1124041853
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1748684247
Short name T1067
Test name
Test status
Simulation time 632674943 ps
CPU time 4.7 seconds
Started Jun 23 05:02:01 PM PDT 24
Finished Jun 23 05:02:06 PM PDT 24
Peak memory 214472 kb
Host smart-28acf28e-7463-4540-b326-e7eaeafa7a1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748684247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1748684247
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3649455146
Short name T985
Test name
Test status
Simulation time 100230860 ps
CPU time 2.6 seconds
Started Jun 23 05:02:01 PM PDT 24
Finished Jun 23 05:02:04 PM PDT 24
Peak memory 214744 kb
Host smart-1091e704-611e-4a78-b41a-7db1016cbc62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649455146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3649455146
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.778323830
Short name T152
Test name
Test status
Simulation time 341881231 ps
CPU time 5.29 seconds
Started Jun 23 05:02:01 PM PDT 24
Finished Jun 23 05:02:07 PM PDT 24
Peak memory 214088 kb
Host smart-1dd91f9d-8139-453a-8de8-db561ce39f60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778323830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.778323830
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1424858849
Short name T1021
Test name
Test status
Simulation time 78859149 ps
CPU time 4.88 seconds
Started Jun 23 05:01:17 PM PDT 24
Finished Jun 23 05:01:22 PM PDT 24
Peak memory 205812 kb
Host smart-1cb56948-26bf-4ef6-998f-47bf56b797f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424858849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
424858849
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3354513881
Short name T942
Test name
Test status
Simulation time 516840343 ps
CPU time 7.75 seconds
Started Jun 23 05:01:17 PM PDT 24
Finished Jun 23 05:01:25 PM PDT 24
Peak memory 205856 kb
Host smart-007ba377-dcab-44d6-b76e-36e87da5b5d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354513881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
354513881
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1256052340
Short name T1000
Test name
Test status
Simulation time 33614140 ps
CPU time 1.24 seconds
Started Jun 23 05:01:16 PM PDT 24
Finished Jun 23 05:01:18 PM PDT 24
Peak memory 205888 kb
Host smart-aac644c8-6e50-483a-a659-6a674b8c0ab9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256052340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
256052340
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2009212205
Short name T139
Test name
Test status
Simulation time 386710399 ps
CPU time 2.29 seconds
Started Jun 23 05:01:18 PM PDT 24
Finished Jun 23 05:01:20 PM PDT 24
Peak memory 214284 kb
Host smart-314bb2ac-9813-43d6-9a59-b752c36ae023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009212205 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2009212205
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3160947118
Short name T953
Test name
Test status
Simulation time 34335753 ps
CPU time 0.94 seconds
Started Jun 23 05:01:18 PM PDT 24
Finished Jun 23 05:01:19 PM PDT 24
Peak memory 205648 kb
Host smart-e2962b2a-19f7-46c2-8f6f-8b0fe9b25791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160947118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3160947118
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2159673006
Short name T916
Test name
Test status
Simulation time 20043972 ps
CPU time 0.83 seconds
Started Jun 23 05:01:17 PM PDT 24
Finished Jun 23 05:01:18 PM PDT 24
Peak memory 205576 kb
Host smart-7fe0bd4a-c6fe-4534-9951-2b0420a1b17d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159673006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2159673006
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.555235305
Short name T1083
Test name
Test status
Simulation time 314475197 ps
CPU time 2.49 seconds
Started Jun 23 05:01:18 PM PDT 24
Finished Jun 23 05:01:21 PM PDT 24
Peak memory 205972 kb
Host smart-f14ce603-177a-4453-9324-c20d00e8b516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555235305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.555235305
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.297482680
Short name T1035
Test name
Test status
Simulation time 296607169 ps
CPU time 4.13 seconds
Started Jun 23 05:01:11 PM PDT 24
Finished Jun 23 05:01:16 PM PDT 24
Peak memory 214356 kb
Host smart-5092d100-e751-420f-925c-8ac5a8a19e3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297482680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.297482680
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.342885709
Short name T956
Test name
Test status
Simulation time 382428262 ps
CPU time 8.48 seconds
Started Jun 23 05:01:16 PM PDT 24
Finished Jun 23 05:01:25 PM PDT 24
Peak memory 214464 kb
Host smart-b5987485-15ef-40a1-96ac-c41c451983bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342885709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.342885709
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1505532676
Short name T1030
Test name
Test status
Simulation time 529861120 ps
CPU time 4.8 seconds
Started Jun 23 05:01:17 PM PDT 24
Finished Jun 23 05:01:22 PM PDT 24
Peak memory 213972 kb
Host smart-5bff1571-83cc-4d3e-8e83-40c5d2696454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505532676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1505532676
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1025961287
Short name T143
Test name
Test status
Simulation time 53541632 ps
CPU time 3.14 seconds
Started Jun 23 05:01:16 PM PDT 24
Finished Jun 23 05:01:20 PM PDT 24
Peak memory 214224 kb
Host smart-460970e9-1d4b-412d-849d-883d7df2a0e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025961287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1025961287
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2277731693
Short name T919
Test name
Test status
Simulation time 9953048 ps
CPU time 0.84 seconds
Started Jun 23 05:02:08 PM PDT 24
Finished Jun 23 05:02:09 PM PDT 24
Peak memory 205576 kb
Host smart-05beac53-8bc9-4ed6-a0e9-1318d6ac7386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277731693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2277731693
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.217326407
Short name T917
Test name
Test status
Simulation time 33159869 ps
CPU time 0.81 seconds
Started Jun 23 05:02:06 PM PDT 24
Finished Jun 23 05:02:07 PM PDT 24
Peak memory 205604 kb
Host smart-80363928-a2c0-426e-b3fa-a9a26b092648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217326407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.217326407
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2389525845
Short name T1057
Test name
Test status
Simulation time 12882669 ps
CPU time 0.83 seconds
Started Jun 23 05:02:06 PM PDT 24
Finished Jun 23 05:02:08 PM PDT 24
Peak memory 205520 kb
Host smart-410db982-60b7-4165-a666-fbb9996e05de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389525845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2389525845
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4283969069
Short name T1036
Test name
Test status
Simulation time 15012306 ps
CPU time 0.72 seconds
Started Jun 23 05:02:05 PM PDT 24
Finished Jun 23 05:02:06 PM PDT 24
Peak memory 205672 kb
Host smart-cc930400-7deb-49a0-812c-b33410750d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283969069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4283969069
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1385245530
Short name T1071
Test name
Test status
Simulation time 17010500 ps
CPU time 0.79 seconds
Started Jun 23 05:02:08 PM PDT 24
Finished Jun 23 05:02:09 PM PDT 24
Peak memory 205576 kb
Host smart-f90a2a6a-0274-4111-bb49-f0a8fe4e4e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385245530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1385245530
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2522145786
Short name T946
Test name
Test status
Simulation time 62930312 ps
CPU time 0.79 seconds
Started Jun 23 05:02:05 PM PDT 24
Finished Jun 23 05:02:06 PM PDT 24
Peak memory 205680 kb
Host smart-35ac16b6-0efa-420d-80f1-06989b3fff89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522145786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2522145786
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.643974663
Short name T935
Test name
Test status
Simulation time 11614146 ps
CPU time 0.74 seconds
Started Jun 23 05:02:05 PM PDT 24
Finished Jun 23 05:02:06 PM PDT 24
Peak memory 205548 kb
Host smart-bca14afc-c2f6-47b5-89ac-0d1802c49674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643974663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.643974663
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3156170379
Short name T1008
Test name
Test status
Simulation time 23035396 ps
CPU time 0.86 seconds
Started Jun 23 05:02:06 PM PDT 24
Finished Jun 23 05:02:07 PM PDT 24
Peak memory 205680 kb
Host smart-47f25a57-d8fa-4b13-8584-5903dd42d259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156170379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3156170379
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.831263595
Short name T927
Test name
Test status
Simulation time 11349468 ps
CPU time 0.73 seconds
Started Jun 23 05:02:05 PM PDT 24
Finished Jun 23 05:02:07 PM PDT 24
Peak memory 205468 kb
Host smart-fd7d288c-2d9b-4b71-9a5e-45e63c62c9b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831263595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.831263595
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2851408743
Short name T1045
Test name
Test status
Simulation time 63348800 ps
CPU time 0.81 seconds
Started Jun 23 05:02:07 PM PDT 24
Finished Jun 23 05:02:08 PM PDT 24
Peak memory 205596 kb
Host smart-e2e9ba00-cd8b-4116-94c9-dd389262c2df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851408743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2851408743
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2688049029
Short name T965
Test name
Test status
Simulation time 209143069 ps
CPU time 6.51 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 205956 kb
Host smart-49a0b940-e392-4e31-b094-5792b9ff8e91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688049029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
688049029
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1049211249
Short name T939
Test name
Test status
Simulation time 869352293 ps
CPU time 16.59 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:47 PM PDT 24
Peak memory 205856 kb
Host smart-7cfef4db-4fbb-41e1-b76a-2e95d826f541
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049211249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
049211249
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4258778528
Short name T981
Test name
Test status
Simulation time 27536012 ps
CPU time 1.13 seconds
Started Jun 23 05:01:25 PM PDT 24
Finished Jun 23 05:01:27 PM PDT 24
Peak memory 206024 kb
Host smart-2e65bae1-3a7d-45ce-b86e-9aa643084af0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258778528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
258778528
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3919500281
Short name T1048
Test name
Test status
Simulation time 31389310 ps
CPU time 1.79 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:38 PM PDT 24
Peak memory 214236 kb
Host smart-18fe7ff1-3d34-48c9-85d4-11bf7cd02aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919500281 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3919500281
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3957693915
Short name T131
Test name
Test status
Simulation time 50782614 ps
CPU time 1.06 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:31 PM PDT 24
Peak memory 205956 kb
Host smart-6d7c0b8a-7a5c-4308-a9f1-153330e4faa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957693915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3957693915
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3817277364
Short name T973
Test name
Test status
Simulation time 31127567 ps
CPU time 0.72 seconds
Started Jun 23 05:01:31 PM PDT 24
Finished Jun 23 05:01:33 PM PDT 24
Peak memory 205648 kb
Host smart-8f3b3a3f-8463-4f04-a855-457cd7a3bd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817277364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3817277364
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2907044129
Short name T959
Test name
Test status
Simulation time 221134490 ps
CPU time 1.71 seconds
Started Jun 23 05:01:31 PM PDT 24
Finished Jun 23 05:01:33 PM PDT 24
Peak memory 205908 kb
Host smart-c0b1b993-2d40-45ec-9158-56858fe5a399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907044129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2907044129
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3086304630
Short name T934
Test name
Test status
Simulation time 147751719 ps
CPU time 2.59 seconds
Started Jun 23 05:01:16 PM PDT 24
Finished Jun 23 05:01:19 PM PDT 24
Peak memory 214384 kb
Host smart-819be266-bea0-420d-b6de-e0e965f6ef9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086304630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3086304630
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2229131105
Short name T983
Test name
Test status
Simulation time 271465637 ps
CPU time 7.43 seconds
Started Jun 23 05:01:29 PM PDT 24
Finished Jun 23 05:01:37 PM PDT 24
Peak memory 214384 kb
Host smart-a2979111-5385-464c-b724-dca5a4f91db6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229131105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2229131105
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3288053635
Short name T955
Test name
Test status
Simulation time 91013458 ps
CPU time 3.44 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 214028 kb
Host smart-436dfaad-7b9d-4f27-a346-4f8f6380e7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288053635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3288053635
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2500712232
Short name T1028
Test name
Test status
Simulation time 663468230 ps
CPU time 4.74 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:35 PM PDT 24
Peak memory 214064 kb
Host smart-1d77ced0-4c72-4a59-8fb8-8f57c333ac0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500712232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2500712232
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.670052273
Short name T1038
Test name
Test status
Simulation time 10924899 ps
CPU time 0.85 seconds
Started Jun 23 05:02:05 PM PDT 24
Finished Jun 23 05:02:06 PM PDT 24
Peak memory 205740 kb
Host smart-e5752506-7228-41b8-9119-f316bb7e6246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670052273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.670052273
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.44829770
Short name T984
Test name
Test status
Simulation time 63522568 ps
CPU time 0.79 seconds
Started Jun 23 05:02:07 PM PDT 24
Finished Jun 23 05:02:09 PM PDT 24
Peak memory 205596 kb
Host smart-aee0a9f6-9545-4e0a-919f-212e101c3fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44829770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.44829770
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3031312252
Short name T1015
Test name
Test status
Simulation time 13101424 ps
CPU time 0.8 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205576 kb
Host smart-e5eb2927-41be-49e6-b58e-f04adb70c04e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031312252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3031312252
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.71408111
Short name T1081
Test name
Test status
Simulation time 10669436 ps
CPU time 0.7 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:12 PM PDT 24
Peak memory 205604 kb
Host smart-5c1d5f5c-3844-49c3-90b0-486fe8f78474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71408111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.71408111
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2824521019
Short name T948
Test name
Test status
Simulation time 14636957 ps
CPU time 0.9 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205852 kb
Host smart-f081a9a3-53a7-4fd4-84c6-a9dc5c2c262f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824521019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2824521019
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1596245148
Short name T1018
Test name
Test status
Simulation time 14045310 ps
CPU time 0.82 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205532 kb
Host smart-7ca368f0-786a-42e1-b4e4-77466eda18ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596245148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1596245148
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2807073271
Short name T963
Test name
Test status
Simulation time 12931764 ps
CPU time 0.74 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:13 PM PDT 24
Peak memory 205680 kb
Host smart-1704f518-00b6-4e99-8b64-85efcdff6ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807073271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2807073271
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4104358275
Short name T1055
Test name
Test status
Simulation time 45890712 ps
CPU time 0.77 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:13 PM PDT 24
Peak memory 205604 kb
Host smart-ab3f61df-d7c8-4f39-adee-e83499e1572c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104358275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4104358275
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2328250901
Short name T924
Test name
Test status
Simulation time 26015098 ps
CPU time 0.83 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205604 kb
Host smart-b15f8505-66f7-4ae6-b6e1-8a7d80479d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328250901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2328250901
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2495452445
Short name T1072
Test name
Test status
Simulation time 9553186 ps
CPU time 0.72 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:12 PM PDT 24
Peak memory 205680 kb
Host smart-10b1b5b4-ca08-4b17-90c0-976b445c839f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495452445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2495452445
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2208734086
Short name T982
Test name
Test status
Simulation time 1003740741 ps
CPU time 15.47 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:48 PM PDT 24
Peak memory 205988 kb
Host smart-98069a2e-3de6-46aa-97df-05921c1b13f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208734086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
208734086
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4153149030
Short name T1043
Test name
Test status
Simulation time 130018795 ps
CPU time 7.23 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 206132 kb
Host smart-66327c47-bd61-471f-b1c0-c378e3bf24e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153149030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4
153149030
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2327548766
Short name T1032
Test name
Test status
Simulation time 176636758 ps
CPU time 1.13 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:31 PM PDT 24
Peak memory 205880 kb
Host smart-de51ac9f-bdf2-4059-bc77-baf21b038196
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327548766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
327548766
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.287707327
Short name T1020
Test name
Test status
Simulation time 30923976 ps
CPU time 1.91 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:33 PM PDT 24
Peak memory 214304 kb
Host smart-4eb96904-2ca3-4b20-a173-0eae0be566bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287707327 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.287707327
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3893734903
Short name T1063
Test name
Test status
Simulation time 27762459 ps
CPU time 1.18 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 206064 kb
Host smart-4623a22f-86b1-4348-8702-c1911302fb5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893734903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3893734903
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2580392301
Short name T998
Test name
Test status
Simulation time 35483111 ps
CPU time 0.68 seconds
Started Jun 23 05:01:21 PM PDT 24
Finished Jun 23 05:01:22 PM PDT 24
Peak memory 205588 kb
Host smart-972f6cd5-05ae-4db5-a63d-70de3f6f2279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580392301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2580392301
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1944087897
Short name T128
Test name
Test status
Simulation time 216888896 ps
CPU time 2.33 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:33 PM PDT 24
Peak memory 206028 kb
Host smart-23ce7a60-6d24-4cd1-94bd-d11bfb8f45b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944087897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1944087897
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.466165403
Short name T969
Test name
Test status
Simulation time 462656293 ps
CPU time 2.32 seconds
Started Jun 23 05:01:21 PM PDT 24
Finished Jun 23 05:01:23 PM PDT 24
Peak memory 214256 kb
Host smart-3e9aca7a-ab31-42ad-897c-e87e94be3dcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466165403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.466165403
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2640972441
Short name T944
Test name
Test status
Simulation time 431649551 ps
CPU time 13.11 seconds
Started Jun 23 05:01:22 PM PDT 24
Finished Jun 23 05:01:35 PM PDT 24
Peak memory 214364 kb
Host smart-8cb69b25-6190-4790-baed-ca288a1b648c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640972441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2640972441
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3061396630
Short name T923
Test name
Test status
Simulation time 531871749 ps
CPU time 4.58 seconds
Started Jun 23 05:01:26 PM PDT 24
Finished Jun 23 05:01:31 PM PDT 24
Peak memory 214120 kb
Host smart-14d815a6-1780-4c11-8f1f-20ce5b31589d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061396630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3061396630
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2771160865
Short name T374
Test name
Test status
Simulation time 679131452 ps
CPU time 2.61 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:33 PM PDT 24
Peak memory 205908 kb
Host smart-c16dd16e-4394-430d-9c83-a0381834ef32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771160865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2771160865
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.578260956
Short name T1061
Test name
Test status
Simulation time 29817250 ps
CPU time 0.72 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:12 PM PDT 24
Peak memory 205664 kb
Host smart-e64ff7ba-a71c-4ede-96ac-2454694be1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578260956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.578260956
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4057611128
Short name T966
Test name
Test status
Simulation time 16570213 ps
CPU time 0.74 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:13 PM PDT 24
Peak memory 205672 kb
Host smart-7df36dc9-602c-4b6d-a2a7-51a3861d0e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057611128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4057611128
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.215403400
Short name T1041
Test name
Test status
Simulation time 30042841 ps
CPU time 0.73 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205588 kb
Host smart-26ee0ba0-9f2e-417d-9671-d1c81ac80ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215403400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.215403400
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3293061884
Short name T1004
Test name
Test status
Simulation time 37923826 ps
CPU time 0.81 seconds
Started Jun 23 05:02:13 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205680 kb
Host smart-166e8749-f89b-43c2-bfb1-9a23f4503c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293061884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3293061884
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2214475706
Short name T1044
Test name
Test status
Simulation time 194919618 ps
CPU time 0.88 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:12 PM PDT 24
Peak memory 205520 kb
Host smart-edaa7083-79a7-42dd-86b8-db7ab91ed97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214475706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2214475706
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3773257147
Short name T954
Test name
Test status
Simulation time 36348111 ps
CPU time 0.71 seconds
Started Jun 23 05:02:12 PM PDT 24
Finished Jun 23 05:02:14 PM PDT 24
Peak memory 205680 kb
Host smart-3c688388-c46e-4e10-a7b0-aca6b28a4c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773257147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3773257147
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3299698674
Short name T997
Test name
Test status
Simulation time 17792024 ps
CPU time 0.7 seconds
Started Jun 23 05:02:09 PM PDT 24
Finished Jun 23 05:02:10 PM PDT 24
Peak memory 205664 kb
Host smart-ef5bee42-d75c-400c-b323-b718e4d5e73b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299698674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3299698674
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.665045956
Short name T964
Test name
Test status
Simulation time 40280964 ps
CPU time 0.73 seconds
Started Jun 23 05:02:10 PM PDT 24
Finished Jun 23 05:02:11 PM PDT 24
Peak memory 205680 kb
Host smart-c8b0687a-194e-4ff9-998d-bb611f67df9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665045956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.665045956
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.845104533
Short name T1014
Test name
Test status
Simulation time 17659634 ps
CPU time 0.75 seconds
Started Jun 23 05:02:11 PM PDT 24
Finished Jun 23 05:02:12 PM PDT 24
Peak memory 205548 kb
Host smart-5bbfba32-7542-4c0a-99b6-d2e6acebf640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845104533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.845104533
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.653204969
Short name T1042
Test name
Test status
Simulation time 78145675 ps
CPU time 0.81 seconds
Started Jun 23 05:02:10 PM PDT 24
Finished Jun 23 05:02:11 PM PDT 24
Peak memory 205680 kb
Host smart-08adc36b-1af6-471e-9e2b-a1b6232fb1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653204969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.653204969
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1884537822
Short name T930
Test name
Test status
Simulation time 22604883 ps
CPU time 1.29 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:31 PM PDT 24
Peak memory 214208 kb
Host smart-8739ce63-d9be-44eb-8f11-a2b672a2bb44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884537822 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1884537822
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3680536140
Short name T1047
Test name
Test status
Simulation time 36937517 ps
CPU time 1.14 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:32 PM PDT 24
Peak memory 205864 kb
Host smart-cfb9a393-28e7-4971-8ffa-401daf89ac06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680536140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3680536140
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2039732105
Short name T1007
Test name
Test status
Simulation time 30635015 ps
CPU time 0.7 seconds
Started Jun 23 05:01:30 PM PDT 24
Finished Jun 23 05:01:31 PM PDT 24
Peak memory 205676 kb
Host smart-0816a7d1-5a23-4676-a7cc-9f087e2afdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039732105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2039732105
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3276887195
Short name T1022
Test name
Test status
Simulation time 55421592 ps
CPU time 2.45 seconds
Started Jun 23 05:01:36 PM PDT 24
Finished Jun 23 05:01:40 PM PDT 24
Peak memory 205864 kb
Host smart-754ec561-5ad6-410a-8962-a704fbdeacbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276887195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3276887195
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2059555745
Short name T1079
Test name
Test status
Simulation time 250892104 ps
CPU time 1.71 seconds
Started Jun 23 05:01:31 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 214364 kb
Host smart-e2fb8c71-73f2-435f-90b2-0c32184b1d2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059555745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2059555745
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3805137123
Short name T967
Test name
Test status
Simulation time 165521318 ps
CPU time 6.52 seconds
Started Jun 23 05:01:36 PM PDT 24
Finished Jun 23 05:01:44 PM PDT 24
Peak memory 220300 kb
Host smart-7eac09ce-35bd-4f04-bc0d-a0023a9f1336
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805137123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3805137123
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2932828223
Short name T932
Test name
Test status
Simulation time 288050273 ps
CPU time 3.43 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 214152 kb
Host smart-d3f2ca89-ca21-4302-965e-df1768ae8bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932828223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2932828223
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.191396970
Short name T941
Test name
Test status
Simulation time 67292926 ps
CPU time 1.23 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 214136 kb
Host smart-74212384-c4dd-44f0-ae2d-e46374335022
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191396970 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.191396970
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2186764858
Short name T980
Test name
Test status
Simulation time 105969061 ps
CPU time 1.24 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 205848 kb
Host smart-871955dc-3291-4f67-b369-d40e1a9b2fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186764858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2186764858
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2610197230
Short name T993
Test name
Test status
Simulation time 19149259 ps
CPU time 0.72 seconds
Started Jun 23 05:01:36 PM PDT 24
Finished Jun 23 05:01:38 PM PDT 24
Peak memory 205576 kb
Host smart-4f0c9f33-ef9f-4581-8919-cd71f81dd7d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610197230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2610197230
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.486069883
Short name T1062
Test name
Test status
Simulation time 215967360 ps
CPU time 1.97 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 205448 kb
Host smart-f472244d-e75b-4306-94a1-c06febb8a7db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486069883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.486069883
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3220977800
Short name T931
Test name
Test status
Simulation time 202134785 ps
CPU time 3.48 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:36 PM PDT 24
Peak memory 219152 kb
Host smart-aee77cde-557c-472c-b30d-e333c61cfb95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220977800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3220977800
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.331961181
Short name T109
Test name
Test status
Simulation time 456142145 ps
CPU time 9.22 seconds
Started Jun 23 05:01:33 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 214304 kb
Host smart-150088e7-0abd-4192-ab2b-f8bd21a82f28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331961181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.331961181
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.703201469
Short name T929
Test name
Test status
Simulation time 99685866 ps
CPU time 3.82 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:40 PM PDT 24
Peak memory 216244 kb
Host smart-7c18dbf1-50e5-42bc-b21b-1cc89e738334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703201469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.703201469
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2963864244
Short name T146
Test name
Test status
Simulation time 592825941 ps
CPU time 3.58 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:37 PM PDT 24
Peak memory 214188 kb
Host smart-d1892e6a-1de8-4e97-8c60-934a957cb0e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963864244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2963864244
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4089652767
Short name T926
Test name
Test status
Simulation time 103657612 ps
CPU time 1.91 seconds
Started Jun 23 05:01:36 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 214284 kb
Host smart-9f9689b6-730f-4c7e-bd70-afe3597dbd72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089652767 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4089652767
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2587993204
Short name T1086
Test name
Test status
Simulation time 18322622 ps
CPU time 0.89 seconds
Started Jun 23 05:01:34 PM PDT 24
Finished Jun 23 05:01:36 PM PDT 24
Peak memory 205796 kb
Host smart-16b5f679-c1c8-45c0-b58e-f1b47496be4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587993204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2587993204
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.128014746
Short name T1076
Test name
Test status
Simulation time 42307121 ps
CPU time 0.8 seconds
Started Jun 23 05:01:36 PM PDT 24
Finished Jun 23 05:01:38 PM PDT 24
Peak memory 205604 kb
Host smart-146fbf8e-97f9-4dfd-8587-1e0a8ecfc7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128014746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.128014746
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.308638971
Short name T1049
Test name
Test status
Simulation time 400178636 ps
CPU time 1.96 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 205948 kb
Host smart-af8c7616-cd19-4e61-af79-b7dce7d52328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308638971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.308638971
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2324996203
Short name T1056
Test name
Test status
Simulation time 95620140 ps
CPU time 2.83 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 214388 kb
Host smart-67ec82e6-e532-4bd8-9dc1-de0a708103f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324996203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2324996203
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2416515541
Short name T132
Test name
Test status
Simulation time 1721131314 ps
CPU time 9.69 seconds
Started Jun 23 05:01:34 PM PDT 24
Finished Jun 23 05:01:45 PM PDT 24
Peak memory 214536 kb
Host smart-cd214002-c7cb-48ac-9af0-4cac0a9b7da0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416515541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2416515541
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.269893299
Short name T970
Test name
Test status
Simulation time 617255273 ps
CPU time 6.23 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 214096 kb
Host smart-8fc96532-aa71-4f00-bee5-019a1cf95374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269893299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.269893299
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3483143722
Short name T1002
Test name
Test status
Simulation time 813353868 ps
CPU time 8.33 seconds
Started Jun 23 05:01:33 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 214160 kb
Host smart-5a229ddb-0162-49fb-a642-1e24f5a9d0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483143722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3483143722
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2431362047
Short name T971
Test name
Test status
Simulation time 31618050 ps
CPU time 1.96 seconds
Started Jun 23 05:01:38 PM PDT 24
Finished Jun 23 05:01:41 PM PDT 24
Peak memory 214168 kb
Host smart-5e7c4bc6-95d0-4d51-b572-3e2ce1fc99a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431362047 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2431362047
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3496512938
Short name T951
Test name
Test status
Simulation time 18141379 ps
CPU time 0.96 seconds
Started Jun 23 05:01:33 PM PDT 24
Finished Jun 23 05:01:35 PM PDT 24
Peak memory 205704 kb
Host smart-f31d179b-f3c8-477c-9a08-bfd8df8a89d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496512938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3496512938
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4006211186
Short name T1026
Test name
Test status
Simulation time 10338103 ps
CPU time 0.84 seconds
Started Jun 23 05:01:32 PM PDT 24
Finished Jun 23 05:01:34 PM PDT 24
Peak memory 205596 kb
Host smart-0b0a9f03-a300-463c-8e60-5a762ab71bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006211186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4006211186
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.560697316
Short name T968
Test name
Test status
Simulation time 50310709 ps
CPU time 2.08 seconds
Started Jun 23 05:01:40 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 205840 kb
Host smart-5275fc5d-7e76-48dd-ac25-2641432daa22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560697316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.560697316
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1061088180
Short name T1084
Test name
Test status
Simulation time 191217683 ps
CPU time 3.08 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 214464 kb
Host smart-28d9295c-fd99-4983-9ddc-7c7f866760d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061088180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1061088180
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2137671477
Short name T938
Test name
Test status
Simulation time 813395870 ps
CPU time 4.94 seconds
Started Jun 23 05:01:31 PM PDT 24
Finished Jun 23 05:01:37 PM PDT 24
Peak memory 214484 kb
Host smart-035fc15a-741e-4d2a-84e7-f66ee5a8857e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137671477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2137671477
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2901837886
Short name T996
Test name
Test status
Simulation time 280008523 ps
CPU time 5.24 seconds
Started Jun 23 05:01:34 PM PDT 24
Finished Jun 23 05:01:40 PM PDT 24
Peak memory 214168 kb
Host smart-032fc6e0-156c-471c-bf23-60880f23d99e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901837886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2901837886
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3499884872
Short name T153
Test name
Test status
Simulation time 569997822 ps
CPU time 4.51 seconds
Started Jun 23 05:01:35 PM PDT 24
Finished Jun 23 05:01:41 PM PDT 24
Peak memory 214172 kb
Host smart-2098ff35-f84f-4b9d-ba50-9c8fdb875520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499884872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3499884872
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1657721508
Short name T1040
Test name
Test status
Simulation time 43211604 ps
CPU time 2.16 seconds
Started Jun 23 05:01:37 PM PDT 24
Finished Jun 23 05:01:40 PM PDT 24
Peak memory 214188 kb
Host smart-d3f0ca8b-a8bc-4d52-a400-abb7e8970ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657721508 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1657721508
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1214763893
Short name T1009
Test name
Test status
Simulation time 54940357 ps
CPU time 1.17 seconds
Started Jun 23 05:01:37 PM PDT 24
Finished Jun 23 05:01:39 PM PDT 24
Peak memory 205816 kb
Host smart-39d61b2a-1661-465f-bc74-f00a3497a6ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214763893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1214763893
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2144060438
Short name T1017
Test name
Test status
Simulation time 27746301 ps
CPU time 0.82 seconds
Started Jun 23 05:01:38 PM PDT 24
Finished Jun 23 05:01:40 PM PDT 24
Peak memory 205604 kb
Host smart-9a3bf24a-6f4f-404b-9e7a-43344559430e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144060438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2144060438
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4133288101
Short name T1075
Test name
Test status
Simulation time 448816203 ps
CPU time 3.28 seconds
Started Jun 23 05:01:38 PM PDT 24
Finished Jun 23 05:01:42 PM PDT 24
Peak memory 205952 kb
Host smart-09c4c14e-1606-4c72-aa36-e63d05cc7880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133288101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4133288101
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3740765295
Short name T112
Test name
Test status
Simulation time 165529710 ps
CPU time 4.68 seconds
Started Jun 23 05:01:37 PM PDT 24
Finished Jun 23 05:01:43 PM PDT 24
Peak memory 214384 kb
Host smart-8721135e-5205-430d-a8f8-1cc8fca3e246
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740765295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3740765295
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2536349603
Short name T945
Test name
Test status
Simulation time 159612713 ps
CPU time 8.42 seconds
Started Jun 23 05:01:36 PM PDT 24
Finished Jun 23 05:01:46 PM PDT 24
Peak memory 214744 kb
Host smart-9cf82fb1-42df-4a9b-8e87-078f4a68aa8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536349603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2536349603
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.455494547
Short name T986
Test name
Test status
Simulation time 520217481 ps
CPU time 3.19 seconds
Started Jun 23 05:01:37 PM PDT 24
Finished Jun 23 05:01:42 PM PDT 24
Peak memory 214116 kb
Host smart-3cde63aa-321d-4b61-99d9-c9a84bb1a01a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455494547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.455494547
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3474758037
Short name T141
Test name
Test status
Simulation time 84333104 ps
CPU time 2.63 seconds
Started Jun 23 05:01:38 PM PDT 24
Finished Jun 23 05:01:42 PM PDT 24
Peak memory 214084 kb
Host smart-99d77c29-17d7-40e2-b8d1-81ff3b2d022b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474758037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3474758037
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.186805235
Short name T830
Test name
Test status
Simulation time 14270660 ps
CPU time 0.91 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:54 PM PDT 24
Peak memory 206092 kb
Host smart-59ccf792-54fd-4a72-8fcd-e3990fadf025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186805235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.186805235
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2850036292
Short name T197
Test name
Test status
Simulation time 499692397 ps
CPU time 5.76 seconds
Started Jun 23 05:02:54 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 214708 kb
Host smart-60ee5ef2-337e-4e35-8e83-524f4c7cad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850036292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2850036292
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3183387430
Short name T568
Test name
Test status
Simulation time 93199194 ps
CPU time 2.7 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:55 PM PDT 24
Peak memory 214264 kb
Host smart-fa9d03db-1247-4270-a895-f22c4f951b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183387430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3183387430
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.340218012
Short name T661
Test name
Test status
Simulation time 304212452 ps
CPU time 2.81 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:02:56 PM PDT 24
Peak memory 208936 kb
Host smart-a067a309-c180-4cff-8a09-10c2f3f31cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340218012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.340218012
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2095029904
Short name T363
Test name
Test status
Simulation time 128017151 ps
CPU time 2.82 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:56 PM PDT 24
Peak memory 222352 kb
Host smart-5217be11-c12d-4a47-8352-e098a4cb1ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095029904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2095029904
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2583432567
Short name T498
Test name
Test status
Simulation time 224501028 ps
CPU time 4.98 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:02:59 PM PDT 24
Peak memory 222496 kb
Host smart-5aedc9ce-e2a7-46fd-99f0-a86b7edf511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583432567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2583432567
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.619480699
Short name T183
Test name
Test status
Simulation time 712294271 ps
CPU time 7.73 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:03:01 PM PDT 24
Peak memory 207456 kb
Host smart-1b4fc0e2-b930-4f99-825a-ba7fb375887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619480699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.619480699
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3669403899
Short name T43
Test name
Test status
Simulation time 545510257 ps
CPU time 15.78 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:03:09 PM PDT 24
Peak memory 234984 kb
Host smart-cf562c72-4583-4ec5-b974-af539d07314e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669403899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3669403899
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1761149210
Short name T540
Test name
Test status
Simulation time 117631353 ps
CPU time 3.33 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:56 PM PDT 24
Peak memory 206884 kb
Host smart-e5c62363-9c0d-4947-93f4-20dfa683e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761149210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1761149210
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3834171706
Short name T899
Test name
Test status
Simulation time 30089791 ps
CPU time 2.25 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:54 PM PDT 24
Peak memory 206976 kb
Host smart-506bb177-3b12-4deb-8add-2680aeb5335c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834171706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3834171706
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.872697318
Short name T220
Test name
Test status
Simulation time 232176612 ps
CPU time 5.74 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 207984 kb
Host smart-c7855147-7ee7-4743-aff9-2c6d75c2b2bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872697318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.872697318
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2681703276
Short name T879
Test name
Test status
Simulation time 368460708 ps
CPU time 4.25 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:02:58 PM PDT 24
Peak memory 208824 kb
Host smart-da05c0e5-9988-45d0-ad21-c2ea476c6108
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681703276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2681703276
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4238400591
Short name T432
Test name
Test status
Simulation time 594149416 ps
CPU time 2.54 seconds
Started Jun 23 05:02:55 PM PDT 24
Finished Jun 23 05:02:58 PM PDT 24
Peak memory 214216 kb
Host smart-75858c25-9b15-456a-a9f3-632f60f9dba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238400591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4238400591
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3043080174
Short name T485
Test name
Test status
Simulation time 5343286715 ps
CPU time 42.86 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:03:35 PM PDT 24
Peak memory 208616 kb
Host smart-993540da-633a-45ba-bf25-e531693dab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043080174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3043080174
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.44764156
Short name T694
Test name
Test status
Simulation time 330168705 ps
CPU time 4.56 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:57 PM PDT 24
Peak memory 218276 kb
Host smart-fcc38934-8668-4698-8787-5e57b0bbd311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44764156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.44764156
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2037864907
Short name T698
Test name
Test status
Simulation time 362676884 ps
CPU time 2.7 seconds
Started Jun 23 05:02:53 PM PDT 24
Finished Jun 23 05:02:56 PM PDT 24
Peak memory 210324 kb
Host smart-b753111f-29ad-4299-9f38-c8db0f65942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037864907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2037864907
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.591633419
Short name T850
Test name
Test status
Simulation time 145552855 ps
CPU time 0.92 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:02:58 PM PDT 24
Peak memory 206092 kb
Host smart-59b36169-e559-4605-8fa6-c3660b1e85e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591633419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.591633419
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1637173565
Short name T752
Test name
Test status
Simulation time 92625901 ps
CPU time 3.98 seconds
Started Jun 23 05:02:59 PM PDT 24
Finished Jun 23 05:03:03 PM PDT 24
Peak memory 209840 kb
Host smart-db66012e-78f5-4230-966b-b2651a3a9455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637173565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1637173565
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2534475978
Short name T2
Test name
Test status
Simulation time 58125155 ps
CPU time 2.06 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:02:58 PM PDT 24
Peak memory 207164 kb
Host smart-67a56757-2e11-44ee-9fc5-68340fcb25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534475978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2534475978
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1349339276
Short name T806
Test name
Test status
Simulation time 136672559 ps
CPU time 4.77 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 214956 kb
Host smart-5baaac50-1c69-4e88-9907-15cb7a9084b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349339276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1349339276
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.176366132
Short name T570
Test name
Test status
Simulation time 178935234 ps
CPU time 2.02 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 220352 kb
Host smart-412dc3c6-a066-4fe0-9a1c-b3505912f86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176366132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.176366132
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3241189555
Short name T636
Test name
Test status
Simulation time 344828103 ps
CPU time 4.34 seconds
Started Jun 23 05:02:55 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 207340 kb
Host smart-86842c55-9f23-41f8-9df3-24738b61b6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241189555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3241189555
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1583856930
Short name T45
Test name
Test status
Simulation time 441381570 ps
CPU time 14.12 seconds
Started Jun 23 05:02:58 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 229784 kb
Host smart-55a8a2d2-32b1-405e-aff5-60b0ce15e7b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583856930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1583856930
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2877806821
Short name T250
Test name
Test status
Simulation time 92164792 ps
CPU time 2.83 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 208680 kb
Host smart-d344c7ad-2ac5-4700-978c-e49b12efbe99
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877806821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2877806821
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.593109280
Short name T567
Test name
Test status
Simulation time 276890112 ps
CPU time 3.44 seconds
Started Jun 23 05:02:59 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 208972 kb
Host smart-affed098-a1fe-446e-bf27-25757262c792
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593109280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.593109280
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.155006458
Short name T285
Test name
Test status
Simulation time 344469836 ps
CPU time 4.26 seconds
Started Jun 23 05:02:59 PM PDT 24
Finished Jun 23 05:03:03 PM PDT 24
Peak memory 208704 kb
Host smart-ddabacec-0588-40fa-9d5d-f8b1baf8de48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155006458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.155006458
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3438285186
Short name T583
Test name
Test status
Simulation time 74399668 ps
CPU time 1.52 seconds
Started Jun 23 05:02:58 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 207868 kb
Host smart-92273db8-c9cf-4670-8cc8-88ed9b7a9404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438285186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3438285186
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1294436688
Short name T607
Test name
Test status
Simulation time 225838891 ps
CPU time 2.59 seconds
Started Jun 23 05:02:52 PM PDT 24
Finished Jun 23 05:02:55 PM PDT 24
Peak memory 206772 kb
Host smart-df4258f5-097c-4f33-8bc3-9f1b4f2cd865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294436688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1294436688
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2534968125
Short name T361
Test name
Test status
Simulation time 1481317534 ps
CPU time 19.16 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:17 PM PDT 24
Peak memory 221004 kb
Host smart-610df7c5-de83-4f88-80db-09b44b6fceda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534968125 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2534968125
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1130778903
Short name T527
Test name
Test status
Simulation time 10808180 ps
CPU time 0.86 seconds
Started Jun 23 05:03:31 PM PDT 24
Finished Jun 23 05:03:33 PM PDT 24
Peak memory 205816 kb
Host smart-6095311a-66b1-4c18-93bb-ba2d9843feec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130778903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1130778903
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4253400017
Short name T390
Test name
Test status
Simulation time 311431438 ps
CPU time 9.13 seconds
Started Jun 23 05:03:27 PM PDT 24
Finished Jun 23 05:03:37 PM PDT 24
Peak memory 215668 kb
Host smart-9b2df8f9-3fc3-4b73-a71c-84a7477a1dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253400017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4253400017
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1879676589
Short name T32
Test name
Test status
Simulation time 176388829 ps
CPU time 1.67 seconds
Started Jun 23 05:03:31 PM PDT 24
Finished Jun 23 05:03:33 PM PDT 24
Peak memory 208304 kb
Host smart-006ace9c-53a9-4254-ad16-dcf38f4a06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879676589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1879676589
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.435428914
Short name T595
Test name
Test status
Simulation time 113563329 ps
CPU time 1.7 seconds
Started Jun 23 05:03:26 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 209288 kb
Host smart-7c7c28a0-cbf2-44ab-a39d-ad5499d43e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435428914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.435428914
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1613683813
Short name T243
Test name
Test status
Simulation time 34693054 ps
CPU time 2.16 seconds
Started Jun 23 05:03:26 PM PDT 24
Finished Jun 23 05:03:29 PM PDT 24
Peak memory 214552 kb
Host smart-3c5ceee2-82c6-4ef5-9122-18a8df1b110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613683813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1613683813
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.135761170
Short name T908
Test name
Test status
Simulation time 243585998 ps
CPU time 2.89 seconds
Started Jun 23 05:03:32 PM PDT 24
Finished Jun 23 05:03:35 PM PDT 24
Peak memory 222532 kb
Host smart-b1212397-ce36-479c-a683-ce72f80fe20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135761170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.135761170
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2397051848
Short name T546
Test name
Test status
Simulation time 247096709 ps
CPU time 3.8 seconds
Started Jun 23 05:03:24 PM PDT 24
Finished Jun 23 05:03:29 PM PDT 24
Peak memory 214360 kb
Host smart-30a95a0e-701c-4e5f-a91b-78a2479cac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397051848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2397051848
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2671901144
Short name T576
Test name
Test status
Simulation time 182077719 ps
CPU time 3.41 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:03:29 PM PDT 24
Peak memory 207492 kb
Host smart-e772dbeb-4853-48dd-b505-07ccb1aa68ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671901144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2671901144
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3699792044
Short name T556
Test name
Test status
Simulation time 170047785 ps
CPU time 2.56 seconds
Started Jun 23 05:03:28 PM PDT 24
Finished Jun 23 05:03:31 PM PDT 24
Peak memory 206808 kb
Host smart-96a1ddea-da33-40de-93e7-094f9ac3091a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699792044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3699792044
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1400208849
Short name T669
Test name
Test status
Simulation time 1207459078 ps
CPU time 34.52 seconds
Started Jun 23 05:03:27 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 207992 kb
Host smart-3da00d1c-c660-475c-a049-8ba0dfb48520
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400208849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1400208849
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1621374215
Short name T665
Test name
Test status
Simulation time 41028378 ps
CPU time 2.38 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 207360 kb
Host smart-606f1f05-9eb8-4131-b00e-db3ee10896c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621374215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1621374215
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2289617441
Short name T484
Test name
Test status
Simulation time 852693928 ps
CPU time 19.94 seconds
Started Jun 23 05:03:26 PM PDT 24
Finished Jun 23 05:03:46 PM PDT 24
Peak memory 208348 kb
Host smart-c46e1610-94fa-4fe1-abe5-2f72b630bb5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289617441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2289617441
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2301292855
Short name T591
Test name
Test status
Simulation time 390420952 ps
CPU time 7.7 seconds
Started Jun 23 05:03:32 PM PDT 24
Finished Jun 23 05:03:40 PM PDT 24
Peak memory 218168 kb
Host smart-4d4eebde-c32a-47cb-a460-6436dbad9ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301292855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2301292855
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2844987369
Short name T831
Test name
Test status
Simulation time 287474873 ps
CPU time 2.61 seconds
Started Jun 23 05:03:28 PM PDT 24
Finished Jun 23 05:03:31 PM PDT 24
Peak memory 206924 kb
Host smart-99bc9a97-bb3b-4ddc-9560-4700b8e6f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844987369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2844987369
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1691547512
Short name T167
Test name
Test status
Simulation time 897198739 ps
CPU time 15.08 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:03:41 PM PDT 24
Peak memory 214320 kb
Host smart-41baf7d5-7a3d-402b-ad60-3691bedb8ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691547512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1691547512
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3473301613
Short name T496
Test name
Test status
Simulation time 59568028 ps
CPU time 2.7 seconds
Started Jun 23 05:03:33 PM PDT 24
Finished Jun 23 05:03:36 PM PDT 24
Peak memory 210332 kb
Host smart-91d531fd-6a14-418d-8440-4681c387558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473301613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3473301613
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3673051652
Short name T686
Test name
Test status
Simulation time 14963520 ps
CPU time 0.9 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:42 PM PDT 24
Peak memory 206100 kb
Host smart-8ee7d6ea-8da7-4b15-bb0c-43da21a3d947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673051652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3673051652
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2311270878
Short name T376
Test name
Test status
Simulation time 74484598 ps
CPU time 4.55 seconds
Started Jun 23 05:03:33 PM PDT 24
Finished Jun 23 05:03:38 PM PDT 24
Peak memory 215512 kb
Host smart-02e137c6-2212-43ed-86d1-78056ac3bf4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311270878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2311270878
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2548763000
Short name T38
Test name
Test status
Simulation time 409207444 ps
CPU time 4.52 seconds
Started Jun 23 05:03:30 PM PDT 24
Finished Jun 23 05:03:35 PM PDT 24
Peak memory 218936 kb
Host smart-e1237b5f-b905-48b0-8600-1a84aa956b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548763000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2548763000
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2067749196
Short name T118
Test name
Test status
Simulation time 441072874 ps
CPU time 7.5 seconds
Started Jun 23 05:03:33 PM PDT 24
Finished Jun 23 05:03:40 PM PDT 24
Peak memory 209520 kb
Host smart-c6e31338-cd65-4a71-9e68-b378aa682bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067749196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2067749196
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4148125193
Short name T854
Test name
Test status
Simulation time 580876300 ps
CPU time 3.66 seconds
Started Jun 23 05:03:32 PM PDT 24
Finished Jun 23 05:03:36 PM PDT 24
Peak memory 214236 kb
Host smart-24ffa7b6-9958-4a9c-9c90-f8d749694001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148125193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4148125193
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4224770104
Short name T730
Test name
Test status
Simulation time 204241620 ps
CPU time 2.42 seconds
Started Jun 23 05:03:31 PM PDT 24
Finished Jun 23 05:03:34 PM PDT 24
Peak memory 206068 kb
Host smart-7a03d1b7-0f98-468f-a316-70d55d092706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224770104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4224770104
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2638745069
Short name T853
Test name
Test status
Simulation time 108795378 ps
CPU time 4.45 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:03:40 PM PDT 24
Peak memory 206648 kb
Host smart-1b9a1482-44af-43b0-9a72-00ba1bbb8142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638745069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2638745069
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1269662037
Short name T785
Test name
Test status
Simulation time 259095908 ps
CPU time 3.98 seconds
Started Jun 23 05:03:34 PM PDT 24
Finished Jun 23 05:03:38 PM PDT 24
Peak memory 207620 kb
Host smart-adb0819a-df23-45c4-a75b-1d63856b49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269662037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1269662037
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.812151245
Short name T530
Test name
Test status
Simulation time 162428801 ps
CPU time 5.39 seconds
Started Jun 23 05:03:34 PM PDT 24
Finished Jun 23 05:03:40 PM PDT 24
Peak memory 208524 kb
Host smart-35a49942-79eb-4a0f-bd6d-2c757bde4ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812151245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.812151245
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4140563960
Short name T187
Test name
Test status
Simulation time 319558102 ps
CPU time 6.76 seconds
Started Jun 23 05:03:33 PM PDT 24
Finished Jun 23 05:03:40 PM PDT 24
Peak memory 206976 kb
Host smart-4788bc50-1478-4659-9033-9fde025149be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140563960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4140563960
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3918681174
Short name T561
Test name
Test status
Simulation time 108865164 ps
CPU time 2.98 seconds
Started Jun 23 05:03:30 PM PDT 24
Finished Jun 23 05:03:33 PM PDT 24
Peak memory 207028 kb
Host smart-6c9361af-326c-4475-8875-d6b64861645f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918681174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3918681174
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3107120129
Short name T602
Test name
Test status
Simulation time 6914204513 ps
CPU time 44.7 seconds
Started Jun 23 05:03:32 PM PDT 24
Finished Jun 23 05:04:17 PM PDT 24
Peak memory 209208 kb
Host smart-ffc667e0-8a5e-4186-a24a-dc35f67b73fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107120129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3107120129
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1088074190
Short name T401
Test name
Test status
Simulation time 144947687 ps
CPU time 2.84 seconds
Started Jun 23 05:03:32 PM PDT 24
Finished Jun 23 05:03:35 PM PDT 24
Peak memory 214308 kb
Host smart-ac2fe30d-dfbb-49e8-9a1a-2ccbe20842d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088074190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1088074190
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.811092364
Short name T411
Test name
Test status
Simulation time 593781554 ps
CPU time 3.96 seconds
Started Jun 23 05:03:32 PM PDT 24
Finished Jun 23 05:03:37 PM PDT 24
Peak memory 206716 kb
Host smart-810d10e9-8e4e-4b14-b119-8ea4e2fe1e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811092364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.811092364
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1940396300
Short name T114
Test name
Test status
Simulation time 734574235 ps
CPU time 15.96 seconds
Started Jun 23 05:03:42 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 222536 kb
Host smart-a3098c3c-35f5-4eec-ab0a-00d27607ea85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940396300 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1940396300
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2937408251
Short name T722
Test name
Test status
Simulation time 1291939543 ps
CPU time 7.56 seconds
Started Jun 23 05:03:31 PM PDT 24
Finished Jun 23 05:03:39 PM PDT 24
Peak memory 208004 kb
Host smart-ad8094a0-d3a1-4790-ac49-acc90c243999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937408251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2937408251
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.250339531
Short name T367
Test name
Test status
Simulation time 132161333 ps
CPU time 2.3 seconds
Started Jun 23 05:03:34 PM PDT 24
Finished Jun 23 05:03:36 PM PDT 24
Peak memory 209976 kb
Host smart-d73d2f3f-1399-4e8d-a921-02ac0eef2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250339531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.250339531
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1071003880
Short name T444
Test name
Test status
Simulation time 87124372 ps
CPU time 0.8 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:42 PM PDT 24
Peak memory 205936 kb
Host smart-de7523ec-f970-4c53-9386-99bb0d3f69ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071003880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1071003880
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2387485874
Short name T622
Test name
Test status
Simulation time 185535827 ps
CPU time 1.69 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:42 PM PDT 24
Peak memory 209772 kb
Host smart-aeea6eaa-52ad-450b-9695-4aab07cb2622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387485874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2387485874
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1937006105
Short name T71
Test name
Test status
Simulation time 498342599 ps
CPU time 4.19 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:45 PM PDT 24
Peak memory 210180 kb
Host smart-5b3a0737-db05-4633-907d-960976cc24ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937006105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1937006105
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1421524417
Short name T332
Test name
Test status
Simulation time 167970220 ps
CPU time 2.55 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 214268 kb
Host smart-a4bbbd17-4716-48b7-9973-e6ba919ef35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421524417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1421524417
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3663507948
Short name T212
Test name
Test status
Simulation time 489565937 ps
CPU time 4.67 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:46 PM PDT 24
Peak memory 208000 kb
Host smart-4142df70-7e4a-4810-918f-116016494bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663507948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3663507948
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1769595561
Short name T900
Test name
Test status
Simulation time 68736368 ps
CPU time 4.07 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 214388 kb
Host smart-15faef35-20c6-45eb-91c6-8b695ceda030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769595561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1769595561
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.324875812
Short name T653
Test name
Test status
Simulation time 69115951 ps
CPU time 3.03 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 206728 kb
Host smart-d91ae930-5436-459e-8209-5b41cc7c6d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324875812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.324875812
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.518218037
Short name T468
Test name
Test status
Simulation time 41559925 ps
CPU time 2.49 seconds
Started Jun 23 05:03:41 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 206948 kb
Host smart-2d5b7e00-8746-45a5-83fb-7c30a5133eb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518218037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.518218037
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1008245392
Short name T381
Test name
Test status
Simulation time 48674866 ps
CPU time 2.47 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 207008 kb
Host smart-8a482043-9069-4157-a08a-beaa0650f5ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008245392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1008245392
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1512328959
Short name T864
Test name
Test status
Simulation time 305637237 ps
CPU time 2.4 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 207004 kb
Host smart-6d61141f-72aa-4ca5-b407-d7ef5cb0b4d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512328959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1512328959
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.839692064
Short name T573
Test name
Test status
Simulation time 165275631 ps
CPU time 2.12 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:41 PM PDT 24
Peak memory 215808 kb
Host smart-227180ee-7941-415f-a40d-cec27378838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839692064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.839692064
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.291782573
Short name T462
Test name
Test status
Simulation time 119933563 ps
CPU time 3.63 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 208704 kb
Host smart-15b1a6cc-0abb-49a6-888f-fa9dc3c2e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291782573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.291782573
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1514661959
Short name T321
Test name
Test status
Simulation time 2997128716 ps
CPU time 29.22 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:04:10 PM PDT 24
Peak memory 215904 kb
Host smart-8d43105d-b177-470e-8b02-52ccc58e5d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514661959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1514661959
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2822673067
Short name T510
Test name
Test status
Simulation time 363425531 ps
CPU time 7.75 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 214312 kb
Host smart-14f697d8-efec-454d-91cc-7f9ab5f85fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822673067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2822673067
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1444778119
Short name T58
Test name
Test status
Simulation time 344728003 ps
CPU time 3.33 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 209912 kb
Host smart-6d710cd3-b1a9-4ca9-8cf1-fe2e41a08266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444778119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1444778119
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1543696945
Short name T499
Test name
Test status
Simulation time 45004049 ps
CPU time 0.79 seconds
Started Jun 23 05:03:43 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 205852 kb
Host smart-bec87757-c770-4eb4-877b-6dd4acdaffc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543696945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1543696945
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3350743263
Short name T574
Test name
Test status
Simulation time 472693508 ps
CPU time 3.15 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:42 PM PDT 24
Peak memory 209008 kb
Host smart-b07d3255-8a81-4c1e-8737-4161c6045122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350743263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3350743263
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2254501608
Short name T857
Test name
Test status
Simulation time 97673868 ps
CPU time 1.63 seconds
Started Jun 23 05:03:36 PM PDT 24
Finished Jun 23 05:03:38 PM PDT 24
Peak memory 207360 kb
Host smart-1ea0bada-d5a4-4a9e-b25a-f2814668ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254501608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2254501608
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3054382475
Short name T859
Test name
Test status
Simulation time 77137303 ps
CPU time 3.52 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 209268 kb
Host smart-392e810a-516a-4c60-9baf-f8deb4438671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054382475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3054382475
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4082996506
Short name T229
Test name
Test status
Simulation time 735163767 ps
CPU time 10.05 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:50 PM PDT 24
Peak memory 208976 kb
Host smart-7e5a892c-939d-44eb-bcaf-25fa63b9977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082996506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4082996506
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2037805524
Short name T713
Test name
Test status
Simulation time 67123327 ps
CPU time 3.44 seconds
Started Jun 23 05:03:42 PM PDT 24
Finished Jun 23 05:03:45 PM PDT 24
Peak memory 208660 kb
Host smart-9486781a-abb6-4f01-b5ff-52c76bd8d2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037805524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2037805524
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1781100212
Short name T596
Test name
Test status
Simulation time 107829548 ps
CPU time 3.75 seconds
Started Jun 23 05:03:38 PM PDT 24
Finished Jun 23 05:03:43 PM PDT 24
Peak memory 208856 kb
Host smart-61bd12cc-c0c0-458d-832b-17d7b038e841
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781100212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1781100212
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3423993318
Short name T228
Test name
Test status
Simulation time 2702759751 ps
CPU time 50.76 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:04:31 PM PDT 24
Peak memory 209184 kb
Host smart-4982f379-fa57-496e-a42b-2113f999fa4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423993318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3423993318
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3815003733
Short name T642
Test name
Test status
Simulation time 60909860 ps
CPU time 3.12 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 206920 kb
Host smart-72f4a1c9-78d1-4067-9c7a-32f9601303ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815003733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3815003733
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3941627460
Short name T289
Test name
Test status
Simulation time 611376221 ps
CPU time 8.25 seconds
Started Jun 23 05:03:39 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 209052 kb
Host smart-61d77303-47b3-4f59-8482-61a61f52aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941627460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3941627460
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1967174582
Short name T739
Test name
Test status
Simulation time 157448510 ps
CPU time 2.52 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 208564 kb
Host smart-9dd07042-a83f-4548-b4b7-3a1eb8b7ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967174582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1967174582
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.372988926
Short name T578
Test name
Test status
Simulation time 1012520500 ps
CPU time 7.46 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 208392 kb
Host smart-5da850f7-7fd8-4427-94c9-4375787b4564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372988926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.372988926
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2902345930
Short name T783
Test name
Test status
Simulation time 33855758 ps
CPU time 1.81 seconds
Started Jun 23 05:03:42 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 209552 kb
Host smart-afe2d143-5e57-4ce0-8344-6a07467f5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902345930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2902345930
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1637538529
Short name T479
Test name
Test status
Simulation time 37630037 ps
CPU time 0.86 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:56 PM PDT 24
Peak memory 205888 kb
Host smart-b6736b61-58f7-45de-a29d-20fb446b40b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637538529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1637538529
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1497856025
Short name T393
Test name
Test status
Simulation time 178512170 ps
CPU time 5.59 seconds
Started Jun 23 05:03:44 PM PDT 24
Finished Jun 23 05:03:50 PM PDT 24
Peak memory 214480 kb
Host smart-7f213840-f27c-43f2-9b2d-8308d17ed7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497856025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1497856025
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3837275386
Short name T500
Test name
Test status
Simulation time 54394272 ps
CPU time 2.61 seconds
Started Jun 23 05:03:44 PM PDT 24
Finished Jun 23 05:03:47 PM PDT 24
Peak memory 214308 kb
Host smart-5ca4254a-49c9-4364-9a63-36b840dcbf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837275386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3837275386
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3218672583
Short name T867
Test name
Test status
Simulation time 79511171 ps
CPU time 3.58 seconds
Started Jun 23 05:03:50 PM PDT 24
Finished Jun 23 05:03:55 PM PDT 24
Peak memory 210264 kb
Host smart-ff191b11-32bf-47f9-a389-f0c5cc0d8908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218672583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3218672583
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4013425977
Short name T851
Test name
Test status
Simulation time 175995499 ps
CPU time 4.4 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 214260 kb
Host smart-c03de3ae-55bf-4399-9182-650c3d1662f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013425977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4013425977
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3304172202
Short name T848
Test name
Test status
Simulation time 176426921 ps
CPU time 3.04 seconds
Started Jun 23 05:03:40 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 209732 kb
Host smart-934190bd-015e-46d8-af0e-e8d31b9c336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304172202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3304172202
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3760912560
Short name T296
Test name
Test status
Simulation time 1053064424 ps
CPU time 6.78 seconds
Started Jun 23 05:03:44 PM PDT 24
Finished Jun 23 05:03:51 PM PDT 24
Peak memory 209396 kb
Host smart-3adf2249-b406-45c9-bc63-42f866ab441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760912560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3760912560
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1482361688
Short name T471
Test name
Test status
Simulation time 2689401726 ps
CPU time 4.98 seconds
Started Jun 23 05:03:43 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 208032 kb
Host smart-c8c00f14-4cd3-4251-a9ab-9221b313ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482361688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1482361688
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3548967789
Short name T688
Test name
Test status
Simulation time 202549614 ps
CPU time 4.01 seconds
Started Jun 23 05:03:44 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 206716 kb
Host smart-eb485138-8278-405d-83ad-8b327318c3b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548967789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3548967789
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.869510230
Short name T619
Test name
Test status
Simulation time 280956438 ps
CPU time 3.42 seconds
Started Jun 23 05:03:44 PM PDT 24
Finished Jun 23 05:03:48 PM PDT 24
Peak memory 208724 kb
Host smart-6a001e0b-27c6-4614-8da4-8995148d3e7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869510230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.869510230
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.872765870
Short name T658
Test name
Test status
Simulation time 36029970 ps
CPU time 2.54 seconds
Started Jun 23 05:03:42 PM PDT 24
Finished Jun 23 05:03:45 PM PDT 24
Peak memory 208636 kb
Host smart-f50d9d19-9b08-4df9-80d0-22f755ca75c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872765870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.872765870
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2295076770
Short name T186
Test name
Test status
Simulation time 101373887 ps
CPU time 2.63 seconds
Started Jun 23 05:03:43 PM PDT 24
Finished Jun 23 05:03:46 PM PDT 24
Peak memory 207304 kb
Host smart-ab3f9ae0-b382-4b3b-8d96-883e94465d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295076770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2295076770
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.921959257
Short name T893
Test name
Test status
Simulation time 62629610 ps
CPU time 2.13 seconds
Started Jun 23 05:03:43 PM PDT 24
Finished Jun 23 05:03:45 PM PDT 24
Peak memory 206704 kb
Host smart-a8dc244a-ae05-47b9-afd6-c9f88c8c336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921959257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.921959257
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3707479902
Short name T707
Test name
Test status
Simulation time 145813638 ps
CPU time 4.76 seconds
Started Jun 23 05:03:44 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 218472 kb
Host smart-315232a4-b530-41f9-864e-e09875d3bd6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707479902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3707479902
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.60315077
Short name T898
Test name
Test status
Simulation time 581678294 ps
CPU time 6.72 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 207328 kb
Host smart-6566b9a9-c570-491d-98b7-a738734db409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60315077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.60315077
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3106693108
Short name T571
Test name
Test status
Simulation time 387994879 ps
CPU time 7.83 seconds
Started Jun 23 05:03:43 PM PDT 24
Finished Jun 23 05:03:51 PM PDT 24
Peak memory 210728 kb
Host smart-c29199d3-36f9-4e85-9828-f685006ca3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106693108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3106693108
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.877517741
Short name T717
Test name
Test status
Simulation time 12026091 ps
CPU time 0.7 seconds
Started Jun 23 05:03:55 PM PDT 24
Finished Jun 23 05:03:56 PM PDT 24
Peak memory 205892 kb
Host smart-0cf8f372-c1da-4f69-9c7c-79d40f2d346a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877517741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.877517741
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1334319688
Short name T218
Test name
Test status
Simulation time 4488319889 ps
CPU time 55.97 seconds
Started Jun 23 05:03:55 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 215688 kb
Host smart-6a594fc5-fdc6-4cfb-8452-041d615a5906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334319688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1334319688
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3965603630
Short name T30
Test name
Test status
Simulation time 659318306 ps
CPU time 6.73 seconds
Started Jun 23 05:03:47 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 210284 kb
Host smart-1f9753a1-ff96-4112-8727-270ec4022591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965603630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3965603630
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3121009656
Short name T837
Test name
Test status
Simulation time 256860670 ps
CPU time 3.67 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:53 PM PDT 24
Peak memory 214376 kb
Host smart-7e7cbfee-c61f-4c26-8b2e-1f879fd5489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121009656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3121009656
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1015278628
Short name T364
Test name
Test status
Simulation time 378936883 ps
CPU time 3.54 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 214280 kb
Host smart-719c8e55-cd3a-4335-9c1a-86a74a030bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015278628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1015278628
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1742129828
Short name T279
Test name
Test status
Simulation time 242421477 ps
CPU time 2.82 seconds
Started Jun 23 05:03:50 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 214268 kb
Host smart-c3f3773d-140f-4bd6-9453-daf8e009b18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742129828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1742129828
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2492814467
Short name T478
Test name
Test status
Simulation time 996494424 ps
CPU time 6.74 seconds
Started Jun 23 05:03:51 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 215744 kb
Host smart-824d4910-1a4a-4d61-b467-fc2f08cac660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492814467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2492814467
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2309944101
Short name T491
Test name
Test status
Simulation time 756211210 ps
CPU time 5.43 seconds
Started Jun 23 05:03:50 PM PDT 24
Finished Jun 23 05:03:56 PM PDT 24
Peak memory 209320 kb
Host smart-726ab73a-40a1-4de2-872a-57a93fa8a15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309944101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2309944101
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2677008778
Short name T681
Test name
Test status
Simulation time 115579594 ps
CPU time 4.59 seconds
Started Jun 23 05:03:50 PM PDT 24
Finished Jun 23 05:03:55 PM PDT 24
Peak memory 208548 kb
Host smart-c0b938a8-9de8-4702-855d-72a84ff05ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677008778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2677008778
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2525895215
Short name T799
Test name
Test status
Simulation time 257329564 ps
CPU time 4.43 seconds
Started Jun 23 05:03:48 PM PDT 24
Finished Jun 23 05:03:53 PM PDT 24
Peak memory 208696 kb
Host smart-f8b46333-d941-4dcd-b553-dcac34936228
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525895215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2525895215
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.75521540
Short name T169
Test name
Test status
Simulation time 358370175 ps
CPU time 10.37 seconds
Started Jun 23 05:03:52 PM PDT 24
Finished Jun 23 05:04:03 PM PDT 24
Peak memory 208516 kb
Host smart-8ead6727-b99d-4cd4-bce1-c85950ec3b70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75521540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.75521540
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.434755001
Short name T77
Test name
Test status
Simulation time 7236600035 ps
CPU time 22.2 seconds
Started Jun 23 05:03:47 PM PDT 24
Finished Jun 23 05:04:10 PM PDT 24
Peak memory 208896 kb
Host smart-1c206b1b-1e51-4bf8-b57b-f79e2f819c26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434755001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.434755001
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2938343494
Short name T422
Test name
Test status
Simulation time 184646219 ps
CPU time 2.42 seconds
Started Jun 23 05:03:52 PM PDT 24
Finished Jun 23 05:03:55 PM PDT 24
Peak memory 209000 kb
Host smart-44e2358f-b247-4469-b9aa-4480f5f0121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938343494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2938343494
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.117510916
Short name T647
Test name
Test status
Simulation time 170645353 ps
CPU time 2.49 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 206956 kb
Host smart-2dde57bf-4c39-477c-8bcb-53c69f9da96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117510916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.117510916
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.963011125
Short name T174
Test name
Test status
Simulation time 2040088226 ps
CPU time 25.3 seconds
Started Jun 23 05:03:53 PM PDT 24
Finished Jun 23 05:04:18 PM PDT 24
Peak memory 222592 kb
Host smart-cabab567-447c-44c8-bc0a-9dc35624f35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963011125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.963011125
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3743254420
Short name T654
Test name
Test status
Simulation time 142100968 ps
CPU time 7.7 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 222636 kb
Host smart-b8892585-6ad2-4f8f-bfd0-12efe9f946bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743254420 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3743254420
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1941499589
Short name T252
Test name
Test status
Simulation time 1270869900 ps
CPU time 4.8 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:55 PM PDT 24
Peak memory 214264 kb
Host smart-a90fdb8b-eba2-4670-900e-56850f911ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941499589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1941499589
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2661038048
Short name T907
Test name
Test status
Simulation time 218392798 ps
CPU time 2.2 seconds
Started Jun 23 05:03:51 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 210120 kb
Host smart-57780a80-27b9-417b-8e62-c184c3020dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661038048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2661038048
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.675133488
Short name T855
Test name
Test status
Simulation time 14191804 ps
CPU time 0.75 seconds
Started Jun 23 05:03:55 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 205960 kb
Host smart-a7ee18fd-6ebd-4d82-b20d-4d5d7336b3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675133488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.675133488
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3710329602
Short name T75
Test name
Test status
Simulation time 218730329 ps
CPU time 4.05 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 214332 kb
Host smart-11517bb4-4519-49f8-bc59-c06a988c6251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710329602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3710329602
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1664196355
Short name T473
Test name
Test status
Simulation time 235140140 ps
CPU time 3.57 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 221756 kb
Host smart-b5243054-efb1-4146-a108-3822e8ab9e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664196355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1664196355
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1905274603
Short name T881
Test name
Test status
Simulation time 25613769 ps
CPU time 2.02 seconds
Started Jun 23 05:03:52 PM PDT 24
Finished Jun 23 05:03:55 PM PDT 24
Peak memory 210292 kb
Host smart-244e6a40-a9e3-4b0c-b41f-1ffc761bcfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905274603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1905274603
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1442641524
Short name T89
Test name
Test status
Simulation time 51971623 ps
CPU time 2.13 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 214448 kb
Host smart-d4c4339f-3ef5-4bce-9773-d717278f42ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442641524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1442641524
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_random.366131444
Short name T338
Test name
Test status
Simulation time 7193420201 ps
CPU time 48.76 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 218472 kb
Host smart-f62434bc-a838-4e21-ba10-b5f4b9450cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366131444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.366131444
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.37197317
Short name T788
Test name
Test status
Simulation time 86637083 ps
CPU time 3.11 seconds
Started Jun 23 05:03:50 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 207476 kb
Host smart-bf944ac0-bff4-405d-b45a-1751e9345671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37197317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.37197317
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.225304445
Short name T489
Test name
Test status
Simulation time 3668922142 ps
CPU time 26.46 seconds
Started Jun 23 05:03:46 PM PDT 24
Finished Jun 23 05:04:13 PM PDT 24
Peak memory 208568 kb
Host smart-0660694e-6882-4967-bfc6-2ded5f26fd91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225304445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.225304445
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1753223314
Short name T652
Test name
Test status
Simulation time 636599675 ps
CPU time 4.5 seconds
Started Jun 23 05:03:49 PM PDT 24
Finished Jun 23 05:03:54 PM PDT 24
Peak memory 206896 kb
Host smart-549ab177-cbe2-456f-9c60-98f987baea2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753223314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1753223314
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1734098773
Short name T554
Test name
Test status
Simulation time 509382279 ps
CPU time 14.49 seconds
Started Jun 23 05:03:52 PM PDT 24
Finished Jun 23 05:04:07 PM PDT 24
Peak memory 208188 kb
Host smart-5255ca7f-c35d-458b-b992-e1ef6deb1ce1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734098773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1734098773
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2349704064
Short name T356
Test name
Test status
Simulation time 221908316 ps
CPU time 2.47 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 208276 kb
Host smart-7dfd8b5e-15ef-437b-bc95-74910170ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349704064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2349704064
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2331376648
Short name T706
Test name
Test status
Simulation time 178652709 ps
CPU time 2.57 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 208784 kb
Host smart-3034b9cb-6c6e-417e-92de-ba11ff668b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331376648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2331376648
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2322693321
Short name T511
Test name
Test status
Simulation time 237247794 ps
CPU time 1.92 seconds
Started Jun 23 05:03:55 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 209060 kb
Host smart-038b2401-dfc6-46ec-abb1-d30166fe6f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322693321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2322693321
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1080680685
Short name T747
Test name
Test status
Simulation time 381970979 ps
CPU time 11.21 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:10 PM PDT 24
Peak memory 218880 kb
Host smart-ebac8a9d-5941-44ba-a8c4-d4e13a2d97e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080680685 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1080680685
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.870226425
Short name T566
Test name
Test status
Simulation time 232015285 ps
CPU time 3.3 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:12 PM PDT 24
Peak memory 207516 kb
Host smart-b67d9129-767f-4c57-8502-3aedd6baa9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870226425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.870226425
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4051059026
Short name T178
Test name
Test status
Simulation time 305092113 ps
CPU time 3.29 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:03 PM PDT 24
Peak memory 210188 kb
Host smart-f1bd5f29-3239-42e8-8238-73e99bd045d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051059026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4051059026
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1317389632
Short name T416
Test name
Test status
Simulation time 17415452 ps
CPU time 1 seconds
Started Jun 23 05:03:57 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 205932 kb
Host smart-13bb85e2-85bf-4b96-832c-6baaa11e7e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317389632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1317389632
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3182181982
Short name T509
Test name
Test status
Simulation time 68495001 ps
CPU time 1.22 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:56 PM PDT 24
Peak memory 207024 kb
Host smart-72770ba6-46d2-4930-ab75-d266d0a579a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182181982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3182181982
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2821606435
Short name T88
Test name
Test status
Simulation time 89581257 ps
CPU time 3.08 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:11 PM PDT 24
Peak memory 214152 kb
Host smart-9c4b7392-780b-4221-8901-6cb5e24e8d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821606435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2821606435
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4201385114
Short name T310
Test name
Test status
Simulation time 47671183 ps
CPU time 3.16 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 214312 kb
Host smart-2bfbf0a1-d934-44ba-9b27-f3cd416874bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201385114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4201385114
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3583881446
Short name T526
Test name
Test status
Simulation time 197883816 ps
CPU time 2.99 seconds
Started Jun 23 05:03:55 PM PDT 24
Finished Jun 23 05:03:59 PM PDT 24
Peak memory 210028 kb
Host smart-ca582ff7-8e2e-4225-9430-d8113c8f54c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583881446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3583881446
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3666528830
Short name T852
Test name
Test status
Simulation time 3897591598 ps
CPU time 17.89 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:26 PM PDT 24
Peak memory 208484 kb
Host smart-8b4e5cc6-7bd0-4e83-9a26-91a468a24cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666528830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3666528830
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1014864377
Short name T708
Test name
Test status
Simulation time 82944505 ps
CPU time 2.62 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 206760 kb
Host smart-94a2dbd4-2c0a-42d2-bd42-d3a3595e5179
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014864377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1014864377
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2141214378
Short name T825
Test name
Test status
Simulation time 487737569 ps
CPU time 5.57 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:04:00 PM PDT 24
Peak memory 209128 kb
Host smart-73df7efb-09e1-40e2-8e29-c02d4c4065b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141214378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2141214378
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1250577368
Short name T451
Test name
Test status
Simulation time 521712557 ps
CPU time 5.49 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 208324 kb
Host smart-400d79ba-7391-43ef-b61c-abb041979f5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250577368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1250577368
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1623499412
Short name T778
Test name
Test status
Simulation time 29087292 ps
CPU time 2.17 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:57 PM PDT 24
Peak memory 218248 kb
Host smart-52b9326c-bf40-40fc-b0ed-9334a5b35279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623499412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1623499412
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2490811248
Short name T715
Test name
Test status
Simulation time 2089755923 ps
CPU time 11.62 seconds
Started Jun 23 05:03:53 PM PDT 24
Finished Jun 23 05:04:05 PM PDT 24
Peak memory 208204 kb
Host smart-d035e0f2-e651-4d02-ab75-6f443dea4ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490811248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2490811248
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2180853922
Short name T550
Test name
Test status
Simulation time 799465547 ps
CPU time 5.92 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 210212 kb
Host smart-6ba28217-c38c-47ae-a34c-1028beb0d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180853922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2180853922
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.40461266
Short name T835
Test name
Test status
Simulation time 112101036 ps
CPU time 2.62 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 210380 kb
Host smart-0dd79138-a2e8-4f2b-b484-3cec8c888ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40461266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.40461266
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1570744847
Short name T408
Test name
Test status
Simulation time 416438181 ps
CPU time 11.39 seconds
Started Jun 23 05:04:00 PM PDT 24
Finished Jun 23 05:04:12 PM PDT 24
Peak memory 214396 kb
Host smart-b5a33d4f-cd50-44c5-84eb-4d9fa1d5987a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570744847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1570744847
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1801965008
Short name T27
Test name
Test status
Simulation time 137767669 ps
CPU time 3.36 seconds
Started Jun 23 05:04:02 PM PDT 24
Finished Jun 23 05:04:05 PM PDT 24
Peak memory 220308 kb
Host smart-421936a6-4766-4fbe-baf3-568a6606e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801965008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1801965008
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1299024901
Short name T56
Test name
Test status
Simulation time 146307142 ps
CPU time 2.53 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 207484 kb
Host smart-9feaedd0-2a8c-44b3-8f16-1dfc5e210391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299024901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1299024901
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2566518421
Short name T94
Test name
Test status
Simulation time 442203582 ps
CPU time 3.7 seconds
Started Jun 23 05:03:57 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 214364 kb
Host smart-e7006d05-a8ad-4e4f-b85d-129570237618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566518421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2566518421
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.262854893
Short name T634
Test name
Test status
Simulation time 92144380 ps
CPU time 2.06 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 214188 kb
Host smart-ceff8da2-6af0-4c4f-903d-caf90931a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262854893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.262854893
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.241849688
Short name T64
Test name
Test status
Simulation time 1671790204 ps
CPU time 24.32 seconds
Started Jun 23 05:04:02 PM PDT 24
Finished Jun 23 05:04:27 PM PDT 24
Peak memory 214324 kb
Host smart-592bdb07-5eb3-49f8-b1ba-89f805b10d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241849688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.241849688
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1090040264
Short name T594
Test name
Test status
Simulation time 1712580545 ps
CPU time 47.73 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 208908 kb
Host smart-6149d755-634f-43b6-854c-0c8ce342f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090040264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1090040264
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2355986955
Short name T703
Test name
Test status
Simulation time 247026843 ps
CPU time 6.64 seconds
Started Jun 23 05:03:56 PM PDT 24
Finished Jun 23 05:04:04 PM PDT 24
Peak memory 208776 kb
Host smart-46dcc273-6b3f-4ccc-b4f1-8e3515349cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355986955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2355986955
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3187913861
Short name T460
Test name
Test status
Simulation time 275743275 ps
CPU time 3.31 seconds
Started Jun 23 05:03:54 PM PDT 24
Finished Jun 23 05:03:59 PM PDT 24
Peak memory 206828 kb
Host smart-2e0c8fde-baec-4f29-b981-79422503ad62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187913861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3187913861
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4173680215
Short name T579
Test name
Test status
Simulation time 846322535 ps
CPU time 6.78 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:06 PM PDT 24
Peak memory 208524 kb
Host smart-f4ee7d57-05cf-4389-9b96-425b9a21b72b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173680215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4173680215
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2357367063
Short name T813
Test name
Test status
Simulation time 181931529 ps
CPU time 3.04 seconds
Started Jun 23 05:04:01 PM PDT 24
Finished Jun 23 05:04:04 PM PDT 24
Peak memory 206904 kb
Host smart-3fc8bad4-7544-4a4b-927a-16be3d688c3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357367063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2357367063
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.178715065
Short name T697
Test name
Test status
Simulation time 216821646 ps
CPU time 3 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 207216 kb
Host smart-faef390e-8dce-49fd-9de8-032f1e085865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178715065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.178715065
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.419233099
Short name T701
Test name
Test status
Simulation time 206797623 ps
CPU time 4.4 seconds
Started Jun 23 05:03:53 PM PDT 24
Finished Jun 23 05:03:58 PM PDT 24
Peak memory 207944 kb
Host smart-ceaac572-38b4-463a-b005-e67204cd141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419233099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.419233099
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.39654327
Short name T125
Test name
Test status
Simulation time 1259420058 ps
CPU time 11.92 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:20 PM PDT 24
Peak memory 218288 kb
Host smart-575e7f49-938d-4d91-a516-19239de2a95b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39654327 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.39654327
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2591849323
Short name T597
Test name
Test status
Simulation time 618783931 ps
CPU time 6.72 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:06 PM PDT 24
Peak memory 207004 kb
Host smart-5616ac29-1059-4684-a620-dc36d0b6c695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591849323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2591849323
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2629666378
Short name T895
Test name
Test status
Simulation time 283934618 ps
CPU time 3.37 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:03 PM PDT 24
Peak memory 210864 kb
Host smart-d566f56a-d3e0-40b6-9e7c-163a12771e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629666378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2629666378
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.137862255
Short name T426
Test name
Test status
Simulation time 11724733 ps
CPU time 0.79 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:09 PM PDT 24
Peak memory 205776 kb
Host smart-80e0abe7-c1c5-4073-8a67-5d8374f6f411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137862255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.137862255
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2645083952
Short name T236
Test name
Test status
Simulation time 132272260 ps
CPU time 2.85 seconds
Started Jun 23 05:03:57 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 215276 kb
Host smart-c22fd765-ea24-4891-840f-927d103ae9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645083952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2645083952
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2720065420
Short name T272
Test name
Test status
Simulation time 1481695885 ps
CPU time 5.19 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:04 PM PDT 24
Peak memory 208676 kb
Host smart-2dce2557-0166-4add-8b89-9a15f491441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720065420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2720065420
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2877116416
Short name T770
Test name
Test status
Simulation time 383598824 ps
CPU time 3.89 seconds
Started Jun 23 05:04:01 PM PDT 24
Finished Jun 23 05:04:06 PM PDT 24
Peak memory 208788 kb
Host smart-877e2369-3f0c-4ae7-8b96-ef3067301d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877116416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2877116416
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2537193394
Short name T819
Test name
Test status
Simulation time 385231537 ps
CPU time 4.59 seconds
Started Jun 23 05:04:08 PM PDT 24
Finished Jun 23 05:04:13 PM PDT 24
Peak memory 222244 kb
Host smart-ce99799e-4f02-4bcd-9998-63afd73523d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537193394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2537193394
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.505409578
Short name T598
Test name
Test status
Simulation time 77419314 ps
CPU time 1.72 seconds
Started Jun 23 05:04:00 PM PDT 24
Finished Jun 23 05:04:02 PM PDT 24
Peak memory 214332 kb
Host smart-4dc053ba-cf24-400e-b97f-10cceb1375e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505409578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.505409578
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1389729554
Short name T798
Test name
Test status
Simulation time 2708777117 ps
CPU time 37.02 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:37 PM PDT 24
Peak memory 218852 kb
Host smart-cddc2d1b-7717-424a-8195-a66cd72c714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389729554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1389729554
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.190588635
Short name T465
Test name
Test status
Simulation time 51472391 ps
CPU time 2.81 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 208544 kb
Host smart-0fcc8ea8-571a-4622-aaa7-dca083095c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190588635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.190588635
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3454952571
Short name T841
Test name
Test status
Simulation time 167363387 ps
CPU time 3.93 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:04 PM PDT 24
Peak memory 206800 kb
Host smart-9606ca2f-eb54-46ab-b6dd-6bc9ce5af479
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454952571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3454952571
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4239061025
Short name T436
Test name
Test status
Simulation time 1233290101 ps
CPU time 6.98 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:05 PM PDT 24
Peak memory 208812 kb
Host smart-e7348124-01fa-4ae7-adce-522b24fe1b4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239061025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4239061025
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2483365867
Short name T481
Test name
Test status
Simulation time 649621479 ps
CPU time 14.41 seconds
Started Jun 23 05:04:00 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 208528 kb
Host smart-59840720-8008-42e1-8802-05ce590b6c5e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483365867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2483365867
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1022816120
Short name T447
Test name
Test status
Simulation time 194210913 ps
CPU time 2.52 seconds
Started Jun 23 05:03:57 PM PDT 24
Finished Jun 23 05:04:00 PM PDT 24
Peak memory 215876 kb
Host smart-f135807f-8053-4864-b53d-ad3ec7c27638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022816120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1022816120
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3011101366
Short name T894
Test name
Test status
Simulation time 98703961 ps
CPU time 2.45 seconds
Started Jun 23 05:03:58 PM PDT 24
Finished Jun 23 05:04:01 PM PDT 24
Peak memory 206772 kb
Host smart-a370c3ba-7c36-4b7a-8f66-fe8af64170ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011101366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3011101366
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1078295301
Short name T821
Test name
Test status
Simulation time 3715406563 ps
CPU time 11.95 seconds
Started Jun 23 05:04:00 PM PDT 24
Finished Jun 23 05:04:12 PM PDT 24
Peak memory 222680 kb
Host smart-70994547-8597-434d-8447-3aaaf2800427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078295301 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1078295301
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2344275700
Short name T397
Test name
Test status
Simulation time 118856500 ps
CPU time 4.94 seconds
Started Jun 23 05:04:03 PM PDT 24
Finished Jun 23 05:04:08 PM PDT 24
Peak memory 208364 kb
Host smart-f8da3d8b-0ea9-463b-be82-0bc8d1163eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344275700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2344275700
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3130248770
Short name T762
Test name
Test status
Simulation time 132907088 ps
CPU time 3.13 seconds
Started Jun 23 05:04:00 PM PDT 24
Finished Jun 23 05:04:04 PM PDT 24
Peak memory 210196 kb
Host smart-438ea7b2-6efb-4a73-8cb0-3cc13b476966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130248770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3130248770
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.498945223
Short name T621
Test name
Test status
Simulation time 42151488 ps
CPU time 0.77 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:03:03 PM PDT 24
Peak memory 205856 kb
Host smart-f2a87010-d098-4bc2-9d07-c606d9176bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498945223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.498945223
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2695610908
Short name T217
Test name
Test status
Simulation time 263397232 ps
CPU time 4.37 seconds
Started Jun 23 05:02:58 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 214292 kb
Host smart-77b70999-ffcc-4d64-93e2-9ad6dbc8597d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695610908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2695610908
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3110475908
Short name T684
Test name
Test status
Simulation time 249481581 ps
CPU time 4.43 seconds
Started Jun 23 05:02:59 PM PDT 24
Finished Jun 23 05:03:04 PM PDT 24
Peak memory 208972 kb
Host smart-890d33f8-5dcf-4c64-9f31-a41106870a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110475908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3110475908
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3221328209
Short name T725
Test name
Test status
Simulation time 327311042 ps
CPU time 3.43 seconds
Started Jun 23 05:02:59 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 207212 kb
Host smart-0566bee4-a85d-4fbb-a417-41b94c03229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221328209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3221328209
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2692588082
Short name T23
Test name
Test status
Simulation time 302833418 ps
CPU time 9.87 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:07 PM PDT 24
Peak memory 214284 kb
Host smart-90b8cfa0-f164-4ebf-9a01-d14f7d8bb84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692588082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2692588082
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1944009439
Short name T330
Test name
Test status
Simulation time 148429271 ps
CPU time 2.37 seconds
Started Jun 23 05:02:58 PM PDT 24
Finished Jun 23 05:03:01 PM PDT 24
Peak memory 214184 kb
Host smart-fed73c17-ae62-40b1-b468-012135e30f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944009439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1944009439
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4185779057
Short name T402
Test name
Test status
Simulation time 270613675 ps
CPU time 5.36 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 220420 kb
Host smart-84c02ee1-fa60-4f08-aaee-f96f695c347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185779057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4185779057
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1358005740
Short name T513
Test name
Test status
Simulation time 357210152 ps
CPU time 6.04 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 209232 kb
Host smart-554f158d-d4e7-492a-9620-c4219668d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358005740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1358005740
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3150835439
Short name T801
Test name
Test status
Simulation time 214487384 ps
CPU time 4.04 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:03:01 PM PDT 24
Peak memory 208584 kb
Host smart-eb0f29ca-cf2d-48e0-a7f0-76cb6876693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150835439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3150835439
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2567825267
Short name T233
Test name
Test status
Simulation time 231454568 ps
CPU time 2.38 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:00 PM PDT 24
Peak memory 206772 kb
Host smart-05fdcbac-4d69-40b4-b335-e9df0b57e327
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567825267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2567825267
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.858868343
Short name T523
Test name
Test status
Simulation time 126363706 ps
CPU time 4.55 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 207984 kb
Host smart-b46dc773-84f6-444d-bfff-3d5e072ae252
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858868343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.858868343
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4200606786
Short name T539
Test name
Test status
Simulation time 198959504 ps
CPU time 5.92 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:04 PM PDT 24
Peak memory 207928 kb
Host smart-5de43a12-051e-467f-a661-d62d24dea24d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200606786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4200606786
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3389698090
Short name T866
Test name
Test status
Simulation time 123156363 ps
CPU time 3.03 seconds
Started Jun 23 05:02:59 PM PDT 24
Finished Jun 23 05:03:02 PM PDT 24
Peak memory 218344 kb
Host smart-f7ced5f1-0996-477b-9132-fb7a02effbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389698090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3389698090
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2544257882
Short name T504
Test name
Test status
Simulation time 1360074591 ps
CPU time 10.65 seconds
Started Jun 23 05:02:57 PM PDT 24
Finished Jun 23 05:03:08 PM PDT 24
Peak memory 207756 kb
Host smart-a825abe1-cad7-4a4a-9426-bed0d932f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544257882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2544257882
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3455243276
Short name T560
Test name
Test status
Simulation time 2291121183 ps
CPU time 21.08 seconds
Started Jun 23 05:02:56 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 208788 kb
Host smart-999b3567-62d8-417d-8eaa-959c2d042c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455243276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3455243276
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.889191732
Short name T387
Test name
Test status
Simulation time 344355179 ps
CPU time 2.78 seconds
Started Jun 23 05:02:58 PM PDT 24
Finished Jun 23 05:03:01 PM PDT 24
Peak memory 210996 kb
Host smart-086c8d63-2123-4215-9616-85be07855bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889191732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.889191732
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2251364764
Short name T502
Test name
Test status
Simulation time 15935158 ps
CPU time 0.85 seconds
Started Jun 23 05:04:04 PM PDT 24
Finished Jun 23 05:04:05 PM PDT 24
Peak memory 205940 kb
Host smart-4ecb9b92-7dd3-4bd7-85ca-498102be87d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251364764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2251364764
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1711910459
Short name T219
Test name
Test status
Simulation time 116630087 ps
CPU time 6.81 seconds
Started Jun 23 05:04:03 PM PDT 24
Finished Jun 23 05:04:11 PM PDT 24
Peak memory 215496 kb
Host smart-fb753b0d-4447-4ec4-8c56-c6bc96642c47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711910459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1711910459
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2183191657
Short name T880
Test name
Test status
Simulation time 52675858 ps
CPU time 2.88 seconds
Started Jun 23 05:04:05 PM PDT 24
Finished Jun 23 05:04:09 PM PDT 24
Peak memory 209740 kb
Host smart-954b17b6-c896-4f57-8702-fd168e8d2d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183191657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2183191657
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2722858439
Short name T425
Test name
Test status
Simulation time 73802762 ps
CPU time 1.87 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:12 PM PDT 24
Peak memory 207240 kb
Host smart-37b3cb00-3106-49d7-8f0c-5e04700843a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722858439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2722858439
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2224141019
Short name T366
Test name
Test status
Simulation time 453817459 ps
CPU time 4.63 seconds
Started Jun 23 05:04:03 PM PDT 24
Finished Jun 23 05:04:08 PM PDT 24
Peak memory 214364 kb
Host smart-e9723678-da65-4ea3-ab02-520a13181724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224141019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2224141019
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2722955714
Short name T223
Test name
Test status
Simulation time 98825745 ps
CPU time 3.2 seconds
Started Jun 23 05:04:03 PM PDT 24
Finished Jun 23 05:04:07 PM PDT 24
Peak memory 214192 kb
Host smart-8da1056c-df8b-4709-8d29-ba7523593bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722955714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2722955714
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3890854506
Short name T630
Test name
Test status
Simulation time 365693965 ps
CPU time 2.67 seconds
Started Jun 23 05:04:05 PM PDT 24
Finished Jun 23 05:04:08 PM PDT 24
Peak memory 206708 kb
Host smart-889e9e3b-9949-4b13-89d2-92fb68b9d707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890854506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3890854506
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2243613420
Short name T664
Test name
Test status
Simulation time 75312778 ps
CPU time 3.61 seconds
Started Jun 23 05:04:06 PM PDT 24
Finished Jun 23 05:04:10 PM PDT 24
Peak memory 209248 kb
Host smart-1eb7efbd-e8f7-4609-a0ff-ca5b6ef5699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243613420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2243613420
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4226776209
Short name T339
Test name
Test status
Simulation time 624741022 ps
CPU time 5.95 seconds
Started Jun 23 05:04:01 PM PDT 24
Finished Jun 23 05:04:07 PM PDT 24
Peak memory 208304 kb
Host smart-d314f517-7e1b-4e5e-ac69-160b64da813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226776209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4226776209
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2437431183
Short name T505
Test name
Test status
Simulation time 91421252 ps
CPU time 2.15 seconds
Started Jun 23 05:04:02 PM PDT 24
Finished Jun 23 05:04:05 PM PDT 24
Peak memory 208588 kb
Host smart-5ef66518-8e12-45e7-b3c4-208eae3edd80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437431183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2437431183
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.266624729
Short name T693
Test name
Test status
Simulation time 117581124 ps
CPU time 3.1 seconds
Started Jun 23 05:03:59 PM PDT 24
Finished Jun 23 05:04:03 PM PDT 24
Peak memory 206896 kb
Host smart-6d4c71b1-e8fd-4f55-a342-50fb0e11312e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266624729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.266624729
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3262936701
Short name T271
Test name
Test status
Simulation time 184396277 ps
CPU time 4.37 seconds
Started Jun 23 05:04:03 PM PDT 24
Finished Jun 23 05:04:08 PM PDT 24
Peak memory 209728 kb
Host smart-1f1ad07f-67b0-4720-ae35-497970fa0113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262936701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3262936701
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.868408232
Short name T418
Test name
Test status
Simulation time 528846965 ps
CPU time 3.83 seconds
Started Jun 23 05:04:01 PM PDT 24
Finished Jun 23 05:04:05 PM PDT 24
Peak memory 208580 kb
Host smart-8a4862be-4266-4223-b290-f471378b9319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868408232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.868408232
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1515306954
Short name T719
Test name
Test status
Simulation time 62174068 ps
CPU time 3.44 seconds
Started Jun 23 05:04:04 PM PDT 24
Finished Jun 23 05:04:08 PM PDT 24
Peak memory 209084 kb
Host smart-f586f860-de4c-4175-b221-8776047a9eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515306954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1515306954
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3467493911
Short name T877
Test name
Test status
Simulation time 132482233 ps
CPU time 4.07 seconds
Started Jun 23 05:04:06 PM PDT 24
Finished Jun 23 05:04:10 PM PDT 24
Peak memory 210564 kb
Host smart-cc760ce4-faca-4897-bbea-12097d15387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467493911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3467493911
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1700003354
Short name T808
Test name
Test status
Simulation time 40490341 ps
CPU time 0.89 seconds
Started Jun 23 05:04:12 PM PDT 24
Finished Jun 23 05:04:14 PM PDT 24
Peak memory 205896 kb
Host smart-34348e23-2ad3-4cbd-8895-eeb5ec9b26a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700003354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1700003354
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4102436372
Short name T239
Test name
Test status
Simulation time 345245083 ps
CPU time 4.75 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 214256 kb
Host smart-1d362b7a-a036-4c41-a78c-f625ae746877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102436372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4102436372
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2394792600
Short name T40
Test name
Test status
Simulation time 444029723 ps
CPU time 7.2 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:18 PM PDT 24
Peak memory 218320 kb
Host smart-78a874aa-ec24-4027-afc6-ad74ed92a258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394792600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2394792600
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3812900636
Short name T519
Test name
Test status
Simulation time 51506238 ps
CPU time 2.57 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:14 PM PDT 24
Peak memory 218272 kb
Host smart-fa92ae42-d889-438e-b08e-8a2e91261b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812900636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3812900636
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2114332542
Short name T93
Test name
Test status
Simulation time 67028550 ps
CPU time 3.37 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 208832 kb
Host smart-cdc16b01-1025-4ca8-b406-c84663e383d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114332542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2114332542
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3613326511
Short name T679
Test name
Test status
Simulation time 148011229 ps
CPU time 4.22 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 220812 kb
Host smart-a243d034-88f4-4b04-b6c4-c27f4d3cbf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613326511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3613326511
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4259418014
Short name T335
Test name
Test status
Simulation time 222739623 ps
CPU time 5.19 seconds
Started Jun 23 05:04:06 PM PDT 24
Finished Jun 23 05:04:11 PM PDT 24
Peak memory 209880 kb
Host smart-55b873d1-7328-43ab-9284-dbd9bc431af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259418014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4259418014
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1984289436
Short name T581
Test name
Test status
Simulation time 81631259 ps
CPU time 2.91 seconds
Started Jun 23 05:04:05 PM PDT 24
Finished Jun 23 05:04:08 PM PDT 24
Peak memory 206652 kb
Host smart-1016e2cf-e341-4fbb-b2e1-d0eba29ab843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984289436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1984289436
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.376905840
Short name T165
Test name
Test status
Simulation time 50389352 ps
CPU time 2.79 seconds
Started Jun 23 05:04:06 PM PDT 24
Finished Jun 23 05:04:09 PM PDT 24
Peak memory 206960 kb
Host smart-472751f8-8201-4b13-bf3e-0f4b8e940c8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376905840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.376905840
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1067773223
Short name T623
Test name
Test status
Simulation time 358080912 ps
CPU time 4.66 seconds
Started Jun 23 05:04:04 PM PDT 24
Finished Jun 23 05:04:09 PM PDT 24
Peak memory 208820 kb
Host smart-ceff913e-0f9b-497e-aec6-664eec7d522e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067773223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1067773223
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.935986291
Short name T441
Test name
Test status
Simulation time 41909387 ps
CPU time 2.42 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:12 PM PDT 24
Peak memory 207000 kb
Host smart-11b40ab2-c4cb-4ef1-bb67-425b5daf3c55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935986291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.935986291
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1216278297
Short name T297
Test name
Test status
Simulation time 649247666 ps
CPU time 3.65 seconds
Started Jun 23 05:04:12 PM PDT 24
Finished Jun 23 05:04:16 PM PDT 24
Peak memory 214500 kb
Host smart-43232eda-db7b-4389-967b-1bb21e3bc108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216278297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1216278297
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1181900998
Short name T914
Test name
Test status
Simulation time 611077280 ps
CPU time 8.63 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 208416 kb
Host smart-1819b73f-6637-4a35-a7e1-7c643cdf08fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181900998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1181900998
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2301593550
Short name T72
Test name
Test status
Simulation time 2005386577 ps
CPU time 19.14 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:31 PM PDT 24
Peak memory 215688 kb
Host smart-da710636-a8a1-4c31-bbd9-37a44b1193a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301593550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2301593550
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2954638712
Short name T147
Test name
Test status
Simulation time 284860027 ps
CPU time 11.47 seconds
Started Jun 23 05:04:09 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 222528 kb
Host smart-cb49fc67-a89b-425d-b416-6a8a32df7718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954638712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2954638712
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.174419428
Short name T635
Test name
Test status
Simulation time 60708126 ps
CPU time 2.46 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:13 PM PDT 24
Peak memory 208396 kb
Host smart-0706aa35-9c1d-442c-ab81-a23dbbf0a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174419428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.174419428
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3758681575
Short name T429
Test name
Test status
Simulation time 40668546 ps
CPU time 1.57 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:13 PM PDT 24
Peak memory 209832 kb
Host smart-f3a6965f-afa5-46a2-baf4-db48f57c7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758681575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3758681575
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2542639614
Short name T590
Test name
Test status
Simulation time 28848324 ps
CPU time 0.81 seconds
Started Jun 23 05:04:23 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 205780 kb
Host smart-88a2ca07-d16c-414d-ac79-e091fa20ca94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542639614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2542639614
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2806715493
Short name T399
Test name
Test status
Simulation time 5987918198 ps
CPU time 25.5 seconds
Started Jun 23 05:04:12 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 215152 kb
Host smart-15a0fb99-eb57-4852-86dc-049c6f76d09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806715493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2806715493
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2648485593
Short name T31
Test name
Test status
Simulation time 37869112 ps
CPU time 2.55 seconds
Started Jun 23 05:04:17 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 209644 kb
Host smart-4d535351-ee1d-418c-bc1b-0ae24a02490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648485593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2648485593
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.589407772
Short name T695
Test name
Test status
Simulation time 16351669 ps
CPU time 1.48 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:12 PM PDT 24
Peak memory 207752 kb
Host smart-26ef7200-fc6f-4a52-864e-390897de4c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589407772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.589407772
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.711783757
Short name T95
Test name
Test status
Simulation time 421164910 ps
CPU time 5.89 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:20 PM PDT 24
Peak memory 208844 kb
Host smart-7f880e50-d0d6-44ed-9335-555547bce4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711783757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.711783757
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1109437925
Short name T827
Test name
Test status
Simulation time 79802733 ps
CPU time 1.65 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 214172 kb
Host smart-68e0866e-7dc3-42d6-8203-f282c9c62ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109437925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1109437925
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1737487029
Short name T716
Test name
Test status
Simulation time 122841585 ps
CPU time 1.99 seconds
Started Jun 23 05:04:12 PM PDT 24
Finished Jun 23 05:04:14 PM PDT 24
Peak memory 206120 kb
Host smart-09143eb3-1fc4-4293-b392-0646e5cd42a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737487029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1737487029
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.441109443
Short name T461
Test name
Test status
Simulation time 184757229 ps
CPU time 4.7 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:16 PM PDT 24
Peak memory 209080 kb
Host smart-cc2f50c4-4269-4a9a-9624-b4e5975f7bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441109443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.441109443
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.733456019
Short name T689
Test name
Test status
Simulation time 103189956 ps
CPU time 2.71 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:14 PM PDT 24
Peak memory 206800 kb
Host smart-b530026a-33d4-4802-a1db-fd89f3dcff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733456019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.733456019
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.459276641
Short name T454
Test name
Test status
Simulation time 427104232 ps
CPU time 3.68 seconds
Started Jun 23 05:04:09 PM PDT 24
Finished Jun 23 05:04:13 PM PDT 24
Peak memory 208548 kb
Host smart-4b3bf570-be19-4d38-9a94-cd17a7401e85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459276641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.459276641
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2936771855
Short name T545
Test name
Test status
Simulation time 20100020 ps
CPU time 1.66 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:14 PM PDT 24
Peak memory 206812 kb
Host smart-a25d5352-8387-42d7-9a7a-df0d17ea2ba0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936771855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2936771855
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3318352686
Short name T503
Test name
Test status
Simulation time 167943079 ps
CPU time 4.57 seconds
Started Jun 23 05:04:10 PM PDT 24
Finished Jun 23 05:04:15 PM PDT 24
Peak memory 208188 kb
Host smart-de03b210-cec9-4fe3-aef1-e91c30fa5c47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318352686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3318352686
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1168861404
Short name T615
Test name
Test status
Simulation time 53221703 ps
CPU time 2.31 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:18 PM PDT 24
Peak memory 208640 kb
Host smart-d117780d-8a62-4b79-b4aa-4b103692dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168861404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1168861404
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3777951794
Short name T493
Test name
Test status
Simulation time 511545545 ps
CPU time 2.82 seconds
Started Jun 23 05:04:11 PM PDT 24
Finished Jun 23 05:04:14 PM PDT 24
Peak memory 208696 kb
Host smart-2c45f196-9787-400b-861b-3832fed4b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777951794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3777951794
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1790150773
Short name T913
Test name
Test status
Simulation time 1591315099 ps
CPU time 18.21 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:33 PM PDT 24
Peak memory 215368 kb
Host smart-d6876dfa-227a-40f0-846f-268f2c49955e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790150773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1790150773
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2702804319
Short name T106
Test name
Test status
Simulation time 798704683 ps
CPU time 18 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:33 PM PDT 24
Peak memory 220252 kb
Host smart-d891c909-d9d8-442b-9b90-9726ba20fd79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702804319 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2702804319
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.626944024
Short name T410
Test name
Test status
Simulation time 289597759 ps
CPU time 3.27 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:18 PM PDT 24
Peak memory 207680 kb
Host smart-185208f3-d412-4863-99f7-0cd8b4d32b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626944024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.626944024
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1888277671
Short name T643
Test name
Test status
Simulation time 1430284294 ps
CPU time 6.58 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 210832 kb
Host smart-954528f1-edfa-4f04-b81c-d230109546b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888277671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1888277671
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1441301180
Short name T599
Test name
Test status
Simulation time 29310841 ps
CPU time 0.74 seconds
Started Jun 23 05:04:21 PM PDT 24
Finished Jun 23 05:04:22 PM PDT 24
Peak memory 205936 kb
Host smart-8d70924e-0155-43d9-9a9c-c7201bc24637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441301180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1441301180
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1125432886
Short name T863
Test name
Test status
Simulation time 216686344 ps
CPU time 2.03 seconds
Started Jun 23 05:04:13 PM PDT 24
Finished Jun 23 05:04:16 PM PDT 24
Peak memory 207616 kb
Host smart-2f14e2dd-8840-4b6b-bfd9-8f58df80e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125432886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1125432886
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2681685682
Short name T829
Test name
Test status
Simulation time 587853084 ps
CPU time 5.23 seconds
Started Jun 23 05:04:16 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 214304 kb
Host smart-69b35e31-365e-4049-96f0-396c9f70b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681685682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2681685682
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.885147676
Short name T807
Test name
Test status
Simulation time 63947205 ps
CPU time 4.89 seconds
Started Jun 23 05:04:16 PM PDT 24
Finished Jun 23 05:04:21 PM PDT 24
Peak memory 210196 kb
Host smart-795e7368-f041-4cdf-92ca-d685ab19d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885147676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.885147676
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3594632164
Short name T341
Test name
Test status
Simulation time 470156953 ps
CPU time 4.19 seconds
Started Jun 23 05:04:15 PM PDT 24
Finished Jun 23 05:04:20 PM PDT 24
Peak memory 207760 kb
Host smart-1d9635b1-e009-4197-81e4-23d0a8613c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594632164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3594632164
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3996678645
Short name T629
Test name
Test status
Simulation time 104772512 ps
CPU time 2.82 seconds
Started Jun 23 05:04:14 PM PDT 24
Finished Jun 23 05:04:17 PM PDT 24
Peak memory 208984 kb
Host smart-e93b6265-0663-421b-a57a-c6d0aeaff210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996678645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3996678645
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.227373985
Short name T870
Test name
Test status
Simulation time 256120529 ps
CPU time 3.07 seconds
Started Jun 23 05:04:13 PM PDT 24
Finished Jun 23 05:04:17 PM PDT 24
Peak memory 208052 kb
Host smart-6f05e605-4648-4b95-9d34-138553310103
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227373985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.227373985
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1318708239
Short name T534
Test name
Test status
Simulation time 382158420 ps
CPU time 4.85 seconds
Started Jun 23 05:04:17 PM PDT 24
Finished Jun 23 05:04:22 PM PDT 24
Peak memory 206836 kb
Host smart-890f27d1-db4f-4014-ae93-ebca059ebf8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318708239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1318708239
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.568196835
Short name T796
Test name
Test status
Simulation time 157472114 ps
CPU time 2.32 seconds
Started Jun 23 05:04:19 PM PDT 24
Finished Jun 23 05:04:22 PM PDT 24
Peak memory 209048 kb
Host smart-9042189d-8c7c-4aac-8e4c-54370e6de8c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568196835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.568196835
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2034723188
Short name T403
Test name
Test status
Simulation time 418426239 ps
CPU time 4.68 seconds
Started Jun 23 05:04:17 PM PDT 24
Finished Jun 23 05:04:22 PM PDT 24
Peak memory 208444 kb
Host smart-1c1dde6a-0bf7-4a91-8e14-227f3c660d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034723188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2034723188
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1013320010
Short name T438
Test name
Test status
Simulation time 263778965 ps
CPU time 3.09 seconds
Started Jun 23 05:04:13 PM PDT 24
Finished Jun 23 05:04:17 PM PDT 24
Peak memory 208396 kb
Host smart-a15ebe33-2c79-47a4-ba5e-8da1c0fa8d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013320010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1013320010
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1603118979
Short name T240
Test name
Test status
Simulation time 1363560160 ps
CPU time 13.12 seconds
Started Jun 23 05:04:15 PM PDT 24
Finished Jun 23 05:04:29 PM PDT 24
Peak memory 215016 kb
Host smart-17c38300-0ac1-40fb-b922-b118accd20c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603118979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1603118979
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3459140557
Short name T843
Test name
Test status
Simulation time 200855357 ps
CPU time 12.6 seconds
Started Jun 23 05:04:17 PM PDT 24
Finished Jun 23 05:04:30 PM PDT 24
Peak memory 222500 kb
Host smart-b9a9e6ca-0eb9-4daf-931a-4884156697c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459140557 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3459140557
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1076326862
Short name T282
Test name
Test status
Simulation time 69030130 ps
CPU time 2.75 seconds
Started Jun 23 05:04:19 PM PDT 24
Finished Jun 23 05:04:22 PM PDT 24
Peak memory 209992 kb
Host smart-48e88437-9944-4d4c-9a09-bcd21d3dd38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076326862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1076326862
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3879224614
Short name T480
Test name
Test status
Simulation time 156223439 ps
CPU time 2.37 seconds
Started Jun 23 05:04:19 PM PDT 24
Finished Jun 23 05:04:22 PM PDT 24
Peak memory 209828 kb
Host smart-9b238c97-13b5-4ea4-a841-77bbbba6fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879224614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3879224614
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4066505120
Short name T662
Test name
Test status
Simulation time 14726754 ps
CPU time 0.96 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 206096 kb
Host smart-f058c755-8a50-4fdd-b745-652db6482c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066505120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4066505120
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.293150298
Short name T342
Test name
Test status
Simulation time 133685776 ps
CPU time 2.69 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 215192 kb
Host smart-38f7b226-f997-4616-916e-787b0b53bd1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293150298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.293150298
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.516699859
Short name T33
Test name
Test status
Simulation time 88433885 ps
CPU time 4.71 seconds
Started Jun 23 05:04:19 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 209844 kb
Host smart-fcf2ff5c-8f64-471a-9528-a93cc0a9f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516699859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.516699859
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2967494351
Short name T1
Test name
Test status
Simulation time 329141682 ps
CPU time 6.01 seconds
Started Jun 23 05:04:29 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 208792 kb
Host smart-9435542c-c0df-4ef3-9d8b-e58726cfa8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967494351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2967494351
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2608423609
Short name T96
Test name
Test status
Simulation time 105696819 ps
CPU time 4.7 seconds
Started Jun 23 05:04:21 PM PDT 24
Finished Jun 23 05:04:26 PM PDT 24
Peak memory 214304 kb
Host smart-b863cfce-9e1b-450a-9dc6-f8157530b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608423609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2608423609
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4214668614
Short name T202
Test name
Test status
Simulation time 127037232 ps
CPU time 3.56 seconds
Started Jun 23 05:04:24 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 214320 kb
Host smart-d767ff54-64d6-44e5-9c2f-23e4e2f76830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214668614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4214668614
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1861293497
Short name T782
Test name
Test status
Simulation time 1497356385 ps
CPU time 6.68 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 208840 kb
Host smart-11d8794d-c0fb-4751-baad-0da0514c7e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861293497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1861293497
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2636442801
Short name T625
Test name
Test status
Simulation time 2572393892 ps
CPU time 49.03 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 208840 kb
Host smart-90ea1aae-3de8-4f09-8e73-63210b6c5b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636442801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2636442801
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2113757380
Short name T544
Test name
Test status
Simulation time 150472208 ps
CPU time 2.42 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 207096 kb
Host smart-30808766-c1a7-4200-b055-e3c8bcb810c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113757380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2113757380
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.951684013
Short name T627
Test name
Test status
Simulation time 39720105 ps
CPU time 2.34 seconds
Started Jun 23 05:04:21 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 206900 kb
Host smart-e98a5c5d-8b6d-43a7-8f8a-394c9f40a2a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951684013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.951684013
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1019750728
Short name T911
Test name
Test status
Simulation time 786074081 ps
CPU time 5.62 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 207740 kb
Host smart-dc1af239-70cc-49fa-ab4d-360a1984386f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019750728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1019750728
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2340332257
Short name T600
Test name
Test status
Simulation time 526896442 ps
CPU time 13.51 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 209856 kb
Host smart-7066083f-c2e0-4b04-9abc-b2a0741282f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340332257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2340332257
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1182599132
Short name T677
Test name
Test status
Simulation time 667845015 ps
CPU time 6.44 seconds
Started Jun 23 05:04:21 PM PDT 24
Finished Jun 23 05:04:29 PM PDT 24
Peak memory 206872 kb
Host smart-e167a643-1e49-409d-b389-8ccf6ce0c56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182599132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1182599132
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.842538547
Short name T177
Test name
Test status
Simulation time 2947350972 ps
CPU time 16.78 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 215604 kb
Host smart-0518edee-6c6f-4b93-a4c2-9f818406a0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842538547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.842538547
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3736054382
Short name T160
Test name
Test status
Simulation time 270788243 ps
CPU time 10.68 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:31 PM PDT 24
Peak memory 222608 kb
Host smart-edf11205-4964-41e1-a85e-89568e38dc35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736054382 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3736054382
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1798234372
Short name T344
Test name
Test status
Simulation time 3285591822 ps
CPU time 12.33 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:34 PM PDT 24
Peak memory 209056 kb
Host smart-fe28f169-c6db-42e5-96c8-41ccee05dbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798234372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1798234372
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3618373520
Short name T372
Test name
Test status
Simulation time 830739689 ps
CPU time 3.35 seconds
Started Jun 23 05:04:24 PM PDT 24
Finished Jun 23 05:04:27 PM PDT 24
Peak memory 210424 kb
Host smart-934fbe05-9a45-43a7-bb28-eb70c991610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618373520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3618373520
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3707926672
Short name T616
Test name
Test status
Simulation time 13442580 ps
CPU time 0.92 seconds
Started Jun 23 05:04:26 PM PDT 24
Finished Jun 23 05:04:27 PM PDT 24
Peak memory 205940 kb
Host smart-e8e3df5a-4c31-4b36-98e7-ce7584f1ad97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707926672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3707926672
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2612890201
Short name T20
Test name
Test status
Simulation time 61617682 ps
CPU time 1.65 seconds
Started Jun 23 05:04:29 PM PDT 24
Finished Jun 23 05:04:31 PM PDT 24
Peak memory 216356 kb
Host smart-7faa1d6e-158e-4267-8f6f-1e8174c167a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612890201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2612890201
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2497093622
Short name T291
Test name
Test status
Simulation time 414857072 ps
CPU time 3.33 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 207664 kb
Host smart-9c4453a0-3428-48f4-8564-9fd1b7d73c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497093622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2497093622
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2974398248
Short name T844
Test name
Test status
Simulation time 188762366 ps
CPU time 7.75 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:33 PM PDT 24
Peak memory 214256 kb
Host smart-26188296-31d9-4d97-9d3f-adc0cfce7746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974398248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2974398248
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.554478630
Short name T213
Test name
Test status
Simulation time 127598331 ps
CPU time 3.31 seconds
Started Jun 23 05:04:24 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 214424 kb
Host smart-451dba18-4545-4feb-a69c-54c6cbfbd802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554478630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.554478630
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1722709729
Short name T274
Test name
Test status
Simulation time 49280768 ps
CPU time 2.8 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 208736 kb
Host smart-6f89f41a-1965-4dfa-abaf-4c13de2818a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722709729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1722709729
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1450104929
Short name T238
Test name
Test status
Simulation time 49230567 ps
CPU time 2.73 seconds
Started Jun 23 05:04:23 PM PDT 24
Finished Jun 23 05:04:26 PM PDT 24
Peak memory 208380 kb
Host smart-cab56db1-501f-4724-af4c-2a162a648ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450104929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1450104929
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1827792947
Short name T517
Test name
Test status
Simulation time 789626911 ps
CPU time 26.71 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:50 PM PDT 24
Peak memory 209200 kb
Host smart-17c77814-807c-4688-8e2e-ebbedb9c9389
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827792947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1827792947
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1801160802
Short name T667
Test name
Test status
Simulation time 190638584 ps
CPU time 2.89 seconds
Started Jun 23 05:04:20 PM PDT 24
Finished Jun 23 05:04:23 PM PDT 24
Peak memory 206824 kb
Host smart-7cd754a0-22f1-4442-838e-5361b75545d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801160802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1801160802
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3901373618
Short name T810
Test name
Test status
Simulation time 1224301281 ps
CPU time 15.49 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:48 PM PDT 24
Peak memory 208352 kb
Host smart-39a85c50-09b7-44a9-b256-9dd22d3bd238
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901373618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3901373618
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.466807422
Short name T477
Test name
Test status
Simulation time 451850697 ps
CPU time 3.62 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:29 PM PDT 24
Peak memory 218572 kb
Host smart-64895a4f-4955-468b-a783-40e31ee69d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466807422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.466807422
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1099664902
Short name T171
Test name
Test status
Simulation time 179401475 ps
CPU time 2.21 seconds
Started Jun 23 05:04:21 PM PDT 24
Finished Jun 23 05:04:24 PM PDT 24
Peak memory 206964 kb
Host smart-17e3a460-a983-47b3-8e27-220fdfd27d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099664902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1099664902
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1858721815
Short name T346
Test name
Test status
Simulation time 1610225166 ps
CPU time 14.29 seconds
Started Jun 23 05:04:24 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 221164 kb
Host smart-f2e52a6f-e9a7-475a-ac62-cdd59ae64c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858721815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1858721815
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2434485733
Short name T117
Test name
Test status
Simulation time 208587991 ps
CPU time 7.91 seconds
Started Jun 23 05:04:26 PM PDT 24
Finished Jun 23 05:04:34 PM PDT 24
Peak memory 219944 kb
Host smart-c4ccbf9c-8722-4676-bc5e-6eb79dcd9087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434485733 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2434485733
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3714370087
Short name T79
Test name
Test status
Simulation time 101929423 ps
CPU time 4.91 seconds
Started Jun 23 05:04:29 PM PDT 24
Finished Jun 23 05:04:34 PM PDT 24
Peak memory 208468 kb
Host smart-12e8828c-2731-4e6b-b3c0-3caa76c27947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714370087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3714370087
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1951689585
Short name T537
Test name
Test status
Simulation time 207822265 ps
CPU time 2.53 seconds
Started Jun 23 05:04:22 PM PDT 24
Finished Jun 23 05:04:25 PM PDT 24
Peak memory 210220 kb
Host smart-57daacd7-ee6e-4584-838e-208c943a57fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951689585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1951689585
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.388490885
Short name T412
Test name
Test status
Simulation time 27559434 ps
CPU time 0.88 seconds
Started Jun 23 05:04:28 PM PDT 24
Finished Jun 23 05:04:30 PM PDT 24
Peak memory 205980 kb
Host smart-1d5473f8-3695-4189-bc0b-e3a6d09d0f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388490885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.388490885
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2311223370
Short name T81
Test name
Test status
Simulation time 140921460 ps
CPU time 2.89 seconds
Started Jun 23 05:04:27 PM PDT 24
Finished Jun 23 05:04:30 PM PDT 24
Peak memory 214508 kb
Host smart-16d23b3f-5fc4-4cba-b822-632f1138c9a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311223370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2311223370
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1353452415
Short name T709
Test name
Test status
Simulation time 149742784 ps
CPU time 2.78 seconds
Started Jun 23 05:04:28 PM PDT 24
Finished Jun 23 05:04:32 PM PDT 24
Peak memory 214628 kb
Host smart-fd01e112-1aa9-4cd2-842e-bebc6ee3ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353452415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1353452415
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1945840986
Short name T612
Test name
Test status
Simulation time 236466615 ps
CPU time 2.03 seconds
Started Jun 23 05:04:26 PM PDT 24
Finished Jun 23 05:04:29 PM PDT 24
Peak memory 209320 kb
Host smart-11263182-6b2d-45c4-9734-d77c00b3e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945840986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1945840986
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1885952405
Short name T365
Test name
Test status
Simulation time 65384898 ps
CPU time 2.02 seconds
Started Jun 23 05:04:24 PM PDT 24
Finished Jun 23 05:04:27 PM PDT 24
Peak memory 215356 kb
Host smart-3740c4d5-3b84-42db-a2bf-6a7b8f34cc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885952405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1885952405
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.390573946
Short name T580
Test name
Test status
Simulation time 397059820 ps
CPU time 5.03 seconds
Started Jun 23 05:04:27 PM PDT 24
Finished Jun 23 05:04:33 PM PDT 24
Peak memory 222404 kb
Host smart-41e1b527-dc55-4071-999d-195c191513ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390573946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.390573946
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1716455992
Short name T883
Test name
Test status
Simulation time 114129651 ps
CPU time 3.31 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 209020 kb
Host smart-998102ef-8524-42b8-b782-357fd542c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716455992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1716455992
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3458008489
Short name T384
Test name
Test status
Simulation time 6588590849 ps
CPU time 26.8 seconds
Started Jun 23 05:04:27 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 218252 kb
Host smart-7facb854-51c8-45d7-92c5-8af9baffa771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458008489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3458008489
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1193578842
Short name T290
Test name
Test status
Simulation time 137972411 ps
CPU time 2.67 seconds
Started Jun 23 05:04:27 PM PDT 24
Finished Jun 23 05:04:30 PM PDT 24
Peak memory 208768 kb
Host smart-73ed10b0-3d9e-48c8-9d10-cf9f6535b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193578842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1193578842
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1182788379
Short name T98
Test name
Test status
Simulation time 852694661 ps
CPU time 5.6 seconds
Started Jun 23 05:04:29 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 207080 kb
Host smart-2383be6c-9244-4d65-abda-393346cd0564
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182788379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1182788379
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2420985602
Short name T463
Test name
Test status
Simulation time 274084300 ps
CPU time 3.23 seconds
Started Jun 23 05:04:27 PM PDT 24
Finished Jun 23 05:04:30 PM PDT 24
Peak memory 207212 kb
Host smart-647ed4e1-d598-42d3-962d-4323dc3a2fc6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420985602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2420985602
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1061148503
Short name T586
Test name
Test status
Simulation time 330983808 ps
CPU time 3.11 seconds
Started Jun 23 05:04:26 PM PDT 24
Finished Jun 23 05:04:29 PM PDT 24
Peak memory 206856 kb
Host smart-52069b82-452e-4343-84b5-ca45f16daa41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061148503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1061148503
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3580152418
Short name T737
Test name
Test status
Simulation time 120425737 ps
CPU time 3.66 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:29 PM PDT 24
Peak memory 214320 kb
Host smart-455afd5e-9ee1-4630-b863-f50e14cb4b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580152418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3580152418
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.541491521
Short name T414
Test name
Test status
Simulation time 22956949 ps
CPU time 1.82 seconds
Started Jun 23 05:04:25 PM PDT 24
Finished Jun 23 05:04:27 PM PDT 24
Peak memory 208424 kb
Host smart-90bcbce2-a9a6-4974-a9af-be8378b339ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541491521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.541491521
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.276712560
Short name T797
Test name
Test status
Simulation time 763532842 ps
CPU time 8.48 seconds
Started Jun 23 05:04:27 PM PDT 24
Finished Jun 23 05:04:36 PM PDT 24
Peak memory 207756 kb
Host smart-423cc88a-e156-4c51-9694-acdeee299fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276712560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.276712560
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1072143935
Short name T113
Test name
Test status
Simulation time 287788969 ps
CPU time 1.77 seconds
Started Jun 23 05:04:26 PM PDT 24
Finished Jun 23 05:04:28 PM PDT 24
Peak memory 209812 kb
Host smart-89dfccbe-d0a2-4644-9e82-e44b20349bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072143935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1072143935
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1876222902
Short name T424
Test name
Test status
Simulation time 13847263 ps
CPU time 0.82 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 205940 kb
Host smart-59017d8d-78e0-4cbc-9c56-af4b440321ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876222902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1876222902
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1624689215
Short name T263
Test name
Test status
Simulation time 1584130746 ps
CPU time 13.85 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 214668 kb
Host smart-c521af89-4349-427f-b51e-7476b4f2ca96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624689215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1624689215
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.540784543
Short name T744
Test name
Test status
Simulation time 2432459856 ps
CPU time 7.07 seconds
Started Jun 23 05:04:31 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 209444 kb
Host smart-f82553d9-e9df-4716-80c9-1aee4cd58a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540784543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.540784543
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1127572675
Short name T802
Test name
Test status
Simulation time 1433853947 ps
CPU time 11.9 seconds
Started Jun 23 05:04:31 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 214304 kb
Host smart-2f2fd620-18b2-47c2-94c9-df30cdcc2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127572675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1127572675
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.793898269
Short name T119
Test name
Test status
Simulation time 156217896 ps
CPU time 2.99 seconds
Started Jun 23 05:04:32 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 222376 kb
Host smart-e667d3c2-e3f5-41b3-8a2b-8834400c1be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793898269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.793898269
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.17396807
Short name T192
Test name
Test status
Simulation time 244303160 ps
CPU time 5.32 seconds
Started Jun 23 05:04:31 PM PDT 24
Finished Jun 23 05:04:37 PM PDT 24
Peak memory 220168 kb
Host smart-1109fc16-1a45-4c6a-ad33-d469510503f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17396807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.17396807
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1490245364
Short name T467
Test name
Test status
Simulation time 67577169 ps
CPU time 3.68 seconds
Started Jun 23 05:04:30 PM PDT 24
Finished Jun 23 05:04:34 PM PDT 24
Peak memory 209908 kb
Host smart-ecaae301-fc30-4329-9cd8-5848e193312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490245364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1490245364
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2740245612
Short name T761
Test name
Test status
Simulation time 108790976 ps
CPU time 3.23 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:37 PM PDT 24
Peak memory 206672 kb
Host smart-3790ff1f-1a52-42de-b8fe-83c31106606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740245612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2740245612
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3155003368
Short name T769
Test name
Test status
Simulation time 32602395 ps
CPU time 2.22 seconds
Started Jun 23 05:04:31 PM PDT 24
Finished Jun 23 05:04:34 PM PDT 24
Peak memory 206720 kb
Host smart-9173a9f4-422e-4c56-8cde-0f9880d7cec7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155003368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3155003368
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2368114697
Short name T336
Test name
Test status
Simulation time 69483746 ps
CPU time 3.29 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:37 PM PDT 24
Peak memory 208868 kb
Host smart-25f37eac-345b-4d10-8648-f924a960e892
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368114697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2368114697
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.592940650
Short name T751
Test name
Test status
Simulation time 55154293 ps
CPU time 2.8 seconds
Started Jun 23 05:04:32 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 207296 kb
Host smart-e540aba8-d8c2-4f46-bfe0-d01f28a6c444
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592940650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.592940650
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.807894223
Short name T704
Test name
Test status
Simulation time 649025000 ps
CPU time 4.37 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:04:38 PM PDT 24
Peak memory 208460 kb
Host smart-50076a28-60bb-42ba-978f-78db905fbefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807894223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.807894223
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2087602099
Short name T494
Test name
Test status
Simulation time 556739521 ps
CPU time 3.87 seconds
Started Jun 23 05:04:34 PM PDT 24
Finished Jun 23 05:04:38 PM PDT 24
Peak memory 206752 kb
Host smart-7be2b5c8-57f9-4cf8-b315-ba88ed0ca762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087602099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2087602099
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1542173120
Short name T626
Test name
Test status
Simulation time 317101069 ps
CPU time 8.62 seconds
Started Jun 23 05:04:32 PM PDT 24
Finished Jun 23 05:04:41 PM PDT 24
Peak memory 222556 kb
Host smart-a7a49407-970a-4df2-b7c5-66b1b74fe8c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542173120 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1542173120
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.813948587
Short name T319
Test name
Test status
Simulation time 1040072982 ps
CPU time 8.01 seconds
Started Jun 23 05:04:34 PM PDT 24
Finished Jun 23 05:04:42 PM PDT 24
Peak memory 208840 kb
Host smart-a2b74e9e-07e3-40f6-8508-ed46952dce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813948587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.813948587
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.950349433
Short name T101
Test name
Test status
Simulation time 20941979 ps
CPU time 1.03 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:38 PM PDT 24
Peak memory 206120 kb
Host smart-bfbf56f4-8edf-4cea-bbf9-3550f4faad7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950349433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.950349433
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.762419415
Short name T743
Test name
Test status
Simulation time 244299135 ps
CPU time 3.59 seconds
Started Jun 23 05:04:38 PM PDT 24
Finished Jun 23 05:04:42 PM PDT 24
Peak memory 214304 kb
Host smart-a7dffc7d-25e4-4119-af5f-4d3eb4a07e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762419415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.762419415
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1002926777
Short name T818
Test name
Test status
Simulation time 65214747 ps
CPU time 2.5 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:40 PM PDT 24
Peak memory 214212 kb
Host smart-c7d51b13-b2be-47c7-bbd0-d05099a1efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002926777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1002926777
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2073764698
Short name T308
Test name
Test status
Simulation time 1042144536 ps
CPU time 4.1 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:42 PM PDT 24
Peak memory 222404 kb
Host smart-6813121c-3623-499a-9940-5af144a4463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073764698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2073764698
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3616043757
Short name T47
Test name
Test status
Simulation time 121869637 ps
CPU time 3.97 seconds
Started Jun 23 05:04:43 PM PDT 24
Finished Jun 23 05:04:48 PM PDT 24
Peak memory 219956 kb
Host smart-e30030a9-8129-4a39-b016-4c61a63dad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616043757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3616043757
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1571340666
Short name T120
Test name
Test status
Simulation time 138600512 ps
CPU time 2.34 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 214316 kb
Host smart-98fb22ad-dd1e-4389-ae45-084194a25e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571340666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1571340666
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1071291067
Short name T604
Test name
Test status
Simulation time 160625456 ps
CPU time 4.19 seconds
Started Jun 23 05:04:32 PM PDT 24
Finished Jun 23 05:04:36 PM PDT 24
Peak memory 208648 kb
Host smart-d094679e-ffaf-40ca-bb7f-63c7f6582933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071291067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1071291067
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2348044101
Short name T352
Test name
Test status
Simulation time 25957824 ps
CPU time 2 seconds
Started Jun 23 05:04:30 PM PDT 24
Finished Jun 23 05:04:32 PM PDT 24
Peak memory 208732 kb
Host smart-c4160662-880d-40dd-9620-3b69b429f2d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348044101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2348044101
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.130669700
Short name T757
Test name
Test status
Simulation time 189907936 ps
CPU time 2.78 seconds
Started Jun 23 05:04:31 PM PDT 24
Finished Jun 23 05:04:35 PM PDT 24
Peak memory 206832 kb
Host smart-8d0ed876-f944-4201-93a2-1eafe29a6700
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130669700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.130669700
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3273575119
Short name T277
Test name
Test status
Simulation time 680583782 ps
CPU time 5.36 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:41 PM PDT 24
Peak memory 207964 kb
Host smart-93074d2b-b79e-4777-9f01-b42d8bdc9bf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273575119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3273575119
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1320011134
Short name T466
Test name
Test status
Simulation time 819079424 ps
CPU time 3.47 seconds
Started Jun 23 05:04:43 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 214288 kb
Host smart-b7b2eb28-6f89-415a-9294-731b51bddf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320011134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1320011134
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3139057916
Short name T874
Test name
Test status
Simulation time 3307450048 ps
CPU time 45.98 seconds
Started Jun 23 05:04:33 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 208516 kb
Host smart-b670f738-a4ac-41f5-86b9-9920380bf746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139057916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3139057916
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1923456375
Short name T858
Test name
Test status
Simulation time 4661149959 ps
CPU time 47.42 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:05:24 PM PDT 24
Peak memory 222704 kb
Host smart-083ff1b6-a85c-4490-b721-81467bf27449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923456375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1923456375
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2755976851
Short name T329
Test name
Test status
Simulation time 343306414 ps
CPU time 13.52 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 220392 kb
Host smart-49e77408-b0fb-4ca1-8545-97013e553ed1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755976851 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2755976851
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.74942322
Short name T359
Test name
Test status
Simulation time 115505286 ps
CPU time 3.76 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:39 PM PDT 24
Peak memory 207688 kb
Host smart-cf113908-b16d-4bbf-b3af-643d20a012d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74942322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.74942322
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.763147604
Short name T15
Test name
Test status
Simulation time 192823498 ps
CPU time 2.28 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:38 PM PDT 24
Peak memory 210224 kb
Host smart-f8fbbe7b-e05d-4376-9659-1dae06f1928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763147604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.763147604
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.394972147
Short name T793
Test name
Test status
Simulation time 42844032 ps
CPU time 0.78 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:36 PM PDT 24
Peak memory 205940 kb
Host smart-9447fbd6-83ad-45ab-a7c5-6ff1d53a2095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394972147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.394972147
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2539567660
Short name T248
Test name
Test status
Simulation time 74421180 ps
CPU time 4.18 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:41 PM PDT 24
Peak memory 214240 kb
Host smart-96573a76-8617-4dc0-9ce1-27c27f9977a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539567660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2539567660
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3602449315
Short name T469
Test name
Test status
Simulation time 69981329 ps
CPU time 2.73 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:40 PM PDT 24
Peak memory 207816 kb
Host smart-5698f813-52ac-47fe-8cfc-e8e51825adf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602449315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3602449315
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2921662009
Short name T222
Test name
Test status
Simulation time 42021966 ps
CPU time 2.28 seconds
Started Jun 23 05:04:43 PM PDT 24
Finished Jun 23 05:04:46 PM PDT 24
Peak memory 217128 kb
Host smart-f0f728ed-a995-4a20-92c2-adf127925815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921662009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2921662009
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2573963162
Short name T60
Test name
Test status
Simulation time 301153327 ps
CPU time 4.14 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:04:46 PM PDT 24
Peak memory 219996 kb
Host smart-aa770801-d509-42c1-93f3-146f864145f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573963162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2573963162
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4224045286
Short name T606
Test name
Test status
Simulation time 377839756 ps
CPU time 9.66 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 209284 kb
Host smart-0f3b1ccd-caf4-409b-b6ad-26e3fa834dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224045286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4224045286
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.417305891
Short name T865
Test name
Test status
Simulation time 81021994 ps
CPU time 3.1 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:40 PM PDT 24
Peak memory 208576 kb
Host smart-1f8e275d-4ac3-41e8-990d-1893d01594f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417305891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.417305891
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3482637019
Short name T549
Test name
Test status
Simulation time 192578235 ps
CPU time 4.46 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:42 PM PDT 24
Peak memory 208196 kb
Host smart-c9ee70b2-cedc-4866-b566-a34acbba7037
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482637019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3482637019
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2668847080
Short name T312
Test name
Test status
Simulation time 226057196 ps
CPU time 5.46 seconds
Started Jun 23 05:04:38 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 209112 kb
Host smart-c269c72d-2fe4-4124-bf33-35c89bb05ed6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668847080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2668847080
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3857074497
Short name T457
Test name
Test status
Simulation time 89397805 ps
CPU time 3.79 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:41 PM PDT 24
Peak memory 208576 kb
Host smart-9ed5cb0e-8508-43a5-bc99-b3ad46b4943e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857074497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3857074497
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.622383645
Short name T624
Test name
Test status
Simulation time 389483856 ps
CPU time 3.35 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:04:40 PM PDT 24
Peak memory 215960 kb
Host smart-e2f566e1-3ef7-48de-a7e5-d245351ed3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622383645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.622383645
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.435970840
Short name T541
Test name
Test status
Simulation time 236849273 ps
CPU time 2.96 seconds
Started Jun 23 05:04:37 PM PDT 24
Finished Jun 23 05:04:40 PM PDT 24
Peak memory 208640 kb
Host smart-374168a3-792a-48a6-8f30-b8748bcc7e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435970840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.435970840
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3608272759
Short name T200
Test name
Test status
Simulation time 2283208200 ps
CPU time 29.98 seconds
Started Jun 23 05:04:36 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 222660 kb
Host smart-e5aedb7c-b80b-41c8-8bdb-3e50cacd8b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608272759 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3608272759
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3199545618
Short name T816
Test name
Test status
Simulation time 1138469209 ps
CPU time 29.15 seconds
Started Jun 23 05:04:39 PM PDT 24
Finished Jun 23 05:05:08 PM PDT 24
Peak memory 208116 kb
Host smart-16d9c4fe-5765-49b1-9682-b231fc724067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199545618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3199545618
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1284246404
Short name T836
Test name
Test status
Simulation time 106201535 ps
CPU time 2.64 seconds
Started Jun 23 05:04:38 PM PDT 24
Finished Jun 23 05:04:41 PM PDT 24
Peak memory 210432 kb
Host smart-70eb0957-5d0d-4cce-b048-e01c98be0cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284246404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1284246404
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4092735363
Short name T732
Test name
Test status
Simulation time 132393311 ps
CPU time 0.77 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:11 PM PDT 24
Peak memory 205940 kb
Host smart-606b8164-c966-478d-ad64-7457baf5b411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092735363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4092735363
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1855295014
Short name T522
Test name
Test status
Simulation time 309287401 ps
CPU time 5.29 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:03:07 PM PDT 24
Peak memory 222572 kb
Host smart-021ad301-3d09-4079-b855-47837862dcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855295014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1855295014
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.880956299
Short name T122
Test name
Test status
Simulation time 664086812 ps
CPU time 3.49 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:07 PM PDT 24
Peak memory 214236 kb
Host smart-6f2128a1-0989-4b9c-b7de-69f03e87d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880956299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.880956299
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1800099393
Short name T823
Test name
Test status
Simulation time 136356405 ps
CPU time 4.5 seconds
Started Jun 23 05:03:05 PM PDT 24
Finished Jun 23 05:03:10 PM PDT 24
Peak memory 214932 kb
Host smart-203614ad-a3be-4b5a-b5ff-24d57e606ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800099393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1800099393
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2970456582
Short name T224
Test name
Test status
Simulation time 102727377 ps
CPU time 2.46 seconds
Started Jun 23 05:03:02 PM PDT 24
Finished Jun 23 05:03:05 PM PDT 24
Peak memory 214184 kb
Host smart-6640b8c8-ba8f-48c0-ba08-e451c6f8cf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970456582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2970456582
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2338734353
Short name T648
Test name
Test status
Simulation time 530322452 ps
CPU time 3.93 seconds
Started Jun 23 05:03:04 PM PDT 24
Finished Jun 23 05:03:08 PM PDT 24
Peak memory 220344 kb
Host smart-a13672b9-4969-4bd4-a7e3-628d5765539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338734353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2338734353
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3587114611
Short name T324
Test name
Test status
Simulation time 111519611 ps
CPU time 2.48 seconds
Started Jun 23 05:03:05 PM PDT 24
Finished Jun 23 05:03:07 PM PDT 24
Peak memory 208288 kb
Host smart-d8216a9c-1a6a-4f34-9334-e52232d33867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587114611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3587114611
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4257112888
Short name T10
Test name
Test status
Simulation time 861296283 ps
CPU time 7.86 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:20 PM PDT 24
Peak memory 230368 kb
Host smart-dc88a809-d37d-4d3b-abb0-af573342cf9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257112888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4257112888
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.956028405
Short name T417
Test name
Test status
Simulation time 114016837 ps
CPU time 3.9 seconds
Started Jun 23 05:03:04 PM PDT 24
Finished Jun 23 05:03:08 PM PDT 24
Peak memory 207944 kb
Host smart-90e3da64-8f02-40fa-b160-3cf77ddd9b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956028405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.956028405
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3933259584
Short name T490
Test name
Test status
Simulation time 126436378 ps
CPU time 3.78 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:07 PM PDT 24
Peak memory 207984 kb
Host smart-861a1e7a-c56b-4324-838e-468313c8efda
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933259584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3933259584
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2939787143
Short name T718
Test name
Test status
Simulation time 144568620 ps
CPU time 4.11 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:08 PM PDT 24
Peak memory 206996 kb
Host smart-e6cecac2-85b4-4141-9fde-0dbbba4b316c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939787143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2939787143
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1448133968
Short name T474
Test name
Test status
Simulation time 241485858 ps
CPU time 2.31 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:05 PM PDT 24
Peak memory 206940 kb
Host smart-450220f8-c1d5-40d1-9b91-c40669e113a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448133968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1448133968
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1034956831
Short name T487
Test name
Test status
Simulation time 126920148 ps
CPU time 2.98 seconds
Started Jun 23 05:03:04 PM PDT 24
Finished Jun 23 05:03:08 PM PDT 24
Peak memory 217972 kb
Host smart-95b910bd-13bd-427d-8e86-99213b35ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034956831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1034956831
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.141240295
Short name T885
Test name
Test status
Simulation time 69551132 ps
CPU time 2.22 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:06 PM PDT 24
Peak memory 206736 kb
Host smart-6a9254d2-69ca-4dc2-adf8-f8c8d0e24b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141240295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.141240295
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1189418932
Short name T663
Test name
Test status
Simulation time 342360319 ps
CPU time 17.34 seconds
Started Jun 23 05:03:05 PM PDT 24
Finished Jun 23 05:03:22 PM PDT 24
Peak memory 221196 kb
Host smart-d521c997-764b-4580-8fda-dd43a3826eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189418932 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1189418932
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1858238096
Short name T13
Test name
Test status
Simulation time 573007247 ps
CPU time 5.61 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:09 PM PDT 24
Peak memory 207708 kb
Host smart-03e8fb60-7cc5-462a-b55d-70b03ddb17b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858238096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1858238096
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2996523595
Short name T55
Test name
Test status
Simulation time 121111185 ps
CPU time 1.86 seconds
Started Jun 23 05:03:03 PM PDT 24
Finished Jun 23 05:03:05 PM PDT 24
Peak memory 210228 kb
Host smart-481ca941-572a-4667-a98a-8377c3aabd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996523595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2996523595
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1168296878
Short name T577
Test name
Test status
Simulation time 44490417 ps
CPU time 0.87 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:04:43 PM PDT 24
Peak memory 205940 kb
Host smart-407c9575-8b8b-4f05-9511-203858e06806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168296878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1168296878
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.357516683
Short name T17
Test name
Test status
Simulation time 82242495 ps
CPU time 3.58 seconds
Started Jun 23 05:04:40 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 214612 kb
Host smart-3dca6369-49b5-4310-a822-992e7bb7a828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357516683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.357516683
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1872980050
Short name T809
Test name
Test status
Simulation time 93866468 ps
CPU time 3.7 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 222452 kb
Host smart-dfd4faf4-4010-4e6f-a7a1-a3d9ae858efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872980050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1872980050
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3945660895
Short name T22
Test name
Test status
Simulation time 141062333 ps
CPU time 2.6 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:04:45 PM PDT 24
Peak memory 208736 kb
Host smart-58ded498-029b-4c2b-b507-9cbb9bd81781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945660895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3945660895
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3743279179
Short name T221
Test name
Test status
Simulation time 120224328 ps
CPU time 2.89 seconds
Started Jun 23 05:04:45 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 214176 kb
Host smart-dd5c371a-4727-45c0-9283-af1b8b10228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743279179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3743279179
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.127401485
Short name T608
Test name
Test status
Simulation time 54279748 ps
CPU time 2.99 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 220052 kb
Host smart-0cf21067-a53b-4386-bb89-b136be5965f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127401485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.127401485
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3639539743
Short name T736
Test name
Test status
Simulation time 98605021 ps
CPU time 4.51 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:04:46 PM PDT 24
Peak memory 214416 kb
Host smart-f89bd7b5-b30b-455f-80ec-3e434d98d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639539743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3639539743
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1555872793
Short name T670
Test name
Test status
Simulation time 311036410 ps
CPU time 4.16 seconds
Started Jun 23 05:04:44 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 206800 kb
Host smart-b7fde37c-0174-4350-b001-fbfadea61c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555872793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1555872793
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3139569308
Short name T298
Test name
Test status
Simulation time 182573216 ps
CPU time 6.63 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 208228 kb
Host smart-8fd5692c-0554-4165-a88c-5321c337558c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139569308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3139569308
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3556242243
Short name T507
Test name
Test status
Simulation time 813632333 ps
CPU time 22.5 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:05:05 PM PDT 24
Peak memory 208992 kb
Host smart-04b187f7-746b-476d-a99e-44b5e97f9eff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556242243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3556242243
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1494216724
Short name T553
Test name
Test status
Simulation time 65152660 ps
CPU time 3.01 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:04:46 PM PDT 24
Peak memory 208748 kb
Host smart-65be90e7-a7d9-4102-ad0f-51d29b671e95
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494216724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1494216724
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2581567765
Short name T458
Test name
Test status
Simulation time 3060075533 ps
CPU time 4.4 seconds
Started Jun 23 05:04:40 PM PDT 24
Finished Jun 23 05:04:45 PM PDT 24
Peak memory 209956 kb
Host smart-34211188-2314-422f-908f-e566c6a4337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581567765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2581567765
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1871735933
Short name T588
Test name
Test status
Simulation time 67248599 ps
CPU time 2.69 seconds
Started Jun 23 05:04:35 PM PDT 24
Finished Jun 23 05:04:38 PM PDT 24
Peak memory 208176 kb
Host smart-1432077c-61f5-4f1d-a687-1433ec111af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871735933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1871735933
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2523936861
Short name T563
Test name
Test status
Simulation time 84042637 ps
CPU time 3.46 seconds
Started Jun 23 05:04:43 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 208296 kb
Host smart-20989afb-3a34-4722-9ec0-074528ddead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523936861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2523936861
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2877743903
Short name T446
Test name
Test status
Simulation time 75841154 ps
CPU time 1.99 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:04:44 PM PDT 24
Peak memory 210012 kb
Host smart-4a5be276-c9dd-469b-81fc-9a9cf69b7fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877743903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2877743903
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2789508275
Short name T515
Test name
Test status
Simulation time 77332694 ps
CPU time 0.95 seconds
Started Jun 23 05:04:49 PM PDT 24
Finished Jun 23 05:04:51 PM PDT 24
Peak memory 206128 kb
Host smart-1ea06ccd-43fd-4718-bb6f-3230447793bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789508275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2789508275
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1896288088
Short name T405
Test name
Test status
Simulation time 276905830 ps
CPU time 11.35 seconds
Started Jun 23 05:04:47 PM PDT 24
Finished Jun 23 05:04:59 PM PDT 24
Peak memory 214284 kb
Host smart-1fea9ffb-a357-4ab4-8b09-e5cb38b6ba85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896288088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1896288088
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2671719111
Short name T24
Test name
Test status
Simulation time 349496752 ps
CPU time 3.22 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 219572 kb
Host smart-be86c37c-ac8f-4e06-8154-d0e168465f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671719111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2671719111
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4024273172
Short name T189
Test name
Test status
Simulation time 238965565 ps
CPU time 4.01 seconds
Started Jun 23 05:04:41 PM PDT 24
Finished Jun 23 05:04:46 PM PDT 24
Peak memory 206932 kb
Host smart-2780f5b5-198a-49ae-8444-504c45584f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024273172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4024273172
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2266377473
Short name T887
Test name
Test status
Simulation time 353217171 ps
CPU time 3.17 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 214364 kb
Host smart-a54487b6-c7f3-4b34-bc81-4feca9f2dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266377473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2266377473
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.871134805
Short name T340
Test name
Test status
Simulation time 304618318 ps
CPU time 3.62 seconds
Started Jun 23 05:04:44 PM PDT 24
Finished Jun 23 05:04:48 PM PDT 24
Peak memory 209408 kb
Host smart-f58b9e8a-73bf-43e3-8132-5b93c08b280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871134805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.871134805
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1889958644
Short name T649
Test name
Test status
Simulation time 386998024 ps
CPU time 4.87 seconds
Started Jun 23 05:04:45 PM PDT 24
Finished Jun 23 05:04:51 PM PDT 24
Peak memory 214200 kb
Host smart-ec379a0c-80d4-4ee9-8bdd-348d3432e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889958644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1889958644
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.943606224
Short name T455
Test name
Test status
Simulation time 720536725 ps
CPU time 4.2 seconds
Started Jun 23 05:04:47 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 206872 kb
Host smart-2e13ab5b-56f3-4fd5-9aac-f649804ff154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943606224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.943606224
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1878889859
Short name T609
Test name
Test status
Simulation time 39375881 ps
CPU time 1.77 seconds
Started Jun 23 05:04:42 PM PDT 24
Finished Jun 23 05:04:45 PM PDT 24
Peak memory 206880 kb
Host smart-9a3d3e61-c709-47fe-a095-b2096bf57293
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878889859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1878889859
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3601938650
Short name T651
Test name
Test status
Simulation time 41570090 ps
CPU time 1.93 seconds
Started Jun 23 05:04:40 PM PDT 24
Finished Jun 23 05:04:42 PM PDT 24
Peak memory 208696 kb
Host smart-891345d7-2e65-4bda-ae4f-a4ffc8ab83f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601938650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3601938650
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2893807014
Short name T666
Test name
Test status
Simulation time 105170251 ps
CPU time 2.83 seconds
Started Jun 23 05:04:44 PM PDT 24
Finished Jun 23 05:04:47 PM PDT 24
Peak memory 206916 kb
Host smart-878b52fe-e4b4-4c99-81b2-62279699d866
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893807014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2893807014
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2050954035
Short name T325
Test name
Test status
Simulation time 624380701 ps
CPU time 4.33 seconds
Started Jun 23 05:04:47 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 208652 kb
Host smart-839b0959-a135-441a-9223-b8915508c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050954035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2050954035
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3163562913
Short name T488
Test name
Test status
Simulation time 5537935827 ps
CPU time 15.89 seconds
Started Jun 23 05:04:40 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 207892 kb
Host smart-170cb84c-1836-4551-bddb-175f5c9cc291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163562913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3163562913
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.4281684092
Short name T162
Test name
Test status
Simulation time 1665781981 ps
CPU time 15.51 seconds
Started Jun 23 05:04:47 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 220640 kb
Host smart-d12faffa-f436-4752-a358-b5e42601c9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281684092 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.4281684092
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.4111989138
Short name T327
Test name
Test status
Simulation time 3911497428 ps
CPU time 46.78 seconds
Started Jun 23 05:04:44 PM PDT 24
Finished Jun 23 05:05:32 PM PDT 24
Peak memory 208444 kb
Host smart-4a6a3810-d71a-4b1f-a305-947e477438bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111989138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.4111989138
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1120528456
Short name T42
Test name
Test status
Simulation time 97975136 ps
CPU time 2.91 seconds
Started Jun 23 05:04:45 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 210556 kb
Host smart-0891d70d-132e-4bd5-b1da-84daf12e2513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120528456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1120528456
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3647521699
Short name T613
Test name
Test status
Simulation time 43101511 ps
CPU time 0.97 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:04:51 PM PDT 24
Peak memory 206044 kb
Host smart-13832eff-1f13-4c8a-8d2e-7c5b590416d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647521699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3647521699
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3090200043
Short name T375
Test name
Test status
Simulation time 42985674 ps
CPU time 3.24 seconds
Started Jun 23 05:04:46 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 215144 kb
Host smart-18bd8c9e-b7c4-4de5-8501-a8065a1763aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090200043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3090200043
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4200445636
Short name T34
Test name
Test status
Simulation time 94890463 ps
CPU time 3.47 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 214612 kb
Host smart-95cf9a01-da3c-4da0-9481-19d506d9db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200445636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4200445636
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.339935315
Short name T826
Test name
Test status
Simulation time 119685810 ps
CPU time 2.26 seconds
Started Jun 23 05:04:46 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 214264 kb
Host smart-295b0c05-0c97-4ea4-8b17-e006cd60280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339935315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.339935315
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3732515340
Short name T789
Test name
Test status
Simulation time 214471051 ps
CPU time 5 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 214356 kb
Host smart-1151c3ad-ebe1-4e53-a07e-d04044aad28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732515340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3732515340
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1613421792
Short name T582
Test name
Test status
Simulation time 65551442 ps
CPU time 2.73 seconds
Started Jun 23 05:04:46 PM PDT 24
Finished Jun 23 05:04:49 PM PDT 24
Peak memory 214140 kb
Host smart-afce080c-890c-462d-9141-3cf7243b9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613421792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1613421792
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1149746668
Short name T396
Test name
Test status
Simulation time 90364913 ps
CPU time 2.23 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:51 PM PDT 24
Peak memory 219604 kb
Host smart-d4d453b4-6597-48af-884a-0db61dcb274d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149746668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1149746668
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2882779766
Short name T905
Test name
Test status
Simulation time 3605509983 ps
CPU time 37.59 seconds
Started Jun 23 05:04:49 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 209648 kb
Host smart-3b032d73-1752-4d18-a088-72ea2c156276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882779766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2882779766
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.502708461
Short name T575
Test name
Test status
Simulation time 292233108 ps
CPU time 3.39 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:04:53 PM PDT 24
Peak memory 206124 kb
Host smart-0d3d7e2b-c0c6-40be-ad34-07e23c65f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502708461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.502708461
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3786796861
Short name T815
Test name
Test status
Simulation time 108994650 ps
CPU time 3.04 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 207268 kb
Host smart-39097825-042f-442b-a8df-debfdac7e85b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786796861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3786796861
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1617691907
Short name T434
Test name
Test status
Simulation time 863508134 ps
CPU time 5.14 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 208552 kb
Host smart-f153d572-2736-4d18-9f06-193c42b019e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617691907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1617691907
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4005764584
Short name T492
Test name
Test status
Simulation time 728260163 ps
CPU time 5.33 seconds
Started Jun 23 05:04:46 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 209048 kb
Host smart-f3a12c09-4177-4817-835c-2d3b9b329c47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005764584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4005764584
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2591102031
Short name T180
Test name
Test status
Simulation time 403381215 ps
CPU time 3.48 seconds
Started Jun 23 05:04:47 PM PDT 24
Finished Jun 23 05:04:51 PM PDT 24
Peak memory 208596 kb
Host smart-c333ae81-90ef-4acb-917e-8ba8f1220ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591102031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2591102031
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.374292583
Short name T765
Test name
Test status
Simulation time 62842892 ps
CPU time 2.7 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:52 PM PDT 24
Peak memory 207096 kb
Host smart-339e9984-e76e-4b49-be1f-dbecf4c5b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374292583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.374292583
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.4147531808
Short name T323
Test name
Test status
Simulation time 455006401 ps
CPU time 12.78 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 219668 kb
Host smart-9313d877-ef94-4a07-ab3c-e7e55244570a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147531808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4147531808
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2897516315
Short name T301
Test name
Test status
Simulation time 949885094 ps
CPU time 5.07 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:58 PM PDT 24
Peak memory 208180 kb
Host smart-dd2b64a8-31ad-4f6c-bf0e-91676fadbbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897516315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2897516315
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2450966025
Short name T123
Test name
Test status
Simulation time 91802996 ps
CPU time 2.49 seconds
Started Jun 23 05:04:48 PM PDT 24
Finished Jun 23 05:04:51 PM PDT 24
Peak memory 210328 kb
Host smart-40189982-ebb5-4a3d-a402-528338120544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450966025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2450966025
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3187966191
Short name T645
Test name
Test status
Simulation time 27168223 ps
CPU time 0.78 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:53 PM PDT 24
Peak memory 205844 kb
Host smart-e9383031-cea1-451b-b08e-5377a5b5d0e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187966191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3187966191
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.820060606
Short name T392
Test name
Test status
Simulation time 1659579563 ps
CPU time 42.98 seconds
Started Jun 23 05:04:57 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 214720 kb
Host smart-a64ca7ed-00a7-4ea2-8f9a-a5e31cc94c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820060606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.820060606
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.749830072
Short name T39
Test name
Test status
Simulation time 68836080 ps
CPU time 3.23 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 209648 kb
Host smart-b7aacfdc-0e57-4670-910c-e5c49e0a679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749830072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.749830072
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3361234777
Short name T565
Test name
Test status
Simulation time 111361499 ps
CPU time 2.96 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 214212 kb
Host smart-9c1bf011-d7a6-4a01-99b5-ea25d9c5bcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361234777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3361234777
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.962504614
Short name T687
Test name
Test status
Simulation time 219072319 ps
CPU time 4.04 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 209548 kb
Host smart-68777e4f-5ebe-445c-86c2-e48924a16ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962504614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.962504614
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2887320130
Short name T786
Test name
Test status
Simulation time 681263271 ps
CPU time 3.48 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 222344 kb
Host smart-aaffd208-7167-42a8-b898-4d9e30da48ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887320130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2887320130
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3694394424
Short name T657
Test name
Test status
Simulation time 251481084 ps
CPU time 2.74 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 207460 kb
Host smart-b0daaab5-1ff6-4306-9953-d5178392d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694394424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3694394424
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1935024014
Short name T678
Test name
Test status
Simulation time 473090248 ps
CPU time 4.66 seconds
Started Jun 23 05:04:54 PM PDT 24
Finished Jun 23 05:04:59 PM PDT 24
Peak memory 208520 kb
Host smart-9e242500-b6d4-4fed-a821-9b8375184578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935024014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1935024014
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3975114245
Short name T288
Test name
Test status
Simulation time 309709915 ps
CPU time 3.07 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:04:54 PM PDT 24
Peak memory 208564 kb
Host smart-8f5aa2cd-167a-412e-afe3-88ad302ed987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975114245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3975114245
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3268474916
Short name T824
Test name
Test status
Simulation time 1169862937 ps
CPU time 15.56 seconds
Started Jun 23 05:04:46 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 208020 kb
Host smart-a60665c0-dea2-4d77-a2c0-c4d59d408554
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268474916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3268474916
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1991489297
Short name T676
Test name
Test status
Simulation time 1210033616 ps
CPU time 7.04 seconds
Started Jun 23 05:04:46 PM PDT 24
Finished Jun 23 05:04:54 PM PDT 24
Peak memory 208612 kb
Host smart-d24c18ea-78ea-47f2-8975-1c9cd6c29c14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991489297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1991489297
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3032600113
Short name T650
Test name
Test status
Simulation time 215227569 ps
CPU time 6.05 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:58 PM PDT 24
Peak memory 207876 kb
Host smart-e5fc753a-16b2-44f4-abfb-bb88c5099fc8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032600113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3032600113
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1311358463
Short name T518
Test name
Test status
Simulation time 91696704 ps
CPU time 3.73 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 218140 kb
Host smart-78be6f91-5321-473c-92e7-5335450a9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311358463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1311358463
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3452529940
Short name T876
Test name
Test status
Simulation time 1118295152 ps
CPU time 4.96 seconds
Started Jun 23 05:04:50 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 206856 kb
Host smart-ca44b2d4-c708-437b-b8eb-983af6fffff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452529940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3452529940
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.4266031406
Short name T357
Test name
Test status
Simulation time 65989800 ps
CPU time 3.97 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 209868 kb
Host smart-edc7b81f-8785-40b3-8c32-a4ce43eda78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266031406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4266031406
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2285914519
Short name T721
Test name
Test status
Simulation time 45433076 ps
CPU time 0.86 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 205936 kb
Host smart-f0fc8873-aa06-41e8-ab39-eb80d7af0851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285914519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2285914519
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2406599982
Short name T727
Test name
Test status
Simulation time 44257853 ps
CPU time 2.06 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:55 PM PDT 24
Peak memory 208268 kb
Host smart-b1023782-cf16-45c9-a7be-41191a61440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406599982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2406599982
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1552294571
Short name T244
Test name
Test status
Simulation time 250728812 ps
CPU time 3.66 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 220864 kb
Host smart-f7049a0b-dc85-4d16-a0b7-1a39b2e91fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552294571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1552294571
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.721617864
Short name T564
Test name
Test status
Simulation time 85444936 ps
CPU time 4.23 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 218980 kb
Host smart-70f1d86b-f3ac-4f33-8d09-398759438c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721617864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.721617864
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.924527438
Short name T237
Test name
Test status
Simulation time 284752263 ps
CPU time 7.44 seconds
Started Jun 23 05:04:55 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 207772 kb
Host smart-1a63d0e0-6446-4d1c-9f31-3344eba650fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924527438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.924527438
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4244856788
Short name T675
Test name
Test status
Simulation time 131424143 ps
CPU time 2.55 seconds
Started Jun 23 05:04:54 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 208608 kb
Host smart-215dcbe4-6da1-4451-8ab8-f6d8064a9ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244856788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4244856788
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1594730811
Short name T711
Test name
Test status
Simulation time 107755742 ps
CPU time 2.9 seconds
Started Jun 23 05:04:54 PM PDT 24
Finished Jun 23 05:04:57 PM PDT 24
Peak memory 208356 kb
Host smart-626dcb20-3ca6-4e28-8d74-80abc00ec6fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594730811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1594730811
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1818837333
Short name T714
Test name
Test status
Simulation time 107002148 ps
CPU time 2.13 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:53 PM PDT 24
Peak memory 209020 kb
Host smart-7d641538-c2ac-4691-a70a-cdf3975e67ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818837333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1818837333
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3677522340
Short name T700
Test name
Test status
Simulation time 359647543 ps
CPU time 5.81 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:59 PM PDT 24
Peak memory 208964 kb
Host smart-ded57f57-16c4-42bb-93c4-3a951c89bbf8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677522340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3677522340
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3099829492
Short name T400
Test name
Test status
Simulation time 65935420 ps
CPU time 1.79 seconds
Started Jun 23 05:04:51 PM PDT 24
Finished Jun 23 05:04:53 PM PDT 24
Peak memory 207996 kb
Host smart-483de4e8-3796-4620-a7f6-cecc8db3b0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099829492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3099829492
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.69731696
Short name T805
Test name
Test status
Simulation time 223645071 ps
CPU time 4.74 seconds
Started Jun 23 05:04:53 PM PDT 24
Finished Jun 23 05:04:58 PM PDT 24
Peak memory 206688 kb
Host smart-c20443b5-3756-440b-b5e4-11fae9369ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69731696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.69731696
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2474540114
Short name T196
Test name
Test status
Simulation time 89301917473 ps
CPU time 276.43 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:09:29 PM PDT 24
Peak memory 222572 kb
Host smart-fbe63cfd-b016-4a81-abec-ecc5f97e093c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474540114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2474540114
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.249358630
Short name T148
Test name
Test status
Simulation time 1059016727 ps
CPU time 11.22 seconds
Started Jun 23 05:04:54 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 219788 kb
Host smart-65c28550-8546-401d-b252-eb3c7ba3f2de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249358630 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.249358630
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2395645999
Short name T692
Test name
Test status
Simulation time 1086371739 ps
CPU time 8.53 seconds
Started Jun 23 05:04:54 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 209492 kb
Host smart-a8c19207-4f00-467a-b910-1d61b97f0821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395645999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2395645999
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2340052804
Short name T54
Test name
Test status
Simulation time 112742979 ps
CPU time 2.56 seconds
Started Jun 23 05:04:55 PM PDT 24
Finished Jun 23 05:04:58 PM PDT 24
Peak memory 210116 kb
Host smart-7fe97e0b-bf60-492c-9eeb-e46274b4d1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340052804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2340052804
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1321796922
Short name T476
Test name
Test status
Simulation time 61103572 ps
CPU time 0.92 seconds
Started Jun 23 05:05:00 PM PDT 24
Finished Jun 23 05:05:01 PM PDT 24
Peak memory 206196 kb
Host smart-e4a44153-7d59-4fa1-bbbd-cf1b718603e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321796922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1321796922
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2409663360
Short name T78
Test name
Test status
Simulation time 129421143 ps
CPU time 2.91 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 214328 kb
Host smart-413a0679-0052-46ef-a353-6cdeed3a7ca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409663360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2409663360
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2425466629
Short name T16
Test name
Test status
Simulation time 105736850 ps
CPU time 3.32 seconds
Started Jun 23 05:05:01 PM PDT 24
Finished Jun 23 05:05:05 PM PDT 24
Peak memory 214600 kb
Host smart-e02fd490-9cf7-4651-8b4a-833cccb78d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425466629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2425466629
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4143648993
Short name T378
Test name
Test status
Simulation time 245724690 ps
CPU time 2.51 seconds
Started Jun 23 05:05:00 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 208816 kb
Host smart-57dda0a8-6dfc-4e75-ac89-eedc737312e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143648993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4143648993
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3261335578
Short name T506
Test name
Test status
Simulation time 276421379 ps
CPU time 4.29 seconds
Started Jun 23 05:04:56 PM PDT 24
Finished Jun 23 05:05:01 PM PDT 24
Peak memory 208768 kb
Host smart-456c8656-66fb-41b4-a8f2-1d39dfd830cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261335578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3261335578
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3167665091
Short name T912
Test name
Test status
Simulation time 170086160 ps
CPU time 7.65 seconds
Started Jun 23 05:04:58 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 222436 kb
Host smart-af11f900-0c51-4753-8649-98a3a0cdada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167665091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3167665091
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3877200480
Short name T734
Test name
Test status
Simulation time 91041556 ps
CPU time 2.74 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 214252 kb
Host smart-7abb99ac-2f3a-451f-ab67-8e3d5b0cede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877200480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3877200480
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3579210621
Short name T748
Test name
Test status
Simulation time 178436298 ps
CPU time 3.21 seconds
Started Jun 23 05:04:58 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 208600 kb
Host smart-8e9e0a7c-cf6a-49af-8c8c-16c5923fbe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579210621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3579210621
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3900592801
Short name T232
Test name
Test status
Simulation time 246306977 ps
CPU time 3.23 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 208520 kb
Host smart-289f0201-5d79-4d38-bc63-e5c835e63b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900592801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3900592801
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.332189917
Short name T428
Test name
Test status
Simulation time 410789753 ps
CPU time 2.93 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 206908 kb
Host smart-02db45c9-8bfa-49de-84c9-bd096e2ca394
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332189917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.332189917
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.281919191
Short name T833
Test name
Test status
Simulation time 728428350 ps
CPU time 6.37 seconds
Started Jun 23 05:04:57 PM PDT 24
Finished Jun 23 05:05:04 PM PDT 24
Peak memory 208784 kb
Host smart-82e4085c-6de9-4039-9798-f3c8a25820aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281919191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.281919191
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3757598198
Short name T822
Test name
Test status
Simulation time 327924348 ps
CPU time 2.74 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 206932 kb
Host smart-f8833621-2783-47ab-aee3-414295286292
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757598198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3757598198
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1357764151
Short name T409
Test name
Test status
Simulation time 34609575 ps
CPU time 2.56 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 216028 kb
Host smart-58399e98-fc9b-49ad-95a8-2a5196bce0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357764151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1357764151
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3947514761
Short name T182
Test name
Test status
Simulation time 124037104 ps
CPU time 2.94 seconds
Started Jun 23 05:04:52 PM PDT 24
Finished Jun 23 05:04:56 PM PDT 24
Peak memory 208628 kb
Host smart-5d23c5ad-8279-40e0-be86-136c83586633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947514761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3947514761
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1314605330
Short name T903
Test name
Test status
Simulation time 757238681 ps
CPU time 27.49 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:27 PM PDT 24
Peak memory 222444 kb
Host smart-78dc3f6b-0115-40e8-b005-6fc1af6c4537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314605330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1314605330
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1355425240
Short name T195
Test name
Test status
Simulation time 362940115 ps
CPU time 14.98 seconds
Started Jun 23 05:04:57 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 222608 kb
Host smart-fbff406d-ca7c-44a5-828c-f061f562717d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355425240 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1355425240
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1808814420
Short name T266
Test name
Test status
Simulation time 570193164 ps
CPU time 14.87 seconds
Started Jun 23 05:05:00 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 210188 kb
Host smart-c7ba57e5-8328-483a-939b-8e7117dd80c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808814420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1808814420
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2711106628
Short name T369
Test name
Test status
Simulation time 992228477 ps
CPU time 6.45 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 211228 kb
Host smart-c4037abf-ad91-496f-8be6-993c66c2d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711106628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2711106628
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3432203836
Short name T82
Test name
Test status
Simulation time 19971514 ps
CPU time 0.7 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 205976 kb
Host smart-d1b99ab9-781b-4713-8617-9e9203c1e212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432203836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3432203836
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1975607651
Short name T407
Test name
Test status
Simulation time 49440273 ps
CPU time 3.62 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 215564 kb
Host smart-e8c36515-dbcc-48c7-bfc1-bf858eeccbac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975607651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1975607651
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1389629602
Short name T811
Test name
Test status
Simulation time 794631704 ps
CPU time 14.12 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 214296 kb
Host smart-934c06a5-91f3-4baa-8e73-63641c9aa210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389629602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1389629602
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.193836411
Short name T497
Test name
Test status
Simulation time 144253436 ps
CPU time 2.08 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 207488 kb
Host smart-0faf74a5-a1f6-4594-8417-3ebd65e679c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193836411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.193836411
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3556891815
Short name T902
Test name
Test status
Simulation time 329132657 ps
CPU time 9.53 seconds
Started Jun 23 05:05:05 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 214264 kb
Host smart-384d8348-8ae0-49b2-b528-ec4166edadd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556891815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3556891815
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2459395273
Short name T890
Test name
Test status
Simulation time 106445231 ps
CPU time 3.08 seconds
Started Jun 23 05:05:03 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 214264 kb
Host smart-50af42c9-9836-4909-84d0-c978e080cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459395273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2459395273
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1920580174
Short name T198
Test name
Test status
Simulation time 64806004 ps
CPU time 2.23 seconds
Started Jun 23 05:04:58 PM PDT 24
Finished Jun 23 05:05:01 PM PDT 24
Peak memory 219152 kb
Host smart-7fa57c21-76d8-47aa-b64d-335b3491951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920580174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1920580174
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3594329997
Short name T179
Test name
Test status
Simulation time 45992980 ps
CPU time 3.25 seconds
Started Jun 23 05:04:58 PM PDT 24
Finished Jun 23 05:05:02 PM PDT 24
Peak memory 214240 kb
Host smart-9e2f0c95-a0d3-4341-9015-8d69dbfe83ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594329997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3594329997
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.861978769
Short name T910
Test name
Test status
Simulation time 372434150 ps
CPU time 5.88 seconds
Started Jun 23 05:04:58 PM PDT 24
Finished Jun 23 05:05:04 PM PDT 24
Peak memory 208608 kb
Host smart-5ae38a21-08a3-4025-bbec-88e1d8505d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861978769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.861978769
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2038504079
Short name T601
Test name
Test status
Simulation time 264382582 ps
CPU time 3.1 seconds
Started Jun 23 05:05:00 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 206776 kb
Host smart-b304da8f-c79b-492e-8a01-4999e35b0b05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038504079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2038504079
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3798967203
Short name T897
Test name
Test status
Simulation time 3115039848 ps
CPU time 20.43 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 208412 kb
Host smart-bb512a89-f02c-4b6d-9f1a-c0a5d61332e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798967203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3798967203
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3561431983
Short name T551
Test name
Test status
Simulation time 324506976 ps
CPU time 2.96 seconds
Started Jun 23 05:04:58 PM PDT 24
Finished Jun 23 05:05:01 PM PDT 24
Peak memory 208464 kb
Host smart-0e43dcf4-6cb2-442f-8189-436a07813669
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561431983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3561431983
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4104712374
Short name T292
Test name
Test status
Simulation time 197564399 ps
CPU time 5.11 seconds
Started Jun 23 05:05:04 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 209060 kb
Host smart-20ff69d6-845d-44d9-9535-10474e1eb6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104712374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4104712374
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1005239435
Short name T380
Test name
Test status
Simulation time 441043190 ps
CPU time 5.71 seconds
Started Jun 23 05:05:00 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 208660 kb
Host smart-fe40bfef-9afc-46f1-a0d4-9e20493901bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005239435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1005239435
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.425003318
Short name T188
Test name
Test status
Simulation time 514069166 ps
CPU time 12.04 seconds
Started Jun 23 05:05:03 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 208024 kb
Host smart-21ea75da-f159-4d88-96b2-bad9a03b58dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425003318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.425003318
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.729118674
Short name T68
Test name
Test status
Simulation time 378260907 ps
CPU time 17.97 seconds
Started Jun 23 05:05:04 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 221828 kb
Host smart-cb286188-2fcb-4f57-be26-482b010dd6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729118674 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.729118674
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3238974281
Short name T231
Test name
Test status
Simulation time 234339072 ps
CPU time 6.62 seconds
Started Jun 23 05:04:59 PM PDT 24
Finished Jun 23 05:05:06 PM PDT 24
Peak memory 218448 kb
Host smart-d33ebf41-745f-414d-8cfc-143412eb225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238974281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3238974281
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2242049757
Short name T370
Test name
Test status
Simulation time 11441803304 ps
CPU time 20.22 seconds
Started Jun 23 05:05:02 PM PDT 24
Finished Jun 23 05:05:23 PM PDT 24
Peak memory 211476 kb
Host smart-03b3eb3d-7669-415a-a573-3d65c968b7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242049757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2242049757
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2091285594
Short name T773
Test name
Test status
Simulation time 15109172 ps
CPU time 0.77 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 205904 kb
Host smart-e8166803-92d4-4fb8-aff0-6e6c62c17752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091285594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2091285594
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1305949368
Short name T345
Test name
Test status
Simulation time 119452532 ps
CPU time 2.55 seconds
Started Jun 23 05:05:05 PM PDT 24
Finished Jun 23 05:05:08 PM PDT 24
Peak memory 214928 kb
Host smart-298fc5fe-6d05-45ae-9517-48724189e262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305949368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1305949368
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.219547238
Short name T170
Test name
Test status
Simulation time 72555673 ps
CPU time 1.45 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 214596 kb
Host smart-4e49c0cf-c3d4-44e2-a8f4-a7d143ede28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219547238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.219547238
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2796790747
Short name T781
Test name
Test status
Simulation time 38557837 ps
CPU time 2.26 seconds
Started Jun 23 05:05:01 PM PDT 24
Finished Jun 23 05:05:03 PM PDT 24
Peak memory 214304 kb
Host smart-7eaed7a5-1003-4a30-b1dc-6c4d72bab744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796790747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2796790747
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2301097543
Short name T742
Test name
Test status
Simulation time 48462788 ps
CPU time 2.01 seconds
Started Jun 23 05:05:02 PM PDT 24
Finished Jun 23 05:05:04 PM PDT 24
Peak memory 214216 kb
Host smart-8615aba3-0d7e-4ef5-b91d-e9ab7b188319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301097543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2301097543
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3101126785
Short name T768
Test name
Test status
Simulation time 99014383 ps
CPU time 2.18 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 214268 kb
Host smart-82f5470e-6373-4d6e-b832-cfbab7222e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101126785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3101126785
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3518568017
Short name T475
Test name
Test status
Simulation time 111250512 ps
CPU time 3.92 seconds
Started Jun 23 05:05:03 PM PDT 24
Finished Jun 23 05:05:07 PM PDT 24
Peak memory 220640 kb
Host smart-b2e07dc6-cd29-4f95-933a-fa3e66a9e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518568017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3518568017
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1670546913
Short name T699
Test name
Test status
Simulation time 132112009 ps
CPU time 5.66 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 210156 kb
Host smart-c27f4107-5b0d-4cee-836a-5b7e9254e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670546913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1670546913
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.831140982
Short name T443
Test name
Test status
Simulation time 106333674 ps
CPU time 3.02 seconds
Started Jun 23 05:05:02 PM PDT 24
Finished Jun 23 05:05:05 PM PDT 24
Peak memory 206816 kb
Host smart-e38c998f-8459-47c0-b7c2-1f3bb849fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831140982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.831140982
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2796130073
Short name T766
Test name
Test status
Simulation time 592251421 ps
CPU time 17.78 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:24 PM PDT 24
Peak memory 208084 kb
Host smart-5c909256-0190-46ba-a2e8-1f5ad61726b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796130073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2796130073
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3602628651
Short name T869
Test name
Test status
Simulation time 1862353271 ps
CPU time 24.8 seconds
Started Jun 23 05:05:02 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 208428 kb
Host smart-7665b508-0972-429c-90e8-0ade168406f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602628651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3602628651
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2612573527
Short name T501
Test name
Test status
Simulation time 225752746 ps
CPU time 4.97 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 208904 kb
Host smart-bfd52da0-34cc-4de9-b70b-3c2391339842
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612573527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2612573527
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.233733365
Short name T729
Test name
Test status
Simulation time 227830076 ps
CPU time 4.44 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:11 PM PDT 24
Peak memory 208168 kb
Host smart-d98aa6c3-1449-40e4-8d35-13d8d4d2e85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233733365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.233733365
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3348296299
Short name T172
Test name
Test status
Simulation time 717793758 ps
CPU time 3.98 seconds
Started Jun 23 05:05:03 PM PDT 24
Finished Jun 23 05:05:07 PM PDT 24
Peak memory 206832 kb
Host smart-15aeff56-8533-4f78-a34f-601dd5507d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348296299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3348296299
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2530932813
Short name T592
Test name
Test status
Simulation time 134397723 ps
CPU time 5.11 seconds
Started Jun 23 05:05:09 PM PDT 24
Finished Jun 23 05:05:14 PM PDT 24
Peak memory 209920 kb
Host smart-c1568923-6bd5-4a82-906f-c26fe4fd6211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530932813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2530932813
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3384623831
Short name T856
Test name
Test status
Simulation time 739632381 ps
CPU time 13.77 seconds
Started Jun 23 05:05:04 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 222604 kb
Host smart-5a3e2fed-0037-4fa5-9879-f5dcf8102b13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384623831 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3384623831
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1577821081
Short name T756
Test name
Test status
Simulation time 104148835 ps
CPU time 5.11 seconds
Started Jun 23 05:05:02 PM PDT 24
Finished Jun 23 05:05:07 PM PDT 24
Peak memory 209292 kb
Host smart-93e75e94-4cb9-498f-ba1d-8f6aa1e42501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577821081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1577821081
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.484007681
Short name T373
Test name
Test status
Simulation time 42580986 ps
CPU time 2.34 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 210108 kb
Host smart-c8e6d368-8cce-41aa-9b59-44f58b284a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484007681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.484007681
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.555792013
Short name T3
Test name
Test status
Simulation time 15568892 ps
CPU time 0.83 seconds
Started Jun 23 05:05:09 PM PDT 24
Finished Jun 23 05:05:11 PM PDT 24
Peak memory 205868 kb
Host smart-f7021a14-d192-4d30-b135-71eb3d612b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555792013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.555792013
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3391161172
Short name T226
Test name
Test status
Simulation time 488520795 ps
CPU time 3.71 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 215312 kb
Host smart-aceb8422-6ef7-49b6-a274-f439a68491be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391161172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3391161172
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1377688844
Short name T8
Test name
Test status
Simulation time 774412381 ps
CPU time 4.04 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 221908 kb
Host smart-6893f462-b19e-4ab3-a2db-0d04bc09a468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377688844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1377688844
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2173212549
Short name T558
Test name
Test status
Simulation time 315008896 ps
CPU time 1.87 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 208312 kb
Host smart-7b5ab058-ffdc-4235-8253-02f29ebbe174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173212549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2173212549
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.526631313
Short name T85
Test name
Test status
Simulation time 356884695 ps
CPU time 2.11 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 214208 kb
Host smart-7a476c41-2d35-4768-acc2-47ee15b7a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526631313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.526631313
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.791645500
Short name T659
Test name
Test status
Simulation time 1769774591 ps
CPU time 8.33 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 221868 kb
Host smart-6c553030-173b-4c2f-8cee-975a20e731e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791645500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.791645500
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4109739696
Short name T205
Test name
Test status
Simulation time 290043499 ps
CPU time 7.78 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:16 PM PDT 24
Peak memory 209768 kb
Host smart-8f633325-4f84-4a10-aabd-00c7dc1b9934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109739696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4109739696
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.574292735
Short name T358
Test name
Test status
Simulation time 197660549 ps
CPU time 3.32 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 209028 kb
Host smart-a34ac958-8f10-431e-96a7-16d9be1a628e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574292735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.574292735
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3197252861
Short name T610
Test name
Test status
Simulation time 485012278 ps
CPU time 2.32 seconds
Started Jun 23 05:05:04 PM PDT 24
Finished Jun 23 05:05:07 PM PDT 24
Peak memory 208840 kb
Host smart-4d885d40-da69-46e5-a556-583a682ebb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197252861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3197252861
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.78660144
Short name T731
Test name
Test status
Simulation time 72344831 ps
CPU time 2.74 seconds
Started Jun 23 05:05:05 PM PDT 24
Finished Jun 23 05:05:08 PM PDT 24
Peak memory 208700 kb
Host smart-ab3a93b4-795f-42cd-8bcd-845381d87e4e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78660144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.78660144
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2871739281
Short name T682
Test name
Test status
Simulation time 39029863 ps
CPU time 2.41 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 207328 kb
Host smart-74eb41c5-f0d5-4347-9deb-03640b764eeb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871739281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2871739281
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3254858104
Short name T521
Test name
Test status
Simulation time 108724976 ps
CPU time 3.76 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:11 PM PDT 24
Peak memory 208584 kb
Host smart-3cfc71d8-f638-4830-8f80-4a7d4ddbd816
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254858104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3254858104
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1219291649
Short name T516
Test name
Test status
Simulation time 293770809 ps
CPU time 3.43 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:11 PM PDT 24
Peak memory 208840 kb
Host smart-ea92dfa1-bf30-4b48-b97c-5a610a18a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219291649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1219291649
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2761513130
Short name T377
Test name
Test status
Simulation time 730848520 ps
CPU time 8.76 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 208052 kb
Host smart-821e6ad7-9526-4aeb-bd4e-d237af23383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761513130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2761513130
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4246153588
Short name T362
Test name
Test status
Simulation time 42948692 ps
CPU time 2.51 seconds
Started Jun 23 05:05:09 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 215300 kb
Host smart-9793e8d7-6488-429e-8edf-a7e204f7e9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246153588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4246153588
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4148330800
Short name T116
Test name
Test status
Simulation time 596786988 ps
CPU time 8.99 seconds
Started Jun 23 05:05:08 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 222560 kb
Host smart-557d390a-c88c-4c4d-9917-caade35a6f62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148330800 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4148330800
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.239836424
Short name T536
Test name
Test status
Simulation time 165446048 ps
CPU time 6.24 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:14 PM PDT 24
Peak memory 209112 kb
Host smart-71049572-7625-4352-8865-81d274f596c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239836424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.239836424
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3368314152
Short name T628
Test name
Test status
Simulation time 44497889 ps
CPU time 1.69 seconds
Started Jun 23 05:05:10 PM PDT 24
Finished Jun 23 05:05:12 PM PDT 24
Peak memory 210004 kb
Host smart-d1745f7d-6340-43a0-89f4-615432bba11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368314152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3368314152
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2031272981
Short name T638
Test name
Test status
Simulation time 15858512 ps
CPU time 0.91 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 206104 kb
Host smart-3c1d616c-74c4-4298-8d10-94aa9b0077fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031272981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2031272981
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.866855377
Short name T300
Test name
Test status
Simulation time 121288412 ps
CPU time 4.38 seconds
Started Jun 23 05:05:09 PM PDT 24
Finished Jun 23 05:05:14 PM PDT 24
Peak memory 215088 kb
Host smart-a095db68-c098-4f99-a2c1-fdd220f33a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=866855377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.866855377
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1743018924
Short name T620
Test name
Test status
Simulation time 44804104 ps
CPU time 2.53 seconds
Started Jun 23 05:05:07 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 208088 kb
Host smart-53a66df1-e557-4e26-bdc8-d74686d0d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743018924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1743018924
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3379211104
Short name T92
Test name
Test status
Simulation time 767763867 ps
CPU time 16.4 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:31 PM PDT 24
Peak memory 214304 kb
Host smart-c577ca90-5021-4fb8-b742-cce9422b4dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379211104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3379211104
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3666677351
Short name T334
Test name
Test status
Simulation time 285301437 ps
CPU time 6.15 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 222444 kb
Host smart-5a03be16-997c-42da-bfb3-5f9ee2ae7d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666677351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3666677351
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3118166071
Short name T452
Test name
Test status
Simulation time 157380720 ps
CPU time 3.82 seconds
Started Jun 23 05:05:11 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 210192 kb
Host smart-ae68bf74-11b2-4f5b-949d-baafa9b1a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118166071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3118166071
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2864216013
Short name T767
Test name
Test status
Simulation time 2690763557 ps
CPU time 6.08 seconds
Started Jun 23 05:05:10 PM PDT 24
Finished Jun 23 05:05:16 PM PDT 24
Peak memory 210316 kb
Host smart-93f0e0d0-766b-4bdc-adc3-89f8c18e56f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864216013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2864216013
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2204136072
Short name T4
Test name
Test status
Simulation time 77172088 ps
CPU time 3.3 seconds
Started Jun 23 05:05:10 PM PDT 24
Finished Jun 23 05:05:14 PM PDT 24
Peak memory 208708 kb
Host smart-1365c354-4474-4107-a92d-de0a08546b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204136072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2204136072
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3428049268
Short name T495
Test name
Test status
Simulation time 237530244 ps
CPU time 2.74 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 207428 kb
Host smart-f628911a-b181-44bd-8970-b327e672c4ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428049268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3428049268
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2158302204
Short name T326
Test name
Test status
Simulation time 107707117 ps
CPU time 2.32 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:09 PM PDT 24
Peak memory 206960 kb
Host smart-1200d611-f924-4d0b-ad14-ef4cf05e63d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158302204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2158302204
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.608814766
Short name T774
Test name
Test status
Simulation time 105186205 ps
CPU time 3.69 seconds
Started Jun 23 05:05:06 PM PDT 24
Finished Jun 23 05:05:10 PM PDT 24
Peak memory 206968 kb
Host smart-91bba286-b67f-419c-b41b-98399967d309
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608814766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.608814766
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.558902736
Short name T353
Test name
Test status
Simulation time 121823495 ps
CPU time 2.94 seconds
Started Jun 23 05:05:15 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 214316 kb
Host smart-b624f208-389b-4aad-8842-3109a4710286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558902736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.558902736
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3419222447
Short name T74
Test name
Test status
Simulation time 68276041 ps
CPU time 2.68 seconds
Started Jun 23 05:05:11 PM PDT 24
Finished Jun 23 05:05:14 PM PDT 24
Peak memory 208320 kb
Host smart-21fb56e2-1799-4e21-b757-d5ece26101c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419222447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3419222447
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3229538632
Short name T206
Test name
Test status
Simulation time 5212533946 ps
CPU time 27.13 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:45 PM PDT 24
Peak memory 220864 kb
Host smart-3b35dc9b-40d9-435e-a81c-f34bbc6ee016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229538632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3229538632
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1399205226
Short name T459
Test name
Test status
Simulation time 145125808 ps
CPU time 4.03 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:21 PM PDT 24
Peak memory 218316 kb
Host smart-fe64afed-b87f-4274-a7f1-6088a3728636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399205226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1399205226
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3885838463
Short name T842
Test name
Test status
Simulation time 3805411603 ps
CPU time 8.64 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:24 PM PDT 24
Peak memory 210932 kb
Host smart-0a73695e-abd0-4e8d-a3c8-627ced2817f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885838463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3885838463
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2926340508
Short name T427
Test name
Test status
Simulation time 9674532 ps
CPU time 0.75 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 206104 kb
Host smart-18add522-93c3-4bfb-991e-0f7023ce5355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926340508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2926340508
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2592200811
Short name T394
Test name
Test status
Simulation time 164544537 ps
CPU time 8.72 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 215412 kb
Host smart-291169a7-9028-4a3e-91b8-1ec498c8a9b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592200811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2592200811
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1319759117
Short name T385
Test name
Test status
Simulation time 368193917 ps
CPU time 3.58 seconds
Started Jun 23 05:03:11 PM PDT 24
Finished Jun 23 05:03:15 PM PDT 24
Peak memory 214668 kb
Host smart-f5627996-39d0-4a0b-a387-42a06735fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319759117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1319759117
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4074892203
Short name T514
Test name
Test status
Simulation time 472255594 ps
CPU time 2.22 seconds
Started Jun 23 05:03:11 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 207388 kb
Host smart-9f38b53e-1d0b-4ee7-a43d-5a47a82e6b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074892203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4074892203
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.575070568
Short name T87
Test name
Test status
Simulation time 119825478 ps
CPU time 4.87 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 214956 kb
Host smart-782f5f3f-381e-47b6-af2b-3c39d4221972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575070568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.575070568
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3332419585
Short name T46
Test name
Test status
Simulation time 96070816 ps
CPU time 3.55 seconds
Started Jun 23 05:03:07 PM PDT 24
Finished Jun 23 05:03:11 PM PDT 24
Peak memory 219992 kb
Host smart-04acb838-7854-4a66-a1d7-5db00e111aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332419585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3332419585
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.180845932
Short name T795
Test name
Test status
Simulation time 73271793 ps
CPU time 3.15 seconds
Started Jun 23 05:03:09 PM PDT 24
Finished Jun 23 05:03:12 PM PDT 24
Peak memory 209376 kb
Host smart-7c6b204c-28da-447d-9977-ab448633e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180845932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.180845932
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1980226177
Short name T632
Test name
Test status
Simulation time 285856450 ps
CPU time 3.87 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 208676 kb
Host smart-3b6d182a-1781-4ea7-8f71-c92142acf257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980226177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1980226177
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.345774780
Short name T559
Test name
Test status
Simulation time 34927081 ps
CPU time 2.28 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 206992 kb
Host smart-fe8c9b17-8b23-468d-a2c5-600127e22f6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345774780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.345774780
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.245703795
Short name T486
Test name
Test status
Simulation time 1517923043 ps
CPU time 3.76 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 208416 kb
Host smart-d9c0f537-db4a-49bf-9cd9-708494a2f063
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245703795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.245703795
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.243907810
Short name T249
Test name
Test status
Simulation time 65558520 ps
CPU time 3.33 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:12 PM PDT 24
Peak memory 208744 kb
Host smart-57413d18-e9c8-49ca-9631-996975a38cb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243907810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.243907810
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.416078109
Short name T314
Test name
Test status
Simulation time 63595003 ps
CPU time 2.88 seconds
Started Jun 23 05:03:11 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 209196 kb
Host smart-90c40368-80ff-428e-bec8-36165415f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416078109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.416078109
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3467451334
Short name T482
Test name
Test status
Simulation time 2325621219 ps
CPU time 27.31 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:41 PM PDT 24
Peak memory 208472 kb
Host smart-f79dc67c-17fa-43e7-a088-a5d821cf7cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467451334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3467451334
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3467707490
Short name T355
Test name
Test status
Simulation time 565115825 ps
CPU time 9.82 seconds
Started Jun 23 05:03:11 PM PDT 24
Finished Jun 23 05:03:21 PM PDT 24
Peak memory 215732 kb
Host smart-117f17c7-56e4-4994-ad0e-d5f86cc0f225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467707490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3467707490
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4186094905
Short name T164
Test name
Test status
Simulation time 1087230309 ps
CPU time 9.89 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 222540 kb
Host smart-9d0578c2-8c5d-4148-894f-686d654782d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186094905 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4186094905
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2278082145
Short name T640
Test name
Test status
Simulation time 754786306 ps
CPU time 6.74 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:17 PM PDT 24
Peak memory 214228 kb
Host smart-2f4f2f18-45a6-4ed2-a0c6-19ce307dc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278082145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2278082145
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3573909166
Short name T5
Test name
Test status
Simulation time 368303306 ps
CPU time 2.61 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:16 PM PDT 24
Peak memory 210288 kb
Host smart-78a902ad-74a2-4257-9d0b-fc96b5af16b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573909166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3573909166
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2018585920
Short name T450
Test name
Test status
Simulation time 7810129 ps
CPU time 0.69 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 205892 kb
Host smart-df153d28-588e-4dac-8675-30b1053f9e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018585920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2018585920
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2035965210
Short name T28
Test name
Test status
Simulation time 33664782 ps
CPU time 1.44 seconds
Started Jun 23 05:05:12 PM PDT 24
Finished Jun 23 05:05:14 PM PDT 24
Peak memory 209032 kb
Host smart-7a80e7ae-eff6-4a45-bb79-9aef30d5cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035965210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2035965210
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.113682481
Short name T800
Test name
Test status
Simulation time 488710931 ps
CPU time 3.86 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 218144 kb
Host smart-57c9cec7-aa44-4091-81d0-9e83366e9e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113682481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.113682481
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.302297965
Short name T589
Test name
Test status
Simulation time 83824669 ps
CPU time 1.98 seconds
Started Jun 23 05:05:15 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 213336 kb
Host smart-d1726084-8cce-4d01-ba40-0f84e0d967a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302297965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.302297965
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3543919476
Short name T242
Test name
Test status
Simulation time 149968683 ps
CPU time 5.73 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 214236 kb
Host smart-953f6af7-7970-4645-a38a-81f14d6c9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543919476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3543919476
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2048667622
Short name T542
Test name
Test status
Simulation time 179112635 ps
CPU time 2.53 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 214812 kb
Host smart-ce46ea20-76b7-4cc6-aa1a-b80dbac70016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048667622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2048667622
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.4140204267
Short name T343
Test name
Test status
Simulation time 82616033 ps
CPU time 4.27 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 210080 kb
Host smart-e15e9630-5fad-435c-8ae9-41a795db1a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140204267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.4140204267
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3445562786
Short name T360
Test name
Test status
Simulation time 95296308 ps
CPU time 3.78 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 208488 kb
Host smart-c58a2be0-e6f4-4d87-8541-548cb2645782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445562786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3445562786
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.600041335
Short name T253
Test name
Test status
Simulation time 510124365 ps
CPU time 3.02 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 206904 kb
Host smart-b1c9bf61-2915-45a8-bcac-a89ed67d5c2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600041335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.600041335
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2590810490
Short name T832
Test name
Test status
Simulation time 35082444 ps
CPU time 2.32 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:17 PM PDT 24
Peak memory 206860 kb
Host smart-8396926c-4be1-418d-9598-6e8286a3d98c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590810490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2590810490
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4210158048
Short name T535
Test name
Test status
Simulation time 341361785 ps
CPU time 4.52 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 208420 kb
Host smart-546837dc-0597-4d2f-b64a-f0ceccc4e1f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210158048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4210158048
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4224585978
Short name T35
Test name
Test status
Simulation time 85226035 ps
CPU time 1.81 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:15 PM PDT 24
Peak memory 209928 kb
Host smart-f72f4a94-7520-43a1-8ba4-01938e1fdfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224585978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4224585978
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.772707946
Short name T672
Test name
Test status
Simulation time 141528870 ps
CPU time 4.46 seconds
Started Jun 23 05:05:15 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 208512 kb
Host smart-6173cded-7b66-4769-98b2-5b8a59ce03a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772707946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.772707946
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.4119208083
Short name T683
Test name
Test status
Simulation time 187106159 ps
CPU time 6.41 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:21 PM PDT 24
Peak memory 219352 kb
Host smart-b0712618-dd67-4c02-9f7f-f34776f7610f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119208083 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.4119208083
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1631002214
Short name T637
Test name
Test status
Simulation time 1254539555 ps
CPU time 4.64 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 209996 kb
Host smart-9ff6dcd7-ae03-4b87-932c-dd5a8723ff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631002214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1631002214
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1357108243
Short name T755
Test name
Test status
Simulation time 504196664 ps
CPU time 2.99 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 209944 kb
Host smart-9cad2830-1bc1-4296-9b45-8be4b1ddbccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357108243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1357108243
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.955878641
Short name T483
Test name
Test status
Simulation time 37308902 ps
CPU time 0.76 seconds
Started Jun 23 05:05:19 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 205864 kb
Host smart-4db3db0a-e040-4bf3-a1b7-3e021593461e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955878641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.955878641
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1547401662
Short name T278
Test name
Test status
Simulation time 1489419325 ps
CPU time 40.92 seconds
Started Jun 23 05:05:21 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 215008 kb
Host smart-1e14f4cf-abc2-4215-b442-5da4b72a3c70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547401662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1547401662
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1749277806
Short name T745
Test name
Test status
Simulation time 113776616 ps
CPU time 2.31 seconds
Started Jun 23 05:05:18 PM PDT 24
Finished Jun 23 05:05:21 PM PDT 24
Peak memory 214288 kb
Host smart-e0b8a6e6-5350-42de-9baa-c51f778b6951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749277806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1749277806
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4219854924
Short name T691
Test name
Test status
Simulation time 201425242 ps
CPU time 4.31 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 214276 kb
Host smart-12119f3b-450c-423a-a115-cde704641e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219854924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4219854924
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_random.3265801291
Short name T532
Test name
Test status
Simulation time 3921348063 ps
CPU time 40.54 seconds
Started Jun 23 05:05:18 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 209740 kb
Host smart-007fe6e5-f7ac-4cf2-a66f-aeb3e63e2def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265801291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3265801291
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3207573018
Short name T315
Test name
Test status
Simulation time 140104043 ps
CPU time 5.52 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 206928 kb
Host smart-1ddec637-cd4d-4903-bb03-a6e4c939c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207573018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3207573018
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3891000376
Short name T464
Test name
Test status
Simulation time 101011266 ps
CPU time 4.13 seconds
Started Jun 23 05:05:13 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 208784 kb
Host smart-d8522cb1-b589-4147-9662-399f53792915
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891000376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3891000376
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1799672713
Short name T617
Test name
Test status
Simulation time 138680796 ps
CPU time 4.48 seconds
Started Jun 23 05:05:15 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 207164 kb
Host smart-0e65fd4d-e70d-437b-bf21-df47315ab3bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799672713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1799672713
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1207909642
Short name T313
Test name
Test status
Simulation time 188577432 ps
CPU time 3.82 seconds
Started Jun 23 05:05:14 PM PDT 24
Finished Jun 23 05:05:18 PM PDT 24
Peak memory 207444 kb
Host smart-01c9dbe8-1ce9-452a-ad5f-6808a1ebada2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207909642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1207909642
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4189965211
Short name T777
Test name
Test status
Simulation time 55263486 ps
CPU time 2.93 seconds
Started Jun 23 05:05:18 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 218516 kb
Host smart-5615d7fc-c2ee-4733-af2a-1813e1cb489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189965211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4189965211
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1130247305
Short name T710
Test name
Test status
Simulation time 273271290 ps
CPU time 2.96 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 206768 kb
Host smart-d96fbfc0-b28b-4ece-b6eb-f2c9cba1e47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130247305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1130247305
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.554001919
Short name T839
Test name
Test status
Simulation time 1399906872 ps
CPU time 19.42 seconds
Started Jun 23 05:05:20 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 215292 kb
Host smart-f62decba-4c08-4744-b2f6-9b368342938e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554001919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.554001919
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3217930419
Short name T784
Test name
Test status
Simulation time 6912035299 ps
CPU time 54.51 seconds
Started Jun 23 05:05:18 PM PDT 24
Finished Jun 23 05:06:13 PM PDT 24
Peak memory 209612 kb
Host smart-cfa1e55d-c84f-47de-8a22-9e33ba43efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217930419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3217930419
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3063696588
Short name T368
Test name
Test status
Simulation time 99126653 ps
CPU time 2.29 seconds
Started Jun 23 05:05:16 PM PDT 24
Finished Jun 23 05:05:19 PM PDT 24
Peak memory 210108 kb
Host smart-f1850796-236a-447f-ac7b-82d3a48dbf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063696588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3063696588
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.52147040
Short name T97
Test name
Test status
Simulation time 20090867 ps
CPU time 0.88 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:26 PM PDT 24
Peak memory 205872 kb
Host smart-e48ffa93-c874-4e6b-9ea2-9c68ce799f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52147040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.52147040
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.723621520
Short name T891
Test name
Test status
Simulation time 1194903468 ps
CPU time 6.36 seconds
Started Jun 23 05:05:21 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 208776 kb
Host smart-56470b51-cf60-493c-bc45-3654936dc782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723621520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.723621520
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1321801931
Short name T36
Test name
Test status
Simulation time 113391473 ps
CPU time 2.87 seconds
Started Jun 23 05:05:19 PM PDT 24
Finished Jun 23 05:05:22 PM PDT 24
Peak memory 222416 kb
Host smart-480282f6-2cd3-4ecb-908b-232a08962196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321801931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1321801931
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3918707618
Short name T728
Test name
Test status
Simulation time 365418343 ps
CPU time 3.55 seconds
Started Jun 23 05:05:19 PM PDT 24
Finished Jun 23 05:05:23 PM PDT 24
Peak memory 214236 kb
Host smart-b6a17823-3aca-41d2-ac7a-aa4cc434f7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918707618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3918707618
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2218347499
Short name T121
Test name
Test status
Simulation time 31422629 ps
CPU time 2.14 seconds
Started Jun 23 05:05:18 PM PDT 24
Finished Jun 23 05:05:21 PM PDT 24
Peak memory 214268 kb
Host smart-82607e4c-f243-4539-b2f3-45f4531a489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218347499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2218347499
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.97236289
Short name T102
Test name
Test status
Simulation time 98061140 ps
CPU time 2.61 seconds
Started Jun 23 05:05:20 PM PDT 24
Finished Jun 23 05:05:23 PM PDT 24
Peak memory 220140 kb
Host smart-57bb206c-a2b1-418b-baa1-445dc58f33b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97236289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.97236289
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2595269872
Short name T395
Test name
Test status
Simulation time 329827547 ps
CPU time 4.46 seconds
Started Jun 23 05:05:18 PM PDT 24
Finished Jun 23 05:05:23 PM PDT 24
Peak memory 222632 kb
Host smart-9fbc7304-baa5-41c2-982c-ed24391d49c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595269872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2595269872
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2467365517
Short name T804
Test name
Test status
Simulation time 167167934 ps
CPU time 3.98 seconds
Started Jun 23 05:05:22 PM PDT 24
Finished Jun 23 05:05:26 PM PDT 24
Peak memory 208524 kb
Host smart-4dee9c7c-0749-4fbe-bdf8-12b19e775a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467365517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2467365517
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1410425499
Short name T472
Test name
Test status
Simulation time 412662648 ps
CPU time 6.19 seconds
Started Jun 23 05:05:21 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 207948 kb
Host smart-7441e194-8e2d-410d-b5fc-30156182bf85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410425499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1410425499
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3915491344
Short name T12
Test name
Test status
Simulation time 34353164 ps
CPU time 2.32 seconds
Started Jun 23 05:05:22 PM PDT 24
Finished Jun 23 05:05:25 PM PDT 24
Peak memory 206944 kb
Host smart-b85c79d9-7708-4b17-a38c-88297a18b9a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915491344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3915491344
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3172099962
Short name T872
Test name
Test status
Simulation time 142883978 ps
CPU time 2.36 seconds
Started Jun 23 05:05:20 PM PDT 24
Finished Jun 23 05:05:23 PM PDT 24
Peak memory 207636 kb
Host smart-960af68e-20f4-437c-866f-deddd1945a73
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172099962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3172099962
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.657134720
Short name T273
Test name
Test status
Simulation time 44081068 ps
CPU time 2.24 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 215868 kb
Host smart-20001f6c-94e0-41af-9ac7-85b388b63f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657134720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.657134720
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1327392808
Short name T726
Test name
Test status
Simulation time 614709801 ps
CPU time 3 seconds
Started Jun 23 05:05:17 PM PDT 24
Finished Jun 23 05:05:20 PM PDT 24
Peak memory 208164 kb
Host smart-c9b3ea90-6dc4-45a5-8617-5ff11c909318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327392808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1327392808
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1570028183
Short name T847
Test name
Test status
Simulation time 1040461511 ps
CPU time 15.05 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:42 PM PDT 24
Peak memory 216724 kb
Host smart-d6b38ad8-abaa-4abe-9691-521e0a896e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570028183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1570028183
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.280487348
Short name T161
Test name
Test status
Simulation time 527969732 ps
CPU time 19.82 seconds
Started Jun 23 05:05:27 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 222624 kb
Host smart-a47ae298-050b-474e-a66b-46ed40937eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280487348 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.280487348
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2643892389
Short name T820
Test name
Test status
Simulation time 215060446 ps
CPU time 6.43 seconds
Started Jun 23 05:05:19 PM PDT 24
Finished Jun 23 05:05:26 PM PDT 24
Peak memory 208568 kb
Host smart-ac1f4c66-8c17-4bb4-983a-0e86e72b126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643892389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2643892389
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1861628352
Short name T163
Test name
Test status
Simulation time 79477015 ps
CPU time 2.12 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:29 PM PDT 24
Peak memory 209756 kb
Host smart-0bbbb9d9-0af2-4541-bb27-6944aed89ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861628352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1861628352
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.678863993
Short name T861
Test name
Test status
Simulation time 11840611 ps
CPU time 0.72 seconds
Started Jun 23 05:05:28 PM PDT 24
Finished Jun 23 05:05:29 PM PDT 24
Peak memory 205824 kb
Host smart-c2bd4bbf-1cb8-4fd8-9b92-ce367b384723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678863993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.678863993
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2393917561
Short name T214
Test name
Test status
Simulation time 133662538 ps
CPU time 6.29 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:49 PM PDT 24
Peak memory 221448 kb
Host smart-8a1995a5-4759-4dab-a2f4-d1e90d1009ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393917561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2393917561
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.57163785
Short name T259
Test name
Test status
Simulation time 88450576 ps
CPU time 2.44 seconds
Started Jun 23 05:05:27 PM PDT 24
Finished Jun 23 05:05:30 PM PDT 24
Peak memory 209180 kb
Host smart-9d11f49e-ecd8-454d-b7a1-58111097069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57163785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.57163785
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.794273648
Short name T724
Test name
Test status
Simulation time 164258294 ps
CPU time 7.66 seconds
Started Jun 23 05:05:29 PM PDT 24
Finished Jun 23 05:05:37 PM PDT 24
Peak memory 214328 kb
Host smart-6e5a1688-9550-468a-a096-3fb8d19896f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794273648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.794273648
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3771262704
Short name T524
Test name
Test status
Simulation time 151247850 ps
CPU time 6.4 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:33 PM PDT 24
Peak memory 214208 kb
Host smart-0bdc8e15-d9ee-4eb7-ba17-f22310479549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771262704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3771262704
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3775620707
Short name T194
Test name
Test status
Simulation time 71294199 ps
CPU time 2.92 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:29 PM PDT 24
Peak memory 208896 kb
Host smart-e0d1b071-464b-4b7a-8c9b-a37492f2b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775620707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3775620707
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1434863844
Short name T557
Test name
Test status
Simulation time 2052273512 ps
CPU time 24.3 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:51 PM PDT 24
Peak memory 214316 kb
Host smart-49fc0f2e-fc53-435c-a9a6-3df684e4095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434863844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1434863844
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.970255547
Short name T433
Test name
Test status
Simulation time 783916087 ps
CPU time 4.4 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:30 PM PDT 24
Peak memory 206880 kb
Host smart-402569d9-ab6d-40c2-874a-340b9fd992e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970255547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.970255547
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.878972689
Short name T889
Test name
Test status
Simulation time 562766050 ps
CPU time 16.56 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 208660 kb
Host smart-ace055a6-4294-43c1-9ff9-1175fca4274f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878972689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.878972689
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1189781389
Short name T584
Test name
Test status
Simulation time 196910530 ps
CPU time 2.46 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 208664 kb
Host smart-401536d5-22b0-4175-b49d-48649ca6d461
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189781389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1189781389
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2855478245
Short name T439
Test name
Test status
Simulation time 53073703 ps
CPU time 2.81 seconds
Started Jun 23 05:05:28 PM PDT 24
Finished Jun 23 05:05:31 PM PDT 24
Peak memory 206992 kb
Host smart-eac461bc-b0c2-4c54-b98e-4db086f71550
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855478245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2855478245
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.77232882
Short name T316
Test name
Test status
Simulation time 137816826 ps
CPU time 2.03 seconds
Started Jun 23 05:05:29 PM PDT 24
Finished Jun 23 05:05:31 PM PDT 24
Peak memory 207716 kb
Host smart-642a10ab-e59a-45b4-a92a-2cead8194a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77232882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.77232882
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2715945550
Short name T787
Test name
Test status
Simulation time 1124448269 ps
CPU time 4.04 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:31 PM PDT 24
Peak memory 208088 kb
Host smart-13ee2908-9efd-4878-bdcf-d6923719086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715945550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2715945550
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3588634441
Short name T753
Test name
Test status
Simulation time 146656923 ps
CPU time 10.07 seconds
Started Jun 23 05:05:24 PM PDT 24
Finished Jun 23 05:05:34 PM PDT 24
Peak memory 222572 kb
Host smart-039ac385-ec24-4672-9e9a-a0397c363e72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588634441 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3588634441
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3741295391
Short name T383
Test name
Test status
Simulation time 772225510 ps
CPU time 18.76 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:44 PM PDT 24
Peak memory 208612 kb
Host smart-dc25044f-12f1-4cb7-8831-07d4cd9945b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741295391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3741295391
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.96691038
Short name T884
Test name
Test status
Simulation time 1322762275 ps
CPU time 2.75 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:29 PM PDT 24
Peak memory 210156 kb
Host smart-d48bb9b1-7600-4af5-abcb-ff980da1f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96691038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.96691038
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2095770995
Short name T685
Test name
Test status
Simulation time 74378847 ps
CPU time 0.72 seconds
Started Jun 23 05:05:31 PM PDT 24
Finished Jun 23 05:05:32 PM PDT 24
Peak memory 205936 kb
Host smart-b1b2b854-4417-481c-83ab-c548c56c4866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095770995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2095770995
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3448059590
Short name T849
Test name
Test status
Simulation time 31944735 ps
CPU time 2.41 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:28 PM PDT 24
Peak memory 214292 kb
Host smart-338b8590-bafb-400f-827b-7f8f585e1c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448059590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3448059590
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2134042838
Short name T69
Test name
Test status
Simulation time 2694934178 ps
CPU time 6.45 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:42 PM PDT 24
Peak memory 210544 kb
Host smart-7d54c018-0ae7-4be1-9182-df96c24057cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134042838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2134042838
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3641776248
Short name T740
Test name
Test status
Simulation time 545450948 ps
CPU time 2.76 seconds
Started Jun 23 05:05:29 PM PDT 24
Finished Jun 23 05:05:32 PM PDT 24
Peak memory 208420 kb
Host smart-2c434e94-1b48-4b23-97af-833766bac5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641776248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3641776248
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2673627415
Short name T306
Test name
Test status
Simulation time 167487366 ps
CPU time 2.02 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:32 PM PDT 24
Peak memory 214192 kb
Host smart-6d9f1829-b04a-49a3-a356-a76ddcb9ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673627415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2673627415
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2631323175
Short name T639
Test name
Test status
Simulation time 345420240 ps
CPU time 9.13 seconds
Started Jun 23 05:05:34 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 214404 kb
Host smart-bb2450be-211e-4d58-85c8-48675ba74358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631323175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2631323175
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2009082061
Short name T293
Test name
Test status
Simulation time 36066681 ps
CPU time 2.69 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:29 PM PDT 24
Peak memory 214212 kb
Host smart-d62580ca-c247-4e79-b37b-bd5e974dda30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009082061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2009082061
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.901839075
Short name T605
Test name
Test status
Simulation time 133536125 ps
CPU time 2.55 seconds
Started Jun 23 05:05:27 PM PDT 24
Finished Jun 23 05:05:30 PM PDT 24
Peak memory 206000 kb
Host smart-719110ca-f205-4007-bee4-a4ec3bf45fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901839075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.901839075
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1517719858
Short name T258
Test name
Test status
Simulation time 151781694 ps
CPU time 4.83 seconds
Started Jun 23 05:05:29 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 208852 kb
Host smart-182fc511-a8ff-4613-870f-1cd7a8359967
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517719858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1517719858
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1405415754
Short name T875
Test name
Test status
Simulation time 47390671 ps
CPU time 2.61 seconds
Started Jun 23 05:05:26 PM PDT 24
Finished Jun 23 05:05:29 PM PDT 24
Peak memory 206804 kb
Host smart-9eeded4b-902b-493e-a04f-40793e3de963
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405415754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1405415754
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2995060256
Short name T379
Test name
Test status
Simulation time 1811865561 ps
CPU time 33.92 seconds
Started Jun 23 05:05:25 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 208616 kb
Host smart-009b1cda-1316-41d4-9814-b0eaffd35e0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995060256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2995060256
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4027411255
Short name T817
Test name
Test status
Simulation time 277127781 ps
CPU time 3.16 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:34 PM PDT 24
Peak memory 210028 kb
Host smart-ec358df0-d397-4eed-8827-958f87829c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027411255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4027411255
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3536095085
Short name T435
Test name
Test status
Simulation time 126901411 ps
CPU time 2.76 seconds
Started Jun 23 05:05:27 PM PDT 24
Finished Jun 23 05:05:30 PM PDT 24
Peak memory 206916 kb
Host smart-de5f2d0c-6a24-4281-81c4-80bb1b260465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536095085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3536095085
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.261675570
Short name T73
Test name
Test status
Simulation time 130977746 ps
CPU time 6.67 seconds
Started Jun 23 05:05:33 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 215440 kb
Host smart-9bff786f-9bc2-4295-bac7-5e6885bf954c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261675570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.261675570
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2095307144
Short name T184
Test name
Test status
Simulation time 61732338 ps
CPU time 3.6 seconds
Started Jun 23 05:05:42 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 207108 kb
Host smart-e5dac679-7d75-4285-965a-c84900fcc9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095307144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2095307144
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.666435759
Short name T814
Test name
Test status
Simulation time 734622714 ps
CPU time 3.09 seconds
Started Jun 23 05:05:32 PM PDT 24
Finished Jun 23 05:05:36 PM PDT 24
Peak memory 210356 kb
Host smart-141755a8-a4b3-4811-a864-58db234b4895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666435759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.666435759
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1366225289
Short name T508
Test name
Test status
Simulation time 50078848 ps
CPU time 0.83 seconds
Started Jun 23 05:05:34 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 205940 kb
Host smart-f720d6d5-eade-4ad0-a86c-f5ea2b015dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366225289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1366225289
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4278822595
Short name T735
Test name
Test status
Simulation time 257235258 ps
CPU time 4.32 seconds
Started Jun 23 05:05:36 PM PDT 24
Finished Jun 23 05:05:41 PM PDT 24
Peak memory 216212 kb
Host smart-81af956e-64ae-4f6c-a74b-3a46e3148428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278822595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4278822595
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.4170639408
Short name T712
Test name
Test status
Simulation time 458694047 ps
CPU time 5.94 seconds
Started Jun 23 05:05:31 PM PDT 24
Finished Jun 23 05:05:37 PM PDT 24
Peak memory 207180 kb
Host smart-b3a649a3-5c0f-40c3-89ed-c33fb574897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170639408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4170639408
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.197844945
Short name T585
Test name
Test status
Simulation time 425986298 ps
CPU time 2.29 seconds
Started Jun 23 05:05:29 PM PDT 24
Finished Jun 23 05:05:32 PM PDT 24
Peak memory 214232 kb
Host smart-839133d0-c13c-4244-b913-4e39705eb77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197844945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.197844945
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1011821971
Short name T618
Test name
Test status
Simulation time 161987983 ps
CPU time 6.03 seconds
Started Jun 23 05:05:32 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 219564 kb
Host smart-ad306495-4da9-4f39-8af0-d7de5f8fd250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011821971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1011821971
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2768443110
Short name T440
Test name
Test status
Simulation time 118930445 ps
CPU time 3.35 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 208400 kb
Host smart-b4238561-28f8-43a0-a364-9806d465e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768443110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2768443110
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2053923571
Short name T347
Test name
Test status
Simulation time 189752792 ps
CPU time 3.44 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:34 PM PDT 24
Peak memory 208600 kb
Host smart-a7ea252c-4bb6-4dfe-8b97-725f13dc082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053923571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2053923571
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3607111074
Short name T812
Test name
Test status
Simulation time 203805863 ps
CPU time 5.23 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:41 PM PDT 24
Peak memory 208820 kb
Host smart-41772136-aec1-419e-ac30-c7faef40dd6c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607111074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3607111074
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.509212761
Short name T317
Test name
Test status
Simulation time 185671803 ps
CPU time 2.49 seconds
Started Jun 23 05:05:38 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 206916 kb
Host smart-290cfe23-ad25-4164-8878-b3379b3d9465
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509212761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.509212761
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3662511394
Short name T873
Test name
Test status
Simulation time 349492449 ps
CPU time 3.46 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 207016 kb
Host smart-f9c1b8d2-b94e-4634-93d7-49baa09e5b76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662511394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3662511394
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1250465883
Short name T845
Test name
Test status
Simulation time 596367758 ps
CPU time 3.86 seconds
Started Jun 23 05:05:31 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 215960 kb
Host smart-c3750acc-764c-4961-bc52-f6a4d41d462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250465883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1250465883
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1143473530
Short name T871
Test name
Test status
Simulation time 70119978 ps
CPU time 3.52 seconds
Started Jun 23 05:05:33 PM PDT 24
Finished Jun 23 05:05:37 PM PDT 24
Peak memory 208600 kb
Host smart-72ce65ca-5711-4b01-a227-75db9a2578c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143473530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1143473530
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2738389558
Short name T302
Test name
Test status
Simulation time 88524266 ps
CPU time 2.22 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 207276 kb
Host smart-e7ae00b1-39a4-4b03-be56-4ff42bcbe73a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738389558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2738389558
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3508160285
Short name T896
Test name
Test status
Simulation time 1612926619 ps
CPU time 30.58 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 209676 kb
Host smart-975e29f5-c225-4a89-b6ea-b087cb0a7df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508160285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3508160285
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2622336924
Short name T382
Test name
Test status
Simulation time 274994765 ps
CPU time 5.8 seconds
Started Jun 23 05:05:33 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 210296 kb
Host smart-1db8ea9a-cc2e-4546-80e3-15b80088ad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622336924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2622336924
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3202419756
Short name T860
Test name
Test status
Simulation time 21425432 ps
CPU time 0.82 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:38 PM PDT 24
Peak memory 205892 kb
Host smart-fe1d3e7c-eadc-47c2-8c50-7267c6359cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202419756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3202419756
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.520096943
Short name T398
Test name
Test status
Simulation time 54061237 ps
CPU time 3.08 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 214324 kb
Host smart-6112fe06-633e-4a91-8f0c-ff98eacffcd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520096943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.520096943
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1783782925
Short name T29
Test name
Test status
Simulation time 139687642 ps
CPU time 2.63 seconds
Started Jun 23 05:05:31 PM PDT 24
Finished Jun 23 05:05:34 PM PDT 24
Peak memory 214328 kb
Host smart-6846d3c6-f44a-4baf-9e4b-afd7541669fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783782925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1783782925
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1210532446
Short name T303
Test name
Test status
Simulation time 59720624 ps
CPU time 2.52 seconds
Started Jun 23 05:05:31 PM PDT 24
Finished Jun 23 05:05:34 PM PDT 24
Peak memory 210424 kb
Host smart-521a9ab9-d352-45c1-8117-263750d2c17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210532446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1210532446
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.46113879
Short name T846
Test name
Test status
Simulation time 882010019 ps
CPU time 2.24 seconds
Started Jun 23 05:05:34 PM PDT 24
Finished Jun 23 05:05:36 PM PDT 24
Peak memory 215028 kb
Host smart-e96415f8-07e3-493a-a8f2-dc2419e272d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46113879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.46113879
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1257602491
Short name T281
Test name
Test status
Simulation time 116537792 ps
CPU time 2.2 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 214248 kb
Host smart-07cddb6f-08ce-4029-a989-c939128aa80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257602491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1257602491
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2563092889
Short name T311
Test name
Test status
Simulation time 186037274 ps
CPU time 4.92 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 209716 kb
Host smart-9e37d351-3893-4109-9a89-ccca89c46941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563092889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2563092889
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1228405587
Short name T631
Test name
Test status
Simulation time 524671160 ps
CPU time 8.47 seconds
Started Jun 23 05:05:33 PM PDT 24
Finished Jun 23 05:05:42 PM PDT 24
Peak memory 214312 kb
Host smart-2ea1a01e-a083-47ed-8181-ca026d80205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228405587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1228405587
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.140934172
Short name T320
Test name
Test status
Simulation time 2946298790 ps
CPU time 14.62 seconds
Started Jun 23 05:05:31 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 208196 kb
Host smart-c1aa7444-197c-4626-98b0-a8214bd0aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140934172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.140934172
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.919470540
Short name T840
Test name
Test status
Simulation time 224488140 ps
CPU time 2.75 seconds
Started Jun 23 05:05:39 PM PDT 24
Finished Jun 23 05:05:42 PM PDT 24
Peak memory 208440 kb
Host smart-42b2668f-afdf-4962-90fd-0a5693e6e5e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919470540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.919470540
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.532384195
Short name T792
Test name
Test status
Simulation time 717962474 ps
CPU time 4.52 seconds
Started Jun 23 05:05:32 PM PDT 24
Finished Jun 23 05:05:37 PM PDT 24
Peak memory 206896 kb
Host smart-60ef765d-09f7-4085-a62c-fbdb833b5403
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532384195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.532384195
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2556628191
Short name T190
Test name
Test status
Simulation time 964980392 ps
CPU time 4.31 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:35 PM PDT 24
Peak memory 207004 kb
Host smart-4e7cfd39-0c1d-4d7f-b747-403dd37ec7e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556628191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2556628191
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3159089050
Short name T437
Test name
Test status
Simulation time 225731297 ps
CPU time 2.74 seconds
Started Jun 23 05:05:39 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 210216 kb
Host smart-4ef7bf11-12ff-4c53-91d2-a0b4aeea1370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159089050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3159089050
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2596905300
Short name T901
Test name
Test status
Simulation time 849764386 ps
CPU time 15.23 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 208444 kb
Host smart-56d2e90a-5752-45cc-8e10-3ef044fae705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596905300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2596905300
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1131797416
Short name T828
Test name
Test status
Simulation time 11962535072 ps
CPU time 26.31 seconds
Started Jun 23 05:05:36 PM PDT 24
Finished Jun 23 05:06:03 PM PDT 24
Peak memory 221248 kb
Host smart-522c7e59-a2d4-46c1-8b89-c6185ff43b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131797416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1131797416
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1861331836
Short name T256
Test name
Test status
Simulation time 96620439 ps
CPU time 4.94 seconds
Started Jun 23 05:05:30 PM PDT 24
Finished Jun 23 05:05:36 PM PDT 24
Peak memory 207540 kb
Host smart-758119ec-6913-412e-b673-2fd722e4ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861331836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1861331836
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.188532355
Short name T124
Test name
Test status
Simulation time 105069253 ps
CPU time 2.83 seconds
Started Jun 23 05:05:36 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 210348 kb
Host smart-a2d1860d-6cea-47ec-8724-fa7a18c42994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188532355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.188532355
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2006570843
Short name T423
Test name
Test status
Simulation time 66227731 ps
CPU time 0.95 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 206052 kb
Host smart-797a0d37-e594-43b2-b63d-b40ca431d9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006570843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2006570843
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2553984455
Short name T276
Test name
Test status
Simulation time 536162667 ps
CPU time 8.16 seconds
Started Jun 23 05:05:38 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 214504 kb
Host smart-177f7a17-270e-4ace-a500-992a7acc6513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553984455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2553984455
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1569872997
Short name T738
Test name
Test status
Simulation time 332432938 ps
CPU time 3.61 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 221820 kb
Host smart-117c2041-ed20-45c1-9069-1e626cde1000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569872997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1569872997
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3772532203
Short name T538
Test name
Test status
Simulation time 26019973 ps
CPU time 1.62 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:45 PM PDT 24
Peak memory 207500 kb
Host smart-6b65c44f-dea3-4729-a23a-73a27622186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772532203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3772532203
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3731455141
Short name T284
Test name
Test status
Simulation time 129280518 ps
CPU time 2.29 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 221016 kb
Host smart-c7c20a8b-7d2a-4f3d-86f5-02ca58948820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731455141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3731455141
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1629404367
Short name T260
Test name
Test status
Simulation time 237149723 ps
CPU time 2.75 seconds
Started Jun 23 05:05:36 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 214184 kb
Host smart-2599c1ad-fc69-4ebf-848e-198bc0265234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629404367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1629404367
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_random.4022864561
Short name T915
Test name
Test status
Simulation time 776139178 ps
CPU time 8.44 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:52 PM PDT 24
Peak memory 207428 kb
Host smart-73705ff5-9ea5-47f1-8a23-4a592832d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022864561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4022864561
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2888853524
Short name T419
Test name
Test status
Simulation time 187048890 ps
CPU time 2.27 seconds
Started Jun 23 05:05:40 PM PDT 24
Finished Jun 23 05:05:42 PM PDT 24
Peak memory 208512 kb
Host smart-6439247c-9ad2-42f9-93eb-315f75b221b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888853524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2888853524
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1184970299
Short name T775
Test name
Test status
Simulation time 413160673 ps
CPU time 6.91 seconds
Started Jun 23 05:05:40 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 207928 kb
Host smart-26aae062-14de-4e17-a70a-472df2b42eeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184970299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1184970299
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1847838179
Short name T76
Test name
Test status
Simulation time 504993461 ps
CPU time 5.83 seconds
Started Jun 23 05:05:42 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 208120 kb
Host smart-2f77d17c-20fe-4489-9ff8-fd7f97a29b60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847838179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1847838179
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.500357652
Short name T633
Test name
Test status
Simulation time 126792950 ps
CPU time 3.18 seconds
Started Jun 23 05:05:38 PM PDT 24
Finished Jun 23 05:05:41 PM PDT 24
Peak memory 208084 kb
Host smart-42f1e091-dc9e-4b3a-98bb-c3e229f9cd82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500357652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.500357652
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2535855874
Short name T225
Test name
Test status
Simulation time 113194224 ps
CPU time 4.19 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 210080 kb
Host smart-ff345190-211a-42aa-b6f3-91d51b666ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535855874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2535855874
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3538617129
Short name T470
Test name
Test status
Simulation time 802040904 ps
CPU time 5.54 seconds
Started Jun 23 05:05:38 PM PDT 24
Finished Jun 23 05:05:44 PM PDT 24
Peak memory 207812 kb
Host smart-ff951fb8-1d78-4f5a-9ceb-992ae6b89d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538617129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3538617129
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3170047974
Short name T674
Test name
Test status
Simulation time 668267992 ps
CPU time 5.35 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 208100 kb
Host smart-0bd46f76-a65c-45f1-bcbc-40989e23d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170047974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3170047974
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2835395520
Short name T746
Test name
Test status
Simulation time 113766114 ps
CPU time 3.74 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 210500 kb
Host smart-632818fb-8356-4cf8-9627-3271fa3468f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835395520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2835395520
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.313322685
Short name T445
Test name
Test status
Simulation time 65537367 ps
CPU time 0.85 seconds
Started Jun 23 05:05:42 PM PDT 24
Finished Jun 23 05:05:43 PM PDT 24
Peak memory 205944 kb
Host smart-827d32c5-9a29-4c39-bae4-1ff04ea44d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313322685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.313322685
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2467662610
Short name T295
Test name
Test status
Simulation time 117678887 ps
CPU time 2.82 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 214328 kb
Host smart-f759c696-f55a-42e8-a265-ca7aaf0c3184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467662610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2467662610
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.302970855
Short name T603
Test name
Test status
Simulation time 185426694 ps
CPU time 4.99 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 211136 kb
Host smart-6d18a6ac-211a-499e-bd4d-4ed8f4020478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302970855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.302970855
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2966252545
Short name T772
Test name
Test status
Simulation time 556418253 ps
CPU time 4.15 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 209408 kb
Host smart-1781cf75-265e-4658-a4ee-f76192116aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966252545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2966252545
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2014638222
Short name T246
Test name
Test status
Simulation time 105860380 ps
CPU time 2.16 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 214252 kb
Host smart-73b23989-647c-4fa0-acec-19c30604e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014638222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2014638222
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2790190862
Short name T882
Test name
Test status
Simulation time 66727022 ps
CPU time 3.37 seconds
Started Jun 23 05:05:36 PM PDT 24
Finished Jun 23 05:05:40 PM PDT 24
Peak memory 208952 kb
Host smart-53044864-b9fe-456c-9aae-66efb613a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790190862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2790190862
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.727044967
Short name T759
Test name
Test status
Simulation time 233932853 ps
CPU time 3.56 seconds
Started Jun 23 05:05:37 PM PDT 24
Finished Jun 23 05:05:41 PM PDT 24
Peak memory 218204 kb
Host smart-a2e59f36-df82-49db-a24c-8d16f1345133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727044967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.727044967
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3335891726
Short name T349
Test name
Test status
Simulation time 81350351 ps
CPU time 2.04 seconds
Started Jun 23 05:05:39 PM PDT 24
Finished Jun 23 05:05:41 PM PDT 24
Peak memory 208660 kb
Host smart-b1212ff7-a66d-44a0-9144-5e2de7905121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335891726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3335891726
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1717327882
Short name T904
Test name
Test status
Simulation time 79619359 ps
CPU time 3.54 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:39 PM PDT 24
Peak memory 207996 kb
Host smart-ba7ef249-00ab-4faa-be4d-d946efa049d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717327882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1717327882
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.791993708
Short name T660
Test name
Test status
Simulation time 74167406 ps
CPU time 1.86 seconds
Started Jun 23 05:05:35 PM PDT 24
Finished Jun 23 05:05:38 PM PDT 24
Peak memory 206884 kb
Host smart-f8439b07-db95-4ff9-8ca5-5d5d3d5647c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791993708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.791993708
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1368472680
Short name T247
Test name
Test status
Simulation time 31470792 ps
CPU time 2.41 seconds
Started Jun 23 05:05:42 PM PDT 24
Finished Jun 23 05:05:45 PM PDT 24
Peak memory 218172 kb
Host smart-07695cf6-c13a-4c48-9940-bfff4f08da53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368472680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1368472680
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.669481662
Short name T680
Test name
Test status
Simulation time 2831193968 ps
CPU time 21.57 seconds
Started Jun 23 05:05:41 PM PDT 24
Finished Jun 23 05:06:04 PM PDT 24
Peak memory 208640 kb
Host smart-0f76ec03-dea3-4bb8-a7d2-c2c8629f8c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669481662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.669481662
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.271039309
Short name T702
Test name
Test status
Simulation time 565868116 ps
CPU time 18.77 seconds
Started Jun 23 05:05:38 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 209400 kb
Host smart-39cd486f-911d-4b31-97eb-844ab374c605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271039309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.271039309
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1689689712
Short name T157
Test name
Test status
Simulation time 104239652 ps
CPU time 2.47 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 209952 kb
Host smart-63ef40c4-433c-4955-bb25-76fa04575cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689689712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1689689712
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1982399139
Short name T413
Test name
Test status
Simulation time 62635143 ps
CPU time 1 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 206104 kb
Host smart-364f9dfe-147e-457f-ad79-2bf6f727826c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982399139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1982399139
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3715405102
Short name T525
Test name
Test status
Simulation time 269863581 ps
CPU time 1.83 seconds
Started Jun 23 05:05:46 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 208216 kb
Host smart-8b58bda2-d1c6-4373-aefc-c29a0c7bc9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715405102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3715405102
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1738482259
Short name T749
Test name
Test status
Simulation time 30917983 ps
CPU time 1.97 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:46 PM PDT 24
Peak memory 214744 kb
Host smart-20a96d36-a5a8-417d-855a-023c3d43b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738482259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1738482259
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1751499590
Short name T763
Test name
Test status
Simulation time 358958221 ps
CPU time 2.96 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 220928 kb
Host smart-229e58d5-34e7-49be-b4d2-538c9c4ba8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751499590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1751499590
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1170359481
Short name T562
Test name
Test status
Simulation time 331564861 ps
CPU time 4.98 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 219736 kb
Host smart-2a297fc6-2566-4790-81f7-82b2a61fdb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170359481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1170359481
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3326164417
Short name T790
Test name
Test status
Simulation time 79037644 ps
CPU time 3.76 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 208624 kb
Host smart-de931379-5a51-4105-a14f-0a3b8e0d9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326164417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3326164417
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3155296101
Short name T803
Test name
Test status
Simulation time 131039193 ps
CPU time 2.31 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:47 PM PDT 24
Peak memory 206976 kb
Host smart-f7be08c8-8929-438d-b051-7447bc009f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155296101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3155296101
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4174044581
Short name T758
Test name
Test status
Simulation time 1160876384 ps
CPU time 12.42 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:57 PM PDT 24
Peak memory 208144 kb
Host smart-e2b8d87d-7c62-4393-b593-55af079718ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174044581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4174044581
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2803393326
Short name T569
Test name
Test status
Simulation time 1116041944 ps
CPU time 6.37 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:51 PM PDT 24
Peak memory 208284 kb
Host smart-75e5ecd7-66c9-476b-b43e-3c531aa535ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803393326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2803393326
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1780242512
Short name T878
Test name
Test status
Simulation time 446384227 ps
CPU time 3.24 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 218264 kb
Host smart-1e49e61b-2f18-4ae9-b8e1-6e2889d1fb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780242512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1780242512
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1505335685
Short name T673
Test name
Test status
Simulation time 1429978167 ps
CPU time 7.83 seconds
Started Jun 23 05:05:43 PM PDT 24
Finished Jun 23 05:05:51 PM PDT 24
Peak memory 207804 kb
Host smart-478a08bd-8e07-4337-9860-8eb6e8ce5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505335685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1505335685
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1724800033
Short name T350
Test name
Test status
Simulation time 662440015 ps
CPU time 17.27 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:06:02 PM PDT 24
Peak memory 220400 kb
Host smart-2467b364-4795-4138-b571-2cdea6091675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724800033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1724800033
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3339643803
Short name T733
Test name
Test status
Simulation time 1303067457 ps
CPU time 14.36 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:59 PM PDT 24
Peak memory 218260 kb
Host smart-e3125b68-7607-4872-b781-2d412e0c1035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339643803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3339643803
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1885802260
Short name T449
Test name
Test status
Simulation time 65915584 ps
CPU time 2.8 seconds
Started Jun 23 05:05:44 PM PDT 24
Finished Jun 23 05:05:48 PM PDT 24
Peak memory 210160 kb
Host smart-e7eecca7-e49c-44c1-9f98-0c9eec4b13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885802260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1885802260
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2680554882
Short name T420
Test name
Test status
Simulation time 19357254 ps
CPU time 0.82 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:14 PM PDT 24
Peak memory 205908 kb
Host smart-0322d523-00fc-4aed-bab5-e5da4d61c1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680554882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2680554882
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3392556697
Short name T234
Test name
Test status
Simulation time 267693183 ps
CPU time 13.51 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 214700 kb
Host smart-47758dfe-d1ca-4e32-ac31-ec4d4f43f6db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392556697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3392556697
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3432113483
Short name T59
Test name
Test status
Simulation time 3891630172 ps
CPU time 11.3 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:20 PM PDT 24
Peak memory 209372 kb
Host smart-524590f5-41a3-4d3b-ba6b-9d106990972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432113483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3432113483
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.808879401
Short name T57
Test name
Test status
Simulation time 130304768 ps
CPU time 3.1 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 207712 kb
Host smart-d3045c2a-62b0-454c-b000-5cc4aaa37fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808879401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.808879401
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3334669137
Short name T52
Test name
Test status
Simulation time 1376707965 ps
CPU time 4.12 seconds
Started Jun 23 05:03:07 PM PDT 24
Finished Jun 23 05:03:11 PM PDT 24
Peak memory 215408 kb
Host smart-da07ff0c-3044-4cc1-a838-ce52595760ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334669137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3334669137
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3949413990
Short name T614
Test name
Test status
Simulation time 107834004 ps
CPU time 1.97 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:10 PM PDT 24
Peak memory 214212 kb
Host smart-5d1d50f6-3374-4a00-be4b-f71baba74789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949413990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3949413990
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.513825415
Short name T204
Test name
Test status
Simulation time 218200752 ps
CPU time 2.71 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 214348 kb
Host smart-ad9bd62f-8b2e-4b35-ab1e-7bae4d6db806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513825415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.513825415
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4009723970
Short name T275
Test name
Test status
Simulation time 635988998 ps
CPU time 7.83 seconds
Started Jun 23 05:03:11 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 214272 kb
Host smart-4bae11e0-8aac-435c-b220-32c5a33b4c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009723970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4009723970
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.101485356
Short name T909
Test name
Test status
Simulation time 758021554 ps
CPU time 5.11 seconds
Started Jun 23 05:03:11 PM PDT 24
Finished Jun 23 05:03:16 PM PDT 24
Peak memory 208988 kb
Host smart-23f0bdb9-04ae-4f67-8dd8-5f9ab9b73534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101485356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.101485356
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3638925762
Short name T771
Test name
Test status
Simulation time 210911256 ps
CPU time 2.32 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:11 PM PDT 24
Peak memory 206804 kb
Host smart-5b119d63-113d-4a94-b9b4-ff8e8d1d4118
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638925762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3638925762
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3463414399
Short name T270
Test name
Test status
Simulation time 367604953 ps
CPU time 2.82 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:15 PM PDT 24
Peak memory 208852 kb
Host smart-5ab0cda7-20de-4172-9c49-a645d6902101
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463414399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3463414399
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1539396496
Short name T794
Test name
Test status
Simulation time 52545466 ps
CPU time 2.74 seconds
Started Jun 23 05:03:10 PM PDT 24
Finished Jun 23 05:03:13 PM PDT 24
Peak memory 206784 kb
Host smart-bcbc1569-41ce-449c-823b-d2671be4d1eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539396496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1539396496
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2071756444
Short name T265
Test name
Test status
Simulation time 349596924 ps
CPU time 3.84 seconds
Started Jun 23 05:03:05 PM PDT 24
Finished Jun 23 05:03:10 PM PDT 24
Peak memory 222324 kb
Host smart-c5efd0dd-e176-4f3b-a34b-6174b964c448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071756444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2071756444
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.4089275371
Short name T442
Test name
Test status
Simulation time 103088542 ps
CPU time 3.05 seconds
Started Jun 23 05:03:08 PM PDT 24
Finished Jun 23 05:03:12 PM PDT 24
Peak memory 208700 kb
Host smart-e4c40fdb-e3f5-47f0-bcff-3b66da7a0ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089275371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.4089275371
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.990475048
Short name T175
Test name
Test status
Simulation time 653138234 ps
CPU time 11.73 seconds
Started Jun 23 05:03:16 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 222488 kb
Host smart-da8a910b-84f2-4146-8baa-75bf14fdf41e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990475048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.990475048
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2682753195
Short name T50
Test name
Test status
Simulation time 1107353838 ps
CPU time 19.56 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:34 PM PDT 24
Peak memory 222596 kb
Host smart-2b01fed5-6715-4cc6-88d7-df128e8d6c9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682753195 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2682753195
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.728713748
Short name T456
Test name
Test status
Simulation time 558608158 ps
CPU time 8.89 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:22 PM PDT 24
Peak memory 208536 kb
Host smart-652a3c12-4dcb-4598-ae76-6c0077035cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728713748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.728713748
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.933002339
Short name T520
Test name
Test status
Simulation time 889075032 ps
CPU time 2.85 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:17 PM PDT 24
Peak memory 209968 kb
Host smart-ff7a503b-c693-4a72-83e3-d667542eb9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933002339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.933002339
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3143287840
Short name T888
Test name
Test status
Simulation time 31445080 ps
CPU time 0.77 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:16 PM PDT 24
Peak memory 205928 kb
Host smart-6a9e4d4c-372d-4805-8f36-5f6633704f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143287840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3143287840
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3949140128
Short name T337
Test name
Test status
Simulation time 112174136 ps
CPU time 4.62 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 214324 kb
Host smart-1fd8a72f-89de-4784-b2cd-800ad8c80005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949140128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3949140128
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1067143196
Short name T230
Test name
Test status
Simulation time 176983071 ps
CPU time 3.64 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 209868 kb
Host smart-dfdecfc6-e8a9-4587-b56e-04f9ac415753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067143196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1067143196
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3450386507
Short name T328
Test name
Test status
Simulation time 118656044 ps
CPU time 2.03 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:17 PM PDT 24
Peak memory 208056 kb
Host smart-57f1b4f4-d9bc-480f-a7b5-cf4d1a58e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450386507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3450386507
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1450812945
Short name T41
Test name
Test status
Simulation time 298713121 ps
CPU time 5.16 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 214140 kb
Host smart-1cbf0349-6531-48ab-a746-16ea7c364cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450812945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1450812945
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2322081961
Short name T199
Test name
Test status
Simulation time 274361729 ps
CPU time 3.36 seconds
Started Jun 23 05:03:17 PM PDT 24
Finished Jun 23 05:03:21 PM PDT 24
Peak memory 218848 kb
Host smart-c39c44d5-b7f3-4a8a-9024-d555506bad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322081961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2322081961
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1696446918
Short name T166
Test name
Test status
Simulation time 1002514196 ps
CPU time 10.62 seconds
Started Jun 23 05:03:15 PM PDT 24
Finished Jun 23 05:03:26 PM PDT 24
Peak memory 218492 kb
Host smart-9ff4e410-8bd7-4490-8485-4f7984ea227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696446918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1696446918
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.165165892
Short name T593
Test name
Test status
Simulation time 980863389 ps
CPU time 7.2 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:22 PM PDT 24
Peak memory 208812 kb
Host smart-6da5944e-1527-4e54-899b-48a8e3874892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165165892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.165165892
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1437052998
Short name T227
Test name
Test status
Simulation time 271400535 ps
CPU time 3.49 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 208732 kb
Host smart-1e51ff16-2704-4645-8d55-ebdbf9fa6542
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437052998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1437052998
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.55899652
Short name T611
Test name
Test status
Simulation time 52416536 ps
CPU time 2.14 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:17 PM PDT 24
Peak memory 208760 kb
Host smart-3f6e45ed-00f7-4699-a211-cb952db33c5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55899652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.55899652
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.695110669
Short name T656
Test name
Test status
Simulation time 1534283821 ps
CPU time 10.12 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 208608 kb
Host smart-ba6604c2-3979-49f0-938c-1698d6397821
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695110669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.695110669
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2017879035
Short name T421
Test name
Test status
Simulation time 225874279 ps
CPU time 2.72 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:22 PM PDT 24
Peak memory 209004 kb
Host smart-618b5085-19c0-47df-9ddf-54d401c7a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017879035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2017879035
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1544233178
Short name T415
Test name
Test status
Simulation time 70277480 ps
CPU time 2.54 seconds
Started Jun 23 05:03:16 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 207248 kb
Host smart-3c842b5a-38dd-4a39-b6ac-fc14c5216f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544233178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1544233178
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2876996799
Short name T251
Test name
Test status
Simulation time 448730058 ps
CPU time 23.43 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:38 PM PDT 24
Peak memory 221376 kb
Host smart-4ea14be5-8665-409d-ae8c-f862cacd2473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876996799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2876996799
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3903104288
Short name T641
Test name
Test status
Simulation time 141322343 ps
CPU time 9.08 seconds
Started Jun 23 05:03:14 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 222540 kb
Host smart-c196e1be-6348-4dcc-bec7-8c566ad0117c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903104288 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3903104288
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.49794304
Short name T386
Test name
Test status
Simulation time 153769691 ps
CPU time 5.23 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 209440 kb
Host smart-92eed8f8-4cee-4b99-a5ab-103d7597beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49794304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.49794304
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3212563678
Short name T371
Test name
Test status
Simulation time 401462010 ps
CPU time 3.24 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:17 PM PDT 24
Peak memory 210676 kb
Host smart-cb5cb2f3-2ab9-45c6-b939-14b2c51b3158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212563678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3212563678
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1479095871
Short name T430
Test name
Test status
Simulation time 17325676 ps
CPU time 0.79 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:21 PM PDT 24
Peak memory 205924 kb
Host smart-27e38cc8-ddcf-4d85-b9cb-776c46d01dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479095871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1479095871
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1485133280
Short name T862
Test name
Test status
Simulation time 204454570 ps
CPU time 10.3 seconds
Started Jun 23 05:03:13 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 215116 kb
Host smart-6530fdcc-28c2-4e81-bc26-f631d95f2a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485133280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1485133280
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2983642811
Short name T543
Test name
Test status
Simulation time 567704415 ps
CPU time 3.9 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:25 PM PDT 24
Peak memory 220408 kb
Host smart-b0c2dcfc-f6b5-4bc5-8889-c2e5352bd353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983642811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2983642811
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2155732910
Short name T309
Test name
Test status
Simulation time 106326781 ps
CPU time 2.98 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 219592 kb
Host smart-a872db93-27bf-45ee-9d8a-f17c625e71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155732910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2155732910
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.43507413
Short name T304
Test name
Test status
Simulation time 416849220 ps
CPU time 2.77 seconds
Started Jun 23 05:03:18 PM PDT 24
Finished Jun 23 05:03:21 PM PDT 24
Peak memory 215492 kb
Host smart-7067ae1e-4c07-49d8-ade6-ff53278a5d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43507413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.43507413
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.752548572
Short name T62
Test name
Test status
Simulation time 107416289 ps
CPU time 4.76 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:25 PM PDT 24
Peak memory 222360 kb
Host smart-ba3f08dd-5c3f-438d-bc48-40c9c1ae5c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752548572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.752548572
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3719264854
Short name T286
Test name
Test status
Simulation time 42325520 ps
CPU time 2.23 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 210036 kb
Host smart-2af177a4-10ad-455d-a085-a0fe3485a356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719264854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3719264854
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1818293137
Short name T780
Test name
Test status
Simulation time 164059667 ps
CPU time 4.31 seconds
Started Jun 23 05:03:18 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 209520 kb
Host smart-62a6f43a-655c-4235-9815-971eb8c28d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818293137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1818293137
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2042052221
Short name T431
Test name
Test status
Simulation time 280612612 ps
CPU time 3.04 seconds
Started Jun 23 05:03:15 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 206884 kb
Host smart-149f0863-b8cd-44a3-be86-e2c043cc859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042052221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2042052221
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3421656123
Short name T644
Test name
Test status
Simulation time 78623473 ps
CPU time 2.47 seconds
Started Jun 23 05:03:16 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 206872 kb
Host smart-417e038d-2eb1-43de-90e8-10267fb58e88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421656123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3421656123
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2131803995
Short name T269
Test name
Test status
Simulation time 258934259 ps
CPU time 2.47 seconds
Started Jun 23 05:03:16 PM PDT 24
Finished Jun 23 05:03:19 PM PDT 24
Peak memory 207344 kb
Host smart-83d96e91-c756-4807-8e15-e86505f170f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131803995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2131803995
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1402386399
Short name T690
Test name
Test status
Simulation time 219480623 ps
CPU time 6.02 seconds
Started Jun 23 05:03:12 PM PDT 24
Finished Jun 23 05:03:18 PM PDT 24
Peak memory 207944 kb
Host smart-a22b39a8-0165-47e2-8975-2af55b75d1e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402386399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1402386399
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1846594467
Short name T528
Test name
Test status
Simulation time 977592000 ps
CPU time 2.84 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:03:38 PM PDT 24
Peak memory 210060 kb
Host smart-9b3e3d15-4448-46e5-9eac-e33be51b2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846594467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1846594467
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3012330276
Short name T99
Test name
Test status
Simulation time 1481836206 ps
CPU time 15.46 seconds
Started Jun 23 05:03:16 PM PDT 24
Finished Jun 23 05:03:32 PM PDT 24
Peak memory 208064 kb
Host smart-7a5b1f6d-f761-4476-846d-74987062e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012330276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3012330276
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.627113621
Short name T548
Test name
Test status
Simulation time 170593257 ps
CPU time 5.83 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:25 PM PDT 24
Peak memory 215656 kb
Host smart-a368ffe1-f978-44a4-8ac6-9ef9a4dc784b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627113621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.627113621
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3797753932
Short name T245
Test name
Test status
Simulation time 71471665 ps
CPU time 4.57 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:26 PM PDT 24
Peak memory 210324 kb
Host smart-336eadd0-9205-4464-b8c2-f7c9f1f0d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797753932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3797753932
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.207798541
Short name T529
Test name
Test status
Simulation time 26793102 ps
CPU time 1.26 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:22 PM PDT 24
Peak memory 209468 kb
Host smart-eb8f18c5-08ca-4797-8092-03d8993c8821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207798541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.207798541
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3877129689
Short name T720
Test name
Test status
Simulation time 36853617 ps
CPU time 0.76 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:20 PM PDT 24
Peak memory 205888 kb
Host smart-068f4a4b-1114-494f-861c-3a5b5af6f253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877129689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3877129689
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1117929015
Short name T126
Test name
Test status
Simulation time 36006733 ps
CPU time 2.93 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 214328 kb
Host smart-904ee57c-7ec9-45d6-949c-4e65aafd02da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117929015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1117929015
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.962428677
Short name T779
Test name
Test status
Simulation time 1203853363 ps
CPU time 6.59 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 222772 kb
Host smart-241deda1-f7ce-4287-8d7a-d9d6a7c18e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962428677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.962428677
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.241580021
Short name T572
Test name
Test status
Simulation time 290235964 ps
CPU time 3.59 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 209796 kb
Host smart-a3550d3f-b264-4647-af27-5f0b642e8a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241580021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.241580021
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4214113230
Short name T91
Test name
Test status
Simulation time 104695180 ps
CPU time 2.76 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 214484 kb
Host smart-190216f1-9c6f-49ab-b909-7210ec70e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214113230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4214113230
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1594700371
Short name T333
Test name
Test status
Simulation time 251401622 ps
CPU time 4 seconds
Started Jun 23 05:03:22 PM PDT 24
Finished Jun 23 05:03:27 PM PDT 24
Peak memory 214264 kb
Host smart-fccd544b-7d43-49ce-9d93-3d2ab734a538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594700371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1594700371
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2741797184
Short name T741
Test name
Test status
Simulation time 130044430 ps
CPU time 4.05 seconds
Started Jun 23 05:03:22 PM PDT 24
Finished Jun 23 05:03:26 PM PDT 24
Peak memory 206452 kb
Host smart-d5e78e61-e1d7-4978-920a-146fb4914ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741797184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2741797184
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2689947487
Short name T533
Test name
Test status
Simulation time 895113918 ps
CPU time 7.63 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 207148 kb
Host smart-c3bad6db-b392-4fa3-9b04-7408f2cc5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689947487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2689947487
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.986862727
Short name T776
Test name
Test status
Simulation time 126102504 ps
CPU time 3.73 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:03:39 PM PDT 24
Peak memory 208348 kb
Host smart-8c972541-b237-4619-bae7-08d5aa1c58fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986862727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.986862727
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3728903844
Short name T655
Test name
Test status
Simulation time 297895653 ps
CPU time 4.55 seconds
Started Jun 23 05:03:18 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 206880 kb
Host smart-7b64a146-f9e9-483e-a673-d21ff0926780
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728903844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3728903844
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4031305335
Short name T531
Test name
Test status
Simulation time 316052295 ps
CPU time 3.11 seconds
Started Jun 23 05:03:21 PM PDT 24
Finished Jun 23 05:03:24 PM PDT 24
Peak memory 206884 kb
Host smart-23ccf427-ca62-4c4f-909b-aee1a0d1e575
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031305335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4031305335
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2688112114
Short name T705
Test name
Test status
Simulation time 193996029 ps
CPU time 6.39 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:03:42 PM PDT 24
Peak memory 208484 kb
Host smart-e136ec7f-b4f7-429b-9149-e2c19cbb7b00
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688112114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2688112114
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2747650739
Short name T547
Test name
Test status
Simulation time 82741283 ps
CPU time 2.9 seconds
Started Jun 23 05:04:17 PM PDT 24
Finished Jun 23 05:04:20 PM PDT 24
Peak memory 208056 kb
Host smart-11f11772-0240-43fa-b517-65db601feb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747650739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2747650739
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2815831613
Short name T448
Test name
Test status
Simulation time 556582886 ps
CPU time 3.07 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 206032 kb
Host smart-a72a2862-9283-4705-aba2-f8dd5e360de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815831613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2815831613
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1650282103
Short name T723
Test name
Test status
Simulation time 156288028 ps
CPU time 9.45 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:30 PM PDT 24
Peak memory 222612 kb
Host smart-1059e2c7-2f50-4ea7-a4b1-f8abd1cbfaed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650282103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1650282103
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2032900762
Short name T892
Test name
Test status
Simulation time 99863421 ps
CPU time 4.27 seconds
Started Jun 23 05:03:21 PM PDT 24
Finished Jun 23 05:03:25 PM PDT 24
Peak memory 208604 kb
Host smart-7375cd45-6aac-4efc-9a61-fd8786a72848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032900762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2032900762
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.594962218
Short name T587
Test name
Test status
Simulation time 241396004 ps
CPU time 2.52 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:03:38 PM PDT 24
Peak memory 210208 kb
Host smart-4b61fd23-22a8-47c5-93d6-cfc3db4df05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594962218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.594962218
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3182122184
Short name T668
Test name
Test status
Simulation time 39418492 ps
CPU time 0.81 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:03:27 PM PDT 24
Peak memory 205908 kb
Host smart-dbc0c2e5-f9d0-4aad-87e3-52af933e0798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182122184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3182122184
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1742277342
Short name T838
Test name
Test status
Simulation time 303450256 ps
CPU time 8.66 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:03:44 PM PDT 24
Peak memory 215772 kb
Host smart-ea7ca09f-c2d9-4c5c-9fec-da40aa3835bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742277342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1742277342
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1837062916
Short name T552
Test name
Test status
Simulation time 389251142 ps
CPU time 4.51 seconds
Started Jun 23 05:03:26 PM PDT 24
Finished Jun 23 05:03:31 PM PDT 24
Peak memory 210464 kb
Host smart-8e34377b-60a5-4248-95f0-0edca4ed0578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837062916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1837062916
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.654590237
Short name T760
Test name
Test status
Simulation time 347494576 ps
CPU time 2.48 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 218200 kb
Host smart-f5ae283c-7600-4199-891a-afdbfa788fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654590237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.654590237
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1968030819
Short name T868
Test name
Test status
Simulation time 133828245 ps
CPU time 3.85 seconds
Started Jun 23 05:03:26 PM PDT 24
Finished Jun 23 05:03:30 PM PDT 24
Peak memory 222552 kb
Host smart-a9319e03-d68f-4057-afbc-0ecdfd5e4cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968030819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1968030819
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3638352448
Short name T262
Test name
Test status
Simulation time 91412196 ps
CPU time 1.87 seconds
Started Jun 23 05:03:27 PM PDT 24
Finished Jun 23 05:03:30 PM PDT 24
Peak memory 214264 kb
Host smart-066e2a5d-7abc-4c36-acdf-8613ece979da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638352448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3638352448
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2240746053
Short name T764
Test name
Test status
Simulation time 89522374 ps
CPU time 3.86 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:03:29 PM PDT 24
Peak memory 214240 kb
Host smart-9a248205-d262-4b0b-a4d1-0fc189141b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240746053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2240746053
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1204307349
Short name T80
Test name
Test status
Simulation time 469439050 ps
CPU time 6.1 seconds
Started Jun 23 05:03:18 PM PDT 24
Finished Jun 23 05:03:25 PM PDT 24
Peak memory 214268 kb
Host smart-88bec613-b1ba-4317-89d9-a53f580e7e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204307349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1204307349
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.481289453
Short name T791
Test name
Test status
Simulation time 129819333 ps
CPU time 3.32 seconds
Started Jun 23 05:03:19 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 208584 kb
Host smart-0defc351-ee25-4981-8554-a52fc8195791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481289453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.481289453
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2704871089
Short name T453
Test name
Test status
Simulation time 607888331 ps
CPU time 5.06 seconds
Started Jun 23 05:03:34 PM PDT 24
Finished Jun 23 05:03:40 PM PDT 24
Peak memory 206728 kb
Host smart-69579359-f20d-45b6-ac4b-06eafac31f5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704871089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2704871089
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3012809662
Short name T671
Test name
Test status
Simulation time 5153454806 ps
CPU time 30.6 seconds
Started Jun 23 05:03:35 PM PDT 24
Finished Jun 23 05:04:06 PM PDT 24
Peak memory 209240 kb
Host smart-e60df4fe-9056-4b46-99b8-7432ddcc54f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012809662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3012809662
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.514264440
Short name T886
Test name
Test status
Simulation time 436383022 ps
CPU time 6.51 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:27 PM PDT 24
Peak memory 208960 kb
Host smart-ae40e49b-48b0-431f-97e6-71e44f1184f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514264440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.514264440
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.620146658
Short name T181
Test name
Test status
Simulation time 113278557 ps
CPU time 2.43 seconds
Started Jun 23 05:03:24 PM PDT 24
Finished Jun 23 05:03:27 PM PDT 24
Peak memory 215964 kb
Host smart-f65b5caf-f8fe-4902-8750-4ed25bd9188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620146658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.620146658
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3385052821
Short name T646
Test name
Test status
Simulation time 43764548 ps
CPU time 1.67 seconds
Started Jun 23 05:03:20 PM PDT 24
Finished Jun 23 05:03:23 PM PDT 24
Peak memory 206844 kb
Host smart-733766ea-eab0-4fe9-8da0-2050a2602792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385052821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3385052821
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.385191094
Short name T210
Test name
Test status
Simulation time 73250208565 ps
CPU time 689.98 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:14:56 PM PDT 24
Peak memory 230800 kb
Host smart-090d08db-9d70-402b-9283-c022b342f71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385191094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.385191094
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1241762842
Short name T268
Test name
Test status
Simulation time 2508135627 ps
CPU time 23.3 seconds
Started Jun 23 05:03:26 PM PDT 24
Finished Jun 23 05:03:49 PM PDT 24
Peak memory 222764 kb
Host smart-c6da9833-2e9b-46fa-a1d0-3f4e08aeb7eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241762842 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1241762842
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3569362784
Short name T906
Test name
Test status
Simulation time 202496261 ps
CPU time 6.26 seconds
Started Jun 23 05:03:27 PM PDT 24
Finished Jun 23 05:03:34 PM PDT 24
Peak memory 209192 kb
Host smart-0515ea7e-41b0-41c0-a02c-83062f86f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569362784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3569362784
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2433690542
Short name T750
Test name
Test status
Simulation time 98038814 ps
CPU time 3.31 seconds
Started Jun 23 05:03:25 PM PDT 24
Finished Jun 23 05:03:28 PM PDT 24
Peak memory 209808 kb
Host smart-2401cd52-8498-494b-b778-fa520efbceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433690542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2433690542
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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