Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

12051

1

T1

10

T2

15

T3

3

auto[Attestation]

8513

1

T1

5

T2

11

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3087	1			T1	4		T2	3		T4	3
auto[Aes]	3664	1			T1	3		T2	5		T14	8
auto[Kmac]	3481	1			T1	2		T2	6		T4	3
auto[Otbn]	3695	1			T1	4		T2	3		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8546	1			T1	5		T2	8		T3	8
auto[OpGenId]	6637	1			T1	2		T2	9		T4	5
auto[OpGenSwOut]	6672	1			T1	8		T2	11		T4	7
auto[OpGenHwOut]	7255	1			T1	5		T2	6		T3	8
auto[OpDisable]	161	1			T1	1		T19	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11779

1

T1

12

T2

12

T3

8

auto[OpDoneFail]

17492

1

T1

9

T2

22

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6978	1			T1	5		T2	7		T3	1
auto[StInit]	4149	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3483	1			T1	5		T2	3		T3	2
auto[StOwnerIntKey]	3050	1			T1	2		T2	6		T3	2
auto[StOwnerKey]	2745	1			T1	3		T2	1		T3	2
auto[StDisabled]	8866	1			T1	4		T2	15		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	321	1			T15	1		T35	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	118	1			T1	1		T19	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	104	1			T29	2		T81	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	85	1			T17	1		T18	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	74	1			T1	1		T35	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	254	1			T4	1		T29	2		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	386	1			T2	2		T15	2		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	113	1			T47	2		T29	2		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T35	1		T29	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T2	1		T17	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	64	1			T19	1		T35	1		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	249	1			T1	1		T2	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	319	1			T1	1		T2	1		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	126	1			T28	1		T29	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T29	2		T62	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T17	1		T47	1		T30	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T145	2		T135	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	242	1			T2	1		T35	1		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	370	1			T35	1		T29	2		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	121	1			T58	2		T25	2		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T1	1		T47	1		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T19	1		T35	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	70	1			T47	1		T58	2		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	262	1			T35	1		T47	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	111	1			T81	1		T58	7		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T4	1		T47	2		T29	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	95	1			T1	1		T4	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	74	1			T47	1		T83	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	78	1			T18	1		T19	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	287	1			T2	2		T17	1		T29	7
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	93	1			T81	3		T54	1		T58	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	116	1			T35	1		T29	3		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T1	1		T47	1		T29	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	61	1			T18	1		T28	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	77	1			T29	3		T58	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	251	1			T28	1		T29	4		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	100	1			T81	1		T58	7		T111	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T18	1		T47	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	86	1			T29	3		T58	2		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T2	1		T28	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	51	1			T18	1		T35	2		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	225	1			T35	1		T47	2		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	75	1			T29	3		T81	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T29	1		T81	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T47	1		T28	1		T29	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T4	1		T35	2		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	59	1			T17	1		T29	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T1	1		T2	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	274	1			T1	1		T35	1		T47	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T29	1		T36	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T19	2		T58	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T58	1		T199	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T18	1		T29	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T35	1		T47	3		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	464	1			T16	16		T35	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	128	1			T16	1		T17	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	112	1			T14	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T18	1		T79	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	105	1			T14	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	295	1			T14	1		T16	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	423	1			T1	1		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T2	1		T18	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T2	1		T29	2		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T61	1		T214	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	117	1			T18	1		T5	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	293	1			T17	1		T28	1		T29	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	432	1			T1	1		T15	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T54	3		T58	2		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T1	1		T47	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T213	1		T58	3		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	94	1			T3	1		T64	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	300	1			T3	2		T35	1		T29	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	66	1			T81	3		T54	2		T58	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	112	1			T17	3		T29	2		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	85	1			T19	1		T36	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T18	1		T35	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	47	1			T19	1		T216	1		T144	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	218	1			T2	1		T47	1		T29	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	81	1			T29	2		T54	2		T58	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	132	1			T14	1		T19	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	111	1			T16	1		T38	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	106	1			T14	1		T16	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T16	1		T19	1		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	266	1			T1	1		T2	1		T14	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	70	1			T29	3		T54	2		T58	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	125	1			T18	1		T47	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T29	2		T61	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T19	1		T35	1		T29	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T18	1		T37	1		T58	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T17	1		T29	6		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	76	1			T54	1		T58	3		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	132	1			T3	1		T18	2		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	122	1			T3	1		T18	1		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T2	1		T3	1		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	105	1			T18	1		T29	2		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	292	1			T3	2		T17	1		T35	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	245	1			T1	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	711	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	230	1			T2	1		T17	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	763	1			T1	1		T2	3		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	222	1			T17	1		T47	1		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	701	1			T1	1		T2	2		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	245	1			T1	1		T19	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	762	1			T35	2		T47	1		T29	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	234	1			T1	1		T4	1		T18	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	514	1			T2	2		T4	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	207	1			T1	1		T18	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	480	1			T35	1		T28	2		T29	7
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T2	1		T18	1		T35	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	449	1			T18	1		T35	1		T47	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	227	1			T4	1		T17	1		T35	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	473	1			T1	1		T2	2		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T18	1		T19	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	611	1			T1	1		T35	2		T47	8
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	295	1			T14	2		T17	1		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	907	1			T14	1		T16	20		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T2	1		T18	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	853	1			T1	1		T2	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T1	1		T3	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	875	1			T1	1		T3	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	173	1			T18	1		T19	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	416	1			T2	1		T17	3		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	285	1			T14	1		T16	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	497	1			T1	1		T2	1		T14	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T18	1		T19	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	493	1			T17	1		T18	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	309	1			T2	1		T3	2		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	519	1			T3	3		T17	1		T18	2