Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35843

1

T1

23

T2

39

T3

21

auto[1]

281

1

T2

8

T119

4

T144

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	35852	1			T1	23		T2	40		T3	21
auto[134217728:268435455]	14	1			T119	1		T136	1		T137	1
auto[268435456:402653183]	8	1			T185	1		T381	1		T390	1
auto[402653184:536870911]	9	1			T135	1		T282	1		T380	1
auto[536870912:671088639]	7	1			T144	1		T286	1		T348	1
auto[671088640:805306367]	8	1			T2	1		T135	1		T267	1
auto[805306368:939524095]	8	1			T145	1		T391	1		T392	1
auto[939524096:1073741823]	6	1			T2	1		T238	1		T392	2
auto[1073741824:1207959551]	4	1			T282	1		T393	1		T394	2
auto[1207959552:1342177279]	10	1			T119	1		T135	1		T348	1
auto[1342177280:1476395007]	7	1			T2	1		T145	1		T238	1
auto[1476395008:1610612735]	10	1			T144	1		T145	1		T137	1
auto[1610612736:1744830463]	10	1			T119	1		T135	1		T370	1
auto[1744830464:1879048191]	9	1			T391	1		T380	1		T272	1
auto[1879048192:2013265919]	10	1			T137	1		T348	1		T282	1
auto[2013265920:2147483647]	6	1			T348	1		T391	1		T284	1
auto[2147483648:2281701375]	11	1			T136	1		T138	1		T369	1
auto[2281701376:2415919103]	9	1			T136	1		T322	1		T395	1
auto[2415919104:2550136831]	11	1			T286	1		T348	1		T380	1
auto[2550136832:2684354559]	8	1			T322	1		T284	1		T272	1
auto[2684354560:2818572287]	7	1			T144	1		T135	1		T285	1
auto[2818572288:2952790015]	10	1			T2	1		T135	1		T362	1
auto[2952790016:3087007743]	8	1			T2	1		T138	1		T322	1
auto[3087007744:3221225471]	15	1			T2	1		T135	1		T362	1
auto[3221225472:3355443199]	4	1			T135	1		T369	1		T285	1
auto[3355443200:3489660927]	12	1			T119	1		T348	1		T369	1
auto[3489660928:3623878655]	7	1			T322	1		T272	1		T185	1
auto[3623878656:3758096383]	6	1			T144	1		T136	1		T362	1
auto[3758096384:3892314111]	9	1			T2	1		T138	1		T362	1
auto[3892314112:4026531839]	9	1			T136	1		T238	1		T380	1
auto[4026531840:4160749567]	8	1			T145	1		T137	1		T138	1
auto[4160749568:4294967295]	12	1			T135	1		T286	1		T348	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	30	34	53.12	30

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[671088640:805306367]]	[auto[0]]	--	--	5
[auto[939524096:1073741823] - auto[4160749568:4294967295]]	[auto[0]]	--	--	25

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35842	1			T1	23		T2	39		T3	21
auto[0:134217727]	auto[1]	10	1			T2	1		T145	2		T369	1
auto[134217728:268435455]	auto[1]	14	1			T119	1		T136	1		T137	1
auto[268435456:402653183]	auto[1]	8	1			T185	1		T381	1		T390	1
auto[402653184:536870911]	auto[1]	9	1			T135	1		T282	1		T380	1
auto[536870912:671088639]	auto[1]	7	1			T144	1		T286	1		T348	1
auto[671088640:805306367]	auto[1]	8	1			T2	1		T135	1		T267	1
auto[805306368:939524095]	auto[0]	1	1			T145	1		-	-		-	-
auto[805306368:939524095]	auto[1]	7	1			T391	1		T392	1		T396	1
auto[939524096:1073741823]	auto[1]	6	1			T2	1		T238	1		T392	2
auto[1073741824:1207959551]	auto[1]	4	1			T282	1		T393	1		T394	2
auto[1207959552:1342177279]	auto[1]	10	1			T119	1		T135	1		T348	1
auto[1342177280:1476395007]	auto[1]	7	1			T2	1		T145	1		T238	1
auto[1476395008:1610612735]	auto[1]	10	1			T144	1		T145	1		T137	1
auto[1610612736:1744830463]	auto[1]	10	1			T119	1		T135	1		T370	1
auto[1744830464:1879048191]	auto[1]	9	1			T391	1		T380	1		T272	1
auto[1879048192:2013265919]	auto[1]	10	1			T137	1		T348	1		T282	1
auto[2013265920:2147483647]	auto[1]	6	1			T348	1		T391	1		T284	1
auto[2147483648:2281701375]	auto[1]	11	1			T136	1		T138	1		T369	1
auto[2281701376:2415919103]	auto[1]	9	1			T136	1		T322	1		T395	1
auto[2415919104:2550136831]	auto[1]	11	1			T286	1		T348	1		T380	1
auto[2550136832:2684354559]	auto[1]	8	1			T322	1		T284	1		T272	1
auto[2684354560:2818572287]	auto[1]	7	1			T144	1		T135	1		T285	1
auto[2818572288:2952790015]	auto[1]	10	1			T2	1		T135	1		T362	1
auto[2952790016:3087007743]	auto[1]	8	1			T2	1		T138	1		T322	1
auto[3087007744:3221225471]	auto[1]	15	1			T2	1		T135	1		T362	1
auto[3221225472:3355443199]	auto[1]	4	1			T135	1		T369	1		T285	1
auto[3355443200:3489660927]	auto[1]	12	1			T119	1		T348	1		T369	1
auto[3489660928:3623878655]	auto[1]	7	1			T322	1		T272	1		T185	1
auto[3623878656:3758096383]	auto[1]	6	1			T144	1		T136	1		T362	1
auto[3758096384:3892314111]	auto[1]	9	1			T2	1		T138	1		T362	1
auto[3892314112:4026531839]	auto[1]	9	1			T136	1		T238	1		T380	1
auto[4026531840:4160749567]	auto[1]	8	1			T145	1		T137	1		T138	1
auto[4160749568:4294967295]	auto[1]	12	1			T135	1		T286	1		T348	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1828

1

T1

2

T2

3

T15

4

auto[1]

1995

1

T1

2

T2

1

T17

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T35	1		T29	3		T83	1
auto[134217728:268435455]	107	1			T17	1		T47	2		T61	1
auto[268435456:402653183]	139	1			T39	1		T133	1		T54	1
auto[402653184:536870911]	101	1			T35	2		T29	2		T54	1
auto[536870912:671088639]	111	1			T28	1		T58	2		T216	1
auto[671088640:805306367]	139	1			T1	1		T35	1		T29	4
auto[805306368:939524095]	132	1			T29	4		T54	1		T50	1
auto[939524096:1073741823]	120	1			T28	1		T29	1		T81	1
auto[1073741824:1207959551]	111	1			T1	1		T2	1		T29	3
auto[1207959552:1342177279]	118	1			T19	1		T39	1		T54	1
auto[1342177280:1476395007]	109	1			T47	1		T29	3		T39	1
auto[1476395008:1610612735]	138	1			T29	5		T54	1		T262	1
auto[1610612736:1744830463]	117	1			T19	1		T47	1		T28	1
auto[1744830464:1879048191]	107	1			T17	1		T29	2		T37	1
auto[1879048192:2013265919]	110	1			T1	1		T29	2		T30	1
auto[2013265920:2147483647]	121	1			T15	1		T47	1		T29	1
auto[2147483648:2281701375]	119	1			T47	1		T61	1		T39	1
auto[2281701376:2415919103]	114	1			T47	1		T29	1		T81	1
auto[2415919104:2550136831]	127	1			T47	1		T29	2		T30	1
auto[2550136832:2684354559]	112	1			T35	1		T29	2		T54	1
auto[2684354560:2818572287]	116	1			T17	1		T54	2		T213	1
auto[2818572288:2952790015]	115	1			T2	1		T29	2		T6	1
auto[2952790016:3087007743]	129	1			T37	1		T5	1		T83	1
auto[3087007744:3221225471]	111	1			T1	1		T29	3		T5	1
auto[3221225472:3355443199]	135	1			T2	1		T15	1		T35	1
auto[3355443200:3489660927]	138	1			T28	1		T29	5		T81	1
auto[3489660928:3623878655]	120	1			T47	1		T29	4		T5	1
auto[3623878656:3758096383]	125	1			T15	1		T29	1		T39	1
auto[3758096384:3892314111]	102	1			T15	1		T29	1		T5	1
auto[3892314112:4026531839]	136	1			T47	1		T29	1		T83	1
auto[4026531840:4160749567]	115	1			T2	1		T35	1		T28	1
auto[4160749568:4294967295]	116	1			T29	2		T39	1		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T29	1		T83	1		T39	1
auto[0:134217727]	auto[1]	56	1			T35	1		T29	2		T262	1
auto[134217728:268435455]	auto[0]	54	1			T47	1		T54	1		T135	1
auto[134217728:268435455]	auto[1]	53	1			T17	1		T47	1		T61	1
auto[268435456:402653183]	auto[0]	64	1			T133	1		T262	1		T31	1
auto[268435456:402653183]	auto[1]	75	1			T39	1		T54	1		T50	1
auto[402653184:536870911]	auto[0]	48	1			T35	1		T29	2		T58	1
auto[402653184:536870911]	auto[1]	53	1			T35	1		T54	1		T214	1
auto[536870912:671088639]	auto[0]	55	1			T28	1		T58	2		T216	1
auto[536870912:671088639]	auto[1]	56	1			T68	2		T49	5		T297	1
auto[671088640:805306367]	auto[0]	68	1			T1	1		T29	2		T61	1
auto[671088640:805306367]	auto[1]	71	1			T35	1		T29	2		T54	1
auto[805306368:939524095]	auto[0]	68	1			T29	1		T54	1		T31	1
auto[805306368:939524095]	auto[1]	64	1			T29	3		T50	1		T135	1
auto[939524096:1073741823]	auto[0]	58	1			T28	1		T29	1		T216	2
auto[939524096:1073741823]	auto[1]	62	1			T81	1		T54	1		T213	1
auto[1073741824:1207959551]	auto[0]	55	1			T1	1		T2	1		T29	1
auto[1073741824:1207959551]	auto[1]	56	1			T29	2		T262	1		T48	1
auto[1207959552:1342177279]	auto[0]	55	1			T39	1		T54	1		T214	1
auto[1207959552:1342177279]	auto[1]	63	1			T19	1		T58	1		T50	1
auto[1342177280:1476395007]	auto[0]	51	1			T29	3		T54	1		T50	1
auto[1342177280:1476395007]	auto[1]	58	1			T47	1		T39	1		T144	1
auto[1476395008:1610612735]	auto[0]	75	1			T29	4		T58	1		T56	1
auto[1476395008:1610612735]	auto[1]	63	1			T29	1		T54	1		T262	1
auto[1610612736:1744830463]	auto[0]	50	1			T28	1		T5	1		T61	1
auto[1610612736:1744830463]	auto[1]	67	1			T19	1		T47	1		T214	1
auto[1744830464:1879048191]	auto[0]	53	1			T29	1		T145	1		T200	1
auto[1744830464:1879048191]	auto[1]	54	1			T17	1		T29	1		T37	1
auto[1879048192:2013265919]	auto[0]	71	1			T29	1		T39	2		T6	2
auto[1879048192:2013265919]	auto[1]	39	1			T1	1		T29	1		T30	1
auto[2013265920:2147483647]	auto[0]	58	1			T15	1		T47	1		T29	1
auto[2013265920:2147483647]	auto[1]	63	1			T54	1		T58	1		T22	1
auto[2147483648:2281701375]	auto[0]	57	1			T61	1		T58	2		T50	1
auto[2147483648:2281701375]	auto[1]	62	1			T47	1		T39	1		T262	1
auto[2281701376:2415919103]	auto[0]	64	1			T29	1		T81	1		T50	1
auto[2281701376:2415919103]	auto[1]	50	1			T47	1		T54	1		T58	1
auto[2415919104:2550136831]	auto[0]	64	1			T29	1		T54	1		T213	1
auto[2415919104:2550136831]	auto[1]	63	1			T47	1		T29	1		T30	1
auto[2550136832:2684354559]	auto[0]	52	1			T35	1		T29	1		T6	1
auto[2550136832:2684354559]	auto[1]	60	1			T29	1		T54	1		T58	2
auto[2684354560:2818572287]	auto[0]	55	1			T50	1		T145	1		T57	1
auto[2684354560:2818572287]	auto[1]	61	1			T17	1		T54	2		T213	1
auto[2818572288:2952790015]	auto[0]	47	1			T2	1		T29	1		T6	1
auto[2818572288:2952790015]	auto[1]	68	1			T29	1		T58	2		T216	1
auto[2952790016:3087007743]	auto[0]	65	1			T37	1		T262	1		T213	1
auto[2952790016:3087007743]	auto[1]	64	1			T5	1		T83	1		T58	1
auto[3087007744:3221225471]	auto[0]	50	1			T29	2		T5	1		T83	1
auto[3087007744:3221225471]	auto[1]	61	1			T1	1		T29	1		T58	1
auto[3221225472:3355443199]	auto[0]	49	1			T2	1		T15	1		T35	1
auto[3221225472:3355443199]	auto[1]	86	1			T28	1		T29	1		T58	2
auto[3355443200:3489660927]	auto[0]	56	1			T28	1		T29	2		T81	1
auto[3355443200:3489660927]	auto[1]	82	1			T29	3		T54	2		T262	1
auto[3489660928:3623878655]	auto[0]	61	1			T29	2		T54	1		T58	1
auto[3489660928:3623878655]	auto[1]	59	1			T47	1		T29	2		T5	1
auto[3623878656:3758096383]	auto[0]	52	1			T15	1		T29	1		T39	1
auto[3623878656:3758096383]	auto[1]	73	1			T133	1		T54	2		T58	1
auto[3758096384:3892314111]	auto[0]	49	1			T15	1		T216	1		T74	1
auto[3758096384:3892314111]	auto[1]	53	1			T29	1		T5	1		T58	1
auto[3892314112:4026531839]	auto[0]	54	1			T47	1		T29	1		T25	1
auto[3892314112:4026531839]	auto[1]	82	1			T83	1		T133	1		T54	2
auto[4026531840:4160749567]	auto[0]	54	1			T35	1		T28	1		T216	1
auto[4026531840:4160749567]	auto[1]	61	1			T2	1		T29	3		T6	1
auto[4160749568:4294967295]	auto[0]	59	1			T29	1		T39	1		T58	1
auto[4160749568:4294967295]	auto[1]	57	1			T29	1		T119	1		T135	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1819

1

T1

2

T2

1

T15

4

auto[1]

2004

1

T1

2

T2

3

T17

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	116	1			T29	1		T30	1		T54	1
auto[134217728:268435455]	119	1			T35	2		T54	1		T262	1
auto[268435456:402653183]	138	1			T39	1		T54	1		T262	1
auto[402653184:536870911]	131	1			T35	1		T47	2		T29	1
auto[536870912:671088639]	120	1			T47	1		T29	2		T39	1
auto[671088640:805306367]	111	1			T1	1		T2	1		T29	5
auto[805306368:939524095]	118	1			T19	1		T29	2		T262	1
auto[939524096:1073741823]	119	1			T35	1		T29	3		T5	1
auto[1073741824:1207959551]	118	1			T1	1		T29	3		T20	1
auto[1207959552:1342177279]	117	1			T35	1		T47	1		T29	1
auto[1342177280:1476395007]	122	1			T29	4		T58	2		T211	1
auto[1476395008:1610612735]	130	1			T29	3		T54	2		T213	1
auto[1610612736:1744830463]	118	1			T1	1		T29	1		T37	1
auto[1744830464:1879048191]	119	1			T5	2		T262	1		T214	1
auto[1879048192:2013265919]	119	1			T19	1		T35	1		T47	1
auto[2013265920:2147483647]	127	1			T47	1		T28	1		T81	1
auto[2147483648:2281701375]	123	1			T29	3		T58	1		T64	1
auto[2281701376:2415919103]	123	1			T15	1		T47	2		T28	1
auto[2415919104:2550136831]	139	1			T28	1		T29	2		T37	1
auto[2550136832:2684354559]	134	1			T28	2		T29	1		T37	1
auto[2684354560:2818572287]	109	1			T2	1		T17	1		T47	1
auto[2818572288:2952790015]	117	1			T28	1		T29	1		T61	1
auto[2952790016:3087007743]	108	1			T15	1		T47	1		T29	1
auto[3087007744:3221225471]	127	1			T47	1		T29	3		T39	2
auto[3221225472:3355443199]	112	1			T1	1		T29	5		T81	1
auto[3355443200:3489660927]	114	1			T54	1		T58	1		T111	1
auto[3489660928:3623878655]	107	1			T2	1		T17	1		T29	4
auto[3623878656:3758096383]	118	1			T15	1		T35	1		T39	1
auto[3758096384:3892314111]	119	1			T2	1		T15	1		T5	1
auto[3892314112:4026531839]	109	1			T17	1		T5	1		T83	1
auto[4026531840:4160749567]	112	1			T29	1		T61	1		T39	2
auto[4160749568:4294967295]	110	1			T29	2		T61	1		T133	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T58	1		T56	2		T51	1
auto[0:134217727]	auto[1]	60	1			T29	1		T30	1		T54	1
auto[134217728:268435455]	auto[0]	53	1			T35	1		T54	1		T262	1
auto[134217728:268435455]	auto[1]	66	1			T35	1		T58	1		T50	1
auto[268435456:402653183]	auto[0]	68	1			T39	1		T54	1		T262	1
auto[268435456:402653183]	auto[1]	70	1			T58	1		T144	1		T135	2
auto[402653184:536870911]	auto[0]	65	1			T35	1		T47	1		T56	1
auto[402653184:536870911]	auto[1]	66	1			T47	1		T29	1		T54	1
auto[536870912:671088639]	auto[0]	53	1			T47	1		T39	1		T57	1
auto[536870912:671088639]	auto[1]	67	1			T29	2		T54	1		T211	1
auto[671088640:805306367]	auto[0]	64	1			T29	4		T83	1		T216	2
auto[671088640:805306367]	auto[1]	47	1			T1	1		T2	1		T29	1
auto[805306368:939524095]	auto[0]	58	1			T29	1		T262	1		T119	1
auto[805306368:939524095]	auto[1]	60	1			T19	1		T29	1		T58	2
auto[939524096:1073741823]	auto[0]	63	1			T35	1		T29	2		T54	2
auto[939524096:1073741823]	auto[1]	56	1			T29	1		T5	1		T262	2
auto[1073741824:1207959551]	auto[0]	53	1			T1	1		T29	2		T20	1
auto[1073741824:1207959551]	auto[1]	65	1			T29	1		T135	1		T111	1
auto[1207959552:1342177279]	auto[0]	53	1			T47	1		T83	1		T54	1
auto[1207959552:1342177279]	auto[1]	64	1			T35	1		T29	1		T61	1
auto[1342177280:1476395007]	auto[0]	58	1			T29	1		T58	1		T240	1
auto[1342177280:1476395007]	auto[1]	64	1			T29	3		T58	1		T211	1
auto[1476395008:1610612735]	auto[0]	57	1			T29	2		T54	1		T213	1
auto[1476395008:1610612735]	auto[1]	73	1			T29	1		T54	1		T216	1
auto[1610612736:1744830463]	auto[0]	61	1			T1	1		T29	1		T37	1
auto[1610612736:1744830463]	auto[1]	57	1			T58	1		T111	1		T206	1
auto[1744830464:1879048191]	auto[0]	56	1			T5	1		T262	1		T214	1
auto[1744830464:1879048191]	auto[1]	63	1			T5	1		T56	1		T25	1
auto[1879048192:2013265919]	auto[0]	65	1			T35	1		T47	1		T29	3
auto[1879048192:2013265919]	auto[1]	54	1			T19	1		T29	4		T58	1
auto[2013265920:2147483647]	auto[0]	55	1			T81	1		T54	2		T6	1
auto[2013265920:2147483647]	auto[1]	72	1			T47	1		T28	1		T39	1
auto[2147483648:2281701375]	auto[0]	55	1			T29	1		T7	1		T49	1
auto[2147483648:2281701375]	auto[1]	68	1			T29	2		T58	1		T64	1
auto[2281701376:2415919103]	auto[0]	55	1			T15	1		T47	1		T29	1
auto[2281701376:2415919103]	auto[1]	68	1			T47	1		T28	1		T58	2
auto[2415919104:2550136831]	auto[0]	72	1			T28	1		T29	1		T37	1
auto[2415919104:2550136831]	auto[1]	67	1			T29	1		T81	1		T54	1
auto[2550136832:2684354559]	auto[0]	69	1			T28	1		T29	1		T58	2
auto[2550136832:2684354559]	auto[1]	65	1			T28	1		T37	1		T30	1
auto[2684354560:2818572287]	auto[0]	46	1			T6	1		T50	1		T62	1
auto[2684354560:2818572287]	auto[1]	63	1			T2	1		T17	1		T47	1
auto[2818572288:2952790015]	auto[0]	59	1			T28	1		T29	1		T61	1
auto[2818572288:2952790015]	auto[1]	58	1			T54	1		T111	1		T87	1
auto[2952790016:3087007743]	auto[0]	52	1			T15	1		T29	1		T58	1
auto[2952790016:3087007743]	auto[1]	56	1			T47	1		T54	1		T50	1
auto[3087007744:3221225471]	auto[0]	59	1			T47	1		T29	1		T39	1
auto[3087007744:3221225471]	auto[1]	68	1			T29	2		T39	1		T214	1
auto[3221225472:3355443199]	auto[0]	54	1			T29	3		T81	1		T54	1
auto[3221225472:3355443199]	auto[1]	58	1			T1	1		T29	2		T214	1
auto[3355443200:3489660927]	auto[0]	53	1			T54	1		T206	1		T48	1
auto[3355443200:3489660927]	auto[1]	61	1			T58	1		T111	1		T7	1
auto[3489660928:3623878655]	auto[0]	58	1			T29	2		T214	1		T58	1
auto[3489660928:3623878655]	auto[1]	49	1			T2	1		T17	1		T29	2
auto[3623878656:3758096383]	auto[0]	50	1			T15	1		T39	1		T200	1
auto[3623878656:3758096383]	auto[1]	68	1			T35	1		T133	1		T54	1
auto[3758096384:3892314111]	auto[0]	56	1			T2	1		T15	1		T135	1
auto[3758096384:3892314111]	auto[1]	63	1			T5	1		T54	1		T59	1
auto[3892314112:4026531839]	auto[0]	38	1			T5	1		T39	1		T56	1
auto[3892314112:4026531839]	auto[1]	71	1			T17	1		T83	1		T7	1
auto[4026531840:4160749567]	auto[0]	50	1			T29	1		T39	2		T50	1
auto[4026531840:4160749567]	auto[1]	62	1			T61	1		T54	1		T20	1
auto[4160749568:4294967295]	auto[0]	55	1			T133	1		T200	1		T111	1
auto[4160749568:4294967295]	auto[1]	55	1			T29	2		T61	1		T133	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1821

1

T1

2

T2

1

T15

3

auto[1]

2002

1

T1

2

T2

3

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	127	1			T28	1		T29	1		T39	1
auto[134217728:268435455]	92	1			T1	1		T29	1		T262	1
auto[268435456:402653183]	100	1			T2	1		T35	1		T29	4
auto[402653184:536870911]	119	1			T47	1		T29	2		T83	1
auto[536870912:671088639]	139	1			T19	1		T47	1		T28	1
auto[671088640:805306367]	123	1			T2	1		T47	2		T29	2
auto[805306368:939524095]	106	1			T47	1		T30	1		T39	1
auto[939524096:1073741823]	103	1			T17	1		T29	2		T58	1
auto[1073741824:1207959551]	120	1			T2	1		T81	1		T262	1
auto[1207959552:1342177279]	125	1			T35	1		T28	1		T29	5
auto[1342177280:1476395007]	116	1			T15	1		T17	1		T29	3
auto[1476395008:1610612735]	134	1			T15	1		T47	1		T29	3
auto[1610612736:1744830463]	128	1			T35	1		T29	4		T54	1
auto[1744830464:1879048191]	121	1			T1	1		T2	1		T19	1
auto[1879048192:2013265919]	124	1			T1	1		T29	2		T81	1
auto[2013265920:2147483647]	132	1			T28	1		T29	2		T37	1
auto[2147483648:2281701375]	104	1			T29	1		T6	1		T58	1
auto[2281701376:2415919103]	112	1			T47	1		T29	2		T61	1
auto[2415919104:2550136831]	119	1			T35	1		T28	2		T29	1
auto[2550136832:2684354559]	114	1			T35	1		T29	1		T5	1
auto[2684354560:2818572287]	120	1			T1	1		T39	1		T214	1
auto[2818572288:2952790015]	128	1			T47	1		T29	4		T37	1
auto[2952790016:3087007743]	120	1			T37	1		T83	1		T54	1
auto[3087007744:3221225471]	131	1			T15	1		T17	1		T29	2
auto[3221225472:3355443199]	111	1			T29	2		T5	1		T61	1
auto[3355443200:3489660927]	123	1			T15	1		T35	1		T29	1
auto[3489660928:3623878655]	123	1			T29	2		T30	1		T54	2
auto[3623878656:3758096383]	145	1			T47	2		T29	2		T133	1
auto[3758096384:3892314111]	119	1			T54	1		T58	1		T145	1
auto[3892314112:4026531839]	107	1			T29	2		T262	1		T50	1
auto[4026531840:4160749567]	101	1			T29	2		T54	2		T213	1
auto[4160749568:4294967295]	137	1			T29	3		T39	1		T54	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T29	1		T39	1		T56	1
auto[0:134217727]	auto[1]	70	1			T28	1		T58	1		T56	1
auto[134217728:268435455]	auto[0]	39	1			T1	1		T214	1		T216	1
auto[134217728:268435455]	auto[1]	53	1			T29	1		T262	1		T213	1
auto[268435456:402653183]	auto[0]	52	1			T35	1		T29	4		T5	1
auto[268435456:402653183]	auto[1]	48	1			T2	1		T30	1		T54	1
auto[402653184:536870911]	auto[0]	58	1			T47	1		T50	1		T52	1
auto[402653184:536870911]	auto[1]	61	1			T29	2		T83	1		T58	1
auto[536870912:671088639]	auto[0]	62	1			T19	1		T28	1		T29	1
auto[536870912:671088639]	auto[1]	77	1			T47	1		T54	1		T213	1
auto[671088640:805306367]	auto[0]	63	1			T47	1		T29	1		T58	1
auto[671088640:805306367]	auto[1]	60	1			T2	1		T47	1		T29	1
auto[805306368:939524095]	auto[0]	54	1			T47	1		T39	1		T58	1
auto[805306368:939524095]	auto[1]	52	1			T30	1		T54	1		T135	1
auto[939524096:1073741823]	auto[0]	36	1			T29	2		T62	1		T57	1
auto[939524096:1073741823]	auto[1]	67	1			T17	1		T58	1		T145	1
auto[1073741824:1207959551]	auto[0]	61	1			T2	1		T111	1		T7	1
auto[1073741824:1207959551]	auto[1]	59	1			T81	1		T262	1		T6	1
auto[1207959552:1342177279]	auto[0]	61	1			T29	3		T50	1		T216	1
auto[1207959552:1342177279]	auto[1]	64	1			T35	1		T28	1		T29	2
auto[1342177280:1476395007]	auto[0]	65	1			T15	1		T29	3		T54	1
auto[1342177280:1476395007]	auto[1]	51	1			T17	1		T5	1		T54	1
auto[1476395008:1610612735]	auto[0]	61	1			T15	1		T47	1		T29	3
auto[1476395008:1610612735]	auto[1]	73	1			T83	1		T61	1		T54	1
auto[1610612736:1744830463]	auto[0]	63	1			T35	1		T29	3		T58	1
auto[1610612736:1744830463]	auto[1]	65	1			T29	1		T54	1		T58	2
auto[1744830464:1879048191]	auto[0]	58	1			T1	1		T47	1		T83	1
auto[1744830464:1879048191]	auto[1]	63	1			T2	1		T19	1		T35	1
auto[1879048192:2013265919]	auto[0]	72	1			T29	1		T81	1		T39	1
auto[1879048192:2013265919]	auto[1]	52	1			T1	1		T29	1		T39	1
auto[2013265920:2147483647]	auto[0]	64	1			T28	1		T29	2		T6	1
auto[2013265920:2147483647]	auto[1]	68	1			T37	1		T58	1		T119	1
auto[2147483648:2281701375]	auto[0]	43	1			T6	1		T62	1		T51	1
auto[2147483648:2281701375]	auto[1]	61	1			T29	1		T58	1		T111	1
auto[2281701376:2415919103]	auto[0]	54	1			T29	2		T61	1		T133	1
auto[2281701376:2415919103]	auto[1]	58	1			T47	1		T54	2		T262	1
auto[2415919104:2550136831]	auto[0]	62	1			T35	1		T28	1		T58	1
auto[2415919104:2550136831]	auto[1]	57	1			T28	1		T29	1		T54	1
auto[2550136832:2684354559]	auto[0]	62	1			T35	1		T29	1		T214	1
auto[2550136832:2684354559]	auto[1]	52	1			T5	1		T39	1		T133	1
auto[2684354560:2818572287]	auto[0]	57	1			T39	1		T56	1		T7	2
auto[2684354560:2818572287]	auto[1]	63	1			T1	1		T214	1		T58	2
auto[2818572288:2952790015]	auto[0]	49	1			T29	1		T37	1		T54	1
auto[2818572288:2952790015]	auto[1]	79	1			T47	1		T29	3		T54	1
auto[2952790016:3087007743]	auto[0]	55	1			T37	1		T83	1		T54	1
auto[2952790016:3087007743]	auto[1]	65	1			T144	1		T276	1		T49	1
auto[3087007744:3221225471]	auto[0]	64	1			T29	1		T81	1		T5	1
auto[3087007744:3221225471]	auto[1]	67	1			T15	1		T17	1		T29	1
auto[3221225472:3355443199]	auto[0]	56	1			T29	1		T61	1		T262	1
auto[3221225472:3355443199]	auto[1]	55	1			T29	1		T5	1		T214	1
auto[3355443200:3489660927]	auto[0]	55	1			T15	1		T58	1		T56	1
auto[3355443200:3489660927]	auto[1]	68	1			T35	1		T29	1		T54	1
auto[3489660928:3623878655]	auto[0]	57	1			T29	1		T262	1		T50	1
auto[3489660928:3623878655]	auto[1]	66	1			T29	1		T30	1		T54	2
auto[3623878656:3758096383]	auto[0]	71	1			T29	1		T58	1		T50	1
auto[3623878656:3758096383]	auto[1]	74	1			T47	2		T29	1		T133	1
auto[3758096384:3892314111]	auto[0]	54	1			T54	1		T145	1		T200	1
auto[3758096384:3892314111]	auto[1]	65	1			T58	1		T265	1		T7	1
auto[3892314112:4026531839]	auto[0]	52	1			T29	1		T50	1		T240	1
auto[3892314112:4026531839]	auto[1]	55	1			T29	1		T262	1		T7	1
auto[4026531840:4160749567]	auto[0]	41	1			T54	1		T213	1		T111	1
auto[4026531840:4160749567]	auto[1]	60	1			T29	2		T54	1		T58	2
auto[4160749568:4294967295]	auto[0]	63	1			T213	1		T7	1		T84	1
auto[4160749568:4294967295]	auto[1]	74	1			T29	3		T39	1		T54	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1859

1

T1

2

T2

2

T15

3

auto[1]

1964

1

T1

2

T2

2

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T1	1		T15	1		T29	5
auto[134217728:268435455]	119	1			T15	1		T47	1		T39	1
auto[268435456:402653183]	90	1			T47	1		T214	1		T50	1
auto[402653184:536870911]	138	1			T29	3		T5	2		T54	1
auto[536870912:671088639]	135	1			T1	1		T28	1		T29	3
auto[671088640:805306367]	105	1			T17	1		T29	2		T58	2
auto[805306368:939524095]	111	1			T28	1		T81	2		T83	2
auto[939524096:1073741823]	103	1			T29	1		T61	1		T262	1
auto[1073741824:1207959551]	123	1			T29	6		T54	1		T58	2
auto[1207959552:1342177279]	125	1			T1	1		T2	1		T47	2
auto[1342177280:1476395007]	126	1			T35	1		T47	1		T29	3
auto[1476395008:1610612735]	115	1			T28	1		T37	1		T54	2
auto[1610612736:1744830463]	120	1			T2	1		T47	1		T29	2
auto[1744830464:1879048191]	108	1			T133	1		T54	1		T58	2
auto[1879048192:2013265919]	117	1			T35	1		T29	1		T58	1
auto[2013265920:2147483647]	123	1			T17	1		T35	1		T29	1
auto[2147483648:2281701375]	128	1			T15	1		T35	1		T29	1
auto[2281701376:2415919103]	118	1			T47	1		T28	1		T29	2
auto[2415919104:2550136831]	100	1			T28	1		T29	1		T61	1
auto[2550136832:2684354559]	132	1			T29	2		T39	2		T133	1
auto[2684354560:2818572287]	127	1			T2	2		T29	2		T54	2
auto[2818572288:2952790015]	123	1			T19	1		T35	1		T47	1
auto[2952790016:3087007743]	118	1			T1	1		T29	2		T5	1
auto[3087007744:3221225471]	120	1			T83	1		T262	1		T216	1
auto[3221225472:3355443199]	130	1			T15	1		T17	1		T28	1
auto[3355443200:3489660927]	124	1			T29	3		T30	1		T39	1
auto[3489660928:3623878655]	107	1			T19	1		T29	2		T39	1
auto[3623878656:3758096383]	97	1			T35	1		T29	3		T262	1
auto[3758096384:3892314111]	132	1			T47	2		T29	3		T5	1
auto[3892314112:4026531839]	140	1			T29	1		T58	2		T144	1
auto[4026531840:4160749567]	106	1			T35	1		T29	2		T81	1
auto[4160749568:4294967295]	146	1			T47	1		T29	3		T54	2