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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5186 1 T1 6 T2 6 T15 4
auto[1] 2460 1 T1 2 T2 2 T15 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 228 1 T15 2 T28 2 T29 6
auto[134217728:268435455] 246 1 T47 2 T29 2 T54 2
auto[268435456:402653183] 212 1 T47 2 T29 2 T39 2
auto[402653184:536870911] 206 1 T19 2 T47 2 T28 2
auto[536870912:671088639] 246 1 T2 2 T47 2 T29 4
auto[671088640:805306367] 224 1 T1 2 T47 2 T29 4
auto[805306368:939524095] 250 1 T19 2 T47 2 T29 4
auto[939524096:1073741823] 240 1 T29 2 T213 2 T6 2
auto[1073741824:1207959551] 262 1 T15 2 T35 2 T47 2
auto[1207959552:1342177279] 292 1 T35 2 T29 8 T5 4
auto[1342177280:1476395007] 264 1 T47 2 T37 2 T81 2
auto[1476395008:1610612735] 232 1 T35 4 T47 2 T29 2
auto[1610612736:1744830463] 194 1 T83 2 T54 8 T213 2
auto[1744830464:1879048191] 248 1 T29 2 T39 2 T54 2
auto[1879048192:2013265919] 216 1 T17 2 T35 2 T29 2
auto[2013265920:2147483647] 194 1 T29 4 T262 2 T216 2
auto[2147483648:2281701375] 226 1 T30 2 T54 2 T211 2
auto[2281701376:2415919103] 238 1 T17 2 T29 4 T54 2
auto[2415919104:2550136831] 210 1 T29 6 T39 2 T262 2
auto[2550136832:2684354559] 238 1 T35 2 T47 2 T28 4
auto[2684354560:2818572287] 258 1 T29 4 T39 2 T54 2
auto[2818572288:2952790015] 206 1 T29 2 T5 2 T61 2
auto[2952790016:3087007743] 234 1 T81 2 T30 4 T133 2
auto[3087007744:3221225471] 270 1 T2 2 T29 2 T37 2
auto[3221225472:3355443199] 278 1 T2 4 T17 2 T28 2
auto[3355443200:3489660927] 224 1 T29 6 T54 2 T50 2
auto[3489660928:3623878655] 268 1 T1 2 T35 2 T28 2
auto[3623878656:3758096383] 296 1 T1 4 T15 2 T58 2
auto[3758096384:3892314111] 212 1 T47 2 T29 6 T39 2
auto[3892314112:4026531839] 242 1 T15 2 T29 4 T61 2
auto[4026531840:4160749567] 224 1 T29 8 T58 4 T50 2
auto[4160749568:4294967295] 268 1 T29 8 T5 2 T61 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 154 1 T15 2 T28 2 T29 4
auto[0:134217727] auto[1] 74 1 T29 2 T58 4 T56 2
auto[134217728:268435455] auto[0] 164 1 T29 2 T54 2 T213 2
auto[134217728:268435455] auto[1] 82 1 T47 2 T297 2 T76 2
auto[268435456:402653183] auto[0] 134 1 T47 2 T39 2 T54 2
auto[268435456:402653183] auto[1] 78 1 T29 2 T31 2 T111 2
auto[402653184:536870911] auto[0] 138 1 T47 2 T28 2 T29 4
auto[402653184:536870911] auto[1] 68 1 T19 2 T54 2 T209 2
auto[536870912:671088639] auto[0] 168 1 T2 2 T47 2 T29 4
auto[536870912:671088639] auto[1] 78 1 T133 2 T54 2 T387 2
auto[671088640:805306367] auto[0] 168 1 T1 2 T29 4 T37 2
auto[671088640:805306367] auto[1] 56 1 T47 2 T54 2 T58 2
auto[805306368:939524095] auto[0] 170 1 T19 2 T81 2 T54 2
auto[805306368:939524095] auto[1] 80 1 T47 2 T29 4 T135 2
auto[939524096:1073741823] auto[0] 156 1 T29 2 T213 2 T6 2
auto[939524096:1073741823] auto[1] 84 1 T50 2 T387 2 T220 2
auto[1073741824:1207959551] auto[0] 196 1 T35 2 T47 2 T29 6
auto[1073741824:1207959551] auto[1] 66 1 T15 2 T29 2 T58 2
auto[1207959552:1342177279] auto[0] 206 1 T35 2 T29 4 T5 4
auto[1207959552:1342177279] auto[1] 86 1 T29 4 T58 4 T200 2
auto[1342177280:1476395007] auto[0] 194 1 T47 2 T37 2 T81 2
auto[1342177280:1476395007] auto[1] 70 1 T111 4 T387 2 T33 2
auto[1476395008:1610612735] auto[0] 158 1 T35 4 T47 2 T29 2
auto[1476395008:1610612735] auto[1] 74 1 T32 2 T7 2 T48 4
auto[1610612736:1744830463] auto[0] 138 1 T54 8 T213 2 T58 2
auto[1610612736:1744830463] auto[1] 56 1 T83 2 T20 2 T7 2
auto[1744830464:1879048191] auto[0] 170 1 T39 2 T58 2 T50 2
auto[1744830464:1879048191] auto[1] 78 1 T29 2 T54 2 T62 2
auto[1879048192:2013265919] auto[0] 140 1 T17 2 T35 2 T29 2
auto[1879048192:2013265919] auto[1] 76 1 T39 2 T133 2 T58 4
auto[2013265920:2147483647] auto[0] 152 1 T29 4 T262 2 T216 2
auto[2013265920:2147483647] auto[1] 42 1 T265 2 T72 2 T137 2
auto[2147483648:2281701375] auto[0] 146 1 T211 2 T119 2 T145 2
auto[2147483648:2281701375] auto[1] 80 1 T30 2 T54 2 T111 6
auto[2281701376:2415919103] auto[0] 158 1 T29 4 T54 2 T214 2
auto[2281701376:2415919103] auto[1] 80 1 T17 2 T213 2 T111 2
auto[2415919104:2550136831] auto[0] 142 1 T29 4 T39 2 T58 2
auto[2415919104:2550136831] auto[1] 68 1 T29 2 T262 2 T211 2
auto[2550136832:2684354559] auto[0] 164 1 T35 2 T28 2 T29 2
auto[2550136832:2684354559] auto[1] 74 1 T47 2 T28 2 T29 4
auto[2684354560:2818572287] auto[0] 174 1 T29 4 T39 2 T54 2
auto[2684354560:2818572287] auto[1] 84 1 T25 2 T51 2 T265 2
auto[2818572288:2952790015] auto[0] 124 1 T29 2 T61 2 T6 2
auto[2818572288:2952790015] auto[1] 82 1 T5 2 T58 2 T22 2
auto[2952790016:3087007743] auto[0] 150 1 T133 2 T58 2 T216 2
auto[2952790016:3087007743] auto[1] 84 1 T81 2 T30 4 T135 2
auto[3087007744:3221225471] auto[0] 184 1 T29 2 T83 2 T54 4
auto[3087007744:3221225471] auto[1] 86 1 T2 2 T37 2 T32 2
auto[3221225472:3355443199] auto[0] 196 1 T2 4 T17 2 T28 2
auto[3221225472:3355443199] auto[1] 82 1 T29 2 T58 2 T144 2
auto[3355443200:3489660927] auto[0] 168 1 T29 2 T54 2 T50 2
auto[3355443200:3489660927] auto[1] 56 1 T29 4 T119 2 T111 2
auto[3489660928:3623878655] auto[0] 170 1 T1 2 T35 2 T28 2
auto[3489660928:3623878655] auto[1] 98 1 T111 2 T48 2 T49 2
auto[3623878656:3758096383] auto[0] 182 1 T1 2 T15 2 T58 2
auto[3623878656:3758096383] auto[1] 114 1 T1 2 T31 2 T21 2
auto[3758096384:3892314111] auto[0] 134 1 T29 6 T54 2 T262 4
auto[3758096384:3892314111] auto[1] 78 1 T47 2 T39 2 T58 4
auto[3892314112:4026531839] auto[0] 154 1 T29 2 T61 2 T54 2
auto[3892314112:4026531839] auto[1] 88 1 T15 2 T29 2 T58 2
auto[4026531840:4160749567] auto[0] 164 1 T29 8 T58 4 T50 2
auto[4026531840:4160749567] auto[1] 60 1 T216 2 T201 2 T265 2
auto[4160749568:4294967295] auto[0] 170 1 T29 6 T5 2 T61 2
auto[4160749568:4294967295] auto[1] 98 1 T29 2 T58 2 T32 2

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