Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1792

1

T1

2

T2

2

T15

3

auto[1]

2031

1

T1

2

T2

2

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	124	1			T214	2		T119	1		T144	1
auto[134217728:268435455]	129	1			T17	1		T29	2		T39	1
auto[268435456:402653183]	130	1			T35	1		T47	1		T29	2
auto[402653184:536870911]	121	1			T61	1		T54	1		T262	1
auto[536870912:671088639]	127	1			T15	1		T29	1		T61	1
auto[671088640:805306367]	113	1			T29	4		T262	1		T58	1
auto[805306368:939524095]	114	1			T29	2		T214	1		T50	3
auto[939524096:1073741823]	121	1			T19	1		T35	1		T54	1
auto[1073741824:1207959551]	109	1			T47	1		T29	1		T5	1
auto[1207959552:1342177279]	116	1			T47	1		T29	2		T5	1
auto[1342177280:1476395007]	117	1			T29	3		T81	1		T39	1
auto[1476395008:1610612735]	102	1			T1	1		T47	1		T28	1
auto[1610612736:1744830463]	128	1			T29	3		T37	1		T83	1
auto[1744830464:1879048191]	121	1			T47	1		T29	5		T54	1
auto[1879048192:2013265919]	150	1			T2	2		T35	2		T29	5
auto[2013265920:2147483647]	98	1			T15	1		T17	1		T81	1
auto[2147483648:2281701375]	112	1			T81	1		T39	1		T54	1
auto[2281701376:2415919103]	110	1			T2	1		T28	1		T29	1
auto[2415919104:2550136831]	121	1			T15	1		T47	1		T29	2
auto[2550136832:2684354559]	116	1			T1	1		T28	1		T29	4
auto[2684354560:2818572287]	113	1			T47	1		T29	2		T262	1
auto[2818572288:2952790015]	114	1			T83	1		T54	1		T58	2
auto[2952790016:3087007743]	139	1			T47	1		T29	2		T201	1
auto[3087007744:3221225471]	143	1			T47	1		T28	1		T29	3
auto[3221225472:3355443199]	122	1			T35	1		T29	4		T5	1
auto[3355443200:3489660927]	118	1			T2	1		T15	1		T29	2
auto[3489660928:3623878655]	121	1			T1	1		T29	3		T37	1
auto[3623878656:3758096383]	107	1			T47	1		T28	1		T29	1
auto[3758096384:3892314111]	106	1			T28	1		T61	1		T262	1
auto[3892314112:4026531839]	119	1			T1	1		T19	1		T39	2
auto[4026531840:4160749567]	108	1			T17	1		T29	2		T61	1
auto[4160749568:4294967295]	134	1			T35	2		T47	1		T29	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T214	2		T209	1		T48	1
auto[0:134217727]	auto[1]	75	1			T119	1		T144	1		T87	1
auto[134217728:268435455]	auto[0]	60	1			T29	1		T39	1		T54	3
auto[134217728:268435455]	auto[1]	69	1			T17	1		T29	1		T133	1
auto[268435456:402653183]	auto[0]	62	1			T35	1		T29	1		T5	1
auto[268435456:402653183]	auto[1]	68	1			T47	1		T29	1		T58	2
auto[402653184:536870911]	auto[0]	56	1			T262	1		T56	1		T51	1
auto[402653184:536870911]	auto[1]	65	1			T61	1		T54	1		T58	1
auto[536870912:671088639]	auto[0]	71	1			T15	1		T61	1		T6	1
auto[536870912:671088639]	auto[1]	56	1			T29	1		T213	1		T50	1
auto[671088640:805306367]	auto[0]	60	1			T29	2		T57	1		T265	1
auto[671088640:805306367]	auto[1]	53	1			T29	2		T262	1		T58	1
auto[805306368:939524095]	auto[0]	51	1			T29	1		T50	3		T200	1
auto[805306368:939524095]	auto[1]	63	1			T29	1		T214	1		T216	1
auto[939524096:1073741823]	auto[0]	46	1			T35	1		T145	1		T48	1
auto[939524096:1073741823]	auto[1]	75	1			T19	1		T54	1		T64	1
auto[1073741824:1207959551]	auto[0]	46	1			T47	1		T216	2		T84	1
auto[1073741824:1207959551]	auto[1]	63	1			T29	1		T5	1		T54	2
auto[1207959552:1342177279]	auto[0]	62	1			T47	1		T29	1		T5	1
auto[1207959552:1342177279]	auto[1]	54	1			T29	1		T30	2		T54	1
auto[1342177280:1476395007]	auto[0]	57	1			T133	1		T58	1		T51	1
auto[1342177280:1476395007]	auto[1]	60	1			T29	3		T81	1		T39	1
auto[1476395008:1610612735]	auto[0]	63	1			T1	1		T47	1		T58	1
auto[1476395008:1610612735]	auto[1]	39	1			T28	1		T58	1		T68	1
auto[1610612736:1744830463]	auto[0]	64	1			T29	2		T39	1		T54	1
auto[1610612736:1744830463]	auto[1]	64	1			T29	1		T37	1		T83	1
auto[1744830464:1879048191]	auto[0]	50	1			T29	2		T262	1		T58	1
auto[1744830464:1879048191]	auto[1]	71	1			T47	1		T29	3		T54	1
auto[1879048192:2013265919]	auto[0]	70	1			T35	2		T29	3		T39	1
auto[1879048192:2013265919]	auto[1]	80	1			T2	2		T29	2		T133	1
auto[2013265920:2147483647]	auto[0]	49	1			T81	1		T54	1		T213	1
auto[2013265920:2147483647]	auto[1]	49	1			T15	1		T17	1		T262	2
auto[2147483648:2281701375]	auto[0]	46	1			T81	1		T31	1		T21	1
auto[2147483648:2281701375]	auto[1]	66	1			T39	1		T54	1		T58	1
auto[2281701376:2415919103]	auto[0]	62	1			T2	1		T28	1		T29	1
auto[2281701376:2415919103]	auto[1]	48	1			T58	1		T119	1		T145	1
auto[2415919104:2550136831]	auto[0]	52	1			T15	1		T47	1		T54	1
auto[2415919104:2550136831]	auto[1]	69	1			T29	2		T54	2		T58	1
auto[2550136832:2684354559]	auto[0]	55	1			T1	1		T28	1		T29	4
auto[2550136832:2684354559]	auto[1]	61	1			T54	1		T50	1		T216	1
auto[2684354560:2818572287]	auto[0]	51	1			T47	1		T29	2		T262	1
auto[2684354560:2818572287]	auto[1]	62	1			T214	1		T58	1		T145	1
auto[2818572288:2952790015]	auto[0]	52	1			T83	1		T58	1		T111	1
auto[2818572288:2952790015]	auto[1]	62	1			T54	1		T58	1		T135	1
auto[2952790016:3087007743]	auto[0]	62	1			T29	1		T201	1		T111	2
auto[2952790016:3087007743]	auto[1]	77	1			T47	1		T29	1		T111	1
auto[3087007744:3221225471]	auto[0]	64	1			T29	2		T83	1		T39	1
auto[3087007744:3221225471]	auto[1]	79	1			T47	1		T28	1		T29	1
auto[3221225472:3355443199]	auto[0]	57	1			T29	3		T56	1		T51	1
auto[3221225472:3355443199]	auto[1]	65	1			T35	1		T29	1		T5	1
auto[3355443200:3489660927]	auto[0]	59	1			T2	1		T15	1		T37	1
auto[3355443200:3489660927]	auto[1]	59	1			T29	2		T39	1		T54	2
auto[3489660928:3623878655]	auto[0]	57	1			T29	2		T37	1		T7	2
auto[3489660928:3623878655]	auto[1]	64	1			T1	1		T29	1		T83	1
auto[3623878656:3758096383]	auto[0]	53	1			T47	1		T29	1		T262	1
auto[3623878656:3758096383]	auto[1]	54	1			T28	1		T54	1		T58	1
auto[3758096384:3892314111]	auto[0]	44	1			T28	1		T216	1		T111	1
auto[3758096384:3892314111]	auto[1]	62	1			T61	1		T262	1		T135	1
auto[3892314112:4026531839]	auto[0]	57	1			T39	2		T58	1		T201	1
auto[3892314112:4026531839]	auto[1]	62	1			T1	1		T19	1		T59	1
auto[4026531840:4160749567]	auto[0]	49	1			T29	1		T25	1		T57	1
auto[4026531840:4160749567]	auto[1]	59	1			T17	1		T29	1		T61	1
auto[4160749568:4294967295]	auto[0]	56	1			T213	1		T6	1		T58	1
auto[4160749568:4294967295]	auto[1]	78	1			T35	2		T47	1		T29	2