dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5206 1 T1 4 T2 6 T15 8
auto[1] 2440 1 T1 4 T2 2 T17 6


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 228 1 T19 2 T29 4 T83 2
auto[134217728:268435455] 256 1 T1 2 T29 2 T54 8
auto[268435456:402653183] 222 1 T29 4 T81 2 T30 2
auto[402653184:536870911] 244 1 T47 2 T59 2 T58 4
auto[536870912:671088639] 236 1 T15 2 T29 6 T83 2
auto[671088640:805306367] 248 1 T47 4 T54 2 T262 2
auto[805306368:939524095] 236 1 T2 2 T15 2 T47 2
auto[939524096:1073741823] 280 1 T47 2 T29 12 T37 2
auto[1073741824:1207959551] 206 1 T17 2 T47 2 T54 4
auto[1207959552:1342177279] 242 1 T29 6 T81 2 T54 2
auto[1342177280:1476395007] 230 1 T2 2 T19 2 T29 4
auto[1476395008:1610612735] 232 1 T35 2 T29 4 T39 2
auto[1610612736:1744830463] 230 1 T30 2 T214 2 T58 4
auto[1744830464:1879048191] 260 1 T47 2 T28 2 T5 4
auto[1879048192:2013265919] 226 1 T17 2 T29 2 T5 2
auto[2013265920:2147483647] 182 1 T17 2 T29 4 T213 2
auto[2147483648:2281701375] 252 1 T29 4 T54 2 T58 2
auto[2281701376:2415919103] 236 1 T29 6 T81 2 T213 2
auto[2415919104:2550136831] 278 1 T15 2 T29 6 T39 2
auto[2550136832:2684354559] 266 1 T35 2 T29 6 T39 2
auto[2684354560:2818572287] 236 1 T2 2 T28 2 T29 2
auto[2818572288:2952790015] 234 1 T28 2 T29 14 T83 2
auto[2952790016:3087007743] 236 1 T35 4 T28 2 T29 8
auto[3087007744:3221225471] 214 1 T35 2 T37 2 T5 2
auto[3221225472:3355443199] 230 1 T47 2 T28 2 T39 6
auto[3355443200:3489660927] 208 1 T29 6 T214 2 T58 2
auto[3489660928:3623878655] 256 1 T1 2 T54 4 T58 6
auto[3623878656:3758096383] 258 1 T1 2 T2 2 T15 2
auto[3758096384:3892314111] 224 1 T35 2 T29 4 T6 2
auto[3892314112:4026531839] 266 1 T35 2 T47 4 T29 2
auto[4026531840:4160749567] 234 1 T28 2 T29 4 T37 2
auto[4160749568:4294967295] 260 1 T1 2 T29 4 T61 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 148 1 T19 2 T29 4 T83 2
auto[0:134217727] auto[1] 80 1 T25 2 T85 2 T297 2
auto[134217728:268435455] auto[0] 170 1 T1 2 T54 8 T6 2
auto[134217728:268435455] auto[1] 86 1 T29 2 T50 2 T20 2
auto[268435456:402653183] auto[0] 150 1 T29 4 T81 2 T30 2
auto[268435456:402653183] auto[1] 72 1 T54 2 T20 2 T265 2
auto[402653184:536870911] auto[0] 158 1 T47 2 T58 4 T50 2
auto[402653184:536870911] auto[1] 86 1 T59 2 T56 2 T22 2
auto[536870912:671088639] auto[0] 160 1 T15 2 T29 4 T83 2
auto[536870912:671088639] auto[1] 76 1 T29 2 T58 4 T22 2
auto[671088640:805306367] auto[0] 160 1 T47 2 T54 2 T262 2
auto[671088640:805306367] auto[1] 88 1 T47 2 T48 4 T65 6
auto[805306368:939524095] auto[0] 176 1 T2 2 T15 2 T47 2
auto[805306368:939524095] auto[1] 60 1 T262 2 T86 2 T76 2
auto[939524096:1073741823] auto[0] 168 1 T29 6 T37 2 T5 2
auto[939524096:1073741823] auto[1] 112 1 T47 2 T29 6 T58 2
auto[1073741824:1207959551] auto[0] 134 1 T47 2 T54 2 T111 4
auto[1073741824:1207959551] auto[1] 72 1 T17 2 T54 2 T265 2
auto[1207959552:1342177279] auto[0] 160 1 T29 4 T81 2 T54 2
auto[1207959552:1342177279] auto[1] 82 1 T29 2 T58 2 T206 2
auto[1342177280:1476395007] auto[0] 156 1 T2 2 T29 4 T54 2
auto[1342177280:1476395007] auto[1] 74 1 T19 2 T54 2 T262 2
auto[1476395008:1610612735] auto[0] 160 1 T35 2 T29 2 T39 2
auto[1476395008:1610612735] auto[1] 72 1 T29 2 T54 2 T58 4
auto[1610612736:1744830463] auto[0] 170 1 T214 2 T58 4 T111 2
auto[1610612736:1744830463] auto[1] 60 1 T30 2 T200 2 T48 4
auto[1744830464:1879048191] auto[0] 192 1 T5 4 T54 2 T58 2
auto[1744830464:1879048191] auto[1] 68 1 T47 2 T28 2 T262 2
auto[1879048192:2013265919] auto[0] 168 1 T29 2 T5 2 T58 2
auto[1879048192:2013265919] auto[1] 58 1 T17 2 T49 2 T74 2
auto[2013265920:2147483647] auto[0] 118 1 T29 4 T213 2 T58 2
auto[2013265920:2147483647] auto[1] 64 1 T17 2 T50 2 T136 2
auto[2147483648:2281701375] auto[0] 166 1 T29 4 T58 2 T56 2
auto[2147483648:2281701375] auto[1] 86 1 T54 2 T351 2 T74 2
auto[2281701376:2415919103] auto[0] 156 1 T29 6 T81 2 T213 2
auto[2281701376:2415919103] auto[1] 80 1 T58 2 T48 2 T220 2
auto[2415919104:2550136831] auto[0] 194 1 T15 2 T29 6 T39 2
auto[2415919104:2550136831] auto[1] 84 1 T57 2 T201 2 T111 2
auto[2550136832:2684354559] auto[0] 188 1 T35 2 T29 4 T39 2
auto[2550136832:2684354559] auto[1] 78 1 T29 2 T214 2 T201 2
auto[2684354560:2818572287] auto[0] 166 1 T2 2 T29 2 T61 2
auto[2684354560:2818572287] auto[1] 70 1 T28 2 T54 2 T22 2
auto[2818572288:2952790015] auto[0] 162 1 T29 10 T83 2 T39 2
auto[2818572288:2952790015] auto[1] 72 1 T28 2 T29 4 T50 2
auto[2952790016:3087007743] auto[0] 154 1 T35 4 T29 8 T54 2
auto[2952790016:3087007743] auto[1] 82 1 T28 2 T50 2 T266 2
auto[3087007744:3221225471] auto[0] 136 1 T35 2 T37 2 T5 2
auto[3087007744:3221225471] auto[1] 78 1 T133 2 T58 2 T57 2
auto[3221225472:3355443199] auto[0] 156 1 T47 2 T28 2 T39 4
auto[3221225472:3355443199] auto[1] 74 1 T39 2 T51 2 T7 2
auto[3355443200:3489660927] auto[0] 144 1 T29 6 T211 4 T7 4
auto[3355443200:3489660927] auto[1] 64 1 T214 2 T58 2 T111 4
auto[3489660928:3623878655] auto[0] 182 1 T1 2 T54 4 T58 6
auto[3489660928:3623878655] auto[1] 74 1 T111 2 T314 4 T49 2
auto[3623878656:3758096383] auto[0] 184 1 T15 2 T83 2 T61 2
auto[3623878656:3758096383] auto[1] 74 1 T1 2 T2 2 T47 2
auto[3758096384:3892314111] auto[0] 152 1 T35 2 T29 2 T6 2
auto[3758096384:3892314111] auto[1] 72 1 T29 2 T62 2 T68 2
auto[3892314112:4026531839] auto[0] 156 1 T35 2 T29 2 T58 2
auto[3892314112:4026531839] auto[1] 110 1 T47 4 T59 2 T56 2
auto[4026531840:4160749567] auto[0] 166 1 T29 4 T37 2 T39 2
auto[4026531840:4160749567] auto[1] 68 1 T28 2 T54 2 T58 2
auto[4160749568:4294967295] auto[0] 196 1 T29 4 T61 2 T58 2
auto[4160749568:4294967295] auto[1] 64 1 T1 2 T7 4 T68 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%