Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.04 97.95 98.58 100.00 99.02 98.41 91.34


Total test records in report: 1086
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1007 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1387994950 Jun 24 06:07:27 PM PDT 24 Jun 24 06:07:33 PM PDT 24 652351745 ps
T1008 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1474573664 Jun 24 06:07:42 PM PDT 24 Jun 24 06:07:47 PM PDT 24 515179011 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3865414850 Jun 24 06:07:31 PM PDT 24 Jun 24 06:07:37 PM PDT 24 152957906 ps
T1010 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.438702716 Jun 24 06:07:29 PM PDT 24 Jun 24 06:07:31 PM PDT 24 76354628 ps
T159 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.325315578 Jun 24 06:07:28 PM PDT 24 Jun 24 06:07:39 PM PDT 24 287105807 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2408276581 Jun 24 06:07:25 PM PDT 24 Jun 24 06:07:27 PM PDT 24 12477072 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1856232406 Jun 24 06:07:25 PM PDT 24 Jun 24 06:07:28 PM PDT 24 30793353 ps
T1013 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1873470147 Jun 24 06:08:01 PM PDT 24 Jun 24 06:08:03 PM PDT 24 14817073 ps
T1014 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.774933697 Jun 24 06:07:56 PM PDT 24 Jun 24 06:08:00 PM PDT 24 157148222 ps
T1015 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2434697004 Jun 24 06:07:51 PM PDT 24 Jun 24 06:07:54 PM PDT 24 27360964 ps
T166 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4111852222 Jun 24 06:07:35 PM PDT 24 Jun 24 06:07:42 PM PDT 24 567698447 ps
T1016 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1820514704 Jun 24 06:07:57 PM PDT 24 Jun 24 06:07:59 PM PDT 24 9396587 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4194540329 Jun 24 06:07:26 PM PDT 24 Jun 24 06:07:29 PM PDT 24 79924404 ps
T1018 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4037276303 Jun 24 06:07:34 PM PDT 24 Jun 24 06:07:46 PM PDT 24 2630887542 ps
T1019 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2900224744 Jun 24 06:07:50 PM PDT 24 Jun 24 06:07:54 PM PDT 24 141709624 ps
T1020 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2895318154 Jun 24 06:07:58 PM PDT 24 Jun 24 06:08:00 PM PDT 24 10116758 ps
T1021 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2466822443 Jun 24 06:07:36 PM PDT 24 Jun 24 06:07:40 PM PDT 24 135518888 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3271328999 Jun 24 06:07:36 PM PDT 24 Jun 24 06:07:39 PM PDT 24 32026506 ps
T1023 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.171300925 Jun 24 06:08:00 PM PDT 24 Jun 24 06:08:02 PM PDT 24 24854558 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1907046315 Jun 24 06:07:40 PM PDT 24 Jun 24 06:07:42 PM PDT 24 34706156 ps
T1025 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2256160278 Jun 24 06:07:49 PM PDT 24 Jun 24 06:07:52 PM PDT 24 276804410 ps
T171 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3771866790 Jun 24 06:07:47 PM PDT 24 Jun 24 06:07:53 PM PDT 24 244221019 ps
T1026 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4064849697 Jun 24 06:07:47 PM PDT 24 Jun 24 06:07:51 PM PDT 24 225974903 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3678604474 Jun 24 06:07:24 PM PDT 24 Jun 24 06:07:26 PM PDT 24 14754798 ps
T1028 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4180609518 Jun 24 06:07:29 PM PDT 24 Jun 24 06:07:33 PM PDT 24 384634387 ps
T1029 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2886570743 Jun 24 06:07:26 PM PDT 24 Jun 24 06:07:30 PM PDT 24 243249913 ps
T1030 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1660852822 Jun 24 06:07:51 PM PDT 24 Jun 24 06:07:54 PM PDT 24 20031322 ps
T1031 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3936444559 Jun 24 06:07:48 PM PDT 24 Jun 24 06:07:51 PM PDT 24 25467392 ps
T1032 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1849178974 Jun 24 06:07:42 PM PDT 24 Jun 24 06:07:49 PM PDT 24 154030255 ps
T1033 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3735411711 Jun 24 06:07:56 PM PDT 24 Jun 24 06:07:58 PM PDT 24 18207616 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1404076966 Jun 24 06:07:33 PM PDT 24 Jun 24 06:07:37 PM PDT 24 621138030 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1402997662 Jun 24 06:07:27 PM PDT 24 Jun 24 06:07:30 PM PDT 24 103807893 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2850668210 Jun 24 06:07:41 PM PDT 24 Jun 24 06:07:45 PM PDT 24 471032459 ps
T1037 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3682253205 Jun 24 06:07:26 PM PDT 24 Jun 24 06:07:36 PM PDT 24 481990968 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3296989653 Jun 24 06:07:25 PM PDT 24 Jun 24 06:07:32 PM PDT 24 324031809 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3748105381 Jun 24 06:07:36 PM PDT 24 Jun 24 06:07:38 PM PDT 24 16255711 ps
T1040 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.990183324 Jun 24 06:07:49 PM PDT 24 Jun 24 06:07:53 PM PDT 24 107006776 ps
T1041 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1211303294 Jun 24 06:07:30 PM PDT 24 Jun 24 06:07:33 PM PDT 24 34584837 ps
T1042 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1726682473 Jun 24 06:07:49 PM PDT 24 Jun 24 06:07:51 PM PDT 24 24132366 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2966590384 Jun 24 06:07:33 PM PDT 24 Jun 24 06:07:36 PM PDT 24 40276293 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4090429691 Jun 24 06:07:26 PM PDT 24 Jun 24 06:07:28 PM PDT 24 151699040 ps
T1045 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2080211401 Jun 24 06:07:30 PM PDT 24 Jun 24 06:07:33 PM PDT 24 74188452 ps
T1046 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1108135566 Jun 24 06:07:54 PM PDT 24 Jun 24 06:07:56 PM PDT 24 30111243 ps
T1047 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3687815493 Jun 24 06:07:32 PM PDT 24 Jun 24 06:07:35 PM PDT 24 37457485 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.755047267 Jun 24 06:07:29 PM PDT 24 Jun 24 06:07:46 PM PDT 24 595240042 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.451207303 Jun 24 06:07:22 PM PDT 24 Jun 24 06:07:31 PM PDT 24 374647848 ps
T1050 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1211251171 Jun 24 06:07:31 PM PDT 24 Jun 24 06:07:36 PM PDT 24 65485202 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1224694847 Jun 24 06:07:45 PM PDT 24 Jun 24 06:07:47 PM PDT 24 24008867 ps
T1052 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1978106489 Jun 24 06:07:59 PM PDT 24 Jun 24 06:08:01 PM PDT 24 18504038 ps
T156 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.158922089 Jun 24 06:07:48 PM PDT 24 Jun 24 06:07:52 PM PDT 24 195622317 ps
T1053 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1985922676 Jun 24 06:07:50 PM PDT 24 Jun 24 06:07:54 PM PDT 24 73689028 ps
T1054 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.296450303 Jun 24 06:07:46 PM PDT 24 Jun 24 06:07:51 PM PDT 24 441109306 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3113701669 Jun 24 06:07:34 PM PDT 24 Jun 24 06:07:38 PM PDT 24 33252867 ps
T1056 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1230842371 Jun 24 06:07:47 PM PDT 24 Jun 24 06:07:49 PM PDT 24 10607303 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2213153208 Jun 24 06:07:29 PM PDT 24 Jun 24 06:07:33 PM PDT 24 81806833 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.798374827 Jun 24 06:07:30 PM PDT 24 Jun 24 06:07:46 PM PDT 24 866451614 ps
T1059 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3048326567 Jun 24 06:07:36 PM PDT 24 Jun 24 06:07:39 PM PDT 24 158372064 ps
T1060 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2149350859 Jun 24 06:07:49 PM PDT 24 Jun 24 06:07:51 PM PDT 24 68197002 ps
T1061 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2583930834 Jun 24 06:07:49 PM PDT 24 Jun 24 06:07:53 PM PDT 24 48704463 ps
T1062 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2276457754 Jun 24 06:07:31 PM PDT 24 Jun 24 06:07:38 PM PDT 24 287897541 ps
T1063 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4244678972 Jun 24 06:07:26 PM PDT 24 Jun 24 06:07:35 PM PDT 24 1064138135 ps
T1064 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1843343098 Jun 24 06:07:25 PM PDT 24 Jun 24 06:07:30 PM PDT 24 248948669 ps
T1065 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3512014213 Jun 24 06:07:49 PM PDT 24 Jun 24 06:07:54 PM PDT 24 132713203 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2151770437 Jun 24 06:07:19 PM PDT 24 Jun 24 06:07:25 PM PDT 24 1043938593 ps
T1067 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3859305651 Jun 24 06:07:31 PM PDT 24 Jun 24 06:07:35 PM PDT 24 97103373 ps
T1068 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.916215059 Jun 24 06:07:58 PM PDT 24 Jun 24 06:08:00 PM PDT 24 12747445 ps
T1069 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1251411618 Jun 24 06:07:35 PM PDT 24 Jun 24 06:07:40 PM PDT 24 154910025 ps
T1070 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1524948552 Jun 24 06:07:36 PM PDT 24 Jun 24 06:07:40 PM PDT 24 192023740 ps
T1071 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2912966593 Jun 24 06:07:25 PM PDT 24 Jun 24 06:07:32 PM PDT 24 915379234 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1719302652 Jun 24 06:07:26 PM PDT 24 Jun 24 06:07:32 PM PDT 24 300252770 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4285293396 Jun 24 06:07:50 PM PDT 24 Jun 24 06:07:53 PM PDT 24 86977147 ps
T1074 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2381518512 Jun 24 06:07:51 PM PDT 24 Jun 24 06:07:54 PM PDT 24 29807046 ps
T1075 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1635098740 Jun 24 06:08:04 PM PDT 24 Jun 24 06:08:07 PM PDT 24 40007269 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.167522052 Jun 24 06:07:30 PM PDT 24 Jun 24 06:07:40 PM PDT 24 190358919 ps
T1077 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.949395278 Jun 24 06:07:40 PM PDT 24 Jun 24 06:07:42 PM PDT 24 12084708 ps
T158 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.901370616 Jun 24 06:07:50 PM PDT 24 Jun 24 06:07:57 PM PDT 24 194305030 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2034452240 Jun 24 06:07:29 PM PDT 24 Jun 24 06:07:32 PM PDT 24 59294808 ps
T1079 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1848889754 Jun 24 06:07:53 PM PDT 24 Jun 24 06:07:58 PM PDT 24 233495376 ps
T1080 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1025646364 Jun 24 06:07:57 PM PDT 24 Jun 24 06:08:00 PM PDT 24 47375969 ps
T1081 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2051169649 Jun 24 06:08:00 PM PDT 24 Jun 24 06:08:02 PM PDT 24 15534053 ps
T1082 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1621398646 Jun 24 06:07:35 PM PDT 24 Jun 24 06:07:47 PM PDT 24 2818719171 ps
T1083 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2795387119 Jun 24 06:07:30 PM PDT 24 Jun 24 06:07:38 PM PDT 24 217108238 ps
T1084 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2859988269 Jun 24 06:07:47 PM PDT 24 Jun 24 06:07:51 PM PDT 24 551383616 ps
T373 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2185337300 Jun 24 06:07:54 PM PDT 24 Jun 24 06:08:00 PM PDT 24 380143241 ps
T1085 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3443587745 Jun 24 06:07:46 PM PDT 24 Jun 24 06:07:50 PM PDT 24 25088278 ps
T1086 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2162072906 Jun 24 06:07:29 PM PDT 24 Jun 24 06:07:32 PM PDT 24 36280122 ps

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1076956286
Short name T2
Test name
Test status
Simulation time 74285720 ps
CPU time 4.2 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 215264 kb
Host smart-174b66ea-eb32-4194-b39f-35c6a87f8bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076956286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1076956286
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2940598260
Short name T29
Test name
Test status
Simulation time 1556451177 ps
CPU time 43.1 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:15:20 PM PDT 24
Peak memory 215080 kb
Host smart-5d17cb3d-a984-4c27-a1f8-38421879718f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940598260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2940598260
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3568183550
Short name T48
Test name
Test status
Simulation time 84644629369 ps
CPU time 797.3 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:29:21 PM PDT 24
Peak memory 222520 kb
Host smart-4fdb7cce-987a-4f47-8eb4-308fff4fb852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568183550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3568183550
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.533555663
Short name T13
Test name
Test status
Simulation time 927214172 ps
CPU time 12.6 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:13:08 PM PDT 24
Peak memory 232052 kb
Host smart-8149541f-86c3-40f1-b406-c1f9679f4a58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533555663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.533555663
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2917381109
Short name T127
Test name
Test status
Simulation time 1554205194 ps
CPU time 21.82 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:26 PM PDT 24
Peak memory 222692 kb
Host smart-1026a635-3e92-4358-a295-3090c56b7abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917381109 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2917381109
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3498731519
Short name T174
Test name
Test status
Simulation time 550901932 ps
CPU time 14.8 seconds
Started Jun 24 06:15:14 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 220200 kb
Host smart-9b48d07a-2aba-462f-81dc-484d636b5405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498731519 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3498731519
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2650347271
Short name T58
Test name
Test status
Simulation time 2379274810 ps
CPU time 30.98 seconds
Started Jun 24 06:15:22 PM PDT 24
Finished Jun 24 06:15:54 PM PDT 24
Peak memory 222148 kb
Host smart-6b95de18-f108-4257-bc03-12431808d863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650347271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2650347271
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3946763594
Short name T15
Test name
Test status
Simulation time 567715697 ps
CPU time 2.96 seconds
Started Jun 24 06:14:34 PM PDT 24
Finished Jun 24 06:14:37 PM PDT 24
Peak memory 222772 kb
Host smart-77538833-27c6-4b5f-87f9-f81374db3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946763594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3946763594
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3763120846
Short name T38
Test name
Test status
Simulation time 300605722 ps
CPU time 2.45 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:53 PM PDT 24
Peak memory 209968 kb
Host smart-9fbe9968-b19b-4951-9f2d-e30a62edf399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763120846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3763120846
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1311488696
Short name T116
Test name
Test status
Simulation time 2768337300 ps
CPU time 12.74 seconds
Started Jun 24 06:07:54 PM PDT 24
Finished Jun 24 06:08:08 PM PDT 24
Peak memory 220936 kb
Host smart-9de05b43-db34-4d0c-9706-2dffa2c02a55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311488696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1311488696
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1010853753
Short name T9
Test name
Test status
Simulation time 1012043900 ps
CPU time 4.66 seconds
Started Jun 24 06:14:59 PM PDT 24
Finished Jun 24 06:15:04 PM PDT 24
Peak memory 210672 kb
Host smart-dcc7e2a6-1778-44e0-92a8-e7501c333720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010853753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1010853753
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2318004177
Short name T49
Test name
Test status
Simulation time 21087917192 ps
CPU time 247.91 seconds
Started Jun 24 06:13:03 PM PDT 24
Finished Jun 24 06:17:12 PM PDT 24
Peak memory 222616 kb
Host smart-8c115bf1-abd2-435d-b236-fa672b4d89fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318004177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2318004177
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1544177849
Short name T391
Test name
Test status
Simulation time 1235668119 ps
CPU time 31.89 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:17:05 PM PDT 24
Peak memory 215104 kb
Host smart-d9ca0d0f-5250-417a-acc8-9a59a4520989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544177849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1544177849
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1637552683
Short name T135
Test name
Test status
Simulation time 2734634345 ps
CPU time 74.19 seconds
Started Jun 24 06:16:47 PM PDT 24
Finished Jun 24 06:18:02 PM PDT 24
Peak memory 215352 kb
Host smart-7924c45f-fb99-4d7f-9614-c7c3c47990ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637552683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1637552683
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.660608962
Short name T22
Test name
Test status
Simulation time 136197356 ps
CPU time 6.33 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:10 PM PDT 24
Peak memory 214288 kb
Host smart-dd650d4c-7816-40bc-a70e-27d307b8fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660608962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.660608962
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3764192461
Short name T396
Test name
Test status
Simulation time 524031508 ps
CPU time 27.85 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:13:24 PM PDT 24
Peak memory 214316 kb
Host smart-b3e58b72-7b59-4137-9c3c-550b4df284e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764192461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3764192461
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1293537715
Short name T74
Test name
Test status
Simulation time 5537116217 ps
CPU time 159.43 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 222584 kb
Host smart-936612a1-74f0-453f-b62e-825b8cb488f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293537715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1293537715
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.33162306
Short name T124
Test name
Test status
Simulation time 309431081 ps
CPU time 6.78 seconds
Started Jun 24 06:07:37 PM PDT 24
Finished Jun 24 06:07:45 PM PDT 24
Peak memory 214212 kb
Host smart-daefc856-3e24-498b-b815-8787fb58aee2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.k
eymgr_shadow_reg_errors_with_csr_rw.33162306
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.745985158
Short name T348
Test name
Test status
Simulation time 284042473 ps
CPU time 5.21 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 215388 kb
Host smart-39ab5565-5f40-4edf-b6e8-b872c7ddc632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745985158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.745985158
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4030135752
Short name T111
Test name
Test status
Simulation time 256586709 ps
CPU time 16.38 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 222596 kb
Host smart-c5311a98-8617-408f-9dc2-1a7083b60614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030135752 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4030135752
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4243734191
Short name T397
Test name
Test status
Simulation time 69705843 ps
CPU time 4.28 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:15 PM PDT 24
Peak memory 215112 kb
Host smart-d59d72bc-07b2-49c7-927f-c4825233b98a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243734191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4243734191
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2828514165
Short name T50
Test name
Test status
Simulation time 67018026 ps
CPU time 2.72 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:12:58 PM PDT 24
Peak memory 214272 kb
Host smart-48664e18-a416-4ebd-af43-94a700f8abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828514165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2828514165
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3085150931
Short name T68
Test name
Test status
Simulation time 59832034 ps
CPU time 4.14 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 222688 kb
Host smart-0f0d3004-afd0-4ccf-a368-dc9b19600d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085150931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3085150931
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.278263600
Short name T93
Test name
Test status
Simulation time 211318978 ps
CPU time 5.14 seconds
Started Jun 24 06:16:03 PM PDT 24
Finished Jun 24 06:16:09 PM PDT 24
Peak memory 220836 kb
Host smart-d5bf3a18-9c6e-48df-8128-7cdbbed790be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278263600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.278263600
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.319227613
Short name T403
Test name
Test status
Simulation time 680210695 ps
CPU time 33.62 seconds
Started Jun 24 06:14:42 PM PDT 24
Finished Jun 24 06:15:16 PM PDT 24
Peak memory 214204 kb
Host smart-6232e27a-efe7-48ff-b35a-7e6298c9ce49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319227613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.319227613
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2592013716
Short name T40
Test name
Test status
Simulation time 86269454 ps
CPU time 1.8 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:22 PM PDT 24
Peak memory 209664 kb
Host smart-dac68ce3-04e5-48fa-b815-ed28a2c4817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592013716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2592013716
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.571559577
Short name T47
Test name
Test status
Simulation time 1701166918 ps
CPU time 14.14 seconds
Started Jun 24 06:16:20 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 221024 kb
Host smart-69dbe813-90ea-4098-8474-6d2e409c0dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571559577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.571559577
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3967461210
Short name T33
Test name
Test status
Simulation time 610299409 ps
CPU time 4.99 seconds
Started Jun 24 06:13:03 PM PDT 24
Finished Jun 24 06:13:09 PM PDT 24
Peak memory 210064 kb
Host smart-d2bd7169-7a24-470d-87c8-cee5ca0538b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967461210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3967461210
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3033788674
Short name T349
Test name
Test status
Simulation time 261814585 ps
CPU time 4.6 seconds
Started Jun 24 06:14:42 PM PDT 24
Finished Jun 24 06:14:48 PM PDT 24
Peak memory 222428 kb
Host smart-0a8a6b49-31e7-4b17-8537-66a704dfcc41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033788674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3033788674
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4194008153
Short name T27
Test name
Test status
Simulation time 374139640 ps
CPU time 4.61 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 214716 kb
Host smart-b59bad5c-412f-45de-9b20-8309f2692af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194008153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4194008153
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2997279453
Short name T224
Test name
Test status
Simulation time 1806664250 ps
CPU time 62.37 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:15:32 PM PDT 24
Peak memory 214652 kb
Host smart-48a5234a-d04b-4a1d-82f7-c139ae23d5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997279453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2997279453
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3315699431
Short name T238
Test name
Test status
Simulation time 53738028 ps
CPU time 3.7 seconds
Started Jun 24 06:12:34 PM PDT 24
Finished Jun 24 06:12:38 PM PDT 24
Peak memory 214320 kb
Host smart-becea1cd-c108-429e-bfc3-96ac758166df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315699431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3315699431
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3791772338
Short name T410
Test name
Test status
Simulation time 111090863 ps
CPU time 0.84 seconds
Started Jun 24 06:14:06 PM PDT 24
Finished Jun 24 06:14:08 PM PDT 24
Peak memory 205884 kb
Host smart-0047de79-458c-42ec-acaf-1fe187016589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791772338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3791772338
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1371821129
Short name T222
Test name
Test status
Simulation time 6110164497 ps
CPU time 61.17 seconds
Started Jun 24 06:15:59 PM PDT 24
Finished Jun 24 06:17:01 PM PDT 24
Peak memory 215488 kb
Host smart-f6cd97cd-0016-4099-a88c-a30a13bf989b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371821129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1371821129
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2144976254
Short name T356
Test name
Test status
Simulation time 868418410 ps
CPU time 24.52 seconds
Started Jun 24 06:16:03 PM PDT 24
Finished Jun 24 06:16:29 PM PDT 24
Peak memory 215112 kb
Host smart-f5551f01-e107-4f40-88bd-f4f3327620a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144976254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2144976254
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3607069239
Short name T155
Test name
Test status
Simulation time 210309283 ps
CPU time 6.18 seconds
Started Jun 24 06:07:32 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 214136 kb
Host smart-e409cd6e-1ed9-417d-82ea-aade3c7ccdbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607069239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3607069239
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.746802293
Short name T292
Test name
Test status
Simulation time 329962161 ps
CPU time 5.11 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:37 PM PDT 24
Peak memory 222452 kb
Host smart-b9059639-1914-47aa-aba8-c57f00ee0aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746802293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.746802293
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.220962347
Short name T221
Test name
Test status
Simulation time 1365902842 ps
CPU time 17.27 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:13:53 PM PDT 24
Peak memory 216672 kb
Host smart-d5443815-8b68-4ea8-9c06-c4033aada510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220962347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.220962347
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2011928631
Short name T145
Test name
Test status
Simulation time 507983368 ps
CPU time 3.77 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:14 PM PDT 24
Peak memory 215244 kb
Host smart-90bfc53d-b68d-4a60-95df-fd22f3f1d9a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011928631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2011928631
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1617367618
Short name T95
Test name
Test status
Simulation time 146619767 ps
CPU time 5.26 seconds
Started Jun 24 06:14:56 PM PDT 24
Finished Jun 24 06:15:03 PM PDT 24
Peak memory 209756 kb
Host smart-ab32616a-9511-4f92-abcf-b0b84ce70a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617367618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1617367618
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2311519573
Short name T59
Test name
Test status
Simulation time 328047310 ps
CPU time 5.44 seconds
Started Jun 24 06:14:54 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 218356 kb
Host smart-d484eb1b-a7f2-41b8-9222-8621dbeb7625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311519573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2311519573
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3163350317
Short name T231
Test name
Test status
Simulation time 3557064502 ps
CPU time 87.66 seconds
Started Jun 24 06:12:53 PM PDT 24
Finished Jun 24 06:14:21 PM PDT 24
Peak memory 216272 kb
Host smart-40c68ae9-37d4-4c32-9bf7-15a167bf74d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163350317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3163350317
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.871098832
Short name T86
Test name
Test status
Simulation time 181859775 ps
CPU time 2.85 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 214320 kb
Host smart-644228f0-fc81-430a-82e7-a664a6359bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871098832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.871098832
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.912039157
Short name T137
Test name
Test status
Simulation time 217670199 ps
CPU time 4.05 seconds
Started Jun 24 06:14:09 PM PDT 24
Finished Jun 24 06:14:14 PM PDT 24
Peak memory 214304 kb
Host smart-e2005be8-3a06-4e81-b0b3-3f399c0026b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912039157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.912039157
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1430663386
Short name T144
Test name
Test status
Simulation time 195957517 ps
CPU time 5.67 seconds
Started Jun 24 06:14:27 PM PDT 24
Finished Jun 24 06:14:34 PM PDT 24
Peak memory 214312 kb
Host smart-8b77ca27-838e-4183-bd61-4240714cff29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430663386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1430663386
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1820664196
Short name T192
Test name
Test status
Simulation time 697081860 ps
CPU time 27.51 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 215084 kb
Host smart-2c0ca7eb-c146-40df-b594-f96b394a61a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820664196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1820664196
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.837172339
Short name T251
Test name
Test status
Simulation time 30629340 ps
CPU time 2.34 seconds
Started Jun 24 06:15:38 PM PDT 24
Finished Jun 24 06:15:40 PM PDT 24
Peak memory 206980 kb
Host smart-690c2904-9add-44d2-8919-16770885ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837172339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.837172339
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1940736059
Short name T399
Test name
Test status
Simulation time 2152415401 ps
CPU time 9.97 seconds
Started Jun 24 06:13:41 PM PDT 24
Finished Jun 24 06:13:52 PM PDT 24
Peak memory 215356 kb
Host smart-c9499fb6-573d-450b-b13b-64b1add8dcb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940736059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1940736059
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2795387119
Short name T1083
Test name
Test status
Simulation time 217108238 ps
CPU time 5.93 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 214124 kb
Host smart-29177e1e-99b5-49a1-aef0-df816200d2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795387119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2795387119
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.563868732
Short name T152
Test name
Test status
Simulation time 150831366 ps
CPU time 5.96 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 214188 kb
Host smart-c2ccefe5-ef4b-47d0-979a-4eaa5e15c6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563868732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
563868732
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1187594736
Short name T218
Test name
Test status
Simulation time 228009033 ps
CPU time 5.78 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:43 PM PDT 24
Peak memory 222820 kb
Host smart-c5b4987b-d338-488b-a577-7047a699992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187594736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1187594736
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1584055446
Short name T147
Test name
Test status
Simulation time 51343812 ps
CPU time 3.11 seconds
Started Jun 24 06:13:38 PM PDT 24
Finished Jun 24 06:13:42 PM PDT 24
Peak memory 217840 kb
Host smart-b96dd4c0-67dd-45d3-b7b8-8784efda2961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584055446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1584055446
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1058491915
Short name T329
Test name
Test status
Simulation time 32985410261 ps
CPU time 175.28 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:17:35 PM PDT 24
Peak memory 222688 kb
Host smart-2455b6a4-41d2-4d2e-b80b-2946a96dd3eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058491915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1058491915
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3103435316
Short name T76
Test name
Test status
Simulation time 2895735742 ps
CPU time 32.11 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 216876 kb
Host smart-56e7be4b-a59f-4762-82dc-22176e2ceb32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103435316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3103435316
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3008996935
Short name T62
Test name
Test status
Simulation time 49804883 ps
CPU time 3.42 seconds
Started Jun 24 06:14:26 PM PDT 24
Finished Jun 24 06:14:31 PM PDT 24
Peak memory 218164 kb
Host smart-5a2b108b-8430-4e1f-9109-7f843149148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008996935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3008996935
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.461742650
Short name T146
Test name
Test status
Simulation time 286081608 ps
CPU time 2.88 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:55 PM PDT 24
Peak memory 217864 kb
Host smart-dfa1baf5-a75c-426c-a1c9-7f3fee0af53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461742650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.461742650
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2784111593
Short name T372
Test name
Test status
Simulation time 68223207 ps
CPU time 2.25 seconds
Started Jun 24 06:14:34 PM PDT 24
Finished Jun 24 06:14:37 PM PDT 24
Peak memory 210756 kb
Host smart-c0bff78c-c268-4505-a851-98a76832b7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784111593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2784111593
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3063098050
Short name T113
Test name
Test status
Simulation time 118317798 ps
CPU time 2.71 seconds
Started Jun 24 06:13:02 PM PDT 24
Finished Jun 24 06:13:06 PM PDT 24
Peak memory 210020 kb
Host smart-99e0b2d2-d0fc-47e3-9a86-ee44bc99ba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063098050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3063098050
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3414917122
Short name T954
Test name
Test status
Simulation time 253263905 ps
CPU time 2.08 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:29 PM PDT 24
Peak memory 214460 kb
Host smart-83a37d9e-bead-4528-9bfc-66e4c8c9e022
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414917122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3414917122
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2764648006
Short name T149
Test name
Test status
Simulation time 212122842 ps
CPU time 3.03 seconds
Started Jun 24 06:16:09 PM PDT 24
Finished Jun 24 06:16:13 PM PDT 24
Peak memory 222624 kb
Host smart-f659d683-5c1f-4ec3-b6f0-a3130270d853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764648006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2764648006
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1570304865
Short name T288
Test name
Test status
Simulation time 684141500 ps
CPU time 3.38 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 214256 kb
Host smart-f457f3d6-e61c-49db-a0ee-6e3d66af11dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570304865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1570304865
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3963509546
Short name T243
Test name
Test status
Simulation time 907519450 ps
CPU time 7.65 seconds
Started Jun 24 06:15:03 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 208908 kb
Host smart-0cdafd96-fae7-4ac6-8c7d-325235408044
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963509546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3963509546
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.692529771
Short name T39
Test name
Test status
Simulation time 174768183 ps
CPU time 7.47 seconds
Started Jun 24 06:15:17 PM PDT 24
Finished Jun 24 06:15:26 PM PDT 24
Peak memory 222472 kb
Host smart-241c4a38-298b-4819-a1b2-3796b0dd3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692529771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.692529771
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1359124360
Short name T277
Test name
Test status
Simulation time 17639849246 ps
CPU time 392.83 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:22:01 PM PDT 24
Peak memory 217768 kb
Host smart-ae7342de-2fb0-4377-972d-bc7461aa9605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359124360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1359124360
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3997046032
Short name T282
Test name
Test status
Simulation time 534283239 ps
CPU time 14.91 seconds
Started Jun 24 06:15:33 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 215628 kb
Host smart-9c453427-cbff-4781-bb58-43bb6a43ba52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997046032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3997046032
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4152738033
Short name T353
Test name
Test status
Simulation time 99682929 ps
CPU time 4.11 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 214256 kb
Host smart-a6f543fa-e6df-4ded-a3c2-13554b7a0eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152738033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4152738033
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4184992949
Short name T195
Test name
Test status
Simulation time 2321150927 ps
CPU time 48.23 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:17:28 PM PDT 24
Peak memory 220840 kb
Host smart-d27b8a98-6369-4c67-bda2-0197786dd484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184992949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4184992949
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2591972098
Short name T378
Test name
Test status
Simulation time 44968839 ps
CPU time 1.79 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:27 PM PDT 24
Peak memory 214232 kb
Host smart-a23c0b68-927c-4ae3-a204-ecdca3e4902f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591972098 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2591972098
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2436164578
Short name T213
Test name
Test status
Simulation time 1517973273 ps
CPU time 25.75 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:46 PM PDT 24
Peak memory 214384 kb
Host smart-a491974c-4386-419a-8fa5-a7c8ea45da73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436164578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2436164578
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1942019507
Short name T278
Test name
Test status
Simulation time 104735265 ps
CPU time 4.22 seconds
Started Jun 24 06:14:29 PM PDT 24
Finished Jun 24 06:14:34 PM PDT 24
Peak memory 208572 kb
Host smart-c5d808c8-a449-4493-a649-5ecb15e3fb18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942019507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1942019507
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3530507787
Short name T346
Test name
Test status
Simulation time 455198239 ps
CPU time 6.4 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:16:39 PM PDT 24
Peak memory 208828 kb
Host smart-49d7433f-62b0-45f1-8320-fa06d929ff3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530507787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3530507787
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1242415481
Short name T237
Test name
Test status
Simulation time 1793020434 ps
CPU time 42.92 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:17:25 PM PDT 24
Peak memory 215660 kb
Host smart-321b55a7-3e21-4ce5-b1de-5beeddb4b7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242415481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1242415481
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2514430696
Short name T66
Test name
Test status
Simulation time 77741260 ps
CPU time 3.01 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 214328 kb
Host smart-0f684c62-fb93-4930-8fde-dae92499f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514430696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2514430696
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3975943551
Short name T294
Test name
Test status
Simulation time 534698178 ps
CPU time 10.23 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 215240 kb
Host smart-7f026f83-e41a-43a8-88be-5d8db3aae26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975943551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3975943551
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3107997653
Short name T53
Test name
Test status
Simulation time 1757102138 ps
CPU time 22.95 seconds
Started Jun 24 06:16:48 PM PDT 24
Finished Jun 24 06:17:12 PM PDT 24
Peak memory 216308 kb
Host smart-fbef097f-2839-4b05-8cbc-f0a43246950d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107997653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3107997653
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3678920358
Short name T321
Test name
Test status
Simulation time 102242872 ps
CPU time 3.4 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:13:56 PM PDT 24
Peak memory 220808 kb
Host smart-972b75e6-41a7-4b57-97a4-c295e5bca11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678920358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3678920358
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.158922089
Short name T156
Test name
Test status
Simulation time 195622317 ps
CPU time 2.43 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 214236 kb
Host smart-f2e153a3-6c04-420f-b70c-ba9e8ff98b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158922089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.158922089
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2800983345
Short name T165
Test name
Test status
Simulation time 55192584 ps
CPU time 3.13 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 214268 kb
Host smart-e81ecbd6-72d4-475c-ac51-7453417b7afb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800983345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2800983345
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2577731439
Short name T161
Test name
Test status
Simulation time 142694375 ps
CPU time 4.31 seconds
Started Jun 24 06:07:52 PM PDT 24
Finished Jun 24 06:07:57 PM PDT 24
Peak memory 214396 kb
Host smart-9b797249-72f8-4931-9113-4e53572aa453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577731439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2577731439
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.901370616
Short name T158
Test name
Test status
Simulation time 194305030 ps
CPU time 5.16 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:57 PM PDT 24
Peak memory 205980 kb
Host smart-df4d9f51-aa7a-425d-89df-2f2a32778a79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901370616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.901370616
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3729379756
Short name T168
Test name
Test status
Simulation time 148468821 ps
CPU time 5.3 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 214164 kb
Host smart-9e80abf5-ad00-4816-ade2-1abf37eaf16e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729379756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3729379756
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3382496069
Short name T46
Test name
Test status
Simulation time 5841522041 ps
CPU time 19.41 seconds
Started Jun 24 06:12:47 PM PDT 24
Finished Jun 24 06:13:07 PM PDT 24
Peak memory 231860 kb
Host smart-d92a2fa9-1aff-4937-9fb7-90eb6eb10c13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382496069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3382496069
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.25988930
Short name T172
Test name
Test status
Simulation time 96435042 ps
CPU time 3.81 seconds
Started Jun 24 06:13:23 PM PDT 24
Finished Jun 24 06:13:28 PM PDT 24
Peak memory 210316 kb
Host smart-dd7a312c-d17f-456b-9c1f-4fa8b4e3dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25988930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.25988930
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2492231184
Short name T148
Test name
Test status
Simulation time 55107010 ps
CPU time 2.24 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:42 PM PDT 24
Peak memory 216340 kb
Host smart-ebcc9c79-737a-4288-aae7-8bd19c458963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492231184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2492231184
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1302490325
Short name T37
Test name
Test status
Simulation time 257757888 ps
CPU time 2.88 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:55 PM PDT 24
Peak memory 222668 kb
Host smart-3cf7abb3-55d9-4b39-b2ee-3da1954af6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302490325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1302490325
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2199877459
Short name T163
Test name
Test status
Simulation time 565601112 ps
CPU time 4.53 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 206180 kb
Host smart-850ae7a1-a24b-498b-986b-1571a3781c48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199877459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2199877459
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3052074190
Short name T72
Test name
Test status
Simulation time 419119608 ps
CPU time 2.94 seconds
Started Jun 24 06:12:34 PM PDT 24
Finished Jun 24 06:12:37 PM PDT 24
Peak memory 207796 kb
Host smart-f5117bd7-4c94-4c8d-8ae0-7bb2ebef05ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052074190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3052074190
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.4275882439
Short name T316
Test name
Test status
Simulation time 168742126 ps
CPU time 2.72 seconds
Started Jun 24 06:12:43 PM PDT 24
Finished Jun 24 06:12:47 PM PDT 24
Peak memory 214232 kb
Host smart-89473890-f531-483e-ab9f-8f00f61bd985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275882439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.4275882439
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2606602375
Short name T537
Test name
Test status
Simulation time 467377387 ps
CPU time 4.74 seconds
Started Jun 24 06:12:46 PM PDT 24
Finished Jun 24 06:12:51 PM PDT 24
Peak memory 210656 kb
Host smart-62e748f1-42be-41ce-8649-004a7298d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606602375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2606602375
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.282251616
Short name T256
Test name
Test status
Simulation time 198907390 ps
CPU time 10.85 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:32 PM PDT 24
Peak memory 214612 kb
Host smart-b0b17195-a79b-4cdd-b6be-dd4c40a5270b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282251616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.282251616
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2670192534
Short name T236
Test name
Test status
Simulation time 274155625 ps
CPU time 11.04 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:34 PM PDT 24
Peak memory 220076 kb
Host smart-faaf043f-d9e7-4f6d-b82c-ab52043a78a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670192534 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2670192534
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1587614497
Short name T825
Test name
Test status
Simulation time 1847758265 ps
CPU time 53.52 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 214860 kb
Host smart-7dad9805-aa8b-4905-ad52-6f338ea96c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587614497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1587614497
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3127194808
Short name T866
Test name
Test status
Simulation time 148983702 ps
CPU time 5.3 seconds
Started Jun 24 06:14:57 PM PDT 24
Finished Jun 24 06:15:04 PM PDT 24
Peak memory 214500 kb
Host smart-60d84911-5ea6-4301-b93d-996eb9322ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127194808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3127194808
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2575872270
Short name T94
Test name
Test status
Simulation time 140311292 ps
CPU time 2.75 seconds
Started Jun 24 06:13:04 PM PDT 24
Finished Jun 24 06:13:08 PM PDT 24
Peak memory 214288 kb
Host smart-aa6e4329-3f4e-42f4-bbcc-af6f3fce5d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575872270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2575872270
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2481389005
Short name T290
Test name
Test status
Simulation time 182146111 ps
CPU time 3 seconds
Started Jun 24 06:14:54 PM PDT 24
Finished Jun 24 06:14:57 PM PDT 24
Peak memory 214284 kb
Host smart-7c3ffecc-0d31-48bd-a783-3415ca8acd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481389005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2481389005
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2204636394
Short name T233
Test name
Test status
Simulation time 152320141 ps
CPU time 7.2 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:16 PM PDT 24
Peak memory 214360 kb
Host smart-1c6bf90f-88bd-47bf-9c9a-ff0dd53fd460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204636394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2204636394
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1983095253
Short name T26
Test name
Test status
Simulation time 259198866 ps
CPU time 6.55 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:34 PM PDT 24
Peak memory 220980 kb
Host smart-d9508e86-bdb7-4bb3-bb97-742ec3f67962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983095253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1983095253
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_random.110729653
Short name T792
Test name
Test status
Simulation time 146073391 ps
CPU time 5.52 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:50 PM PDT 24
Peak memory 207700 kb
Host smart-309bfa8e-6e5e-48cc-a9f8-ca7a483f168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110729653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.110729653
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.813942881
Short name T322
Test name
Test status
Simulation time 221850285 ps
CPU time 4.65 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 215140 kb
Host smart-6760b19a-9987-4f30-b378-f502519cea0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813942881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.813942881
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3699053506
Short name T320
Test name
Test status
Simulation time 32214792 ps
CPU time 2.39 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 214252 kb
Host smart-f1f3db4d-6926-4784-8c93-dff48f828ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699053506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3699053506
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2799732733
Short name T201
Test name
Test status
Simulation time 167997554 ps
CPU time 2.42 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 218400 kb
Host smart-9c8022f8-7802-4c45-bf64-2076abb7bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799732733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2799732733
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1737962883
Short name T219
Test name
Test status
Simulation time 161056609 ps
CPU time 5.92 seconds
Started Jun 24 06:16:24 PM PDT 24
Finished Jun 24 06:16:31 PM PDT 24
Peak memory 222632 kb
Host smart-b4e57c02-9852-4795-8beb-dc5a6ee0837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737962883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1737962883
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2862952231
Short name T150
Test name
Test status
Simulation time 199616424 ps
CPU time 4.1 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:36 PM PDT 24
Peak memory 218464 kb
Host smart-5947db46-eada-4502-8a4f-fe99b5c20607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862952231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2862952231
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2912966593
Short name T1071
Test name
Test status
Simulation time 915379234 ps
CPU time 5.98 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 205976 kb
Host smart-a859d6a0-d8c9-44ee-a796-f1b840deffc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912966593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
912966593
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.565910537
Short name T992
Test name
Test status
Simulation time 503633022 ps
CPU time 12.33 seconds
Started Jun 24 06:07:28 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 205976 kb
Host smart-2e4d1b07-b5cb-4605-a75c-a870fd251631
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565910537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.565910537
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3678604474
Short name T1027
Test name
Test status
Simulation time 14754798 ps
CPU time 1.15 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:26 PM PDT 24
Peak memory 205904 kb
Host smart-e26a7ef5-7393-4e26-9a62-4f14d76ed445
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678604474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
678604474
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2213153208
Short name T1057
Test name
Test status
Simulation time 81806833 ps
CPU time 1.46 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 217196 kb
Host smart-576eaf81-9914-4519-b1ba-8f32f6482f80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213153208 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2213153208
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.438702716
Short name T1010
Test name
Test status
Simulation time 76354628 ps
CPU time 0.92 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:31 PM PDT 24
Peak memory 205764 kb
Host smart-1e3f015d-2885-4f8d-b669-73d8573de05c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438702716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.438702716
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4163933752
Short name T983
Test name
Test status
Simulation time 30950765 ps
CPU time 0.72 seconds
Started Jun 24 06:07:23 PM PDT 24
Finished Jun 24 06:07:25 PM PDT 24
Peak memory 205692 kb
Host smart-eb45e6c9-babc-4667-9f33-ae4242cd2676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163933752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4163933752
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1020289950
Short name T971
Test name
Test status
Simulation time 79197087 ps
CPU time 2.2 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 205980 kb
Host smart-ac0b1bbf-49d7-45a1-8c23-dc069540d8d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020289950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1020289950
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2761986944
Short name T123
Test name
Test status
Simulation time 365316997 ps
CPU time 6.11 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 214488 kb
Host smart-7bde5745-6f87-45a6-a709-2954eadf9a00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761986944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2761986944
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2717292966
Short name T974
Test name
Test status
Simulation time 46280780 ps
CPU time 1.6 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:26 PM PDT 24
Peak memory 214160 kb
Host smart-e2decf61-9a8c-464f-8143-74acc489df49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717292966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2717292966
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2013917421
Short name T160
Test name
Test status
Simulation time 527430891 ps
CPU time 5.46 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 214168 kb
Host smart-5013daf0-e719-42d1-8af1-c8ad929aaf55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013917421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2013917421
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.451207303
Short name T1049
Test name
Test status
Simulation time 374647848 ps
CPU time 8.51 seconds
Started Jun 24 06:07:22 PM PDT 24
Finished Jun 24 06:07:31 PM PDT 24
Peak memory 206020 kb
Host smart-7571a503-7ba2-4563-a1c1-abd12912d9d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451207303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.451207303
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.798374827
Short name T1058
Test name
Test status
Simulation time 866451614 ps
CPU time 13.21 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:46 PM PDT 24
Peak memory 205988 kb
Host smart-30127a07-4b45-48cc-9a8b-978eb6448b23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798374827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.798374827
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3491279359
Short name T950
Test name
Test status
Simulation time 42426139 ps
CPU time 0.96 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:26 PM PDT 24
Peak memory 205988 kb
Host smart-0368d3dc-4af1-4787-9036-b40231c49dcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491279359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
491279359
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1856232406
Short name T1012
Test name
Test status
Simulation time 30793353 ps
CPU time 1.19 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:28 PM PDT 24
Peak memory 206148 kb
Host smart-86a8f38c-7068-48fe-8ede-30be8d8c2912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856232406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1856232406
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3673026248
Short name T926
Test name
Test status
Simulation time 13730107 ps
CPU time 0.73 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:31 PM PDT 24
Peak memory 205668 kb
Host smart-f6b396cb-0eb6-4af0-9da4-b3a05eb9fac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673026248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3673026248
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4267767274
Short name T142
Test name
Test status
Simulation time 108900585 ps
CPU time 3.39 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:28 PM PDT 24
Peak memory 205848 kb
Host smart-c0b4a737-8df6-4ff5-8ea2-cef085e14128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267767274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4267767274
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4180609518
Short name T1028
Test name
Test status
Simulation time 384634387 ps
CPU time 2.96 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 214464 kb
Host smart-6997666b-cf1f-4579-aeff-1ce05c8090b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180609518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4180609518
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3296989653
Short name T1038
Test name
Test status
Simulation time 324031809 ps
CPU time 5.07 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 220656 kb
Host smart-7c47b849-4a7f-43e3-b4ef-f27887139d0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296989653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3296989653
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1402997662
Short name T1035
Test name
Test status
Simulation time 103807893 ps
CPU time 1.95 seconds
Started Jun 24 06:07:27 PM PDT 24
Finished Jun 24 06:07:30 PM PDT 24
Peak memory 214120 kb
Host smart-a3623ba3-c534-46f0-80a8-059a5cd3a18d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402997662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1402997662
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1595795105
Short name T946
Test name
Test status
Simulation time 53616865 ps
CPU time 2.49 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:28 PM PDT 24
Peak memory 214156 kb
Host smart-dbb278f3-5e86-4eb7-9d22-91a1c2c3e0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595795105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1595795105
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3443587745
Short name T1085
Test name
Test status
Simulation time 25088278 ps
CPU time 1.1 seconds
Started Jun 24 06:07:46 PM PDT 24
Finished Jun 24 06:07:50 PM PDT 24
Peak memory 205884 kb
Host smart-d1c5a3fa-7416-4411-8f0a-b638626de1e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443587745 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3443587745
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3271328999
Short name T1022
Test name
Test status
Simulation time 32026506 ps
CPU time 1.13 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 205980 kb
Host smart-0645239e-d8cc-4472-8e74-47eecece7c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271328999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3271328999
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3553279946
Short name T981
Test name
Test status
Simulation time 16760578 ps
CPU time 0.74 seconds
Started Jun 24 06:07:32 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 205692 kb
Host smart-a632077e-0736-4006-b650-7754194e9eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553279946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3553279946
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.160832046
Short name T980
Test name
Test status
Simulation time 37832135 ps
CPU time 1.39 seconds
Started Jun 24 06:07:41 PM PDT 24
Finished Jun 24 06:07:43 PM PDT 24
Peak memory 205936 kb
Host smart-8692861d-9dc1-40cc-adbc-293c9a661439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160832046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.160832046
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.755756856
Short name T985
Test name
Test status
Simulation time 348435563 ps
CPU time 3.37 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 214496 kb
Host smart-296a0ef0-443a-4334-8087-6cb31ff5f4e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755756856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.755756856
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.978279759
Short name T976
Test name
Test status
Simulation time 968890495 ps
CPU time 16.53 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:43 PM PDT 24
Peak memory 214472 kb
Host smart-5c816c5d-7718-4589-81c4-21a2f21584ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978279759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.978279759
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1843343098
Short name T1064
Test name
Test status
Simulation time 248948669 ps
CPU time 3.93 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:30 PM PDT 24
Peak memory 214188 kb
Host smart-d0973a2f-a09c-402d-a9d6-ed29d254fd9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843343098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1843343098
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3701736937
Short name T379
Test name
Test status
Simulation time 23821656 ps
CPU time 1.72 seconds
Started Jun 24 06:07:44 PM PDT 24
Finished Jun 24 06:07:47 PM PDT 24
Peak memory 214292 kb
Host smart-4c4c3007-e7fc-4a65-902f-e453160fd932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701736937 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3701736937
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2999708950
Short name T962
Test name
Test status
Simulation time 68583935 ps
CPU time 0.95 seconds
Started Jun 24 06:07:40 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 205740 kb
Host smart-78abe7d2-01af-4563-a2e0-be87e51deec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999708950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2999708950
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3748105381
Short name T1039
Test name
Test status
Simulation time 16255711 ps
CPU time 0.72 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 205596 kb
Host smart-86ae2a27-da5f-40c0-a527-3d7b04f0914c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748105381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3748105381
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.263269004
Short name T965
Test name
Test status
Simulation time 39002470 ps
CPU time 1.65 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 206004 kb
Host smart-c2319aa5-ba24-4536-b4f8-42c235818667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263269004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.263269004
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2798744881
Short name T117
Test name
Test status
Simulation time 92368935 ps
CPU time 2.69 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 219220 kb
Host smart-c9881dd4-2d49-47b4-8e09-f68c6b32bb86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798744881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2798744881
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1849178974
Short name T1032
Test name
Test status
Simulation time 154030255 ps
CPU time 6.23 seconds
Started Jun 24 06:07:42 PM PDT 24
Finished Jun 24 06:07:49 PM PDT 24
Peak memory 214436 kb
Host smart-39134615-e8ec-4a3b-ab94-fda2a2d50e08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849178974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1849178974
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1474573664
Short name T1008
Test name
Test status
Simulation time 515179011 ps
CPU time 3.56 seconds
Started Jun 24 06:07:42 PM PDT 24
Finished Jun 24 06:07:47 PM PDT 24
Peak memory 214084 kb
Host smart-43f1937d-48e1-46d8-90e8-992030a69e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474573664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1474573664
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.760671223
Short name T953
Test name
Test status
Simulation time 66436292 ps
CPU time 2.31 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 214252 kb
Host smart-27f65b30-c8a8-42c6-a264-a44e7b23e88a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760671223 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.760671223
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.920022045
Short name T153
Test name
Test status
Simulation time 22308098 ps
CPU time 0.97 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:37 PM PDT 24
Peak memory 205672 kb
Host smart-a721e456-c596-458d-82a5-6533ae6f54ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920022045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.920022045
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2939856567
Short name T998
Test name
Test status
Simulation time 23455270 ps
CPU time 0.76 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:46 PM PDT 24
Peak memory 205692 kb
Host smart-6533b36c-611c-4547-9680-f9104e1d71c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939856567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2939856567
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3335088107
Short name T948
Test name
Test status
Simulation time 84641556 ps
CPU time 1.59 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:50 PM PDT 24
Peak memory 214188 kb
Host smart-18454514-805d-4e34-9ea2-37b763540bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335088107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3335088107
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2850668210
Short name T1036
Test name
Test status
Simulation time 471032459 ps
CPU time 2.73 seconds
Started Jun 24 06:07:41 PM PDT 24
Finished Jun 24 06:07:45 PM PDT 24
Peak memory 214544 kb
Host smart-499bfc9c-0542-4dd8-ad85-894f36de8498
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850668210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2850668210
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1621398646
Short name T1082
Test name
Test status
Simulation time 2818719171 ps
CPU time 9.96 seconds
Started Jun 24 06:07:35 PM PDT 24
Finished Jun 24 06:07:47 PM PDT 24
Peak memory 214568 kb
Host smart-87e826f0-fe54-400b-b664-f85a93ea1788
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621398646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1621398646
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1168127791
Short name T990
Test name
Test status
Simulation time 35171523 ps
CPU time 1.93 seconds
Started Jun 24 06:07:39 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 214124 kb
Host smart-5a5b63c1-ec2f-4364-9a80-32f363f68575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168127791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1168127791
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1956914603
Short name T923
Test name
Test status
Simulation time 102917620 ps
CPU time 2 seconds
Started Jun 24 06:07:33 PM PDT 24
Finished Jun 24 06:07:37 PM PDT 24
Peak memory 214192 kb
Host smart-08967560-0c6d-4673-abea-ff6bb4d75282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956914603 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1956914603
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1224694847
Short name T1051
Test name
Test status
Simulation time 24008867 ps
CPU time 0.88 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:47 PM PDT 24
Peak memory 205752 kb
Host smart-3ee46ab8-c042-4f54-8d80-a9be27b5363b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224694847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1224694847
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1986470072
Short name T982
Test name
Test status
Simulation time 32698757 ps
CPU time 0.7 seconds
Started Jun 24 06:07:32 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 205592 kb
Host smart-ba8ad1c7-fb4b-4b09-9e31-fe91e2025158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986470072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1986470072
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1404076966
Short name T1034
Test name
Test status
Simulation time 621138030 ps
CPU time 1.64 seconds
Started Jun 24 06:07:33 PM PDT 24
Finished Jun 24 06:07:37 PM PDT 24
Peak memory 205964 kb
Host smart-f5a57da0-79b4-4277-b236-adb52e61dacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404076966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1404076966
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3325072322
Short name T956
Test name
Test status
Simulation time 307401594 ps
CPU time 2.15 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 214468 kb
Host smart-7515985c-de1d-409f-bde4-272eb2b676bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325072322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3325072322
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4037276303
Short name T1018
Test name
Test status
Simulation time 2630887542 ps
CPU time 10 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:46 PM PDT 24
Peak memory 214520 kb
Host smart-2abef639-2e15-4368-9b5d-0f93bc748656
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037276303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4037276303
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1377582654
Short name T947
Test name
Test status
Simulation time 64585524 ps
CPU time 3.85 seconds
Started Jun 24 06:07:37 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 216976 kb
Host smart-22ce04b5-3df5-4150-805b-fb04577ea8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377582654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1377582654
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3764242037
Short name T157
Test name
Test status
Simulation time 863450676 ps
CPU time 6.98 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 214172 kb
Host smart-a3fe3fd3-5f45-48d2-9bf4-95dbe9dc6fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764242037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3764242037
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.833551523
Short name T151
Test name
Test status
Simulation time 99986437 ps
CPU time 2.03 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 214268 kb
Host smart-96fdb603-4921-47a1-b93a-6f6225c775ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833551523 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.833551523
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1294605662
Short name T961
Test name
Test status
Simulation time 23525923 ps
CPU time 1.12 seconds
Started Jun 24 06:07:53 PM PDT 24
Finished Jun 24 06:07:55 PM PDT 24
Peak memory 205932 kb
Host smart-fef4b959-927c-47b2-8653-3d8e564ebefb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294605662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1294605662
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4041806135
Short name T988
Test name
Test status
Simulation time 37935128 ps
CPU time 0.76 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 205620 kb
Host smart-a1b8fc46-fd4b-417b-a634-cede58d28127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041806135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4041806135
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.187752932
Short name T997
Test name
Test status
Simulation time 77947003 ps
CPU time 2 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 205976 kb
Host smart-fcba723f-c0ec-431e-8f08-d0da47d49a64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187752932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.187752932
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4183039068
Short name T125
Test name
Test status
Simulation time 447708277 ps
CPU time 3.57 seconds
Started Jun 24 06:07:33 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 218292 kb
Host smart-3ba4e625-5793-440b-a6c8-bdd19f4553fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183039068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4183039068
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.774933697
Short name T1014
Test name
Test status
Simulation time 157148222 ps
CPU time 3.18 seconds
Started Jun 24 06:07:56 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 214152 kb
Host smart-49e57c07-5790-4105-98ab-095cb9c65bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774933697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.774933697
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4091209833
Short name T994
Test name
Test status
Simulation time 27889101 ps
CPU time 1.08 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 206284 kb
Host smart-1ddd6265-7a62-4ed4-b6bf-93890c7d7b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091209833 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4091209833
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.156126429
Short name T139
Test name
Test status
Simulation time 48481116 ps
CPU time 1.26 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 205928 kb
Host smart-e67025a2-3e37-4cd9-b302-b69355ec033f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156126429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.156126429
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1888942928
Short name T930
Test name
Test status
Simulation time 10981767 ps
CPU time 0.84 seconds
Started Jun 24 06:07:46 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 205616 kb
Host smart-37a5ee96-8d96-42fe-aa57-34eeb2b16f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888942928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1888942928
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3373257602
Short name T993
Test name
Test status
Simulation time 74493486 ps
CPU time 2.48 seconds
Started Jun 24 06:07:57 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 206008 kb
Host smart-b79ab4eb-1205-4b15-92d7-f86d564d4bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373257602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3373257602
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2900224744
Short name T1019
Test name
Test status
Simulation time 141709624 ps
CPU time 2.39 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 214552 kb
Host smart-1e209690-0a41-4c22-81d6-e1fa6d48d9ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900224744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2900224744
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1549508070
Short name T122
Test name
Test status
Simulation time 653769327 ps
CPU time 5.46 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 214488 kb
Host smart-70522b34-c868-43a8-bd9b-65a3371c9e7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549508070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1549508070
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1096035368
Short name T929
Test name
Test status
Simulation time 68738640 ps
CPU time 2.74 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 216372 kb
Host smart-7f377833-723a-497c-9415-5c502689e748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096035368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1096035368
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1985922676
Short name T1053
Test name
Test status
Simulation time 73689028 ps
CPU time 2.82 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 214160 kb
Host smart-1e84578d-08c9-4e51-a732-fa34384a322f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985922676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1985922676
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3936444559
Short name T1031
Test name
Test status
Simulation time 25467392 ps
CPU time 1.49 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 214176 kb
Host smart-65c67190-aad1-4ccc-b15b-5bb271a0eafe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936444559 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3936444559
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4285293396
Short name T1073
Test name
Test status
Simulation time 86977147 ps
CPU time 1.43 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 206044 kb
Host smart-b797c935-71bf-429f-a2e9-e682e74a8e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285293396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4285293396
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1037421765
Short name T972
Test name
Test status
Simulation time 33503541 ps
CPU time 0.72 seconds
Started Jun 24 06:07:55 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 205696 kb
Host smart-92bf9eba-41fa-46cd-b5ac-aa7807cc7687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037421765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1037421765
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1548134703
Short name T979
Test name
Test status
Simulation time 429418585 ps
CPU time 4.03 seconds
Started Jun 24 06:07:46 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 205980 kb
Host smart-8e72d342-5cfa-4062-bd5b-1a668e6cfbe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548134703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1548134703
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3512014213
Short name T1065
Test name
Test status
Simulation time 132713203 ps
CPU time 4.03 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 214412 kb
Host smart-f74c9ce6-7b4c-4f33-be9f-fd29ad106d86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512014213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3512014213
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3097725804
Short name T966
Test name
Test status
Simulation time 331567554 ps
CPU time 4.07 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 220528 kb
Host smart-de50e863-cb40-43c3-ab4b-8d62b7a1ec1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097725804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3097725804
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4064849697
Short name T1026
Test name
Test status
Simulation time 225974903 ps
CPU time 3.12 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 214128 kb
Host smart-dfb96e3c-3a8d-4e1a-a95b-656ae1035d29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064849697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4064849697
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1992603637
Short name T986
Test name
Test status
Simulation time 36933901 ps
CPU time 1.55 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 214140 kb
Host smart-1beb7704-c423-41e2-9284-b628d2da45f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992603637 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1992603637
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1428005570
Short name T143
Test name
Test status
Simulation time 17071478 ps
CPU time 1.23 seconds
Started Jun 24 06:07:46 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 205964 kb
Host smart-f7f965ea-6319-488b-8b74-9e1c6b41065d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428005570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1428005570
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3945378817
Short name T995
Test name
Test status
Simulation time 76139383 ps
CPU time 0.77 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 205616 kb
Host smart-d6cb0163-99fa-4b4f-9372-2fbba4bb9ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945378817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3945378817
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.990183324
Short name T1040
Test name
Test status
Simulation time 107006776 ps
CPU time 2.23 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 205976 kb
Host smart-49d3f599-7a7e-4cb1-95e8-0aa3d41b27ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990183324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.990183324
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1049948531
Short name T939
Test name
Test status
Simulation time 51531017 ps
CPU time 1.46 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:48 PM PDT 24
Peak memory 214432 kb
Host smart-534f8e2a-9114-4cb9-a187-4b086ba4d25a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049948531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1049948531
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1129327089
Short name T942
Test name
Test status
Simulation time 152094015 ps
CPU time 3.86 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 214160 kb
Host smart-8835b5a7-e9da-48db-b646-5c0c70be37b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129327089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1129327089
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4116041016
Short name T931
Test name
Test status
Simulation time 22192286 ps
CPU time 1.3 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 214156 kb
Host smart-b81f4395-7fb3-4e3d-a7c2-8d1126f43dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116041016 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4116041016
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2434697004
Short name T1015
Test name
Test status
Simulation time 27360964 ps
CPU time 1.49 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 205904 kb
Host smart-5b484104-af60-427f-b12d-b6faf62f72a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434697004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2434697004
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1230842371
Short name T1056
Test name
Test status
Simulation time 10607303 ps
CPU time 0.72 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:49 PM PDT 24
Peak memory 205720 kb
Host smart-7f24a441-a858-4401-ae7d-735964d7c48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230842371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1230842371
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.296450303
Short name T1054
Test name
Test status
Simulation time 441109306 ps
CPU time 3.94 seconds
Started Jun 24 06:07:46 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 205904 kb
Host smart-dc4a302b-57d5-4859-ab42-7e4c010680bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296450303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.296450303
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1966637351
Short name T115
Test name
Test status
Simulation time 237246136 ps
CPU time 1.59 seconds
Started Jun 24 06:07:48 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 214492 kb
Host smart-d070436e-7712-45d0-ad7d-ad06a212cf2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966637351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1966637351
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2198623582
Short name T114
Test name
Test status
Simulation time 77316099 ps
CPU time 4.37 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:55 PM PDT 24
Peak memory 214748 kb
Host smart-c27d9111-a5e5-4df1-9a5d-b27b79f4ddaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198623582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2198623582
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1848889754
Short name T1079
Test name
Test status
Simulation time 233495376 ps
CPU time 4.29 seconds
Started Jun 24 06:07:53 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 216252 kb
Host smart-9a131dfd-bd77-46c3-a333-cca601275169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848889754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1848889754
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.259482539
Short name T959
Test name
Test status
Simulation time 94408448 ps
CPU time 1.79 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 214196 kb
Host smart-125d44e6-9f2b-4337-bead-c41d048a474a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259482539 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.259482539
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.972723573
Short name T943
Test name
Test status
Simulation time 254992690 ps
CPU time 1.14 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:47 PM PDT 24
Peak memory 205924 kb
Host smart-14fe2364-7d92-4d9a-bfad-86bec041e0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972723573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.972723573
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3166330525
Short name T1004
Test name
Test status
Simulation time 14721649 ps
CPU time 0.77 seconds
Started Jun 24 06:07:44 PM PDT 24
Finished Jun 24 06:07:46 PM PDT 24
Peak memory 205696 kb
Host smart-5ee02da9-fe6d-43c8-98bb-9dfe0f60cc28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166330525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3166330525
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2784623250
Short name T1006
Test name
Test status
Simulation time 241110443 ps
CPU time 2.04 seconds
Started Jun 24 06:07:43 PM PDT 24
Finished Jun 24 06:07:45 PM PDT 24
Peak memory 206100 kb
Host smart-113e1cdb-5695-4b64-90e3-50cdd7b705d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784623250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2784623250
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2256160278
Short name T1025
Test name
Test status
Simulation time 276804410 ps
CPU time 1.72 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:52 PM PDT 24
Peak memory 214496 kb
Host smart-55a51342-f28a-4c10-b112-7ee63bd5073e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256160278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2256160278
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1048444017
Short name T958
Test name
Test status
Simulation time 343405502 ps
CPU time 6.93 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:59 PM PDT 24
Peak memory 220548 kb
Host smart-0e2970b7-e8d2-4e3b-a0b8-1aed87c5dfb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048444017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1048444017
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2765665684
Short name T927
Test name
Test status
Simulation time 456316119 ps
CPU time 4.75 seconds
Started Jun 24 06:07:45 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 214132 kb
Host smart-e1abcb0b-c54d-476e-a9f4-511d0ab25d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765665684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2765665684
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2185337300
Short name T373
Test name
Test status
Simulation time 380143241 ps
CPU time 4.58 seconds
Started Jun 24 06:07:54 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 214176 kb
Host smart-10c19f9e-30c7-42a6-84ec-1a815ee15d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185337300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2185337300
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3807906778
Short name T934
Test name
Test status
Simulation time 754723255 ps
CPU time 6.8 seconds
Started Jun 24 06:07:24 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 205796 kb
Host smart-6848109b-3b15-42bd-906a-e8cf96215152
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807906778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
807906778
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.755047267
Short name T1048
Test name
Test status
Simulation time 595240042 ps
CPU time 14.79 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:46 PM PDT 24
Peak memory 205924 kb
Host smart-8a26e2e9-8ac3-48ec-97e3-66c14b2aa300
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755047267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.755047267
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.426229199
Short name T964
Test name
Test status
Simulation time 108958716 ps
CPU time 1.16 seconds
Started Jun 24 06:07:53 PM PDT 24
Finished Jun 24 06:07:55 PM PDT 24
Peak memory 205968 kb
Host smart-5de05266-256c-4736-9a42-0e73815de120
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426229199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.426229199
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3626761615
Short name T967
Test name
Test status
Simulation time 196621960 ps
CPU time 1.49 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 216944 kb
Host smart-c076e939-6350-47ef-87d9-dc3fe0f31c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626761615 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3626761615
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2080211401
Short name T1045
Test name
Test status
Simulation time 74188452 ps
CPU time 0.87 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 205748 kb
Host smart-ca0f0dd5-bd65-4dd2-a735-08e23f779b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080211401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2080211401
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4194540329
Short name T1017
Test name
Test status
Simulation time 79924404 ps
CPU time 0.72 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:29 PM PDT 24
Peak memory 205696 kb
Host smart-1db1e12f-fcac-456d-9cf0-5e1d35155776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194540329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4194540329
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2886570743
Short name T1029
Test name
Test status
Simulation time 243249913 ps
CPU time 2.66 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:30 PM PDT 24
Peak memory 205920 kb
Host smart-943a028b-b95c-4c8d-93cf-1bb8e90bf4c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886570743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2886570743
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1597696034
Short name T118
Test name
Test status
Simulation time 145019188 ps
CPU time 1.28 seconds
Started Jun 24 06:07:27 PM PDT 24
Finished Jun 24 06:07:29 PM PDT 24
Peak memory 214488 kb
Host smart-df1f3c84-7df6-4c52-81f1-fcc1aee932bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597696034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1597696034
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.500972375
Short name T1003
Test name
Test status
Simulation time 446954069 ps
CPU time 10.16 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 221668 kb
Host smart-98f8d6a7-fd2c-40f5-96cc-7769821137c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500972375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.500972375
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3859305651
Short name T1067
Test name
Test status
Simulation time 97103373 ps
CPU time 1.56 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 215628 kb
Host smart-d2f5fdc2-3d7c-4621-9ea2-31bbd720ceb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859305651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3859305651
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3963957310
Short name T920
Test name
Test status
Simulation time 24959035 ps
CPU time 0.85 seconds
Started Jun 24 06:07:50 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 205620 kb
Host smart-11ef8756-ee2a-4621-ba89-bc2463673850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963957310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3963957310
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1726682473
Short name T1042
Test name
Test status
Simulation time 24132366 ps
CPU time 0.92 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 205684 kb
Host smart-29f3a2ae-e7ba-41e4-a0cb-394902517e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726682473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1726682473
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2522303775
Short name T938
Test name
Test status
Simulation time 8830511 ps
CPU time 0.77 seconds
Started Jun 24 06:07:43 PM PDT 24
Finished Jun 24 06:07:44 PM PDT 24
Peak memory 205620 kb
Host smart-7d6faa72-894e-44c4-8c6d-8c46fa8ff6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522303775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2522303775
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2149350859
Short name T1060
Test name
Test status
Simulation time 68197002 ps
CPU time 0.73 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 205692 kb
Host smart-1b2d6b0e-4088-40ec-b7f7-9d0693b28b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149350859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2149350859
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1660852822
Short name T1030
Test name
Test status
Simulation time 20031322 ps
CPU time 0.74 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 205692 kb
Host smart-6e5ea739-8a74-4633-951e-358af370679c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660852822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1660852822
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2846927930
Short name T968
Test name
Test status
Simulation time 48353939 ps
CPU time 0.83 seconds
Started Jun 24 06:07:56 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 205624 kb
Host smart-f3bc3381-8810-47a7-b6e4-66d03ff86671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846927930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2846927930
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2864718353
Short name T940
Test name
Test status
Simulation time 42858965 ps
CPU time 0.72 seconds
Started Jun 24 06:07:59 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 205516 kb
Host smart-7d34b0e2-c8fc-433a-b894-b0dc967422d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864718353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2864718353
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3937963919
Short name T975
Test name
Test status
Simulation time 9234591 ps
CPU time 0.69 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 205592 kb
Host smart-46bb7fbb-2009-40bc-8489-fb8031329e43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937963919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3937963919
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.184934033
Short name T922
Test name
Test status
Simulation time 14443753 ps
CPU time 0.83 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 205620 kb
Host smart-d84a39e8-1e4d-4f3b-8e4a-e8a8861a52fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184934033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.184934033
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1873470147
Short name T1013
Test name
Test status
Simulation time 14817073 ps
CPU time 0.94 seconds
Started Jun 24 06:08:01 PM PDT 24
Finished Jun 24 06:08:03 PM PDT 24
Peak memory 205796 kb
Host smart-24eb0ff9-9313-4bad-809c-878c85376c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873470147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1873470147
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.167522052
Short name T1076
Test name
Test status
Simulation time 190358919 ps
CPU time 7.08 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 205980 kb
Host smart-3b10ce92-0929-4f33-9f6e-042a2be5a2dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167522052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.167522052
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3682253205
Short name T1037
Test name
Test status
Simulation time 481990968 ps
CPU time 7.83 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 206040 kb
Host smart-d28799e2-33c6-42d7-ae42-69094079a0eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682253205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
682253205
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3319025944
Short name T936
Test name
Test status
Simulation time 22538519 ps
CPU time 1.27 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 205972 kb
Host smart-5b30d95a-8bcf-45e2-b1bd-d45c6bd12104
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319025944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
319025944
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3219395188
Short name T951
Test name
Test status
Simulation time 34065016 ps
CPU time 1.86 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 214308 kb
Host smart-8fb84b3f-561d-49a1-8782-41a6c5de536d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219395188 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3219395188
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4090429691
Short name T1044
Test name
Test status
Simulation time 151699040 ps
CPU time 1.06 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:28 PM PDT 24
Peak memory 205512 kb
Host smart-8dc257b4-a125-4909-9437-88a0b5d5a4a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090429691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4090429691
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2408276581
Short name T1011
Test name
Test status
Simulation time 12477072 ps
CPU time 0.7 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:27 PM PDT 24
Peak memory 205620 kb
Host smart-8969a25c-ffc9-4936-8c8e-a0c21b020151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408276581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2408276581
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2162072906
Short name T1086
Test name
Test status
Simulation time 36280122 ps
CPU time 1.5 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 206000 kb
Host smart-45f88b6e-b58c-4b85-9b87-2e2b69cae9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162072906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2162072906
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1674091951
Short name T937
Test name
Test status
Simulation time 258944967 ps
CPU time 1.79 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 214484 kb
Host smart-ad9ea497-51d0-4717-8214-5ff2e0634e36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674091951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1674091951
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.177431522
Short name T121
Test name
Test status
Simulation time 306544762 ps
CPU time 6.67 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 214828 kb
Host smart-7a31247d-7532-4bd9-b774-a540e464a4db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177431522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.177431522
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.602675296
Short name T935
Test name
Test status
Simulation time 98543828 ps
CPU time 2.52 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:30 PM PDT 24
Peak memory 214240 kb
Host smart-856c4b34-06ea-4d7c-87d5-64ba95c092e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602675296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.602675296
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.576960535
Short name T162
Test name
Test status
Simulation time 452495096 ps
CPU time 4.67 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 214172 kb
Host smart-42eb74f5-8f43-4b2d-9dfe-cffc2b53f582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576960535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
576960535
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3393166942
Short name T928
Test name
Test status
Simulation time 12774673 ps
CPU time 0.77 seconds
Started Jun 24 06:07:55 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 205696 kb
Host smart-880135b8-ece3-48e2-9fd4-95a2a760e5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393166942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3393166942
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2051169649
Short name T1081
Test name
Test status
Simulation time 15534053 ps
CPU time 0.94 seconds
Started Jun 24 06:08:00 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 205900 kb
Host smart-1519e577-6f1d-4147-bce3-a6b3ad00a66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051169649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2051169649
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1108135566
Short name T1046
Test name
Test status
Simulation time 30111243 ps
CPU time 0.89 seconds
Started Jun 24 06:07:54 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 205696 kb
Host smart-33538698-30a9-4e4d-8570-043faf31369b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108135566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1108135566
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4159772122
Short name T963
Test name
Test status
Simulation time 120866716 ps
CPU time 0.85 seconds
Started Jun 24 06:07:57 PM PDT 24
Finished Jun 24 06:07:59 PM PDT 24
Peak memory 205696 kb
Host smart-e0b2f677-1370-4f41-a7b1-2354c0883d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159772122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4159772122
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1025646364
Short name T1080
Test name
Test status
Simulation time 47375969 ps
CPU time 0.81 seconds
Started Jun 24 06:07:57 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 205692 kb
Host smart-4f329e6d-3555-466e-b6ec-01cc20ad17ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025646364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1025646364
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1139842152
Short name T921
Test name
Test status
Simulation time 8825955 ps
CPU time 0.79 seconds
Started Jun 24 06:07:58 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 205704 kb
Host smart-81b7a105-2be6-4621-af5a-6cf2fdf929ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139842152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1139842152
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2381518512
Short name T1074
Test name
Test status
Simulation time 29807046 ps
CPU time 1.06 seconds
Started Jun 24 06:07:51 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 205792 kb
Host smart-64789736-0388-460e-8732-215c9ea0ab59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381518512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2381518512
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4089165271
Short name T996
Test name
Test status
Simulation time 20912376 ps
CPU time 0.81 seconds
Started Jun 24 06:08:07 PM PDT 24
Finished Jun 24 06:08:09 PM PDT 24
Peak memory 205668 kb
Host smart-f678d955-8847-449f-ab22-1b7c55c145ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089165271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4089165271
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.346334263
Short name T945
Test name
Test status
Simulation time 78106650 ps
CPU time 0.72 seconds
Started Jun 24 06:08:04 PM PDT 24
Finished Jun 24 06:08:07 PM PDT 24
Peak memory 205592 kb
Host smart-e362fb8c-9eba-4665-945e-b5ef060162bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346334263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.346334263
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.492879333
Short name T987
Test name
Test status
Simulation time 23367470 ps
CPU time 0.69 seconds
Started Jun 24 06:07:54 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 205688 kb
Host smart-7e454c58-44a6-47f1-a902-301b7ac746b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492879333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.492879333
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2276457754
Short name T1062
Test name
Test status
Simulation time 287897541 ps
CPU time 4.94 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 205976 kb
Host smart-37cf0124-7109-41ee-85ea-7824d5013019
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276457754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
276457754
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.849301108
Short name T984
Test name
Test status
Simulation time 3415348644 ps
CPU time 23.85 seconds
Started Jun 24 06:07:38 PM PDT 24
Finished Jun 24 06:08:03 PM PDT 24
Peak memory 206036 kb
Host smart-5fe81637-da57-4f2b-b0c1-73a01b077d2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849301108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.849301108
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2034452240
Short name T1078
Test name
Test status
Simulation time 59294808 ps
CPU time 0.91 seconds
Started Jun 24 06:07:29 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 205728 kb
Host smart-9e813738-d784-4ae1-a11b-aefd7c6f69c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034452240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
034452240
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.437285735
Short name T949
Test name
Test status
Simulation time 52469610 ps
CPU time 1.64 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 214160 kb
Host smart-6756f348-bee2-43df-80c3-c1470692e3c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437285735 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.437285735
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.144315345
Short name T141
Test name
Test status
Simulation time 24598590 ps
CPU time 0.93 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:49 PM PDT 24
Peak memory 205804 kb
Host smart-0ceac40c-a71b-46a8-98f8-5289d17b419e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144315345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.144315345
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3225148934
Short name T977
Test name
Test status
Simulation time 11573144 ps
CPU time 0.74 seconds
Started Jun 24 06:07:40 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 205672 kb
Host smart-bc189b76-76a3-4c66-8677-f514f3a2f224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225148934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3225148934
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2966590384
Short name T1043
Test name
Test status
Simulation time 40276293 ps
CPU time 1.7 seconds
Started Jun 24 06:07:33 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 205976 kb
Host smart-561f0d66-1ec3-49cb-a5f5-7d6c7c53eed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966590384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2966590384
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1719302652
Short name T1072
Test name
Test status
Simulation time 300252770 ps
CPU time 3.9 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:32 PM PDT 24
Peak memory 214488 kb
Host smart-5d836e8d-fdbf-4da0-a03d-3bb153c2e17a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719302652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1719302652
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4244678972
Short name T1063
Test name
Test status
Simulation time 1064138135 ps
CPU time 7.62 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 220476 kb
Host smart-300ba855-7766-489f-b503-5cd4b20a3d11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244678972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4244678972
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1118445690
Short name T1005
Test name
Test status
Simulation time 39166570 ps
CPU time 3 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 214152 kb
Host smart-2428208c-719f-4aca-b9ae-92822d47afff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118445690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1118445690
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.325315578
Short name T159
Test name
Test status
Simulation time 287105807 ps
CPU time 10.71 seconds
Started Jun 24 06:07:28 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 214080 kb
Host smart-c8b41b11-ca9d-44cf-91d0-3e8fd0ea6332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325315578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
325315578
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3735411711
Short name T1033
Test name
Test status
Simulation time 18207616 ps
CPU time 0.71 seconds
Started Jun 24 06:07:56 PM PDT 24
Finished Jun 24 06:07:58 PM PDT 24
Peak memory 205688 kb
Host smart-08ba1eec-79e8-49ba-9d7c-0dc9568ca962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735411711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3735411711
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1067965419
Short name T933
Test name
Test status
Simulation time 13452059 ps
CPU time 0.9 seconds
Started Jun 24 06:08:00 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 205700 kb
Host smart-6a5b2dbc-b931-4b1e-9a10-20690fbea8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067965419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1067965419
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1635098740
Short name T1075
Test name
Test status
Simulation time 40007269 ps
CPU time 0.81 seconds
Started Jun 24 06:08:04 PM PDT 24
Finished Jun 24 06:08:07 PM PDT 24
Peak memory 205692 kb
Host smart-a05fabdf-62e4-490b-a9d6-1d55fefe5bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635098740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1635098740
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1820514704
Short name T1016
Test name
Test status
Simulation time 9396587 ps
CPU time 0.73 seconds
Started Jun 24 06:07:57 PM PDT 24
Finished Jun 24 06:07:59 PM PDT 24
Peak memory 205712 kb
Host smart-d37d1c4b-446f-4a7d-8f53-d2bd5363cf1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820514704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1820514704
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1978106489
Short name T1052
Test name
Test status
Simulation time 18504038 ps
CPU time 0.71 seconds
Started Jun 24 06:07:59 PM PDT 24
Finished Jun 24 06:08:01 PM PDT 24
Peak memory 205696 kb
Host smart-05730f62-6a08-465b-950c-f1fbe2f22c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978106489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1978106489
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.171300925
Short name T1023
Test name
Test status
Simulation time 24854558 ps
CPU time 0.72 seconds
Started Jun 24 06:08:00 PM PDT 24
Finished Jun 24 06:08:02 PM PDT 24
Peak memory 205688 kb
Host smart-fc2aaeca-9dfc-4276-b212-a432e0a19e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171300925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.171300925
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2895318154
Short name T1020
Test name
Test status
Simulation time 10116758 ps
CPU time 0.78 seconds
Started Jun 24 06:07:58 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 205692 kb
Host smart-725673c2-4169-4814-8ca5-be7e6a0f19b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895318154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2895318154
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.968924427
Short name T925
Test name
Test status
Simulation time 21949741 ps
CPU time 0.74 seconds
Started Jun 24 06:08:04 PM PDT 24
Finished Jun 24 06:08:07 PM PDT 24
Peak memory 205704 kb
Host smart-d3a2faf4-84fd-4f9d-b404-aabbcbbb6ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968924427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.968924427
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.537138610
Short name T973
Test name
Test status
Simulation time 25549512 ps
CPU time 0.9 seconds
Started Jun 24 06:07:54 PM PDT 24
Finished Jun 24 06:07:56 PM PDT 24
Peak memory 205788 kb
Host smart-f03ceadb-45b0-455c-822e-15c9ed08d3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537138610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.537138610
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.916215059
Short name T1068
Test name
Test status
Simulation time 12747445 ps
CPU time 0.87 seconds
Started Jun 24 06:07:58 PM PDT 24
Finished Jun 24 06:08:00 PM PDT 24
Peak memory 205632 kb
Host smart-1f904e2b-e601-4b9c-b0e0-1809ca24fad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916215059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.916215059
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3113701669
Short name T1055
Test name
Test status
Simulation time 33252867 ps
CPU time 1.58 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 206064 kb
Host smart-bf14e8d9-1329-49a7-a994-8e786ea0b3e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113701669 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3113701669
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.643622835
Short name T932
Test name
Test status
Simulation time 23547400 ps
CPU time 0.84 seconds
Started Jun 24 06:07:37 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 205824 kb
Host smart-4b2455bb-14aa-47db-b341-f056c6e18c74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643622835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.643622835
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3751042297
Short name T1000
Test name
Test status
Simulation time 55183992 ps
CPU time 0.88 seconds
Started Jun 24 06:07:35 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 205892 kb
Host smart-93ba1981-df58-4c23-9306-2ea7717e6c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751042297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3751042297
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2583930834
Short name T1061
Test name
Test status
Simulation time 48704463 ps
CPU time 2 seconds
Started Jun 24 06:07:49 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 206028 kb
Host smart-353a2e7b-54b6-48db-a8e5-6c05ee40fd79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583930834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2583930834
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3230983212
Short name T1001
Test name
Test status
Simulation time 120991884 ps
CPU time 2.52 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 214320 kb
Host smart-8d11b720-d027-4483-a9d8-94099cb0f4c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230983212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3230983212
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1251411618
Short name T1069
Test name
Test status
Simulation time 154910025 ps
CPU time 3.61 seconds
Started Jun 24 06:07:35 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 220464 kb
Host smart-e83ca8fd-6aab-4648-a9ad-f0ff83638353
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251411618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1251411618
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2466822443
Short name T1021
Test name
Test status
Simulation time 135518888 ps
CPU time 1.91 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 214188 kb
Host smart-3a573792-7faa-48b5-9c94-600a16cf204f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466822443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2466822443
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1681747780
Short name T170
Test name
Test status
Simulation time 328934051 ps
CPU time 11.21 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:44 PM PDT 24
Peak memory 214068 kb
Host smart-a5e430d4-0aa6-47b0-88c2-c1788da7bbbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681747780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1681747780
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3844195870
Short name T969
Test name
Test status
Simulation time 51318582 ps
CPU time 0.96 seconds
Started Jun 24 06:07:33 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 206044 kb
Host smart-f8cb71c0-d6bb-4905-8db0-36b192543eb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844195870 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3844195870
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1064532112
Short name T140
Test name
Test status
Simulation time 50221932 ps
CPU time 1.24 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 206068 kb
Host smart-ef67dc72-6474-4048-a75b-a44c29dea6f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064532112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1064532112
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.338934207
Short name T919
Test name
Test status
Simulation time 12613929 ps
CPU time 0.87 seconds
Started Jun 24 06:07:25 PM PDT 24
Finished Jun 24 06:07:27 PM PDT 24
Peak memory 205712 kb
Host smart-162ff5b0-a015-4fae-8095-a9d3c67b2f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338934207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.338934207
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4174777813
Short name T941
Test name
Test status
Simulation time 24124701 ps
CPU time 1.32 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 206016 kb
Host smart-1e9b23b2-2250-46a9-81a3-1bff8e34651e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174777813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4174777813
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1875638398
Short name T955
Test name
Test status
Simulation time 76087113 ps
CPU time 2.15 seconds
Started Jun 24 06:07:38 PM PDT 24
Finished Jun 24 06:07:41 PM PDT 24
Peak memory 214524 kb
Host smart-6d18161a-141d-4b21-b810-58a05e269d66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875638398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1875638398
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.642183938
Short name T999
Test name
Test status
Simulation time 1412322239 ps
CPU time 12.5 seconds
Started Jun 24 06:07:35 PM PDT 24
Finished Jun 24 06:07:49 PM PDT 24
Peak memory 214512 kb
Host smart-21263b09-a37d-4f41-8703-b75af346c312
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642183938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.642183938
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2151770437
Short name T1066
Test name
Test status
Simulation time 1043938593 ps
CPU time 3.1 seconds
Started Jun 24 06:07:19 PM PDT 24
Finished Jun 24 06:07:25 PM PDT 24
Peak memory 217112 kb
Host smart-550d8d4f-2827-4cd1-89ff-4afc1a9ace3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151770437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2151770437
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3771866790
Short name T171
Test name
Test status
Simulation time 244221019 ps
CPU time 5.51 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:53 PM PDT 24
Peak memory 214196 kb
Host smart-62efe319-5a1d-4899-869e-e31cee92cecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771866790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3771866790
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4123768313
Short name T154
Test name
Test status
Simulation time 24538977 ps
CPU time 1.12 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:34 PM PDT 24
Peak memory 206108 kb
Host smart-1653275d-4ba9-4f33-8b91-fef717ffee36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123768313 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4123768313
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1907046315
Short name T1024
Test name
Test status
Simulation time 34706156 ps
CPU time 0.82 seconds
Started Jun 24 06:07:40 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 205808 kb
Host smart-caa8897c-cf9b-4707-ab21-666d035dc260
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907046315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1907046315
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.125548309
Short name T924
Test name
Test status
Simulation time 15099634 ps
CPU time 0.76 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:38 PM PDT 24
Peak memory 205856 kb
Host smart-07eaa057-9b74-4151-b9fb-43faca6de951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125548309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.125548309
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1524948552
Short name T1070
Test name
Test status
Simulation time 192023740 ps
CPU time 2.22 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 206040 kb
Host smart-d665b362-de35-41f3-8dc2-a3d5b85ec25d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524948552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1524948552
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1221929837
Short name T970
Test name
Test status
Simulation time 170565285 ps
CPU time 1.45 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:49 PM PDT 24
Peak memory 214444 kb
Host smart-69381517-88cd-445d-810d-31735b994050
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221929837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1221929837
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3865414850
Short name T1009
Test name
Test status
Simulation time 152957906 ps
CPU time 4.12 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:37 PM PDT 24
Peak memory 214508 kb
Host smart-d316ccae-0464-4607-ac3a-eceacb225fb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865414850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3865414850
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.4122141771
Short name T952
Test name
Test status
Simulation time 85841499 ps
CPU time 2.27 seconds
Started Jun 24 06:07:27 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 214232 kb
Host smart-f9a4fef6-60af-4453-bc24-8692c7b36c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122141771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.4122141771
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1137931149
Short name T1002
Test name
Test status
Simulation time 607146651 ps
CPU time 3.85 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 214180 kb
Host smart-d5061ef2-ca27-44e2-8ed7-e47dbdcdd033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137931149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1137931149
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3048326567
Short name T1059
Test name
Test status
Simulation time 158372064 ps
CPU time 1.12 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 205976 kb
Host smart-210981fe-b47f-4c83-a508-af45b32e6721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048326567 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3048326567
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3687815493
Short name T1047
Test name
Test status
Simulation time 37457485 ps
CPU time 0.84 seconds
Started Jun 24 06:07:32 PM PDT 24
Finished Jun 24 06:07:35 PM PDT 24
Peak memory 205812 kb
Host smart-0124cc4e-1abe-455a-9cd1-5df4c395a213
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687815493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3687815493
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.949395278
Short name T1077
Test name
Test status
Simulation time 12084708 ps
CPU time 0.88 seconds
Started Jun 24 06:07:40 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 205616 kb
Host smart-b77d7c2a-5e93-46b6-84fd-8e78a4a4c3d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949395278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.949395278
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.644175798
Short name T960
Test name
Test status
Simulation time 440070599 ps
CPU time 4.05 seconds
Started Jun 24 06:07:34 PM PDT 24
Finished Jun 24 06:07:40 PM PDT 24
Peak memory 206124 kb
Host smart-1685d68b-ad0e-4422-a34e-bd0b9fe32eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644175798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.644175798
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2859988269
Short name T1084
Test name
Test status
Simulation time 551383616 ps
CPU time 2.9 seconds
Started Jun 24 06:07:47 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 214508 kb
Host smart-edb5d3d3-de00-4ec0-a524-7bc31031a1d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859988269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2859988269
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4027828501
Short name T978
Test name
Test status
Simulation time 7911927738 ps
CPU time 16.64 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:54 PM PDT 24
Peak memory 222716 kb
Host smart-6ea63a28-b1ba-4aef-b07f-bd25944ad5e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027828501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4027828501
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1740376303
Short name T944
Test name
Test status
Simulation time 246524324 ps
CPU time 3.35 seconds
Started Jun 24 06:07:33 PM PDT 24
Finished Jun 24 06:07:39 PM PDT 24
Peak memory 217408 kb
Host smart-eb1ccc8b-98d8-4080-8b78-1a0b53c84849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740376303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1740376303
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4111852222
Short name T166
Test name
Test status
Simulation time 567698447 ps
CPU time 4.72 seconds
Started Jun 24 06:07:35 PM PDT 24
Finished Jun 24 06:07:42 PM PDT 24
Peak memory 214420 kb
Host smart-c27aec89-b82c-4f4c-a9d4-440b2c6a2690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111852222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4111852222
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1571242278
Short name T989
Test name
Test status
Simulation time 33333084 ps
CPU time 2.43 seconds
Started Jun 24 06:07:26 PM PDT 24
Finished Jun 24 06:07:30 PM PDT 24
Peak memory 213980 kb
Host smart-1dc8c1e2-7b3c-4ee8-bb9b-7e03a5864aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571242278 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1571242278
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1211303294
Short name T1041
Test name
Test status
Simulation time 34584837 ps
CPU time 1.22 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 205968 kb
Host smart-77fa92c5-ed13-4913-905f-0353e68f938b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211303294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1211303294
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.144253164
Short name T991
Test name
Test status
Simulation time 12371531 ps
CPU time 0.7 seconds
Started Jun 24 06:07:30 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 205668 kb
Host smart-3ef44843-8ee2-4b74-9abb-0636ac08c0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144253164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.144253164
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3329950714
Short name T957
Test name
Test status
Simulation time 230569683 ps
CPU time 1.57 seconds
Started Jun 24 06:07:40 PM PDT 24
Finished Jun 24 06:07:43 PM PDT 24
Peak memory 206072 kb
Host smart-aa358333-0663-47f7-b04b-6a229d85e82e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329950714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3329950714
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1253422317
Short name T120
Test name
Test status
Simulation time 151100895 ps
CPU time 2.89 seconds
Started Jun 24 06:07:36 PM PDT 24
Finished Jun 24 06:07:41 PM PDT 24
Peak memory 214412 kb
Host smart-8ccb9792-97e1-444d-ad7a-109d0abdf42a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253422317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1253422317
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1387994950
Short name T1007
Test name
Test status
Simulation time 652351745 ps
CPU time 4.38 seconds
Started Jun 24 06:07:27 PM PDT 24
Finished Jun 24 06:07:33 PM PDT 24
Peak memory 214456 kb
Host smart-1f065504-44de-4018-aa9f-2fcc21f38a3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387994950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1387994950
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1211251171
Short name T1050
Test name
Test status
Simulation time 65485202 ps
CPU time 2.53 seconds
Started Jun 24 06:07:31 PM PDT 24
Finished Jun 24 06:07:36 PM PDT 24
Peak memory 214232 kb
Host smart-6ad5b628-f4b5-4d5f-9ee4-45dee98fb5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211251171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1211251171
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.382015470
Short name T804
Test name
Test status
Simulation time 50926561 ps
CPU time 0.93 seconds
Started Jun 24 06:12:45 PM PDT 24
Finished Jun 24 06:12:46 PM PDT 24
Peak memory 206084 kb
Host smart-0f733f4a-d618-4ba1-8088-2eef7099989f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382015470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.382015470
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2968722761
Short name T470
Test name
Test status
Simulation time 244404160 ps
CPU time 4.02 seconds
Started Jun 24 06:12:44 PM PDT 24
Finished Jun 24 06:12:49 PM PDT 24
Peak memory 214696 kb
Host smart-1adbb5e9-ba48-4bd6-a5bf-91f5649e6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968722761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2968722761
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1425225550
Short name T906
Test name
Test status
Simulation time 145781606 ps
CPU time 5.24 seconds
Started Jun 24 06:12:44 PM PDT 24
Finished Jun 24 06:12:50 PM PDT 24
Peak memory 214304 kb
Host smart-2cbb306b-6fce-48a8-b16b-b11f563d11c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425225550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1425225550
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2570919738
Short name T235
Test name
Test status
Simulation time 39202269 ps
CPU time 2.5 seconds
Started Jun 24 06:12:43 PM PDT 24
Finished Jun 24 06:12:46 PM PDT 24
Peak memory 215924 kb
Host smart-f149c514-282b-409c-8fd0-003ae237c483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570919738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2570919738
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1119914426
Short name T527
Test name
Test status
Simulation time 1331074948 ps
CPU time 30.17 seconds
Started Jun 24 06:12:37 PM PDT 24
Finished Jun 24 06:13:08 PM PDT 24
Peak memory 208632 kb
Host smart-e7ee99bc-404d-4c51-aab2-28120466f74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119914426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1119914426
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.236525972
Short name T847
Test name
Test status
Simulation time 130294047 ps
CPU time 2.51 seconds
Started Jun 24 06:12:34 PM PDT 24
Finished Jun 24 06:12:37 PM PDT 24
Peak memory 206976 kb
Host smart-d7ed481b-e010-47a4-88f6-9fcd40bb87da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236525972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.236525972
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.120768475
Short name T301
Test name
Test status
Simulation time 53644450 ps
CPU time 2.71 seconds
Started Jun 24 06:12:34 PM PDT 24
Finished Jun 24 06:12:38 PM PDT 24
Peak memory 208704 kb
Host smart-602f7cf3-5968-49ec-b4d5-0da4679d655c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120768475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.120768475
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2583756978
Short name T724
Test name
Test status
Simulation time 103133013 ps
CPU time 2.07 seconds
Started Jun 24 06:12:35 PM PDT 24
Finished Jun 24 06:12:37 PM PDT 24
Peak memory 209020 kb
Host smart-95ef4269-fad7-4a56-afab-fbfa41306a84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583756978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2583756978
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.103700652
Short name T891
Test name
Test status
Simulation time 328502143 ps
CPU time 4.26 seconds
Started Jun 24 06:12:34 PM PDT 24
Finished Jun 24 06:12:39 PM PDT 24
Peak memory 208884 kb
Host smart-d7283075-d924-47f0-9ea4-8ba97e65eaf4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103700652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.103700652
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.991878239
Short name T265
Test name
Test status
Simulation time 377037435 ps
CPU time 4.38 seconds
Started Jun 24 06:12:45 PM PDT 24
Finished Jun 24 06:12:50 PM PDT 24
Peak memory 214312 kb
Host smart-35aa47b3-3c4a-4326-92b8-6d1e94bdd0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991878239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.991878239
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2906193809
Short name T105
Test name
Test status
Simulation time 48271264 ps
CPU time 2.39 seconds
Started Jun 24 06:12:33 PM PDT 24
Finished Jun 24 06:12:36 PM PDT 24
Peak memory 206760 kb
Host smart-08a27842-de28-4524-9f75-46411973c67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906193809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2906193809
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1835646730
Short name T386
Test name
Test status
Simulation time 560802229 ps
CPU time 6.12 seconds
Started Jun 24 06:12:44 PM PDT 24
Finished Jun 24 06:12:50 PM PDT 24
Peak memory 208956 kb
Host smart-e5ee0b43-54e1-4121-9ed0-83906e4166a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835646730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1835646730
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1275662283
Short name T178
Test name
Test status
Simulation time 290063318 ps
CPU time 9.55 seconds
Started Jun 24 06:12:47 PM PDT 24
Finished Jun 24 06:12:58 PM PDT 24
Peak memory 222532 kb
Host smart-849291c6-ab8e-4ede-9c3b-f1a8b7766ef7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275662283 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1275662283
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2464542600
Short name T602
Test name
Test status
Simulation time 35310791 ps
CPU time 2.01 seconds
Started Jun 24 06:12:44 PM PDT 24
Finished Jun 24 06:12:47 PM PDT 24
Peak memory 222372 kb
Host smart-413915b9-89cf-4550-a4a4-10b6b778c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464542600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2464542600
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3711756252
Short name T529
Test name
Test status
Simulation time 37593503 ps
CPU time 1.02 seconds
Started Jun 24 06:12:54 PM PDT 24
Finished Jun 24 06:12:56 PM PDT 24
Peak memory 206072 kb
Host smart-07c037ad-5e49-482e-8e1e-5f6a296f6abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711756252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3711756252
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2110045514
Short name T664
Test name
Test status
Simulation time 123716439 ps
CPU time 1.61 seconds
Started Jun 24 06:12:57 PM PDT 24
Finished Jun 24 06:12:59 PM PDT 24
Peak memory 214320 kb
Host smart-a507c688-89d5-4095-bb4c-b7fc7fed865e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110045514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2110045514
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2875875935
Short name T303
Test name
Test status
Simulation time 31482612 ps
CPU time 2.16 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:12:58 PM PDT 24
Peak memory 219660 kb
Host smart-64fd93e5-f15a-4811-9116-99def928b265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875875935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2875875935
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2353738370
Short name T252
Test name
Test status
Simulation time 331339527 ps
CPU time 4.56 seconds
Started Jun 24 06:12:54 PM PDT 24
Finished Jun 24 06:12:59 PM PDT 24
Peak memory 206148 kb
Host smart-086d9653-d9a6-4255-9cf5-dbfbc7e0e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353738370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2353738370
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2564993995
Short name T606
Test name
Test status
Simulation time 159235008 ps
CPU time 3.51 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:12:59 PM PDT 24
Peak memory 220408 kb
Host smart-79e44269-89ed-4656-8b14-d14fd29797e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564993995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2564993995
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2354007638
Short name T324
Test name
Test status
Simulation time 848036113 ps
CPU time 3.32 seconds
Started Jun 24 06:12:53 PM PDT 24
Finished Jun 24 06:12:57 PM PDT 24
Peak memory 222488 kb
Host smart-8e810941-8025-4a88-aaa9-406a9af60703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354007638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2354007638
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2125136380
Short name T468
Test name
Test status
Simulation time 144218451 ps
CPU time 3.48 seconds
Started Jun 24 06:12:43 PM PDT 24
Finished Jun 24 06:12:47 PM PDT 24
Peak memory 208584 kb
Host smart-2afcefa4-e479-4a37-bb41-94b0737de55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125136380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2125136380
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.114373223
Short name T800
Test name
Test status
Simulation time 706793032 ps
CPU time 4.85 seconds
Started Jun 24 06:12:47 PM PDT 24
Finished Jun 24 06:12:52 PM PDT 24
Peak memory 207808 kb
Host smart-88881524-2828-44e6-8ba4-086ae3c5924c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114373223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.114373223
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.59177608
Short name T549
Test name
Test status
Simulation time 292599973 ps
CPU time 3.4 seconds
Started Jun 24 06:12:45 PM PDT 24
Finished Jun 24 06:12:49 PM PDT 24
Peak memory 206916 kb
Host smart-9682101f-9871-404f-8c90-4d5570e78dc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59177608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.59177608
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2690401231
Short name T772
Test name
Test status
Simulation time 55310923 ps
CPU time 2.91 seconds
Started Jun 24 06:12:46 PM PDT 24
Finished Jun 24 06:12:50 PM PDT 24
Peak memory 206828 kb
Host smart-104a2c69-40bc-4280-9677-4e6e1e58dbe6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690401231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2690401231
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3938474830
Short name T834
Test name
Test status
Simulation time 694234564 ps
CPU time 2.67 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:12:58 PM PDT 24
Peak memory 222432 kb
Host smart-f0ab8dd3-2fa6-4d36-8147-24a63d7bf3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938474830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3938474830
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2818140611
Short name T425
Test name
Test status
Simulation time 400523215 ps
CPU time 2.97 seconds
Started Jun 24 06:12:44 PM PDT 24
Finished Jun 24 06:12:48 PM PDT 24
Peak memory 208292 kb
Host smart-537244e3-5398-4fd9-b0c2-ea1574d28d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818140611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2818140611
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1480396774
Short name T663
Test name
Test status
Simulation time 97987805 ps
CPU time 4.51 seconds
Started Jun 24 06:12:56 PM PDT 24
Finished Jun 24 06:13:01 PM PDT 24
Peak memory 209352 kb
Host smart-026971d5-866d-40a1-b41d-e2a784e80c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480396774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1480396774
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.348700138
Short name T188
Test name
Test status
Simulation time 386203318 ps
CPU time 11.1 seconds
Started Jun 24 06:12:56 PM PDT 24
Finished Jun 24 06:13:07 PM PDT 24
Peak memory 210944 kb
Host smart-25881508-f149-4b68-a97e-0d799384a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348700138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.348700138
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1283599927
Short name T518
Test name
Test status
Simulation time 104414854 ps
CPU time 4.7 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 208900 kb
Host smart-f4612b83-b42f-400e-a1f8-c313a1acc410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283599927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1283599927
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1028808440
Short name T250
Test name
Test status
Simulation time 170260014 ps
CPU time 3.62 seconds
Started Jun 24 06:14:06 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 210080 kb
Host smart-3e103a54-9f95-4031-87d0-4dc7d34f68d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028808440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1028808440
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.558961494
Short name T354
Test name
Test status
Simulation time 103328302 ps
CPU time 1.81 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 222372 kb
Host smart-65888637-748a-49f3-92d5-23981b3d067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558961494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.558961494
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4143992034
Short name T485
Test name
Test status
Simulation time 30744681 ps
CPU time 2.45 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 207800 kb
Host smart-65b888b4-1d24-4883-b1d5-dbdd837a7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143992034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4143992034
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1222991132
Short name T281
Test name
Test status
Simulation time 312477562 ps
CPU time 4.36 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:15 PM PDT 24
Peak memory 207444 kb
Host smart-595a080a-9536-4373-bebc-068a4691d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222991132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1222991132
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2384948537
Short name T519
Test name
Test status
Simulation time 109821732 ps
CPU time 3.91 seconds
Started Jun 24 06:14:07 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 208332 kb
Host smart-17d4d1ea-d731-4d50-a908-56b5bf0cf0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384948537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2384948537
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1535357477
Short name T690
Test name
Test status
Simulation time 167374115 ps
CPU time 2.59 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 206932 kb
Host smart-286c4626-6df2-4cb7-bf22-63a63a542d21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535357477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1535357477
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2267059144
Short name T864
Test name
Test status
Simulation time 3390053109 ps
CPU time 36.91 seconds
Started Jun 24 06:14:12 PM PDT 24
Finished Jun 24 06:14:50 PM PDT 24
Peak memory 209264 kb
Host smart-37dbd0e5-d99f-4ee6-82f3-ba73960fc74e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267059144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2267059144
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1443572391
Short name T579
Test name
Test status
Simulation time 379252544 ps
CPU time 3.75 seconds
Started Jun 24 06:14:12 PM PDT 24
Finished Jun 24 06:14:17 PM PDT 24
Peak memory 207552 kb
Host smart-e1ae402c-65e5-416d-89c3-8828baa6bab3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443572391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1443572391
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3102039239
Short name T355
Test name
Test status
Simulation time 68302179 ps
CPU time 3.04 seconds
Started Jun 24 06:14:11 PM PDT 24
Finished Jun 24 06:14:15 PM PDT 24
Peak memory 214520 kb
Host smart-faffd93a-cca4-4895-b866-6babc0b9c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102039239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3102039239
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3706582329
Short name T758
Test name
Test status
Simulation time 59546833 ps
CPU time 2.85 seconds
Started Jun 24 06:14:09 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 208644 kb
Host smart-ab497984-492b-4879-b130-badb765112b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706582329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3706582329
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1453901192
Short name T189
Test name
Test status
Simulation time 26339640 ps
CPU time 2 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 207596 kb
Host smart-7f13b704-8b6f-4876-bd8e-91f137bbe5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453901192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1453901192
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.247556372
Short name T130
Test name
Test status
Simulation time 1557452429 ps
CPU time 28.19 seconds
Started Jun 24 06:14:09 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 211100 kb
Host smart-32cd620b-8406-4f56-84ab-dcfb6c790097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247556372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.247556372
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2335345293
Short name T856
Test name
Test status
Simulation time 38588361 ps
CPU time 0.94 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:20 PM PDT 24
Peak memory 206060 kb
Host smart-f3462b79-49c1-4aff-8f0f-ecc189cbcdc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335345293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2335345293
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1386665862
Short name T23
Test name
Test status
Simulation time 261799711 ps
CPU time 2.81 seconds
Started Jun 24 06:14:16 PM PDT 24
Finished Jun 24 06:14:20 PM PDT 24
Peak memory 216280 kb
Host smart-4a6dcb68-9f60-4ffe-903a-d3a9dbf25ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386665862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1386665862
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.608759769
Short name T824
Test name
Test status
Simulation time 307811432 ps
CPU time 3.97 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 209724 kb
Host smart-14282314-6321-47cf-9c8b-3a35d7e19ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608759769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.608759769
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.453303208
Short name T270
Test name
Test status
Simulation time 71548187 ps
CPU time 2.53 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 214284 kb
Host smart-9cab212e-d100-4585-a49a-bb84da2ca180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453303208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.453303208
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3413732557
Short name T744
Test name
Test status
Simulation time 363406166 ps
CPU time 3.62 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:24 PM PDT 24
Peak memory 214256 kb
Host smart-1b24e716-7f4c-4102-8627-b49952aaf463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413732557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3413732557
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.965778567
Short name T586
Test name
Test status
Simulation time 196866711 ps
CPU time 5.9 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 218660 kb
Host smart-69e10b09-cd24-4999-a806-ab21a4c6c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965778567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.965778567
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3656761227
Short name T545
Test name
Test status
Simulation time 194331293 ps
CPU time 4.89 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:27 PM PDT 24
Peak memory 214264 kb
Host smart-b00e5efb-3842-4415-9167-a5b29958d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656761227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3656761227
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2988695108
Short name T199
Test name
Test status
Simulation time 38164876 ps
CPU time 2.64 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 208548 kb
Host smart-e95f7c1c-d530-4b2d-814d-6f6cca1bed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988695108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2988695108
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.149338747
Short name T610
Test name
Test status
Simulation time 106883470 ps
CPU time 2.9 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 208504 kb
Host smart-8ac9d05d-6005-40a5-9b0c-06f724288bd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149338747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.149338747
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.203016134
Short name T365
Test name
Test status
Simulation time 190985176 ps
CPU time 6.69 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:26 PM PDT 24
Peak memory 208292 kb
Host smart-5b3e25d0-f95f-4790-956b-c142595e26a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203016134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.203016134
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2830232760
Short name T741
Test name
Test status
Simulation time 706977368 ps
CPU time 7.57 seconds
Started Jun 24 06:14:16 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 208524 kb
Host smart-604082ae-edc8-47ba-962c-dbb09ded4bd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830232760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2830232760
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2768402989
Short name T536
Test name
Test status
Simulation time 1241672653 ps
CPU time 7.87 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:26 PM PDT 24
Peak memory 210284 kb
Host smart-549fe6a8-c9c5-481d-816b-d8e8ee788fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768402989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2768402989
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.887255427
Short name T918
Test name
Test status
Simulation time 3121312210 ps
CPU time 48.74 seconds
Started Jun 24 06:14:07 PM PDT 24
Finished Jun 24 06:14:57 PM PDT 24
Peak memory 206964 kb
Host smart-524e5ed5-c7cf-4a5b-87c0-f8f2a8847341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887255427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.887255427
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3726500345
Short name T697
Test name
Test status
Simulation time 462458230 ps
CPU time 16.46 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 221188 kb
Host smart-3bcebfa2-af7e-48c6-b3da-312293adcf45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726500345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3726500345
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3696738002
Short name T626
Test name
Test status
Simulation time 660710221 ps
CPU time 5.49 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:24 PM PDT 24
Peak memory 207572 kb
Host smart-93c487fa-9579-44eb-b1ce-ced499623797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696738002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3696738002
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.674464368
Short name T203
Test name
Test status
Simulation time 114087711 ps
CPU time 2.31 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 210092 kb
Host smart-5d512f4d-2547-4abe-a36a-a25e6e773201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674464368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.674464368
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1101558394
Short name T476
Test name
Test status
Simulation time 58786713 ps
CPU time 0.71 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 205860 kb
Host smart-b8979f29-f5a9-4ac7-a496-7493eea5203c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101558394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1101558394
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3294677517
Short name T400
Test name
Test status
Simulation time 832873522 ps
CPU time 10.25 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:29 PM PDT 24
Peak memory 214304 kb
Host smart-f0f60bd0-d2bd-4f1a-8b56-a55e3b449e80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3294677517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3294677517
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3688560177
Short name T860
Test name
Test status
Simulation time 90696033 ps
CPU time 2.74 seconds
Started Jun 24 06:14:16 PM PDT 24
Finished Jun 24 06:14:20 PM PDT 24
Peak memory 209336 kb
Host smart-ee192295-f2ad-4870-bcea-3e35418c9a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688560177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3688560177
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1364970562
Short name T444
Test name
Test status
Simulation time 66985649 ps
CPU time 1.49 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:22 PM PDT 24
Peak memory 207316 kb
Host smart-4328ccc0-863a-4f3d-bb0a-ee458fc89da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364970562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1364970562
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4241467382
Short name T25
Test name
Test status
Simulation time 44906119 ps
CPU time 3.3 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:26 PM PDT 24
Peak memory 220376 kb
Host smart-31121795-e441-4495-a288-17fc44c75a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241467382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4241467382
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1443926932
Short name T368
Test name
Test status
Simulation time 139878442 ps
CPU time 3.11 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:22 PM PDT 24
Peak memory 214212 kb
Host smart-0d2a9004-e877-4a80-ba2d-3238ad9200f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443926932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1443926932
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1955429918
Short name T336
Test name
Test status
Simulation time 283675612 ps
CPU time 8.21 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:31 PM PDT 24
Peak memory 209836 kb
Host smart-e819fcc8-0058-49d0-bad6-0794136e7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955429918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1955429918
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3033488925
Short name T366
Test name
Test status
Simulation time 907906656 ps
CPU time 14.79 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:35 PM PDT 24
Peak memory 214304 kb
Host smart-6b59c168-17ba-4e76-8991-76f396276fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033488925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3033488925
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3301721838
Short name T717
Test name
Test status
Simulation time 119461485 ps
CPU time 3.68 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 206956 kb
Host smart-61f87697-b347-4dad-8052-749a5073d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301721838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3301721838
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.923659983
Short name T450
Test name
Test status
Simulation time 269811371 ps
CPU time 3.67 seconds
Started Jun 24 06:14:16 PM PDT 24
Finished Jun 24 06:14:20 PM PDT 24
Peak memory 208720 kb
Host smart-12093b6a-1822-4d9d-abdd-3e457db48526
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923659983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.923659983
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.969704225
Short name T827
Test name
Test status
Simulation time 441126751 ps
CPU time 5.35 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:26 PM PDT 24
Peak memory 208588 kb
Host smart-049af79b-7acd-4e5f-b273-eb32f197747a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969704225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.969704225
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2206283040
Short name T524
Test name
Test status
Simulation time 132668781 ps
CPU time 4.83 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:24 PM PDT 24
Peak memory 208524 kb
Host smart-3dc0c347-f640-4fda-9f30-15246e4034bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206283040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2206283040
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.215408670
Short name T437
Test name
Test status
Simulation time 3032740109 ps
CPU time 48.92 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 208764 kb
Host smart-797bb711-b9c4-477b-8419-44f28dc69e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215408670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.215408670
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.845181157
Short name T819
Test name
Test status
Simulation time 555300920 ps
CPU time 20.52 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:40 PM PDT 24
Peak memory 222596 kb
Host smart-e8f6e97b-963f-4196-8021-9f82a5ea7ee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845181157 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.845181157
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2178972978
Short name T905
Test name
Test status
Simulation time 255022147 ps
CPU time 6.85 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:26 PM PDT 24
Peak memory 208376 kb
Host smart-e5924471-12aa-4f50-9982-e5d07057249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178972978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2178972978
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2078678037
Short name T510
Test name
Test status
Simulation time 48426598 ps
CPU time 1.52 seconds
Started Jun 24 06:14:18 PM PDT 24
Finished Jun 24 06:14:21 PM PDT 24
Peak memory 209872 kb
Host smart-f81bbdd3-3a17-4c8e-bced-75ec6d39631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078678037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2078678037
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1292128403
Short name T564
Test name
Test status
Simulation time 35508644 ps
CPU time 0.84 seconds
Started Jun 24 06:14:26 PM PDT 24
Finished Jun 24 06:14:28 PM PDT 24
Peak memory 205908 kb
Host smart-d3f08065-4971-44ed-8780-67d85b2b1c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292128403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1292128403
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1407125550
Short name T673
Test name
Test status
Simulation time 683398701 ps
CPU time 4.74 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:22 PM PDT 24
Peak memory 209716 kb
Host smart-bbda0b09-d680-4a58-8bf6-fb1e2054fec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407125550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1407125550
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.531942774
Short name T338
Test name
Test status
Simulation time 227166044 ps
CPU time 2.34 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 222424 kb
Host smart-e58d1358-40b6-4181-acd2-c14f0349773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531942774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.531942774
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1117273475
Short name T807
Test name
Test status
Simulation time 335556910 ps
CPU time 4.27 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 220352 kb
Host smart-b0237f10-2fe2-4efe-8f6b-73c160946cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117273475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1117273475
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1993893446
Short name T471
Test name
Test status
Simulation time 232946024 ps
CPU time 5.28 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:24 PM PDT 24
Peak memory 209400 kb
Host smart-4e19b81f-f300-4c34-b3a2-dbc86c9c5f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993893446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1993893446
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3982731301
Short name T452
Test name
Test status
Simulation time 552616622 ps
CPU time 4.41 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 208648 kb
Host smart-04df09cd-3bd3-48a1-8044-ae95b1146e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982731301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3982731301
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3415023417
Short name T455
Test name
Test status
Simulation time 91741870 ps
CPU time 3.89 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 208312 kb
Host smart-6619005f-a8e3-4def-88f0-e6c3ee8e8378
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415023417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3415023417
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4120715549
Short name T504
Test name
Test status
Simulation time 49730348 ps
CPU time 2.83 seconds
Started Jun 24 06:14:21 PM PDT 24
Finished Jun 24 06:14:25 PM PDT 24
Peak memory 208640 kb
Host smart-a6026bed-fe8a-4495-952a-3a7a2d7a7320
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120715549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4120715549
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4082284540
Short name T449
Test name
Test status
Simulation time 272732824 ps
CPU time 3.37 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:24 PM PDT 24
Peak memory 208740 kb
Host smart-5aab9a6f-e060-48c0-974b-95d49efe5b82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082284540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4082284540
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1819461233
Short name T879
Test name
Test status
Simulation time 911160855 ps
CPU time 4.33 seconds
Started Jun 24 06:14:17 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 207980 kb
Host smart-0cff8739-514d-4d65-ad91-25e78c47ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819461233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1819461233
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3403081329
Short name T816
Test name
Test status
Simulation time 65613893 ps
CPU time 1.73 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:21 PM PDT 24
Peak memory 206712 kb
Host smart-50860801-cf78-477d-afd3-ffbd6da1fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403081329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3403081329
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4242925370
Short name T745
Test name
Test status
Simulation time 273418356 ps
CPU time 17.12 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:46 PM PDT 24
Peak memory 222600 kb
Host smart-babc603a-ad7f-460b-aff2-fc0864fd2f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242925370 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4242925370
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1654196025
Short name T880
Test name
Test status
Simulation time 55516662 ps
CPU time 3.42 seconds
Started Jun 24 06:14:20 PM PDT 24
Finished Jun 24 06:14:24 PM PDT 24
Peak memory 209144 kb
Host smart-4d5eb208-49e6-4126-94aa-9408d3fe3db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654196025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1654196025
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4158743241
Short name T514
Test name
Test status
Simulation time 113250618 ps
CPU time 2.78 seconds
Started Jun 24 06:14:19 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 210484 kb
Host smart-e418439b-763e-4948-85a2-3dad9689c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158743241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4158743241
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1851971658
Short name T543
Test name
Test status
Simulation time 59597244 ps
CPU time 0.76 seconds
Started Jun 24 06:14:29 PM PDT 24
Finished Jun 24 06:14:31 PM PDT 24
Peak memory 205920 kb
Host smart-4a442663-038e-47cd-a502-44b9af811733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851971658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1851971658
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2148512093
Short name T381
Test name
Test status
Simulation time 80162758 ps
CPU time 4.75 seconds
Started Jun 24 06:14:26 PM PDT 24
Finished Jun 24 06:14:32 PM PDT 24
Peak memory 222492 kb
Host smart-0795c1c1-dbc9-4e95-bb6f-cb82e23a7ad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148512093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2148512093
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1539818910
Short name T525
Test name
Test status
Simulation time 188367097 ps
CPU time 2.95 seconds
Started Jun 24 06:14:29 PM PDT 24
Finished Jun 24 06:14:33 PM PDT 24
Peak memory 209076 kb
Host smart-63d5acf4-c205-47f7-b2bc-fd23918794da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539818910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1539818910
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.58592391
Short name T872
Test name
Test status
Simulation time 1134099120 ps
CPU time 5.93 seconds
Started Jun 24 06:14:30 PM PDT 24
Finished Jun 24 06:14:36 PM PDT 24
Peak memory 214376 kb
Host smart-0c590b93-f182-424c-b362-291e73c003c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58592391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.58592391
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2821117020
Short name T69
Test name
Test status
Simulation time 1342537922 ps
CPU time 6.75 seconds
Started Jun 24 06:14:30 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 214248 kb
Host smart-339fbb8f-c5e8-4d70-9464-c8e50c829392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821117020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2821117020
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2058805796
Short name T907
Test name
Test status
Simulation time 470189134 ps
CPU time 4.09 seconds
Started Jun 24 06:14:27 PM PDT 24
Finished Jun 24 06:14:32 PM PDT 24
Peak memory 220440 kb
Host smart-f021e7fc-29d5-41fe-a0c2-73b76baec0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058805796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2058805796
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.938539596
Short name T35
Test name
Test status
Simulation time 282076224 ps
CPU time 5.77 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:35 PM PDT 24
Peak memory 210316 kb
Host smart-7a8bb634-aa72-4ea2-bca0-fd798c9f91c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938539596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.938539596
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.923555858
Short name T416
Test name
Test status
Simulation time 518070822 ps
CPU time 5.59 seconds
Started Jun 24 06:14:29 PM PDT 24
Finished Jun 24 06:14:36 PM PDT 24
Peak memory 208144 kb
Host smart-b212813b-a2e2-4b94-8328-869698de7e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923555858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.923555858
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1975271153
Short name T796
Test name
Test status
Simulation time 64522720 ps
CPU time 3.32 seconds
Started Jun 24 06:14:26 PM PDT 24
Finished Jun 24 06:14:31 PM PDT 24
Peak memory 207976 kb
Host smart-f38dbb5e-90ee-4fdd-bb76-abeb8b8da20f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975271153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1975271153
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3552984384
Short name T499
Test name
Test status
Simulation time 228011668 ps
CPU time 3.2 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:32 PM PDT 24
Peak memory 206960 kb
Host smart-d77ba9f6-1386-4013-90db-d8c401e4c3b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552984384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3552984384
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3501159368
Short name T695
Test name
Test status
Simulation time 1012483778 ps
CPU time 7.25 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:36 PM PDT 24
Peak memory 218412 kb
Host smart-d162bdcc-c59a-45ec-b24d-5fe36aa7d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501159368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3501159368
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.659387390
Short name T750
Test name
Test status
Simulation time 69687055 ps
CPU time 2.86 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:32 PM PDT 24
Peak memory 208352 kb
Host smart-9e61559e-9fe7-4ee8-9077-89f3db416370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659387390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.659387390
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.888053182
Short name T605
Test name
Test status
Simulation time 4788688168 ps
CPU time 26.23 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:55 PM PDT 24
Peak memory 220080 kb
Host smart-21bd1530-5e83-468a-8f63-21d26ab9236a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888053182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.888053182
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.855368551
Short name T821
Test name
Test status
Simulation time 156040416 ps
CPU time 6.04 seconds
Started Jun 24 06:14:31 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 208952 kb
Host smart-f1fb26cb-293c-472e-8a2e-7786175ad6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855368551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.855368551
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.141935460
Short name T706
Test name
Test status
Simulation time 55435776 ps
CPU time 1.4 seconds
Started Jun 24 06:14:26 PM PDT 24
Finished Jun 24 06:14:28 PM PDT 24
Peak memory 209820 kb
Host smart-9684f862-a023-4387-aed7-d245e1b8aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141935460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.141935460
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.549909867
Short name T843
Test name
Test status
Simulation time 11160611 ps
CPU time 0.78 seconds
Started Jun 24 06:14:42 PM PDT 24
Finished Jun 24 06:14:43 PM PDT 24
Peak memory 205840 kb
Host smart-2a5c96d6-d6e2-4629-bff6-50be385ce178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549909867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.549909867
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4023743810
Short name T725
Test name
Test status
Simulation time 520095783 ps
CPU time 5.26 seconds
Started Jun 24 06:14:27 PM PDT 24
Finished Jun 24 06:14:33 PM PDT 24
Peak memory 207696 kb
Host smart-4b76eae5-6149-4c05-8a8c-3837dea7f91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023743810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4023743810
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1475871706
Short name T714
Test name
Test status
Simulation time 186831337 ps
CPU time 3.07 seconds
Started Jun 24 06:14:27 PM PDT 24
Finished Jun 24 06:14:31 PM PDT 24
Peak memory 214416 kb
Host smart-5f623ff1-fcd6-4288-bdc0-2543ffb095da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475871706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1475871706
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2127352566
Short name T884
Test name
Test status
Simulation time 165498425 ps
CPU time 2.8 seconds
Started Jun 24 06:14:29 PM PDT 24
Finished Jun 24 06:14:33 PM PDT 24
Peak memory 214256 kb
Host smart-d591d607-2f41-4f27-87f3-58fe9c717f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127352566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2127352566
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.110898713
Short name T660
Test name
Test status
Simulation time 415996111 ps
CPU time 4.47 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:33 PM PDT 24
Peak memory 220484 kb
Host smart-24514c13-9aff-4d6e-bd12-3b021dbdb724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110898713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.110898713
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1999757743
Short name T802
Test name
Test status
Simulation time 133121368 ps
CPU time 5.46 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:35 PM PDT 24
Peak memory 218404 kb
Host smart-c31ee623-9d16-4523-b222-4ee7e2cf32de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999757743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1999757743
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.502244927
Short name T326
Test name
Test status
Simulation time 349608199 ps
CPU time 3.9 seconds
Started Jun 24 06:14:31 PM PDT 24
Finished Jun 24 06:14:35 PM PDT 24
Peak memory 208704 kb
Host smart-1953b35a-083e-4f62-a3bb-16f598698d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502244927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.502244927
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.436526714
Short name T568
Test name
Test status
Simulation time 91806797 ps
CPU time 1.9 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:32 PM PDT 24
Peak memory 207028 kb
Host smart-4a29ee13-e12a-4a84-b87c-b0b0f8d1d98b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436526714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.436526714
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2064499350
Short name T805
Test name
Test status
Simulation time 628220885 ps
CPU time 6.92 seconds
Started Jun 24 06:14:27 PM PDT 24
Finished Jun 24 06:14:35 PM PDT 24
Peak memory 208152 kb
Host smart-d9399eac-4837-40af-a4e2-ee7824af7d8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064499350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2064499350
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2483576415
Short name T530
Test name
Test status
Simulation time 100027817 ps
CPU time 1.89 seconds
Started Jun 24 06:14:28 PM PDT 24
Finished Jun 24 06:14:31 PM PDT 24
Peak memory 206812 kb
Host smart-a5270b37-3329-4fcc-b2f3-2ccdb3d08866
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483576415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2483576415
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1001573130
Short name T823
Test name
Test status
Simulation time 496908945 ps
CPU time 5.57 seconds
Started Jun 24 06:14:32 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 208876 kb
Host smart-d5b27851-efcc-48ce-a16f-f218d9938aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001573130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1001573130
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1071500363
Short name T107
Test name
Test status
Simulation time 782911905 ps
CPU time 4.49 seconds
Started Jun 24 06:14:32 PM PDT 24
Finished Jun 24 06:14:37 PM PDT 24
Peak memory 207108 kb
Host smart-281babf4-3948-4cd7-b632-f7f716c3ea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071500363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1071500363
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2464744094
Short name T28
Test name
Test status
Simulation time 923106928 ps
CPU time 10.12 seconds
Started Jun 24 06:14:27 PM PDT 24
Finished Jun 24 06:14:39 PM PDT 24
Peak memory 207476 kb
Host smart-eb10cf4e-d93d-4e8f-8d1a-6f9e4c9dabc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464744094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2464744094
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4049292751
Short name T169
Test name
Test status
Simulation time 54094754 ps
CPU time 1.89 seconds
Started Jun 24 06:14:35 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 209612 kb
Host smart-f67ff380-cd2c-4fa2-8aeb-30bf855724b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049292751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4049292751
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.470711153
Short name T183
Test name
Test status
Simulation time 47570776 ps
CPU time 0.78 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:37 PM PDT 24
Peak memory 205936 kb
Host smart-614c4b23-6912-402a-85b4-dee8884705f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470711153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.470711153
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.45454197
Short name T646
Test name
Test status
Simulation time 581954624 ps
CPU time 5.47 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:45 PM PDT 24
Peak memory 222756 kb
Host smart-80853478-a73b-4f61-9dd5-f6f49562be05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45454197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.45454197
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2043325171
Short name T687
Test name
Test status
Simulation time 110552396 ps
CPU time 3.66 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 209252 kb
Host smart-3693b735-59a7-43e2-a19f-e69a726252f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043325171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2043325171
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4062150621
Short name T340
Test name
Test status
Simulation time 479459863 ps
CPU time 3.64 seconds
Started Jun 24 06:14:35 PM PDT 24
Finished Jun 24 06:14:40 PM PDT 24
Peak memory 214316 kb
Host smart-5273774c-8205-46ee-a31e-7b57d35c0b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062150621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4062150621
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.513056343
Short name T873
Test name
Test status
Simulation time 83180278 ps
CPU time 3.95 seconds
Started Jun 24 06:14:37 PM PDT 24
Finished Jun 24 06:14:42 PM PDT 24
Peak memory 214236 kb
Host smart-514ac883-7269-4f21-827d-74c44fc80a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513056343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.513056343
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2837781610
Short name T666
Test name
Test status
Simulation time 197181816 ps
CPU time 3 seconds
Started Jun 24 06:14:34 PM PDT 24
Finished Jun 24 06:14:37 PM PDT 24
Peak memory 210560 kb
Host smart-c2c323fb-b38b-4597-9b43-097b9f2c90fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837781610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2837781610
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2642685993
Short name T302
Test name
Test status
Simulation time 57597963 ps
CPU time 3.51 seconds
Started Jun 24 06:14:41 PM PDT 24
Finished Jun 24 06:14:46 PM PDT 24
Peak memory 207496 kb
Host smart-4f9785fb-c978-47fd-a9ba-794cba463ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642685993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2642685993
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2493192920
Short name T263
Test name
Test status
Simulation time 789930457 ps
CPU time 18.2 seconds
Started Jun 24 06:14:43 PM PDT 24
Finished Jun 24 06:15:02 PM PDT 24
Peak memory 208868 kb
Host smart-ab8a9ddd-8ac1-4a93-b8cd-7a73e9ebe9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493192920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2493192920
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3892930809
Short name T590
Test name
Test status
Simulation time 343078774 ps
CPU time 5.56 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:43 PM PDT 24
Peak memory 208072 kb
Host smart-61c2ec3b-2427-4b1e-8625-bd33ce432cdb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892930809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3892930809
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2255529164
Short name T448
Test name
Test status
Simulation time 62585855 ps
CPU time 2.38 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:42 PM PDT 24
Peak memory 206916 kb
Host smart-eb7fb3f1-874a-462f-ade1-14309186b933
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255529164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2255529164
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2165223900
Short name T385
Test name
Test status
Simulation time 975018282 ps
CPU time 7.85 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:45 PM PDT 24
Peak memory 208764 kb
Host smart-1fae0d14-fe71-4de9-b5ba-5e5b05a8b92c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165223900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2165223900
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2406732857
Short name T713
Test name
Test status
Simulation time 904254887 ps
CPU time 9.43 seconds
Started Jun 24 06:14:35 PM PDT 24
Finished Jun 24 06:14:46 PM PDT 24
Peak memory 208508 kb
Host smart-1da88f90-23de-40aa-bdc9-c6599550b6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406732857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2406732857
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2289787244
Short name T576
Test name
Test status
Simulation time 111866387 ps
CPU time 3.91 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 208512 kb
Host smart-5dc446c3-babb-439c-9933-9d1803b8ea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289787244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2289787244
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3678813293
Short name T771
Test name
Test status
Simulation time 308143365 ps
CPU time 17.05 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:57 PM PDT 24
Peak memory 216648 kb
Host smart-6e4409c3-85a3-4c45-9632-f1b6892af5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678813293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3678813293
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3496909485
Short name T674
Test name
Test status
Simulation time 14238739 ps
CPU time 0.77 seconds
Started Jun 24 06:14:34 PM PDT 24
Finished Jun 24 06:14:35 PM PDT 24
Peak memory 205920 kb
Host smart-38f171c2-d2a7-4d9e-958e-35d1903c96c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496909485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3496909485
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.508467793
Short name T632
Test name
Test status
Simulation time 122940729 ps
CPU time 3.78 seconds
Started Jun 24 06:14:39 PM PDT 24
Finished Jun 24 06:14:43 PM PDT 24
Peak memory 214380 kb
Host smart-79866e09-b079-4bae-ad45-ca858c7f8233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508467793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.508467793
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2340776154
Short name T269
Test name
Test status
Simulation time 154554946 ps
CPU time 2.68 seconds
Started Jun 24 06:14:37 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 214280 kb
Host smart-04bae2c4-5f4b-4882-944c-f0a8eb0ecb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340776154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2340776154
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.823151024
Short name T822
Test name
Test status
Simulation time 210093545 ps
CPU time 4.79 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:44 PM PDT 24
Peak memory 222384 kb
Host smart-3ee5760e-d1ea-486e-8939-57c1e86fb58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823151024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.823151024
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1916362875
Short name T229
Test name
Test status
Simulation time 109135993 ps
CPU time 2.52 seconds
Started Jun 24 06:14:43 PM PDT 24
Finished Jun 24 06:14:46 PM PDT 24
Peak memory 220332 kb
Host smart-42539dc7-f724-4870-94e8-fa8f6878fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916362875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1916362875
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.31331360
Short name T558
Test name
Test status
Simulation time 523368463 ps
CPU time 10.76 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:50 PM PDT 24
Peak memory 214304 kb
Host smart-3e5da317-e039-4f31-8616-9e49cbeaf644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31331360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.31331360
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2684529105
Short name T497
Test name
Test status
Simulation time 567029382 ps
CPU time 2.97 seconds
Started Jun 24 06:14:37 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 207312 kb
Host smart-f1b4617d-62fe-4151-ac18-a531dabaa2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684529105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2684529105
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.269036900
Short name T312
Test name
Test status
Simulation time 1446334552 ps
CPU time 4.18 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:14:42 PM PDT 24
Peak memory 208804 kb
Host smart-584f5513-4829-464c-a7a5-81caadd1de1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269036900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.269036900
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3770910477
Short name T472
Test name
Test status
Simulation time 52381247 ps
CPU time 2.71 seconds
Started Jun 24 06:14:35 PM PDT 24
Finished Jun 24 06:14:39 PM PDT 24
Peak memory 208752 kb
Host smart-8454ad0c-3ccb-47aa-8015-251667f1e3f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770910477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3770910477
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3181554950
Short name T672
Test name
Test status
Simulation time 183082091 ps
CPU time 2.59 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:42 PM PDT 24
Peak memory 206992 kb
Host smart-cc312025-c373-4d64-a518-ea0a54aa2bb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181554950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3181554950
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1247940203
Short name T18
Test name
Test status
Simulation time 356972053 ps
CPU time 3.82 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:43 PM PDT 24
Peak memory 206896 kb
Host smart-2f3dafaa-e26b-4528-b7b2-de57b5d1ea6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247940203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1247940203
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1850576242
Short name T865
Test name
Test status
Simulation time 872931630 ps
CPU time 16.5 seconds
Started Jun 24 06:14:41 PM PDT 24
Finished Jun 24 06:14:59 PM PDT 24
Peak memory 208752 kb
Host smart-3517cf28-a725-451f-b45b-fb73b71c9d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850576242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1850576242
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2273384472
Short name T164
Test name
Test status
Simulation time 83700463 ps
CPU time 2.66 seconds
Started Jun 24 06:14:35 PM PDT 24
Finished Jun 24 06:14:38 PM PDT 24
Peak memory 209900 kb
Host smart-5963cf2e-76e1-4e56-8f4e-4e21270637bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273384472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2273384472
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4153729889
Short name T565
Test name
Test status
Simulation time 16761596 ps
CPU time 0.73 seconds
Started Jun 24 06:14:56 PM PDT 24
Finished Jun 24 06:14:58 PM PDT 24
Peak memory 205936 kb
Host smart-af9292c6-24a3-416c-972e-3cf48ade85d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153729889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4153729889
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2059122067
Short name T370
Test name
Test status
Simulation time 38416705 ps
CPU time 3.05 seconds
Started Jun 24 06:14:46 PM PDT 24
Finished Jun 24 06:14:50 PM PDT 24
Peak memory 214308 kb
Host smart-4f963a74-1645-4f4f-a07e-f5d30615bdf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059122067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2059122067
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2747111398
Short name T789
Test name
Test status
Simulation time 70056834 ps
CPU time 3.19 seconds
Started Jun 24 06:14:47 PM PDT 24
Finished Jun 24 06:14:51 PM PDT 24
Peak memory 214288 kb
Host smart-f1623b2f-e74d-41f1-a58b-c05dae58625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747111398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2747111398
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2986572874
Short name T840
Test name
Test status
Simulation time 985247408 ps
CPU time 17.47 seconds
Started Jun 24 06:14:46 PM PDT 24
Finished Jun 24 06:15:04 PM PDT 24
Peak memory 214324 kb
Host smart-d52fba0a-5b44-449a-a2a0-a454d02bb5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986572874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2986572874
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3840251510
Short name T850
Test name
Test status
Simulation time 338068939 ps
CPU time 3.4 seconds
Started Jun 24 06:14:45 PM PDT 24
Finished Jun 24 06:14:49 PM PDT 24
Peak memory 214256 kb
Host smart-495011bf-7c4f-4839-8759-6fb86ae42949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840251510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3840251510
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.847497892
Short name T6
Test name
Test status
Simulation time 505670585 ps
CPU time 2.36 seconds
Started Jun 24 06:14:46 PM PDT 24
Finished Jun 24 06:14:49 PM PDT 24
Peak memory 209824 kb
Host smart-3ea9cccd-5432-4146-8e0a-3e0c78f86b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847497892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.847497892
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2812261536
Short name T613
Test name
Test status
Simulation time 240330216 ps
CPU time 8.24 seconds
Started Jun 24 06:14:34 PM PDT 24
Finished Jun 24 06:14:43 PM PDT 24
Peak memory 207184 kb
Host smart-ca72c032-0a67-4e44-b893-96b738056e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812261536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2812261536
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1701215428
Short name T645
Test name
Test status
Simulation time 5660704949 ps
CPU time 34.34 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 208816 kb
Host smart-77c034f2-281c-4f48-8921-eaee9982d8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701215428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1701215428
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.122627602
Short name T639
Test name
Test status
Simulation time 116804253 ps
CPU time 2.35 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 207020 kb
Host smart-4406886b-fabe-4930-b0fa-64b623ec34e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122627602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.122627602
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2452220345
Short name T495
Test name
Test status
Simulation time 6662580068 ps
CPU time 65.74 seconds
Started Jun 24 06:14:36 PM PDT 24
Finished Jun 24 06:15:42 PM PDT 24
Peak memory 208728 kb
Host smart-bd466b3f-a732-4ac9-8c03-9972f0cea672
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452220345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2452220345
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1858971367
Short name T684
Test name
Test status
Simulation time 1925362639 ps
CPU time 43.17 seconds
Started Jun 24 06:14:42 PM PDT 24
Finished Jun 24 06:15:26 PM PDT 24
Peak memory 207824 kb
Host smart-fff9b2c6-cfd5-4213-86ec-f644dc95b14d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858971367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1858971367
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2338757965
Short name T885
Test name
Test status
Simulation time 285781221 ps
CPU time 2.05 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:14:58 PM PDT 24
Peak memory 206900 kb
Host smart-154656d5-6b1a-486c-8749-2e716f73e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338757965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2338757965
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.655098555
Short name T438
Test name
Test status
Simulation time 80801707 ps
CPU time 1.82 seconds
Started Jun 24 06:14:38 PM PDT 24
Finished Jun 24 06:14:41 PM PDT 24
Peak memory 208636 kb
Host smart-81e5e40d-9646-4821-a174-b79ea3601d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655098555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.655098555
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3519435403
Short name T769
Test name
Test status
Simulation time 1071107687 ps
CPU time 17.48 seconds
Started Jun 24 06:15:03 PM PDT 24
Finished Jun 24 06:15:22 PM PDT 24
Peak memory 215340 kb
Host smart-af9e135e-66f6-45f9-99f4-65b56da9b179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519435403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3519435403
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3076488828
Short name T103
Test name
Test status
Simulation time 33670409 ps
CPU time 2.44 seconds
Started Jun 24 06:14:44 PM PDT 24
Finished Jun 24 06:14:47 PM PDT 24
Peak memory 207468 kb
Host smart-1b81ee86-d682-4381-960d-33d77cfd00fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076488828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3076488828
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2763521015
Short name T134
Test name
Test status
Simulation time 104939875 ps
CPU time 1.56 seconds
Started Jun 24 06:14:54 PM PDT 24
Finished Jun 24 06:14:57 PM PDT 24
Peak memory 209796 kb
Host smart-b2f10a5b-1097-4c7f-ae75-adc70d7f66f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763521015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2763521015
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.904582556
Short name T494
Test name
Test status
Simulation time 37612741 ps
CPU time 0.91 seconds
Started Jun 24 06:14:56 PM PDT 24
Finished Jun 24 06:14:59 PM PDT 24
Peak memory 205932 kb
Host smart-1ea58d5b-5e44-49bf-a006-1bc24ed8fe3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904582556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.904582556
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4014652943
Short name T185
Test name
Test status
Simulation time 47508035 ps
CPU time 3.09 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 214516 kb
Host smart-fee11594-fe29-41d8-9bcb-1624f4502c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014652943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4014652943
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2536525581
Short name T719
Test name
Test status
Simulation time 136775969 ps
CPU time 1.72 seconds
Started Jun 24 06:14:53 PM PDT 24
Finished Jun 24 06:14:56 PM PDT 24
Peak memory 207588 kb
Host smart-776924fe-0096-41d4-9a76-2bc6c8b82c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536525581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2536525581
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4238923302
Short name T97
Test name
Test status
Simulation time 717030923 ps
CPU time 4.91 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:02 PM PDT 24
Peak memory 208808 kb
Host smart-bdffad1e-d124-47cf-a114-34dc9914d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238923302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4238923302
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3305364174
Short name T559
Test name
Test status
Simulation time 359683161 ps
CPU time 2.76 seconds
Started Jun 24 06:14:53 PM PDT 24
Finished Jun 24 06:14:57 PM PDT 24
Peak memory 209980 kb
Host smart-771a355b-a70d-4adf-9dce-84bc39d736dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305364174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3305364174
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2766480736
Short name T216
Test name
Test status
Simulation time 123461222 ps
CPU time 5.78 seconds
Started Jun 24 06:14:57 PM PDT 24
Finished Jun 24 06:15:05 PM PDT 24
Peak memory 214336 kb
Host smart-45dd790d-58b7-4fda-98b8-2ad7379ae5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766480736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2766480736
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1530901348
Short name T561
Test name
Test status
Simulation time 1382329279 ps
CPU time 12.65 seconds
Started Jun 24 06:14:57 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 208264 kb
Host smart-8fe4c94f-d169-4d57-ad32-cc8dd88563f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530901348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1530901348
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.994558103
Short name T738
Test name
Test status
Simulation time 159831747 ps
CPU time 4.52 seconds
Started Jun 24 06:14:54 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 207828 kb
Host smart-fc1a3d19-c838-4847-ac3b-3ab0b652e94e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994558103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.994558103
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1985520360
Short name T742
Test name
Test status
Simulation time 496557637 ps
CPU time 11.15 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:07 PM PDT 24
Peak memory 208008 kb
Host smart-7db3e832-1ad8-4ea1-9e11-4632048763f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985520360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1985520360
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.46993072
Short name T593
Test name
Test status
Simulation time 2196908637 ps
CPU time 16.79 seconds
Started Jun 24 06:14:57 PM PDT 24
Finished Jun 24 06:15:16 PM PDT 24
Peak memory 209076 kb
Host smart-666fa534-9be6-4ff8-9f82-c6dc6c9d1ac6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46993072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.46993072
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1052324768
Short name T897
Test name
Test status
Simulation time 121082321 ps
CPU time 4.49 seconds
Started Jun 24 06:14:54 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 209704 kb
Host smart-2908fbce-6590-4ddf-b744-9e23ce00df01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052324768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1052324768
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2588055181
Short name T531
Test name
Test status
Simulation time 1816544709 ps
CPU time 4.11 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 207896 kb
Host smart-a5f3b699-aa42-493d-b068-a23d462a35dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588055181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2588055181
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.4069194525
Short name T223
Test name
Test status
Simulation time 4342287286 ps
CPU time 41.73 seconds
Started Jun 24 06:14:57 PM PDT 24
Finished Jun 24 06:15:41 PM PDT 24
Peak memory 216092 kb
Host smart-ef26fe0f-639f-4506-9646-509af617a8e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069194525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.4069194525
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3519103258
Short name T498
Test name
Test status
Simulation time 100498538 ps
CPU time 4.69 seconds
Started Jun 24 06:14:59 PM PDT 24
Finished Jun 24 06:15:04 PM PDT 24
Peak memory 209620 kb
Host smart-0d5bd342-b335-436e-9b7b-f974a389e0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519103258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3519103258
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.566407035
Short name T43
Test name
Test status
Simulation time 1342014296 ps
CPU time 2.09 seconds
Started Jun 24 06:14:57 PM PDT 24
Finished Jun 24 06:15:01 PM PDT 24
Peak memory 209904 kb
Host smart-c60b5569-6fa5-4cbc-b07d-3ea0cd2b21ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566407035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.566407035
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1663504864
Short name T436
Test name
Test status
Simulation time 61540798 ps
CPU time 0.75 seconds
Started Jun 24 06:13:13 PM PDT 24
Finished Jun 24 06:13:15 PM PDT 24
Peak memory 205912 kb
Host smart-d36a2318-6cce-4ad9-88f8-cbf75a79d640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663504864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1663504864
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3167125548
Short name T184
Test name
Test status
Simulation time 308317641 ps
CPU time 4.51 seconds
Started Jun 24 06:13:04 PM PDT 24
Finished Jun 24 06:13:09 PM PDT 24
Peak memory 218468 kb
Host smart-f4ff3d78-3d72-4f7d-923c-bad6f155415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167125548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3167125548
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1038362912
Short name T187
Test name
Test status
Simulation time 44287884 ps
CPU time 1.82 seconds
Started Jun 24 06:13:03 PM PDT 24
Finished Jun 24 06:13:06 PM PDT 24
Peak memory 214260 kb
Host smart-c23a8369-06d9-424e-962b-96ca082c6911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038362912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1038362912
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2988267745
Short name T659
Test name
Test status
Simulation time 251471484 ps
CPU time 2.63 seconds
Started Jun 24 06:13:05 PM PDT 24
Finished Jun 24 06:13:08 PM PDT 24
Peak memory 220256 kb
Host smart-fb478eda-1b3d-4818-9e09-b749fdd5ca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988267745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2988267745
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.836366152
Short name T260
Test name
Test status
Simulation time 55084785 ps
CPU time 2.94 seconds
Started Jun 24 06:13:05 PM PDT 24
Finished Jun 24 06:13:08 PM PDT 24
Peak memory 209124 kb
Host smart-a9b83704-459c-42b2-b97a-d208a8340982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836366152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.836366152
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2105709231
Short name T11
Test name
Test status
Simulation time 1103477985 ps
CPU time 9.68 seconds
Started Jun 24 06:13:03 PM PDT 24
Finished Jun 24 06:13:13 PM PDT 24
Peak memory 233348 kb
Host smart-23c12ff0-cc79-4047-a133-1177657061eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105709231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2105709231
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.696705168
Short name T861
Test name
Test status
Simulation time 101071308 ps
CPU time 3.82 seconds
Started Jun 24 06:13:03 PM PDT 24
Finished Jun 24 06:13:07 PM PDT 24
Peak memory 208216 kb
Host smart-27510aa6-7bb8-44a5-ae5d-6fc1fa9adfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696705168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.696705168
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.797344424
Short name T462
Test name
Test status
Simulation time 289848299 ps
CPU time 8.28 seconds
Started Jun 24 06:13:02 PM PDT 24
Finished Jun 24 06:13:11 PM PDT 24
Peak memory 208176 kb
Host smart-ddc5190f-cd20-4a4c-a288-e3bd717310ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797344424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.797344424
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2441729429
Short name T434
Test name
Test status
Simulation time 152045937 ps
CPU time 4.35 seconds
Started Jun 24 06:13:04 PM PDT 24
Finished Jun 24 06:13:09 PM PDT 24
Peak memory 208712 kb
Host smart-c1562ccd-4599-450c-b82d-4e595adb98e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441729429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2441729429
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4283218809
Short name T456
Test name
Test status
Simulation time 112589140 ps
CPU time 2.71 seconds
Started Jun 24 06:13:04 PM PDT 24
Finished Jun 24 06:13:07 PM PDT 24
Peak memory 207020 kb
Host smart-b47c076c-864a-4e84-828e-fe7be900a8f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283218809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4283218809
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.477950380
Short name T830
Test name
Test status
Simulation time 39402982 ps
CPU time 2 seconds
Started Jun 24 06:13:04 PM PDT 24
Finished Jun 24 06:13:07 PM PDT 24
Peak memory 208552 kb
Host smart-931a7f0d-1e6a-4f53-937c-9b1dbed20d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477950380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.477950380
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4030965516
Short name T205
Test name
Test status
Simulation time 2325500464 ps
CPU time 3.73 seconds
Started Jun 24 06:12:55 PM PDT 24
Finished Jun 24 06:12:59 PM PDT 24
Peak memory 207640 kb
Host smart-7416fc5c-4c9f-4e3c-9456-a38e021c2d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030965516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4030965516
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.176627695
Short name T325
Test name
Test status
Simulation time 280895405 ps
CPU time 6.32 seconds
Started Jun 24 06:13:04 PM PDT 24
Finished Jun 24 06:13:11 PM PDT 24
Peak memory 214264 kb
Host smart-5be7fb2d-77a2-4f79-baf5-be9ad2de9ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176627695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.176627695
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1050422423
Short name T833
Test name
Test status
Simulation time 10710678 ps
CPU time 0.78 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:10 PM PDT 24
Peak memory 205920 kb
Host smart-97358e7d-6aaf-4465-a090-4f25cf709202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050422423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1050422423
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3466536733
Short name T273
Test name
Test status
Simulation time 216568888 ps
CPU time 4.24 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 215824 kb
Host smart-6589608d-adac-462b-8c8b-2bf6b9584b7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466536733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3466536733
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2089570466
Short name T42
Test name
Test status
Simulation time 74227071 ps
CPU time 2.88 seconds
Started Jun 24 06:14:54 PM PDT 24
Finished Jun 24 06:14:59 PM PDT 24
Peak memory 209616 kb
Host smart-b165fa95-0434-48e8-b596-a56fcc36e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089570466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2089570466
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3159137735
Short name T297
Test name
Test status
Simulation time 1921180844 ps
CPU time 30.44 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:27 PM PDT 24
Peak memory 214300 kb
Host smart-268acbd3-dd91-4aef-bece-bf3c63a9ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159137735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3159137735
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2317900388
Short name T341
Test name
Test status
Simulation time 340984162 ps
CPU time 3.73 seconds
Started Jun 24 06:15:03 PM PDT 24
Finished Jun 24 06:15:07 PM PDT 24
Peak memory 214312 kb
Host smart-a5a4cbfd-08df-4438-8c3f-5b14a498ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317900388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2317900388
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2276769789
Short name T705
Test name
Test status
Simulation time 232530380 ps
CPU time 5.21 seconds
Started Jun 24 06:15:03 PM PDT 24
Finished Jun 24 06:15:09 PM PDT 24
Peak memory 210220 kb
Host smart-0ed9b854-8185-426d-8c82-21b1ada11cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276769789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2276769789
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3004659538
Short name T275
Test name
Test status
Simulation time 50492365 ps
CPU time 2.88 seconds
Started Jun 24 06:15:02 PM PDT 24
Finished Jun 24 06:15:06 PM PDT 24
Peak memory 206776 kb
Host smart-0d5d3561-2f7e-47ea-8a70-f2f3728cc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004659538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3004659538
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2045055843
Short name T505
Test name
Test status
Simulation time 2454681585 ps
CPU time 16.13 seconds
Started Jun 24 06:15:02 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 208088 kb
Host smart-9f9e9b73-86bd-49a3-93eb-49ca833a5bb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045055843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2045055843
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1803825348
Short name T350
Test name
Test status
Simulation time 122002025 ps
CPU time 2.21 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:14:59 PM PDT 24
Peak memory 208820 kb
Host smart-0f3daf3c-7889-4cad-8011-853fe41cf576
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803825348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1803825348
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1084707784
Short name T431
Test name
Test status
Simulation time 322855520 ps
CPU time 3.24 seconds
Started Jun 24 06:14:58 PM PDT 24
Finished Jun 24 06:15:03 PM PDT 24
Peak memory 209748 kb
Host smart-c9bfb9a3-1212-47be-8940-0a9d8204cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084707784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1084707784
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2736802150
Short name T389
Test name
Test status
Simulation time 27635351 ps
CPU time 1.86 seconds
Started Jun 24 06:14:56 PM PDT 24
Finished Jun 24 06:15:00 PM PDT 24
Peak memory 206880 kb
Host smart-90560908-417f-46ee-b509-f37087f3a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736802150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2736802150
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3717491149
Short name T77
Test name
Test status
Simulation time 994478960 ps
CPU time 37.16 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 219704 kb
Host smart-fc38e07e-513f-48a7-903f-b64ad2ad0454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717491149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3717491149
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2644280673
Short name T803
Test name
Test status
Simulation time 506664987 ps
CPU time 19.54 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:28 PM PDT 24
Peak memory 221340 kb
Host smart-771e76bb-23a2-468d-b644-672d597b7421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644280673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2644280673
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1441351732
Short name T688
Test name
Test status
Simulation time 3731170661 ps
CPU time 17.72 seconds
Started Jun 24 06:14:55 PM PDT 24
Finished Jun 24 06:15:14 PM PDT 24
Peak memory 209684 kb
Host smart-de4dad27-2ad1-4a3f-845a-fb5ab6679a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441351732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1441351732
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1037937238
Short name T831
Test name
Test status
Simulation time 112776127 ps
CPU time 1.49 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 209972 kb
Host smart-6e3cfe48-a0da-4b70-88ca-368254011c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037937238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1037937238
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.267160254
Short name T101
Test name
Test status
Simulation time 26156032 ps
CPU time 0.76 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 205936 kb
Host smart-edcec1e8-1a5e-4ea5-9826-1a56f88997d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267160254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.267160254
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.839781716
Short name T31
Test name
Test status
Simulation time 173726005 ps
CPU time 3.61 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:10 PM PDT 24
Peak memory 210456 kb
Host smart-5ecef129-f43c-42fe-8973-ae7f942ceb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839781716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.839781716
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2313457989
Short name T722
Test name
Test status
Simulation time 318993325 ps
CPU time 7.88 seconds
Started Jun 24 06:15:11 PM PDT 24
Finished Jun 24 06:15:20 PM PDT 24
Peak memory 209444 kb
Host smart-f5dca8ff-f54c-4543-8d94-fa2089a42863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313457989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2313457989
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2556418420
Short name T293
Test name
Test status
Simulation time 91550131 ps
CPU time 2.92 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:09 PM PDT 24
Peak memory 214300 kb
Host smart-ef8812ad-22f8-4faa-979c-4fb57ac843ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556418420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2556418420
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2464119518
Short name T291
Test name
Test status
Simulation time 233194377 ps
CPU time 5.66 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 222396 kb
Host smart-0c7c17a2-dd0f-45a3-9de3-c5a83dbc46b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464119518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2464119518
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3269367934
Short name T650
Test name
Test status
Simulation time 113827301 ps
CPU time 2.35 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 220072 kb
Host smart-ae8070f2-7bb8-41ee-aea1-750300a59078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269367934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3269367934
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2004397536
Short name T633
Test name
Test status
Simulation time 1874563424 ps
CPU time 53.46 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:16:03 PM PDT 24
Peak memory 209308 kb
Host smart-87ca0161-1394-4171-9a63-3d6726b58737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004397536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2004397536
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4036146600
Short name T842
Test name
Test status
Simulation time 188924322 ps
CPU time 6.43 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:17 PM PDT 24
Peak memory 207976 kb
Host smart-542a9fdc-c68a-4453-b2df-b0cd4f42fe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036146600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4036146600
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2912022845
Short name T16
Test name
Test status
Simulation time 90639053 ps
CPU time 4.46 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 209296 kb
Host smart-225e0068-ada8-4925-9126-93240d865548
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912022845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2912022845
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1700118122
Short name T671
Test name
Test status
Simulation time 59770855 ps
CPU time 2.36 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 207060 kb
Host smart-90f0efb8-d1e3-4f27-96f3-2a43477d8ce1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700118122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1700118122
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2149065169
Short name T484
Test name
Test status
Simulation time 379845827 ps
CPU time 5.71 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 208000 kb
Host smart-fd8d0e24-049e-4d7a-bd89-bdd72cb1202c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149065169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2149065169
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2188808847
Short name T493
Test name
Test status
Simulation time 48081252 ps
CPU time 1.79 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 215716 kb
Host smart-81093d9a-0b62-4976-830e-e79a42692d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188808847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2188808847
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3565701222
Short name T481
Test name
Test status
Simulation time 1336303709 ps
CPU time 20.42 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:28 PM PDT 24
Peak memory 208016 kb
Host smart-c618beda-3a0f-4ee2-b9c6-2ffb8c3daa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565701222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3565701222
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2744508184
Short name T359
Test name
Test status
Simulation time 554244306 ps
CPU time 13.84 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:22 PM PDT 24
Peak memory 222384 kb
Host smart-fef7b6ed-b2e7-495c-8e7e-adf0a8caa037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744508184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2744508184
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2883275699
Short name T112
Test name
Test status
Simulation time 727064427 ps
CPU time 25.62 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:35 PM PDT 24
Peak memory 222596 kb
Host smart-1f0123d8-c261-4803-b174-e39e0f051cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883275699 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2883275699
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3076079614
Short name T133
Test name
Test status
Simulation time 248884081 ps
CPU time 6.44 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:15 PM PDT 24
Peak memory 209364 kb
Host smart-e857d623-fc29-4b54-a309-d5da2a45fb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076079614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3076079614
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3421083749
Short name T60
Test name
Test status
Simulation time 25066768 ps
CPU time 1.6 seconds
Started Jun 24 06:15:10 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 209860 kb
Host smart-20da3bc9-3a51-469f-a4a7-28f5b653ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421083749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3421083749
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1090069207
Short name T788
Test name
Test status
Simulation time 21147922 ps
CPU time 0.8 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:08 PM PDT 24
Peak memory 205940 kb
Host smart-8adb1722-04eb-4994-88a1-a8cf1c45c1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090069207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1090069207
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.324640765
Short name T404
Test name
Test status
Simulation time 7337654323 ps
CPU time 57.41 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 214440 kb
Host smart-739b0c0a-a283-496a-b2f5-f5faad6f39e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324640765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.324640765
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.271059090
Short name T597
Test name
Test status
Simulation time 76332687 ps
CPU time 1.29 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:09 PM PDT 24
Peak memory 206924 kb
Host smart-5e599024-1cf3-4b92-b8a1-2b28ca5c87df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271059090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.271059090
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1909648537
Short name T255
Test name
Test status
Simulation time 113390267 ps
CPU time 2.44 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 214280 kb
Host smart-a7cef403-2861-427e-bcd3-fcfb80cbb346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909648537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1909648537
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3338611881
Short name T794
Test name
Test status
Simulation time 112147956 ps
CPU time 2.81 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:10 PM PDT 24
Peak memory 214248 kb
Host smart-4202ba68-e3c5-4588-8bef-e52f66b303e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338611881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3338611881
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.415665737
Short name T753
Test name
Test status
Simulation time 888575915 ps
CPU time 23.23 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:33 PM PDT 24
Peak memory 208248 kb
Host smart-9256e32d-19f4-4f9c-8fe0-ba396b4f432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415665737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.415665737
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.81219650
Short name T700
Test name
Test status
Simulation time 22249116 ps
CPU time 1.85 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 206824 kb
Host smart-277f8ca4-cb6e-4a7a-ad28-a8d260fac4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81219650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.81219650
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2435876122
Short name T685
Test name
Test status
Simulation time 5147988118 ps
CPU time 36.6 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 208324 kb
Host smart-1e9f37dc-cf59-4e36-82e1-daf29cb77e56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435876122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2435876122
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.201266235
Short name T562
Test name
Test status
Simulation time 75645061 ps
CPU time 3.2 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 208044 kb
Host smart-22dc8196-c2a8-469c-9eff-6a08b1f11676
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201266235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.201266235
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.933190406
Short name T799
Test name
Test status
Simulation time 170674239 ps
CPU time 3.29 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:10 PM PDT 24
Peak memory 206924 kb
Host smart-0328cb14-5f38-4cd4-8eeb-e8434ce475fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933190406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.933190406
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3686000887
Short name T398
Test name
Test status
Simulation time 31339174 ps
CPU time 2.25 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:09 PM PDT 24
Peak memory 208324 kb
Host smart-b91408f8-80db-45c1-bcf3-dd2ec645caf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686000887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3686000887
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4283235760
Short name T384
Test name
Test status
Simulation time 249151169 ps
CPU time 5.76 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 208408 kb
Host smart-42ca6538-19da-48e7-b807-180f06dd35c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283235760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4283235760
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1701265329
Short name T345
Test name
Test status
Simulation time 447041985 ps
CPU time 22.66 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 222432 kb
Host smart-d73fd0a1-65a9-4641-87a2-5bb6cdc5b0c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701265329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1701265329
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1466227442
Short name T182
Test name
Test status
Simulation time 419562866 ps
CPU time 6.95 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 222632 kb
Host smart-9ced4921-b912-44f8-93d6-6513ead7be55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466227442 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1466227442
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3463536812
Short name T585
Test name
Test status
Simulation time 744809144 ps
CPU time 9.15 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:16 PM PDT 24
Peak memory 207556 kb
Host smart-f3d655db-31dc-47f9-a37d-8bf8a6d75fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463536812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3463536812
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3527991371
Short name T375
Test name
Test status
Simulation time 63839659 ps
CPU time 1.93 seconds
Started Jun 24 06:15:10 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 210024 kb
Host smart-8cb442bf-5fae-49ab-aa98-9d53f2904cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527991371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3527991371
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2917799443
Short name T417
Test name
Test status
Simulation time 18303724 ps
CPU time 0.82 seconds
Started Jun 24 06:15:17 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 205920 kb
Host smart-39729c7a-bb08-4872-b898-bd6be1aaea9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917799443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2917799443
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3387822981
Short name T790
Test name
Test status
Simulation time 223467223 ps
CPU time 4.03 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 214520 kb
Host smart-f600c588-e086-41b3-a4c9-45a28c159464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387822981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3387822981
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.4272643170
Short name T763
Test name
Test status
Simulation time 237203031 ps
CPU time 2.91 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:20 PM PDT 24
Peak memory 222716 kb
Host smart-d6d15927-676f-42a2-b1cb-3cf8f241f805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272643170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.4272643170
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1891132727
Short name T477
Test name
Test status
Simulation time 59285760 ps
CPU time 2.98 seconds
Started Jun 24 06:15:04 PM PDT 24
Finished Jun 24 06:15:08 PM PDT 24
Peak memory 214224 kb
Host smart-daf688cc-9ad6-42c8-af24-b869dcbd6af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891132727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1891132727
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2869028135
Short name T721
Test name
Test status
Simulation time 31890245 ps
CPU time 2.57 seconds
Started Jun 24 06:15:05 PM PDT 24
Finished Jun 24 06:15:09 PM PDT 24
Peak memory 214380 kb
Host smart-7195ae59-2c26-4881-9754-8964b63dc3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869028135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2869028135
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3756903991
Short name T317
Test name
Test status
Simulation time 444897144 ps
CPU time 3.22 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:11 PM PDT 24
Peak memory 214260 kb
Host smart-53613e7b-d3dd-47ff-971a-3ee84c2b1de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756903991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3756903991
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4122193330
Short name T475
Test name
Test status
Simulation time 173663167 ps
CPU time 4.14 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:14 PM PDT 24
Peak memory 214412 kb
Host smart-50dcc79f-bdd9-48e5-a6df-e0a9cdb2f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122193330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4122193330
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1685822923
Short name T360
Test name
Test status
Simulation time 116196654 ps
CPU time 4.53 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 218148 kb
Host smart-5937562c-91e7-460b-98f7-62012cc31b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685822923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1685822923
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1758191564
Short name T732
Test name
Test status
Simulation time 127997343 ps
CPU time 2.47 seconds
Started Jun 24 06:15:08 PM PDT 24
Finished Jun 24 06:15:13 PM PDT 24
Peak memory 207360 kb
Host smart-b4401316-38e5-4a48-a7fa-1da2a622a96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758191564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1758191564
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.568395853
Short name T820
Test name
Test status
Simulation time 80545412 ps
CPU time 3.69 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:12 PM PDT 24
Peak memory 206864 kb
Host smart-6ef96451-162d-42bf-89e4-6b2e95ad2a56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568395853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.568395853
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3315314960
Short name T733
Test name
Test status
Simulation time 74703858 ps
CPU time 2.32 seconds
Started Jun 24 06:15:06 PM PDT 24
Finished Jun 24 06:15:09 PM PDT 24
Peak memory 206844 kb
Host smart-45ee382d-e455-4757-92ff-d5d83c380c77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315314960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3315314960
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3585093552
Short name T502
Test name
Test status
Simulation time 605160768 ps
CPU time 5.5 seconds
Started Jun 24 06:15:07 PM PDT 24
Finished Jun 24 06:15:14 PM PDT 24
Peak memory 208664 kb
Host smart-e8a7c13f-72aa-401c-bd7e-afba55fdea5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585093552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3585093552
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2596217375
Short name T212
Test name
Test status
Simulation time 3983380553 ps
CPU time 24.95 seconds
Started Jun 24 06:15:20 PM PDT 24
Finished Jun 24 06:15:46 PM PDT 24
Peak memory 208536 kb
Host smart-760ec391-9f51-4ded-9765-7b4cc5b22a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596217375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2596217375
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2077562539
Short name T464
Test name
Test status
Simulation time 260117190 ps
CPU time 3.24 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:14 PM PDT 24
Peak memory 207340 kb
Host smart-41810653-c0d7-4b89-b5da-90e5ae6972ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077562539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2077562539
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2413661116
Short name T259
Test name
Test status
Simulation time 187114419 ps
CPU time 5.64 seconds
Started Jun 24 06:15:09 PM PDT 24
Finished Jun 24 06:15:16 PM PDT 24
Peak memory 209656 kb
Host smart-5a78e0a6-c16f-4ed3-b1f8-1dfa3eff9155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413661116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2413661116
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1155876776
Short name T614
Test name
Test status
Simulation time 51629479 ps
CPU time 2.65 seconds
Started Jun 24 06:15:14 PM PDT 24
Finished Jun 24 06:15:18 PM PDT 24
Peak memory 209904 kb
Host smart-64b69602-131d-4a63-9d99-2ea5fe109b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155876776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1155876776
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.538232726
Short name T415
Test name
Test status
Simulation time 17063828 ps
CPU time 0.89 seconds
Started Jun 24 06:15:17 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 206108 kb
Host smart-450d7263-afb7-4c50-b0ef-22ba5a6c583d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538232726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.538232726
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1811714034
Short name T394
Test name
Test status
Simulation time 448824168 ps
CPU time 6.82 seconds
Started Jun 24 06:15:15 PM PDT 24
Finished Jun 24 06:15:23 PM PDT 24
Peak memory 214316 kb
Host smart-c376266b-7a8c-466b-87bc-455834c13fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811714034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1811714034
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2787068057
Short name T10
Test name
Test status
Simulation time 385091055 ps
CPU time 3.47 seconds
Started Jun 24 06:15:14 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 222860 kb
Host smart-c668ab96-47ea-4ede-bb97-a7b92dbbd173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787068057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2787068057
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3286457911
Short name T904
Test name
Test status
Simulation time 54911755 ps
CPU time 1.53 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:22 PM PDT 24
Peak memory 207516 kb
Host smart-9b668e61-f762-4f40-b9ab-4a741a55b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286457911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3286457911
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.271095052
Short name T757
Test name
Test status
Simulation time 118405407 ps
CPU time 2.09 seconds
Started Jun 24 06:15:18 PM PDT 24
Finished Jun 24 06:15:22 PM PDT 24
Peak memory 214760 kb
Host smart-3812cf20-5e20-4692-8aea-ddc5e6c12223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271095052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.271095052
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2689235708
Short name T509
Test name
Test status
Simulation time 54227713 ps
CPU time 3.37 seconds
Started Jun 24 06:15:14 PM PDT 24
Finished Jun 24 06:15:18 PM PDT 24
Peak memory 208980 kb
Host smart-ac364081-01fc-46ef-a10e-e96819375b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689235708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2689235708
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3170574042
Short name T17
Test name
Test status
Simulation time 289122667 ps
CPU time 4.03 seconds
Started Jun 24 06:15:15 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 209428 kb
Host smart-8a6a63fe-607f-42ba-9989-ee2970dbe161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170574042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3170574042
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3861870034
Short name T433
Test name
Test status
Simulation time 236287957 ps
CPU time 6.6 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:24 PM PDT 24
Peak memory 207872 kb
Host smart-5d02d34b-31a4-4c9f-9287-751f4cb3dad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861870034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3861870034
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4209862223
Short name T651
Test name
Test status
Simulation time 397034994 ps
CPU time 7.14 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:24 PM PDT 24
Peak memory 207988 kb
Host smart-9a58082d-1770-4bad-a342-3991ab54e3de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209862223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4209862223
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3969168455
Short name T280
Test name
Test status
Simulation time 77478900 ps
CPU time 3.15 seconds
Started Jun 24 06:15:17 PM PDT 24
Finished Jun 24 06:15:22 PM PDT 24
Peak memory 208528 kb
Host smart-05ca5009-ea97-4bda-b791-ed10ef8f48f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969168455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3969168455
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1812358795
Short name T787
Test name
Test status
Simulation time 36671868 ps
CPU time 2.44 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:20 PM PDT 24
Peak memory 206832 kb
Host smart-68fb604b-054f-4937-a2bf-e3354a0a203e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812358795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1812358795
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1605160125
Short name T200
Test name
Test status
Simulation time 824511584 ps
CPU time 16.23 seconds
Started Jun 24 06:15:20 PM PDT 24
Finished Jun 24 06:15:37 PM PDT 24
Peak memory 222456 kb
Host smart-318a31d4-d6c5-4a73-b567-ad97eaa6b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605160125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1605160125
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.31868972
Short name T408
Test name
Test status
Simulation time 192965219 ps
CPU time 4.05 seconds
Started Jun 24 06:15:15 PM PDT 24
Finished Jun 24 06:15:21 PM PDT 24
Peak memory 208408 kb
Host smart-13fdce46-556f-4a84-bb41-56dcbe7d2c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31868972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.31868972
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.874774219
Short name T129
Test name
Test status
Simulation time 246735137 ps
CPU time 11.77 seconds
Started Jun 24 06:15:14 PM PDT 24
Finished Jun 24 06:15:27 PM PDT 24
Peak memory 222524 kb
Host smart-be928792-5d6c-4de6-bb92-09a458cd5406
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874774219 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.874774219
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1515538289
Short name T440
Test name
Test status
Simulation time 327742312 ps
CPU time 7.85 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:25 PM PDT 24
Peak memory 209148 kb
Host smart-286721fa-1362-4231-b01c-9b661f1015ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515538289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1515538289
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1541542439
Short name T377
Test name
Test status
Simulation time 91624137 ps
CPU time 2.45 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:23 PM PDT 24
Peak memory 210160 kb
Host smart-7e848f97-eb7c-4c47-8b7e-8bf1d1e485ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541542439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1541542439
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1500607939
Short name T908
Test name
Test status
Simulation time 43579920 ps
CPU time 0.96 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:21 PM PDT 24
Peak memory 206064 kb
Host smart-cb572003-2612-4c94-a2a9-0334dcc3bfde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500607939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1500607939
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1920960030
Short name T272
Test name
Test status
Simulation time 228072778 ps
CPU time 6.65 seconds
Started Jun 24 06:15:20 PM PDT 24
Finished Jun 24 06:15:28 PM PDT 24
Peak memory 214472 kb
Host smart-2cea8345-4f53-4213-8d3c-8e0d3dbf43c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920960030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1920960030
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1892853321
Short name T41
Test name
Test status
Simulation time 2658957529 ps
CPU time 10.08 seconds
Started Jun 24 06:15:18 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 209868 kb
Host smart-67763a42-e5f6-4915-8803-99cc7c67ef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892853321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1892853321
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3948289883
Short name T813
Test name
Test status
Simulation time 96542885 ps
CPU time 3.19 seconds
Started Jun 24 06:15:18 PM PDT 24
Finished Jun 24 06:15:22 PM PDT 24
Peak memory 214296 kb
Host smart-d8dbd2c0-bd44-4d70-ac52-809472eae6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948289883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3948289883
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.587724337
Short name T287
Test name
Test status
Simulation time 49545696 ps
CPU time 2.65 seconds
Started Jun 24 06:15:12 PM PDT 24
Finished Jun 24 06:15:16 PM PDT 24
Peak memory 214292 kb
Host smart-1df269c0-3380-45f8-95d3-7c5ff613eb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587724337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.587724337
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.858887668
Short name T635
Test name
Test status
Simulation time 136457420 ps
CPU time 2.86 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:23 PM PDT 24
Peak memory 222000 kb
Host smart-c2532460-92e1-48b5-870f-b0d8244e4f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858887668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.858887668
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.271294228
Short name T323
Test name
Test status
Simulation time 151052809 ps
CPU time 3.08 seconds
Started Jun 24 06:15:15 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 210192 kb
Host smart-e2ee079c-7998-464a-8596-ef9400ca9c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271294228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.271294228
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.157885372
Short name T735
Test name
Test status
Simulation time 2212235356 ps
CPU time 15.31 seconds
Started Jun 24 06:15:14 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 209060 kb
Host smart-1f239bcc-65cb-46e5-83c1-aec4f25865fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157885372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.157885372
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2330960797
Short name T637
Test name
Test status
Simulation time 144491795 ps
CPU time 2.79 seconds
Started Jun 24 06:15:13 PM PDT 24
Finished Jun 24 06:15:17 PM PDT 24
Peak memory 206864 kb
Host smart-058905c8-e33d-4fd8-ba38-527f360fd010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330960797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2330960797
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2014562869
Short name T557
Test name
Test status
Simulation time 2596672097 ps
CPU time 47.59 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:16:05 PM PDT 24
Peak memory 208944 kb
Host smart-03c7133e-fa5c-4367-9d69-5af775323af0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014562869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2014562869
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3930848209
Short name T584
Test name
Test status
Simulation time 590208075 ps
CPU time 3.12 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:24 PM PDT 24
Peak memory 208632 kb
Host smart-eab9d6bf-fed3-4af2-b1ae-32e3350a831d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930848209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3930848209
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3154023953
Short name T647
Test name
Test status
Simulation time 338199928 ps
CPU time 5.03 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:26 PM PDT 24
Peak memory 208844 kb
Host smart-df5f19ce-44f7-4ef5-9cd9-70f79ccc67f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154023953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3154023953
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2147972843
Short name T295
Test name
Test status
Simulation time 287005054 ps
CPU time 7.01 seconds
Started Jun 24 06:15:17 PM PDT 24
Finished Jun 24 06:15:25 PM PDT 24
Peak memory 214332 kb
Host smart-e9d2b2eb-e8cf-45a1-93b5-232fb5c7495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147972843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2147972843
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3504693557
Short name T770
Test name
Test status
Simulation time 532319296 ps
CPU time 13.65 seconds
Started Jun 24 06:15:17 PM PDT 24
Finished Jun 24 06:15:32 PM PDT 24
Peak memory 208300 kb
Host smart-9c2857e7-0f91-41ba-bd46-8ad14a8ecd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504693557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3504693557
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2827280645
Short name T683
Test name
Test status
Simulation time 482145779 ps
CPU time 13.67 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 222680 kb
Host smart-9d7c5f20-c843-4955-b39a-d46823cb3f94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827280645 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2827280645
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1382183900
Short name T625
Test name
Test status
Simulation time 1200829704 ps
CPU time 8.5 seconds
Started Jun 24 06:15:15 PM PDT 24
Finished Jun 24 06:15:24 PM PDT 24
Peak memory 207736 kb
Host smart-5c3f2675-e5c7-44c2-8e9b-14720f6a39ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382183900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1382183900
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4287305830
Short name T547
Test name
Test status
Simulation time 55559955 ps
CPU time 2 seconds
Started Jun 24 06:15:16 PM PDT 24
Finished Jun 24 06:15:19 PM PDT 24
Peak memory 209728 kb
Host smart-3436dfce-1472-43e5-bf6b-1f84fe45e026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287305830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4287305830
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.62640236
Short name T676
Test name
Test status
Simulation time 15314240 ps
CPU time 0.91 seconds
Started Jun 24 06:15:29 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 206116 kb
Host smart-1eacd325-7e91-438a-a35e-94f2d34f0d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62640236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.62640236
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1370473373
Short name T390
Test name
Test status
Simulation time 2274817957 ps
CPU time 31.42 seconds
Started Jun 24 06:15:29 PM PDT 24
Finished Jun 24 06:16:01 PM PDT 24
Peak memory 214480 kb
Host smart-2072b0a2-1bc0-4ad9-babc-e8aa839d44cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370473373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1370473373
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1957396231
Short name T517
Test name
Test status
Simulation time 91791508 ps
CPU time 3.29 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 214592 kb
Host smart-a2de7d1c-6648-42c6-9cbc-2680af40be37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957396231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1957396231
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.257936431
Short name T762
Test name
Test status
Simulation time 386093402 ps
CPU time 4.54 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:37 PM PDT 24
Peak memory 209460 kb
Host smart-76118118-b4f4-4eb6-bb37-fc9d61a769ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257936431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.257936431
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3600139798
Short name T541
Test name
Test status
Simulation time 31785098 ps
CPU time 1.5 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 214168 kb
Host smart-cee81006-6387-45fa-bffd-289b1ae8bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600139798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3600139798
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3877522392
Short name T901
Test name
Test status
Simulation time 841687801 ps
CPU time 11.7 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 221740 kb
Host smart-74964365-cb1a-4e8b-959b-94f3e4c07cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877522392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3877522392
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4220165602
Short name T573
Test name
Test status
Simulation time 135405549 ps
CPU time 3.3 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:36 PM PDT 24
Peak memory 220200 kb
Host smart-fa429e69-52da-4cc3-935b-3b72ccd6c7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220165602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4220165602
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3397951042
Short name T881
Test name
Test status
Simulation time 62363614 ps
CPU time 3.34 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 207508 kb
Host smart-fa60e3d2-cd43-4bfc-bc74-3fd88ed25037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397951042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3397951042
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3221828815
Short name T242
Test name
Test status
Simulation time 140534170 ps
CPU time 3.49 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:23 PM PDT 24
Peak memory 206896 kb
Host smart-e8516a12-b4d7-4d4a-83b2-3e64bbf7f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221828815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3221828815
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1982710672
Short name T419
Test name
Test status
Simulation time 59980226 ps
CPU time 2.89 seconds
Started Jun 24 06:15:30 PM PDT 24
Finished Jun 24 06:15:34 PM PDT 24
Peak memory 207012 kb
Host smart-662e4e3c-65e3-4a40-8517-04b12071cacc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982710672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1982710672
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3755208511
Short name T812
Test name
Test status
Simulation time 408530095 ps
CPU time 7.46 seconds
Started Jun 24 06:15:18 PM PDT 24
Finished Jun 24 06:15:27 PM PDT 24
Peak memory 207084 kb
Host smart-ee9a85e3-44e9-48f4-b5e1-5d906a022b1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755208511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3755208511
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.702898522
Short name T388
Test name
Test status
Simulation time 28517502 ps
CPU time 2.14 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:28 PM PDT 24
Peak memory 208580 kb
Host smart-668c9dc3-59e0-4bf4-a4ed-dda105cbef27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702898522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.702898522
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2093002195
Short name T854
Test name
Test status
Simulation time 29582978 ps
CPU time 2.22 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:27 PM PDT 24
Peak memory 209412 kb
Host smart-a14f27f3-12e7-4ec6-86cf-2a4da7c7ac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093002195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2093002195
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3490647659
Short name T594
Test name
Test status
Simulation time 337921070 ps
CPU time 2.74 seconds
Started Jun 24 06:15:19 PM PDT 24
Finished Jun 24 06:15:23 PM PDT 24
Peak memory 206864 kb
Host smart-07e25eee-bf9b-44aa-b237-d6f311004a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490647659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3490647659
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.80262130
Short name T540
Test name
Test status
Simulation time 249325771 ps
CPU time 9.37 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:36 PM PDT 24
Peak memory 222496 kb
Host smart-df13f963-99f5-4e21-992a-a36d73fa2887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80262130 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.80262130
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.53291470
Short name T809
Test name
Test status
Simulation time 127470578 ps
CPU time 4.92 seconds
Started Jun 24 06:15:28 PM PDT 24
Finished Jun 24 06:15:34 PM PDT 24
Peak memory 208668 kb
Host smart-d6757346-acde-4d51-81da-b66b187f6c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53291470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.53291470
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1826481140
Short name T532
Test name
Test status
Simulation time 83138701 ps
CPU time 3 seconds
Started Jun 24 06:15:31 PM PDT 24
Finished Jun 24 06:15:35 PM PDT 24
Peak memory 210116 kb
Host smart-52a2ac6d-5201-4eed-ba6b-6284efc82799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826481140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1826481140
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2068121026
Short name T429
Test name
Test status
Simulation time 37509952 ps
CPU time 0.86 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 205916 kb
Host smart-aa9ff8d0-b2e5-4aa9-ab53-24698df62da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068121026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2068121026
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3933836904
Short name T406
Test name
Test status
Simulation time 327340202 ps
CPU time 4.85 seconds
Started Jun 24 06:15:23 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 215292 kb
Host smart-97a1484b-010c-4bc1-b6ed-e6a0572c6fac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933836904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3933836904
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3045426511
Short name T631
Test name
Test status
Simulation time 175967677 ps
CPU time 5.3 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 209512 kb
Host smart-5cd767a8-4171-48d0-bf54-392c52d77051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045426511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3045426511
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1390984242
Short name T882
Test name
Test status
Simulation time 278078388 ps
CPU time 2.52 seconds
Started Jun 24 06:15:28 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 218292 kb
Host smart-25f81438-8a20-4f46-83c4-0bfbd80ebc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390984242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1390984242
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4229991809
Short name T367
Test name
Test status
Simulation time 86861945 ps
CPU time 2.91 seconds
Started Jun 24 06:15:29 PM PDT 24
Finished Jun 24 06:15:33 PM PDT 24
Peak memory 214320 kb
Host smart-d5afc5dc-a059-44ea-8c79-2e5686821997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229991809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4229991809
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.352042735
Short name T696
Test name
Test status
Simulation time 247201478 ps
CPU time 4.59 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:33 PM PDT 24
Peak memory 214308 kb
Host smart-df656e5e-896b-4bd3-a72c-5314e49f0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352042735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.352042735
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3720399908
Short name T869
Test name
Test status
Simulation time 105763922 ps
CPU time 3.02 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 214396 kb
Host smart-273876f2-6e61-47d6-8237-fc35e96ac0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720399908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3720399908
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3287476525
Short name T387
Test name
Test status
Simulation time 458044855 ps
CPU time 5.02 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 209672 kb
Host smart-fda6119b-b163-4f19-9922-acf24b3a774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287476525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3287476525
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3444880951
Short name T411
Test name
Test status
Simulation time 191540025 ps
CPU time 2.78 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:28 PM PDT 24
Peak memory 207112 kb
Host smart-7c13ad52-d827-4341-97c0-c79a58e378fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444880951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3444880951
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2473802001
Short name T734
Test name
Test status
Simulation time 562204846 ps
CPU time 17.52 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:43 PM PDT 24
Peak memory 209052 kb
Host smart-b55e1d6d-bdeb-4a7f-bf7a-0bfd459ae10b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473802001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2473802001
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3092907342
Short name T810
Test name
Test status
Simulation time 150730498 ps
CPU time 2.37 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 206872 kb
Host smart-1ad67cb8-3efa-44a3-bf82-7cb88e491250
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092907342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3092907342
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1048111483
Short name T720
Test name
Test status
Simulation time 1863009212 ps
CPU time 24.79 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:50 PM PDT 24
Peak memory 208008 kb
Host smart-bac1b9d7-79a3-4dc7-9ee5-123bc6c7109a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048111483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1048111483
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1268388790
Short name T445
Test name
Test status
Simulation time 20957247 ps
CPU time 1.61 seconds
Started Jun 24 06:15:23 PM PDT 24
Finished Jun 24 06:15:26 PM PDT 24
Peak memory 207268 kb
Host smart-f99bd48f-9cde-429b-8087-838552899655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268388790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1268388790
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2583670826
Short name T413
Test name
Test status
Simulation time 654540689 ps
CPU time 4.15 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 207904 kb
Host smart-eb9c6ce6-c078-45d8-9e64-e58ce26950d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583670826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2583670826
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2881483245
Short name T862
Test name
Test status
Simulation time 678582293 ps
CPU time 13.5 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:40 PM PDT 24
Peak memory 222344 kb
Host smart-2ed97f0a-582f-4a78-86d3-c90a9e174dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881483245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2881483245
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1315150641
Short name T648
Test name
Test status
Simulation time 571483282 ps
CPU time 6.37 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:32 PM PDT 24
Peak memory 209500 kb
Host smart-b1b0b36e-b17d-4c20-9c41-26ed5097a590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315150641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1315150641
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.815528542
Short name T132
Test name
Test status
Simulation time 163149254 ps
CPU time 2.85 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 210388 kb
Host smart-7c9cce87-1306-4aff-bbdd-621d64c788a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815528542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.815528542
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2015352061
Short name T409
Test name
Test status
Simulation time 22710863 ps
CPU time 0.75 seconds
Started Jun 24 06:15:37 PM PDT 24
Finished Jun 24 06:15:39 PM PDT 24
Peak memory 205864 kb
Host smart-1e9d71b3-3cf1-41bf-9944-999155a34340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015352061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2015352061
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.73868018
Short name T284
Test name
Test status
Simulation time 9306259099 ps
CPU time 76.57 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:16:41 PM PDT 24
Peak memory 215464 kb
Host smart-f194b580-a59f-42f4-a127-76f76193471c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73868018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.73868018
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2394325220
Short name T580
Test name
Test status
Simulation time 214364644 ps
CPU time 3.69 seconds
Started Jun 24 06:15:29 PM PDT 24
Finished Jun 24 06:15:34 PM PDT 24
Peak memory 214696 kb
Host smart-6b452f61-a835-407b-aeda-9a9c0ff8b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394325220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2394325220
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.204754602
Short name T479
Test name
Test status
Simulation time 274643168 ps
CPU time 3.19 seconds
Started Jun 24 06:15:26 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 207628 kb
Host smart-0bdd5a87-f009-412b-9e73-6f01bc81d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204754602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.204754602
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1780280589
Short name T542
Test name
Test status
Simulation time 142142537 ps
CPU time 4.21 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:33 PM PDT 24
Peak memory 222392 kb
Host smart-0592fd1e-3d47-411f-aefa-a54559270803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780280589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1780280589
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1068588934
Short name T686
Test name
Test status
Simulation time 519715959 ps
CPU time 3.95 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 209864 kb
Host smart-98f0be7b-3dc9-444f-8d2a-cab5b3cfc0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068588934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1068588934
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1068155073
Short name T443
Test name
Test status
Simulation time 327285324 ps
CPU time 4.84 seconds
Started Jun 24 06:15:26 PM PDT 24
Finished Jun 24 06:15:32 PM PDT 24
Peak memory 207120 kb
Host smart-c31bbf6c-8517-4931-b793-125a3a1ab3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068155073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1068155073
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2903013379
Short name T491
Test name
Test status
Simulation time 181660326 ps
CPU time 2.67 seconds
Started Jun 24 06:15:27 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 206844 kb
Host smart-385cb315-1e21-4fc1-ba12-b6f324ab6583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903013379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2903013379
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1192735871
Short name T82
Test name
Test status
Simulation time 112031879 ps
CPU time 3.32 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:29 PM PDT 24
Peak memory 207956 kb
Host smart-c12eea2a-04ad-4f0b-8ac9-b6f542333aec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192735871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1192735871
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3708379345
Short name T615
Test name
Test status
Simulation time 242857166 ps
CPU time 4.1 seconds
Started Jun 24 06:15:25 PM PDT 24
Finished Jun 24 06:15:30 PM PDT 24
Peak memory 207028 kb
Host smart-d62d58b0-6b95-4c6c-b733-92c76b778598
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708379345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3708379345
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1031091252
Short name T868
Test name
Test status
Simulation time 357805006 ps
CPU time 3.19 seconds
Started Jun 24 06:15:29 PM PDT 24
Finished Jun 24 06:15:33 PM PDT 24
Peak memory 206788 kb
Host smart-d35be595-301e-4006-bde6-0fde6fb78a86
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031091252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1031091252
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.823510236
Short name T106
Test name
Test status
Simulation time 213067489 ps
CPU time 3.38 seconds
Started Jun 24 06:15:26 PM PDT 24
Finished Jun 24 06:15:31 PM PDT 24
Peak memory 218132 kb
Host smart-000712c8-826f-4a23-9130-21a524045464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823510236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.823510236
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1349172904
Short name T451
Test name
Test status
Simulation time 125424492 ps
CPU time 2.21 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:35 PM PDT 24
Peak memory 206828 kb
Host smart-cc550311-1cf6-4084-a0f1-6435cec98c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349172904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1349172904
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.582427365
Short name T54
Test name
Test status
Simulation time 2739773533 ps
CPU time 21.98 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 221108 kb
Host smart-69768672-b016-4c36-826f-1cd3bd38915b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582427365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.582427365
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2779578613
Short name T783
Test name
Test status
Simulation time 612521602 ps
CPU time 22.24 seconds
Started Jun 24 06:15:24 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 222616 kb
Host smart-116b1c83-6bbd-4402-9875-a9606584ca01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779578613 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2779578613
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1696442621
Short name T607
Test name
Test status
Simulation time 398993142 ps
CPU time 6.48 seconds
Started Jun 24 06:15:26 PM PDT 24
Finished Jun 24 06:15:33 PM PDT 24
Peak memory 214300 kb
Host smart-fc66ee8f-bf48-412e-86a4-1041a5dc4f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696442621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1696442621
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1174761513
Short name T204
Test name
Test status
Simulation time 302037715 ps
CPU time 3.06 seconds
Started Jun 24 06:15:22 PM PDT 24
Finished Jun 24 06:15:25 PM PDT 24
Peak memory 209864 kb
Host smart-0bf885ac-e68d-4caf-9bcf-06ce2081bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174761513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1174761513
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3768414096
Short name T851
Test name
Test status
Simulation time 30527600 ps
CPU time 0.78 seconds
Started Jun 24 06:15:44 PM PDT 24
Finished Jun 24 06:15:46 PM PDT 24
Peak memory 205928 kb
Host smart-0c594523-75e2-4280-847b-67780ea8836a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768414096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3768414096
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2397842378
Short name T32
Test name
Test status
Simulation time 73803169 ps
CPU time 2.95 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:36 PM PDT 24
Peak memory 220076 kb
Host smart-51914a20-f154-49de-877d-13e2ae8b68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397842378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2397842378
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.874846957
Short name T304
Test name
Test status
Simulation time 148841324 ps
CPU time 5.25 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:39 PM PDT 24
Peak memory 208816 kb
Host smart-09eb170d-47bb-418d-be2d-403b9573feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874846957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.874846957
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2764415850
Short name T692
Test name
Test status
Simulation time 163507796 ps
CPU time 5 seconds
Started Jun 24 06:15:34 PM PDT 24
Finished Jun 24 06:15:40 PM PDT 24
Peak memory 221348 kb
Host smart-86586142-23c8-4504-8852-b80357e2b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764415850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2764415850
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2842689466
Short name T601
Test name
Test status
Simulation time 331987666 ps
CPU time 2.88 seconds
Started Jun 24 06:15:31 PM PDT 24
Finished Jun 24 06:15:35 PM PDT 24
Peak memory 222476 kb
Host smart-a2d2730c-6760-4834-a4b5-e3125eacac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842689466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2842689466
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4006950126
Short name T334
Test name
Test status
Simulation time 311580789 ps
CPU time 5.82 seconds
Started Jun 24 06:15:38 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 207536 kb
Host smart-16b182b2-cba4-420c-8837-c5a85d0c9020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006950126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4006950126
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.4255240971
Short name T890
Test name
Test status
Simulation time 53459645 ps
CPU time 2.92 seconds
Started Jun 24 06:15:34 PM PDT 24
Finished Jun 24 06:15:38 PM PDT 24
Peak memory 206944 kb
Host smart-e97dc799-0e0e-4df6-afe9-d43751729d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255240971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.4255240971
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1997993058
Short name T776
Test name
Test status
Simulation time 31633635 ps
CPU time 2.27 seconds
Started Jun 24 06:15:38 PM PDT 24
Finished Jun 24 06:15:40 PM PDT 24
Peak memory 208656 kb
Host smart-ff4cd8f5-16ae-4295-a242-beba67193c65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997993058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1997993058
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1380215573
Short name T513
Test name
Test status
Simulation time 173393891 ps
CPU time 2.46 seconds
Started Jun 24 06:15:31 PM PDT 24
Finished Jun 24 06:15:34 PM PDT 24
Peak memory 206808 kb
Host smart-9d97a03a-11a1-4fc9-a794-47ba738df352
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380215573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1380215573
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4267763264
Short name T197
Test name
Test status
Simulation time 610601353 ps
CPU time 14.75 seconds
Started Jun 24 06:15:32 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 208148 kb
Host smart-f866925f-692b-4504-8185-01841b710ef6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267763264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4267763264
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1847094609
Short name T775
Test name
Test status
Simulation time 3085833691 ps
CPU time 19.14 seconds
Started Jun 24 06:15:35 PM PDT 24
Finished Jun 24 06:15:54 PM PDT 24
Peak memory 210432 kb
Host smart-6c66a793-2d70-4aa2-891f-415f94f0701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847094609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1847094609
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1036325237
Short name T473
Test name
Test status
Simulation time 1376943325 ps
CPU time 13.65 seconds
Started Jun 24 06:15:34 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 208156 kb
Host smart-7b18f827-21dc-43f8-aa02-3961790964c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036325237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1036325237
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.77354963
Short name T274
Test name
Test status
Simulation time 55100047029 ps
CPU time 270.83 seconds
Started Jun 24 06:15:41 PM PDT 24
Finished Jun 24 06:20:13 PM PDT 24
Peak memory 217876 kb
Host smart-5ac5a24c-704a-4508-b4eb-b29316f7b3aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77354963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.77354963
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2530200899
Short name T131
Test name
Test status
Simulation time 1686247498 ps
CPU time 14.92 seconds
Started Jun 24 06:15:42 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 222600 kb
Host smart-a2f244e6-25ce-495d-83c5-e1ff60ae2a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530200899 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2530200899
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3727403466
Short name T736
Test name
Test status
Simulation time 1318080188 ps
CPU time 29.93 seconds
Started Jun 24 06:15:29 PM PDT 24
Finished Jun 24 06:16:00 PM PDT 24
Peak memory 208748 kb
Host smart-aa08b246-a718-49a9-820e-621c0b17fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727403466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3727403466
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3249439711
Short name T675
Test name
Test status
Simulation time 308311352 ps
CPU time 2 seconds
Started Jun 24 06:15:34 PM PDT 24
Finished Jun 24 06:15:37 PM PDT 24
Peak memory 210076 kb
Host smart-fd5a76ff-6711-4733-beb8-98834473b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249439711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3249439711
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.337701132
Short name T894
Test name
Test status
Simulation time 9635002 ps
CPU time 0.76 seconds
Started Jun 24 06:13:23 PM PDT 24
Finished Jun 24 06:13:25 PM PDT 24
Peak memory 205908 kb
Host smart-d0882169-9a88-4d96-81c3-2c8341534784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337701132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.337701132
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2666766133
Short name T362
Test name
Test status
Simulation time 82719037 ps
CPU time 4.6 seconds
Started Jun 24 06:13:14 PM PDT 24
Finished Jun 24 06:13:19 PM PDT 24
Peak memory 214740 kb
Host smart-d71326ff-178f-4d31-9f23-7275738073ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666766133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2666766133
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1746313359
Short name T837
Test name
Test status
Simulation time 72391374 ps
CPU time 3.96 seconds
Started Jun 24 06:13:21 PM PDT 24
Finished Jun 24 06:13:25 PM PDT 24
Peak memory 214316 kb
Host smart-8137d67a-584a-4b8e-ab09-d362453a63d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746313359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1746313359
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3746091283
Short name T501
Test name
Test status
Simulation time 48160852 ps
CPU time 2.12 seconds
Started Jun 24 06:13:20 PM PDT 24
Finished Jun 24 06:13:23 PM PDT 24
Peak memory 214304 kb
Host smart-7028f9ec-eab0-49fc-b8db-a4f831b8140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746091283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3746091283
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.322274702
Short name T658
Test name
Test status
Simulation time 37874869 ps
CPU time 2.23 seconds
Started Jun 24 06:13:24 PM PDT 24
Finished Jun 24 06:13:27 PM PDT 24
Peak memory 214404 kb
Host smart-af124f49-3b3e-41e7-b643-32877880820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322274702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.322274702
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3456434876
Short name T217
Test name
Test status
Simulation time 539860075 ps
CPU time 4.91 seconds
Started Jun 24 06:13:24 PM PDT 24
Finished Jun 24 06:13:30 PM PDT 24
Peak memory 206872 kb
Host smart-f3a96a04-1164-44a3-b354-9ebf50f13740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456434876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3456434876
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2441138983
Short name T914
Test name
Test status
Simulation time 140851246 ps
CPU time 3.5 seconds
Started Jun 24 06:13:22 PM PDT 24
Finished Jun 24 06:13:26 PM PDT 24
Peak memory 209328 kb
Host smart-2a430de1-ad8e-40f3-a076-5379200ee49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441138983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2441138983
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.628817224
Short name T599
Test name
Test status
Simulation time 369836649 ps
CPU time 5.89 seconds
Started Jun 24 06:13:14 PM PDT 24
Finished Jun 24 06:13:21 PM PDT 24
Peak memory 208760 kb
Host smart-7158ff7e-399c-4411-9971-c8772a931dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628817224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.628817224
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1335376139
Short name T45
Test name
Test status
Simulation time 452152955 ps
CPU time 10.08 seconds
Started Jun 24 06:13:23 PM PDT 24
Finished Jun 24 06:13:34 PM PDT 24
Peak memory 231516 kb
Host smart-0dc6f12b-675d-4a3e-a617-72a8fedbf84f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335376139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1335376139
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.862778090
Short name T560
Test name
Test status
Simulation time 1515142278 ps
CPU time 19.16 seconds
Started Jun 24 06:13:14 PM PDT 24
Finished Jun 24 06:13:34 PM PDT 24
Peak memory 207992 kb
Host smart-e4c25c4e-8059-4c7e-83cd-d6148d0530d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862778090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.862778090
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.725225272
Short name T845
Test name
Test status
Simulation time 588149736 ps
CPU time 4.88 seconds
Started Jun 24 06:13:13 PM PDT 24
Finished Jun 24 06:13:18 PM PDT 24
Peak memory 206880 kb
Host smart-7644b9cf-18c0-4700-a427-2ba85a391a9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725225272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.725225272
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.672996254
Short name T609
Test name
Test status
Simulation time 440175132 ps
CPU time 6.51 seconds
Started Jun 24 06:13:15 PM PDT 24
Finished Jun 24 06:13:22 PM PDT 24
Peak memory 208168 kb
Host smart-bac993e4-8478-48ff-a7ac-5252a5dd04b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672996254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.672996254
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2181112820
Short name T3
Test name
Test status
Simulation time 247163687 ps
CPU time 2.76 seconds
Started Jun 24 06:13:14 PM PDT 24
Finished Jun 24 06:13:17 PM PDT 24
Peak memory 206952 kb
Host smart-03ff8c5a-ced9-4d08-a250-c2b3bbcb6207
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181112820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2181112820
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1605774339
Short name T442
Test name
Test status
Simulation time 60447076 ps
CPU time 1.63 seconds
Started Jun 24 06:13:21 PM PDT 24
Finished Jun 24 06:13:23 PM PDT 24
Peak memory 209176 kb
Host smart-eab86a7c-366a-4b96-9021-7e847cded82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605774339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1605774339
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4171890641
Short name T535
Test name
Test status
Simulation time 92015091 ps
CPU time 2.37 seconds
Started Jun 24 06:13:14 PM PDT 24
Finished Jun 24 06:13:16 PM PDT 24
Peak memory 208556 kb
Host smart-eb4d5946-3caa-4f84-b558-884af829f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171890641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4171890641
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.448663357
Short name T67
Test name
Test status
Simulation time 479481553 ps
CPU time 23.77 seconds
Started Jun 24 06:13:22 PM PDT 24
Finished Jun 24 06:13:47 PM PDT 24
Peak memory 222500 kb
Host smart-a75a9f6a-1074-4e1e-8df5-ccb94e264b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448663357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.448663357
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2772445662
Short name T915
Test name
Test status
Simulation time 2311420208 ps
CPU time 24.65 seconds
Started Jun 24 06:13:21 PM PDT 24
Finished Jun 24 06:13:46 PM PDT 24
Peak memory 222720 kb
Host smart-4215deb8-ab3c-49e0-8f6b-11f9ce83ec0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772445662 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2772445662
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3433390042
Short name T190
Test name
Test status
Simulation time 193660117 ps
CPU time 3.93 seconds
Started Jun 24 06:13:22 PM PDT 24
Finished Jun 24 06:13:27 PM PDT 24
Peak memory 214364 kb
Host smart-bb3a8118-4b09-4588-9a99-669bd73dd127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433390042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3433390042
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.117604495
Short name T421
Test name
Test status
Simulation time 29198344 ps
CPU time 0.78 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 205932 kb
Host smart-c7b8609a-fc82-41ab-ae92-05ad216b9db4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117604495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.117604495
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2921291398
Short name T24
Test name
Test status
Simulation time 551588533 ps
CPU time 4.01 seconds
Started Jun 24 06:15:45 PM PDT 24
Finished Jun 24 06:15:50 PM PDT 24
Peak memory 222740 kb
Host smart-759e63bc-c5ef-4876-bdb7-1adcaef72352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921291398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2921291398
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3362887546
Short name T698
Test name
Test status
Simulation time 600664918 ps
CPU time 4.2 seconds
Started Jun 24 06:15:48 PM PDT 24
Finished Jun 24 06:15:53 PM PDT 24
Peak memory 218264 kb
Host smart-f8db6625-7534-47c0-ad77-50d8b8b0ba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362887546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3362887546
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3234009738
Short name T92
Test name
Test status
Simulation time 2588741298 ps
CPU time 16.3 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 221116 kb
Host smart-0e1976f2-04a6-49cc-86e7-d8a421ba949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234009738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3234009738
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.952837625
Short name T835
Test name
Test status
Simulation time 64839997 ps
CPU time 3.1 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 221380 kb
Host smart-4c1b2128-21f1-4978-9d09-bc9e71f6d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952837625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.952837625
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.585567237
Short name T57
Test name
Test status
Simulation time 44566473 ps
CPU time 1.93 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:46 PM PDT 24
Peak memory 214752 kb
Host smart-b0547c40-002c-400e-8f94-a5dd5fe677a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585567237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.585567237
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2124527801
Short name T483
Test name
Test status
Simulation time 971926951 ps
CPU time 32.91 seconds
Started Jun 24 06:15:42 PM PDT 24
Finished Jun 24 06:16:16 PM PDT 24
Peak memory 208772 kb
Host smart-f19fcc26-75b7-4741-ac74-10aa4500577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124527801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2124527801
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.732100620
Short name T342
Test name
Test status
Simulation time 61289223 ps
CPU time 2.33 seconds
Started Jun 24 06:15:41 PM PDT 24
Finished Jun 24 06:15:44 PM PDT 24
Peak memory 207432 kb
Host smart-f66e7541-ce4f-4c84-b144-575175c96b60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732100620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.732100620
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.932341075
Short name T899
Test name
Test status
Simulation time 428836845 ps
CPU time 2.55 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 207420 kb
Host smart-4da3aedb-5d73-4bf1-a983-f865ef6b91ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932341075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.932341075
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2285723596
Short name T383
Test name
Test status
Simulation time 41676244 ps
CPU time 2.36 seconds
Started Jun 24 06:15:40 PM PDT 24
Finished Jun 24 06:15:43 PM PDT 24
Peak memory 206968 kb
Host smart-f6b212c7-da7b-48da-bba8-98b8a0e5a57e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285723596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2285723596
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2236158764
Short name T737
Test name
Test status
Simulation time 499644427 ps
CPU time 8.62 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:53 PM PDT 24
Peak memory 214312 kb
Host smart-91090ed5-dd37-49d4-87c8-e98a22f6869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236158764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2236158764
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1773840827
Short name T534
Test name
Test status
Simulation time 36082668 ps
CPU time 2.15 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 206728 kb
Host smart-00e4ef4a-cf23-489f-83f0-39c4cb810a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773840827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1773840827
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1702513396
Short name T678
Test name
Test status
Simulation time 2140001386 ps
CPU time 41.53 seconds
Started Jun 24 06:15:41 PM PDT 24
Finished Jun 24 06:16:24 PM PDT 24
Peak memory 222464 kb
Host smart-142a5b58-dc80-4361-9521-3113922d469f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702513396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1702513396
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2380914239
Short name T874
Test name
Test status
Simulation time 635520960 ps
CPU time 21.91 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 222684 kb
Host smart-b53c243f-c6c5-4812-85f7-06734fe895dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380914239 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2380914239
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3604942408
Short name T426
Test name
Test status
Simulation time 556037851 ps
CPU time 6.68 seconds
Started Jun 24 06:15:41 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 208052 kb
Host smart-33974347-6842-4ca9-b7b3-94b91fac5fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604942408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3604942408
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1334681503
Short name T578
Test name
Test status
Simulation time 57566459 ps
CPU time 2.56 seconds
Started Jun 24 06:15:47 PM PDT 24
Finished Jun 24 06:15:50 PM PDT 24
Peak memory 209888 kb
Host smart-ee8fa86c-21ee-4462-9e14-6eb3511c7793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334681503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1334681503
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1193187142
Short name T711
Test name
Test status
Simulation time 37938710 ps
CPU time 1.04 seconds
Started Jun 24 06:15:45 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 206092 kb
Host smart-6b2eb4e4-f969-4ebd-89d5-3a5277e2bd6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193187142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1193187142
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3152194402
Short name T239
Test name
Test status
Simulation time 767460435 ps
CPU time 3.44 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 214316 kb
Host smart-d21c2ea5-d66a-4c54-961a-a98d02f548a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3152194402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3152194402
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1818507453
Short name T34
Test name
Test status
Simulation time 139777082 ps
CPU time 5.36 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 210464 kb
Host smart-5390a326-85a8-4cc3-82d8-8701d42130da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818507453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1818507453
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3951024529
Short name T351
Test name
Test status
Simulation time 707613019 ps
CPU time 4.93 seconds
Started Jun 24 06:15:47 PM PDT 24
Finished Jun 24 06:15:53 PM PDT 24
Peak memory 218576 kb
Host smart-723f2bec-bc16-4fe4-a413-df557533e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951024529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3951024529
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.366299392
Short name T51
Test name
Test status
Simulation time 1187340819 ps
CPU time 4.25 seconds
Started Jun 24 06:15:41 PM PDT 24
Finished Jun 24 06:15:46 PM PDT 24
Peak memory 221828 kb
Host smart-039f24df-98a6-41dd-84c1-7235fd71b7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366299392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.366299392
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1070298878
Short name T817
Test name
Test status
Simulation time 95970011 ps
CPU time 2.45 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 214240 kb
Host smart-3e8753f2-f552-4ff8-ab8a-66cd7c97edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070298878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1070298878
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3812142922
Short name T228
Test name
Test status
Simulation time 476198695 ps
CPU time 3.39 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 219700 kb
Host smart-21a44de4-8327-4661-b629-0fc72b094c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812142922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3812142922
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2952563166
Short name T815
Test name
Test status
Simulation time 6919300594 ps
CPU time 71.44 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:16:56 PM PDT 24
Peak memory 219800 kb
Host smart-f0ad2456-4ab7-4bc3-9227-ddc6811ea618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952563166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2952563166
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1730962351
Short name T591
Test name
Test status
Simulation time 237290164 ps
CPU time 3.14 seconds
Started Jun 24 06:15:42 PM PDT 24
Finished Jun 24 06:15:46 PM PDT 24
Peak memory 206868 kb
Host smart-753ed534-c44e-4ac2-aac6-db9bf1edfed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730962351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1730962351
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3863347428
Short name T506
Test name
Test status
Simulation time 183726543 ps
CPU time 3.48 seconds
Started Jun 24 06:15:45 PM PDT 24
Finished Jun 24 06:15:50 PM PDT 24
Peak memory 209144 kb
Host smart-ce87b8a9-bda1-469f-9992-cc118a363691
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863347428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3863347428
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1120770777
Short name T298
Test name
Test status
Simulation time 112381156 ps
CPU time 3.83 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 208828 kb
Host smart-69f49390-215c-46c4-8c21-e4212fa0adef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120770777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1120770777
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1621093862
Short name T569
Test name
Test status
Simulation time 53376279 ps
CPU time 3.04 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 208876 kb
Host smart-643b312d-3ac0-46c3-883e-857fb5952cd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621093862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1621093862
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3649540418
Short name T548
Test name
Test status
Simulation time 63136759 ps
CPU time 2.43 seconds
Started Jun 24 06:15:45 PM PDT 24
Finished Jun 24 06:15:48 PM PDT 24
Peak memory 209284 kb
Host smart-794d9950-5e99-4a77-9510-973cbdb2ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649540418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3649540418
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1066164
Short name T4
Test name
Test status
Simulation time 83134151 ps
CPU time 1.92 seconds
Started Jun 24 06:15:42 PM PDT 24
Finished Jun 24 06:15:45 PM PDT 24
Peak memory 207668 kb
Host smart-c15e3f96-3e6a-4de3-82c0-a4b8b4d46c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1066164
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.4292885273
Short name T226
Test name
Test status
Simulation time 1532487633 ps
CPU time 36.06 seconds
Started Jun 24 06:15:45 PM PDT 24
Finished Jun 24 06:16:23 PM PDT 24
Peak memory 221788 kb
Host smart-ccf28a21-2835-4541-a11a-d187a766ea74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292885273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.4292885273
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2133254564
Short name T181
Test name
Test status
Simulation time 1741786708 ps
CPU time 10.9 seconds
Started Jun 24 06:15:44 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 221536 kb
Host smart-5aac0f15-38c0-413c-92d4-c02d9099a757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133254564 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2133254564
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2772796058
Short name T887
Test name
Test status
Simulation time 134951090 ps
CPU time 4.68 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 214308 kb
Host smart-896f61fd-732f-4cc7-b873-19f32a6106cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772796058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2772796058
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1664077007
Short name T374
Test name
Test status
Simulation time 35514434 ps
CPU time 1.98 seconds
Started Jun 24 06:15:42 PM PDT 24
Finished Jun 24 06:15:45 PM PDT 24
Peak memory 209884 kb
Host smart-a4f6ae21-adce-431d-a850-a22d27d450cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664077007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1664077007
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2902837933
Short name T749
Test name
Test status
Simulation time 11418899 ps
CPU time 0.88 seconds
Started Jun 24 06:15:47 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 205896 kb
Host smart-ce7bff71-eb85-4c7b-b80e-43eba1996e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902837933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2902837933
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2438477370
Short name T267
Test name
Test status
Simulation time 217822749 ps
CPU time 5.05 seconds
Started Jun 24 06:15:54 PM PDT 24
Finished Jun 24 06:16:01 PM PDT 24
Peak memory 214772 kb
Host smart-4d7f0251-f209-464b-96ba-81cc0c6f3490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438477370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2438477370
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3013555479
Short name T71
Test name
Test status
Simulation time 146111715 ps
CPU time 4.08 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 214616 kb
Host smart-951b14af-f369-4726-8f22-19e63e2b9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013555479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3013555479
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2649730818
Short name T1
Test name
Test status
Simulation time 599195354 ps
CPU time 20.42 seconds
Started Jun 24 06:15:54 PM PDT 24
Finished Jun 24 06:16:16 PM PDT 24
Peak memory 218532 kb
Host smart-be10ea4e-ac2b-43fb-9f93-ad1067640f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649730818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2649730818
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3189652222
Short name T773
Test name
Test status
Simulation time 1894417708 ps
CPU time 6.95 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:16:03 PM PDT 24
Peak memory 214288 kb
Host smart-b4412a6d-753f-4cff-a098-7533ceaf649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189652222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3189652222
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1427961628
Short name T253
Test name
Test status
Simulation time 142885706 ps
CPU time 2.13 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 214228 kb
Host smart-1dc39ed3-9e24-46a2-8196-8198273dfc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427961628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1427961628
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1338476993
Short name T629
Test name
Test status
Simulation time 94957883 ps
CPU time 2.88 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:15:54 PM PDT 24
Peak memory 220172 kb
Host smart-c54e7ada-99ae-42f5-b858-223aa6735421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338476993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1338476993
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1896521443
Short name T358
Test name
Test status
Simulation time 1550663418 ps
CPU time 9.21 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:16:03 PM PDT 24
Peak memory 220156 kb
Host smart-f508cea7-620c-437e-8729-3b6cfcdb89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896521443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1896521443
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4137392975
Short name T582
Test name
Test status
Simulation time 280378759 ps
CPU time 4.5 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:49 PM PDT 24
Peak memory 206832 kb
Host smart-07126dc7-b603-4103-b5d3-52572cc62cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137392975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4137392975
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4233555052
Short name T422
Test name
Test status
Simulation time 44379389 ps
CPU time 2.6 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 207016 kb
Host smart-d494cc9b-4ec7-4eeb-9c22-7d1bfc917ab2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233555052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4233555052
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3739294936
Short name T460
Test name
Test status
Simulation time 23573123 ps
CPU time 1.81 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:45 PM PDT 24
Peak memory 206828 kb
Host smart-65d9f34d-a892-4e89-95bd-d899ed81e77c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739294936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3739294936
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3685499298
Short name T515
Test name
Test status
Simulation time 741188198 ps
CPU time 5.35 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:16:00 PM PDT 24
Peak memory 207960 kb
Host smart-ae161244-c611-44aa-b233-6dd8436f1420
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685499298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3685499298
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3179511017
Short name T832
Test name
Test status
Simulation time 251252062 ps
CPU time 2.77 seconds
Started Jun 24 06:15:59 PM PDT 24
Finished Jun 24 06:16:03 PM PDT 24
Peak memory 215964 kb
Host smart-f4c8451b-b47d-4cde-bd7d-698992a57366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179511017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3179511017
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2243492027
Short name T511
Test name
Test status
Simulation time 24204452 ps
CPU time 1.69 seconds
Started Jun 24 06:15:43 PM PDT 24
Finished Jun 24 06:15:47 PM PDT 24
Peak memory 206972 kb
Host smart-0b6c88fa-ef1a-4ed4-9b76-98bcfcee8c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243492027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2243492027
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2239816877
Short name T669
Test name
Test status
Simulation time 7780877446 ps
CPU time 48.82 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 208532 kb
Host smart-1e948256-5505-4242-836a-60a3f8799534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239816877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2239816877
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3734463601
Short name T44
Test name
Test status
Simulation time 10744933888 ps
CPU time 24.8 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 211156 kb
Host smart-03bc1427-0ccd-4a54-90d2-82195b5317b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734463601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3734463601
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2104350706
Short name T855
Test name
Test status
Simulation time 60368186 ps
CPU time 1 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:54 PM PDT 24
Peak memory 206060 kb
Host smart-7c433fbd-5dd2-427c-807f-4dc2c6eacb5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104350706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2104350706
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3372355658
Short name T138
Test name
Test status
Simulation time 283153280 ps
CPU time 4.34 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:16:00 PM PDT 24
Peak memory 214312 kb
Host smart-254d3733-39db-4aa9-9da0-cb95a9f13f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372355658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3372355658
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2889116464
Short name T727
Test name
Test status
Simulation time 544041331 ps
CPU time 3.98 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 214332 kb
Host smart-1ef31fa0-3e3a-4d1c-8e5b-8a9e50f476fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889116464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2889116464
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4047505010
Short name T642
Test name
Test status
Simulation time 82434223 ps
CPU time 2.59 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 214520 kb
Host smart-393d83dd-f3ab-431f-8d20-53cde53e8ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047505010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4047505010
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4184554597
Short name T654
Test name
Test status
Simulation time 381188255 ps
CPU time 3.14 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 209752 kb
Host smart-c4598d9f-d3bf-47e1-8bc8-caf6e5194633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184554597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4184554597
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2695001996
Short name T867
Test name
Test status
Simulation time 9012981570 ps
CPU time 38.61 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 208328 kb
Host smart-f9150cf8-1075-4655-90f1-09dcc4350749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695001996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2695001996
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1063307855
Short name T644
Test name
Test status
Simulation time 1943658808 ps
CPU time 6.17 seconds
Started Jun 24 06:15:54 PM PDT 24
Finished Jun 24 06:16:02 PM PDT 24
Peak memory 206872 kb
Host smart-ad0ed5ea-8b9b-4c90-87b4-10295654cb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063307855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1063307855
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2651766380
Short name T79
Test name
Test status
Simulation time 934401731 ps
CPU time 6.88 seconds
Started Jun 24 06:15:50 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 207952 kb
Host smart-8c759636-29c2-4035-be20-21e4e21de900
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651766380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2651766380
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3728825632
Short name T521
Test name
Test status
Simulation time 242788130 ps
CPU time 4.29 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 206936 kb
Host smart-ddd8dd58-d68d-494d-923c-b71428480d9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728825632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3728825632
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3711355483
Short name T588
Test name
Test status
Simulation time 4177765452 ps
CPU time 25.92 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:16:18 PM PDT 24
Peak memory 208480 kb
Host smart-e1dbc55b-12c1-4eaf-b1db-8217e70d19cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711355483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3711355483
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2469930729
Short name T271
Test name
Test status
Simulation time 89469609 ps
CPU time 2.67 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 209396 kb
Host smart-4b8a1d18-c0d8-43d6-b364-030f7a046dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469930729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2469930729
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1957248372
Short name T910
Test name
Test status
Simulation time 98489236 ps
CPU time 1.91 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:55 PM PDT 24
Peak memory 208548 kb
Host smart-3fba826e-fecc-49de-86ba-712a967b370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957248372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1957248372
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.523160158
Short name T193
Test name
Test status
Simulation time 372296982 ps
CPU time 14.33 seconds
Started Jun 24 06:15:59 PM PDT 24
Finished Jun 24 06:16:15 PM PDT 24
Peak memory 219612 kb
Host smart-112f0fc8-3d5d-41c7-a758-257f4e91df35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523160158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.523160158
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2075374951
Short name T179
Test name
Test status
Simulation time 206933543 ps
CPU time 7.51 seconds
Started Jun 24 06:15:50 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 222600 kb
Host smart-1d25b3a4-975a-4fec-aab0-6bf44ec0d4df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075374951 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2075374951
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3402627956
Short name T309
Test name
Test status
Simulation time 101650927 ps
CPU time 5.17 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:16:01 PM PDT 24
Peak memory 209800 kb
Host smart-ba54380b-a346-4814-a02d-3b60b2cd45f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402627956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3402627956
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2639375630
Short name T640
Test name
Test status
Simulation time 1862558728 ps
CPU time 5.46 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:16:00 PM PDT 24
Peak memory 210944 kb
Host smart-27c287f8-c596-4186-8c0b-5ff1f7d8d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639375630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2639375630
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.690413102
Short name T731
Test name
Test status
Simulation time 33381717 ps
CPU time 0.86 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 205940 kb
Host smart-8e06e6df-9068-4c88-bfef-3bfefd99b455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690413102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.690413102
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3757479469
Short name T369
Test name
Test status
Simulation time 206238331 ps
CPU time 4.05 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:15:59 PM PDT 24
Peak memory 214388 kb
Host smart-76ce0c37-7fff-4efd-a1c0-ecfd54f3c996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757479469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3757479469
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3377042272
Short name T624
Test name
Test status
Simulation time 155579217 ps
CPU time 5.87 seconds
Started Jun 24 06:15:54 PM PDT 24
Finished Jun 24 06:16:01 PM PDT 24
Peak memory 209916 kb
Host smart-74f4783a-5f9e-43c8-836a-5ebb5c0be604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377042272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3377042272
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2350726380
Short name T781
Test name
Test status
Simulation time 539463605 ps
CPU time 3.93 seconds
Started Jun 24 06:15:50 PM PDT 24
Finished Jun 24 06:15:54 PM PDT 24
Peak memory 218344 kb
Host smart-dcec7b2c-cec5-4776-8af8-97d0c7ed249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350726380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2350726380
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1297206757
Short name T88
Test name
Test status
Simulation time 69855885 ps
CPU time 3.18 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 214292 kb
Host smart-62426b0c-64db-4bc4-ba88-81e9576ddc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297206757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1297206757
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3250730394
Short name T566
Test name
Test status
Simulation time 186496916 ps
CPU time 2.91 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:15:54 PM PDT 24
Peak memory 214232 kb
Host smart-fbc79bbf-775a-471b-962a-2dc4babf3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250730394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3250730394
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.390491112
Short name T888
Test name
Test status
Simulation time 129216827 ps
CPU time 4.25 seconds
Started Jun 24 06:15:54 PM PDT 24
Finished Jun 24 06:16:00 PM PDT 24
Peak memory 209760 kb
Host smart-714c6beb-4a69-4f45-8853-ca4d6bced1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390491112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.390491112
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2697766646
Short name T691
Test name
Test status
Simulation time 316331408 ps
CPU time 10.44 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:16:03 PM PDT 24
Peak memory 209872 kb
Host smart-46641563-057b-4566-a5f5-1fcbe8d7eeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697766646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2697766646
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.444547109
Short name T467
Test name
Test status
Simulation time 275652322 ps
CPU time 3.54 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 208264 kb
Host smart-77ad5da6-a53a-41c1-8301-917236500f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444547109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.444547109
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2895550625
Short name T870
Test name
Test status
Simulation time 60390937 ps
CPU time 3.02 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 208632 kb
Host smart-5e18e540-643e-4989-9832-664982eb1537
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895550625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2895550625
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.699803432
Short name T482
Test name
Test status
Simulation time 333481563 ps
CPU time 3.17 seconds
Started Jun 24 06:15:51 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 206936 kb
Host smart-c4130fbf-a571-4c4e-8074-afd713fa9c35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699803432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.699803432
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3847727563
Short name T198
Test name
Test status
Simulation time 537859220 ps
CPU time 3.38 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:16:00 PM PDT 24
Peak memory 206764 kb
Host smart-d2ed9276-fa99-4891-949e-16a4a6e98f48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847727563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3847727563
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.480561359
Short name T715
Test name
Test status
Simulation time 134432210 ps
CPU time 3.58 seconds
Started Jun 24 06:16:00 PM PDT 24
Finished Jun 24 06:16:04 PM PDT 24
Peak memory 209308 kb
Host smart-82628782-5664-4daa-993d-b5c669868294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480561359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.480561359
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3136710431
Short name T661
Test name
Test status
Simulation time 230540982 ps
CPU time 1.67 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:56 PM PDT 24
Peak memory 206840 kb
Host smart-a5de3375-28c1-47a1-b96b-e0f8985d4690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136710431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3136710431
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1555106251
Short name T313
Test name
Test status
Simulation time 5288582756 ps
CPU time 161.58 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:18:38 PM PDT 24
Peak memory 216464 kb
Host smart-04bb6267-307c-4491-9525-14d4eb34632f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555106251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1555106251
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3870694001
Short name T81
Test name
Test status
Simulation time 109974561 ps
CPU time 7.44 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:16:01 PM PDT 24
Peak memory 222600 kb
Host smart-dbcc4fcf-6a40-409c-b65b-dfbd5af8767c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870694001 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3870694001
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1084186220
Short name T708
Test name
Test status
Simulation time 775908126 ps
CPU time 4.56 seconds
Started Jun 24 06:15:52 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 207764 kb
Host smart-8c86f634-1e19-46b9-9839-00bc4730ccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084186220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1084186220
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1630391839
Short name T814
Test name
Test status
Simulation time 389781866 ps
CPU time 2.08 seconds
Started Jun 24 06:15:53 PM PDT 24
Finished Jun 24 06:15:57 PM PDT 24
Peak memory 209780 kb
Host smart-3e18d3db-fc06-4d5b-8c28-bfb30f554121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630391839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1630391839
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.463065518
Short name T898
Test name
Test status
Simulation time 14145903 ps
CPU time 0.86 seconds
Started Jun 24 06:16:00 PM PDT 24
Finished Jun 24 06:16:02 PM PDT 24
Peak memory 205940 kb
Host smart-7e3292b7-f975-40f1-828d-a4a0351051ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463065518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.463065518
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2735243699
Short name T307
Test name
Test status
Simulation time 337853179 ps
CPU time 6.16 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:10 PM PDT 24
Peak memory 215244 kb
Host smart-207ff8db-bdb8-4db5-8b40-b4d50f655ee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735243699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2735243699
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2796974341
Short name T618
Test name
Test status
Simulation time 31734285 ps
CPU time 2.13 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 220692 kb
Host smart-85bb62c0-4046-462a-954c-f65a4009c555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796974341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2796974341
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.59964708
Short name T327
Test name
Test status
Simulation time 1216603077 ps
CPU time 3.3 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 214280 kb
Host smart-5fbe8cd4-e437-4fe9-9e18-b6397c003518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59964708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.59964708
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3865018693
Short name T492
Test name
Test status
Simulation time 947151662 ps
CPU time 3.79 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:08 PM PDT 24
Peak memory 214452 kb
Host smart-07b67299-bf62-40f4-98a2-5e2cf5c6306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865018693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3865018693
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1760977503
Short name T828
Test name
Test status
Simulation time 418604362 ps
CPU time 5.71 seconds
Started Jun 24 06:16:04 PM PDT 24
Finished Jun 24 06:16:10 PM PDT 24
Peak memory 214292 kb
Host smart-e4d43bba-f642-4e6c-b9e0-22f40906d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760977503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1760977503
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1830758688
Short name T616
Test name
Test status
Simulation time 77740706 ps
CPU time 2.88 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 214356 kb
Host smart-dacb030f-6463-40e4-9e0a-07783ee6f679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830758688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1830758688
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3002442690
Short name T554
Test name
Test status
Simulation time 61665323 ps
CPU time 2.97 seconds
Started Jun 24 06:15:56 PM PDT 24
Finished Jun 24 06:16:01 PM PDT 24
Peak memory 208540 kb
Host smart-79e63ad6-3d37-46bb-8bec-19d7aa08a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002442690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3002442690
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3038889176
Short name T210
Test name
Test status
Simulation time 132731017 ps
CPU time 3.45 seconds
Started Jun 24 06:16:04 PM PDT 24
Finished Jun 24 06:16:08 PM PDT 24
Peak memory 208504 kb
Host smart-9cfa2946-bef7-4907-a425-fd875454c0ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038889176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3038889176
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4292488844
Short name T347
Test name
Test status
Simulation time 46860547 ps
CPU time 1.91 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 206988 kb
Host smart-b8dd28ec-48d2-4160-8fa9-8a313cfea092
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292488844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4292488844
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3939590781
Short name T567
Test name
Test status
Simulation time 34314941 ps
CPU time 2.22 seconds
Started Jun 24 06:16:05 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 207004 kb
Host smart-b6a77d0d-afe3-4719-bad1-fb2ec3f5d2c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939590781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3939590781
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2618633974
Short name T487
Test name
Test status
Simulation time 433170194 ps
CPU time 8.64 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:11 PM PDT 24
Peak memory 208504 kb
Host smart-79ff1b90-2b69-44a2-99c9-f9db024ffe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618633974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2618633974
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3001250708
Short name T620
Test name
Test status
Simulation time 124153175 ps
CPU time 2.28 seconds
Started Jun 24 06:15:55 PM PDT 24
Finished Jun 24 06:15:58 PM PDT 24
Peak memory 206864 kb
Host smart-79e754e3-4f90-44bc-b9a5-4af6c9347a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001250708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3001250708
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3010315508
Short name T331
Test name
Test status
Simulation time 1630267193 ps
CPU time 17.17 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 222592 kb
Host smart-fe1ed95d-7c7d-4dc9-9068-59fa42951fe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010315508 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3010315508
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2696478884
Short name T589
Test name
Test status
Simulation time 141055170 ps
CPU time 2.87 seconds
Started Jun 24 06:16:05 PM PDT 24
Finished Jun 24 06:16:09 PM PDT 24
Peak memory 209056 kb
Host smart-67cb4687-58a1-4b36-a405-65ec54ff4bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696478884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2696478884
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2784840678
Short name T657
Test name
Test status
Simulation time 51431598 ps
CPU time 2.92 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 210388 kb
Host smart-03bffe25-2d25-41e5-9e37-5ae3cf197450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784840678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2784840678
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1733900564
Short name T208
Test name
Test status
Simulation time 6462381 ps
CPU time 0.81 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:04 PM PDT 24
Peak memory 205924 kb
Host smart-83fcfe99-6132-4233-8f9a-3e62e4815e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733900564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1733900564
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1247859164
Short name T849
Test name
Test status
Simulation time 1431239786 ps
CPU time 19.26 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:23 PM PDT 24
Peak memory 214988 kb
Host smart-ecf2eaf0-9811-487a-b619-949ad182556a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247859164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1247859164
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.4116788902
Short name T550
Test name
Test status
Simulation time 188907726 ps
CPU time 3.02 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 222036 kb
Host smart-98bf1504-2f28-4f0b-a498-f04cd0f6739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116788902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.4116788902
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2069728599
Short name T896
Test name
Test status
Simulation time 268394578 ps
CPU time 3.33 seconds
Started Jun 24 06:16:03 PM PDT 24
Finished Jun 24 06:16:08 PM PDT 24
Peak memory 209036 kb
Host smart-694baebf-5f0a-49ba-a3de-cb5a3b1dc53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069728599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2069728599
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.393502583
Short name T98
Test name
Test status
Simulation time 96070297 ps
CPU time 2.16 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 208920 kb
Host smart-820f0dd1-b1e6-411f-b856-dd853b0a5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393502583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.393502583
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1092709124
Short name T306
Test name
Test status
Simulation time 146173600 ps
CPU time 5.55 seconds
Started Jun 24 06:16:04 PM PDT 24
Finished Jun 24 06:16:11 PM PDT 24
Peak memory 222512 kb
Host smart-9bd92668-96b2-4329-acc8-fd572e4073e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092709124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1092709124
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3625557120
Short name T220
Test name
Test status
Simulation time 267968226 ps
CPU time 3.72 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 214344 kb
Host smart-fb226d51-55b0-4e3a-9545-2a41357d7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625557120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3625557120
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1175702124
Short name T528
Test name
Test status
Simulation time 225792553 ps
CPU time 6.7 seconds
Started Jun 24 06:16:03 PM PDT 24
Finished Jun 24 06:16:11 PM PDT 24
Peak memory 218280 kb
Host smart-afe163c6-b5d5-45f0-a7e8-8770725ffd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175702124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1175702124
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1800615222
Short name T608
Test name
Test status
Simulation time 4410329391 ps
CPU time 30.3 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:32 PM PDT 24
Peak memory 208620 kb
Host smart-638c3835-007a-4194-8aca-b19aadd1c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800615222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1800615222
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.342782064
Short name T430
Test name
Test status
Simulation time 861769415 ps
CPU time 7.34 seconds
Started Jun 24 06:16:00 PM PDT 24
Finished Jun 24 06:16:08 PM PDT 24
Peak memory 206924 kb
Host smart-e7984ddf-1c54-43a0-8a8b-7360ad648eba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342782064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.342782064
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3634957415
Short name T877
Test name
Test status
Simulation time 306152602 ps
CPU time 4.29 seconds
Started Jun 24 06:16:00 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 209084 kb
Host smart-27e91ae4-25c9-4ca1-88f7-a6e32969d1b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634957415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3634957415
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2786909040
Short name T811
Test name
Test status
Simulation time 91754548 ps
CPU time 4.1 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 206996 kb
Host smart-1e9a41ef-40ac-429e-9956-4cdb40bd5023
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786909040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2786909040
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3647787514
Short name T756
Test name
Test status
Simulation time 2591522929 ps
CPU time 22.81 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:26 PM PDT 24
Peak memory 214428 kb
Host smart-e6fc011c-5030-404e-b005-3b578892f59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647787514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3647787514
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2738394180
Short name T777
Test name
Test status
Simulation time 402640375 ps
CPU time 4.72 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 206904 kb
Host smart-12cba6f8-fb8c-4d90-9c37-1b53abff8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738394180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2738394180
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3870579275
Short name T785
Test name
Test status
Simulation time 2348324837 ps
CPU time 21.68 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:25 PM PDT 24
Peak memory 222728 kb
Host smart-56a8ac0f-4b3f-455f-b535-715859e5b2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870579275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3870579275
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2037577005
Short name T507
Test name
Test status
Simulation time 56716366 ps
CPU time 3.81 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 208260 kb
Host smart-fdf8f72d-91b6-47a7-9904-79d19be4d8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037577005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2037577005
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2548877939
Short name T702
Test name
Test status
Simulation time 101200049 ps
CPU time 2.29 seconds
Started Jun 24 06:16:03 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 210492 kb
Host smart-480109ba-da98-46b9-aa66-f80bfc48c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548877939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2548877939
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2624113344
Short name T108
Test name
Test status
Simulation time 11072817 ps
CPU time 0.83 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:12 PM PDT 24
Peak memory 205928 kb
Host smart-8aeb5220-367b-4031-bded-ee5297a5a4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624113344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2624113344
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.702006681
Short name T454
Test name
Test status
Simulation time 318162377 ps
CPU time 4.53 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 222724 kb
Host smart-fcd95c87-034d-4344-bdf8-8130ec46eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702006681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.702006681
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.799275221
Short name T75
Test name
Test status
Simulation time 327676202 ps
CPU time 7.17 seconds
Started Jun 24 06:16:03 PM PDT 24
Finished Jun 24 06:16:12 PM PDT 24
Peak memory 209040 kb
Host smart-2992da88-2527-4144-b2eb-6077f94b1077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799275221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.799275221
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3022911313
Short name T876
Test name
Test status
Simulation time 197280659 ps
CPU time 2.36 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:15 PM PDT 24
Peak memory 214248 kb
Host smart-746b211a-500d-45c3-abd9-b20648f1e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022911313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3022911313
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3205045153
Short name T56
Test name
Test status
Simulation time 235665573 ps
CPU time 2.19 seconds
Started Jun 24 06:16:04 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 206060 kb
Host smart-97ce34ac-01ea-43e9-87b3-c7e4047805a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205045153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3205045153
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2586366052
Short name T262
Test name
Test status
Simulation time 315619024 ps
CPU time 7.72 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:10 PM PDT 24
Peak memory 218396 kb
Host smart-956c7331-7681-41e4-b0a1-f4bc51cb7f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586366052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2586366052
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3510147957
Short name T574
Test name
Test status
Simulation time 477703381 ps
CPU time 5.96 seconds
Started Jun 24 06:16:00 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 208704 kb
Host smart-4a7c1217-1a96-48c9-ba6f-8970e935c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510147957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3510147957
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.716101361
Short name T264
Test name
Test status
Simulation time 69871464 ps
CPU time 3.34 seconds
Started Jun 24 06:16:01 PM PDT 24
Finished Jun 24 06:16:06 PM PDT 24
Peak memory 208808 kb
Host smart-92614cef-b8c5-4d75-b324-cfd6ba323b53
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716101361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.716101361
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1820419617
Short name T496
Test name
Test status
Simulation time 380533295 ps
CPU time 3.88 seconds
Started Jun 24 06:16:04 PM PDT 24
Finished Jun 24 06:16:09 PM PDT 24
Peak memory 206852 kb
Host smart-491daaa9-3edd-491c-b3c4-4fd4836b06f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820419617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1820419617
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4111031165
Short name T439
Test name
Test status
Simulation time 199143716 ps
CPU time 3.03 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:07 PM PDT 24
Peak memory 206972 kb
Host smart-2f8c66be-b332-478c-962b-63310e92a9fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111031165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4111031165
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3890628427
Short name T299
Test name
Test status
Simulation time 602752456 ps
CPU time 7.26 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:25 PM PDT 24
Peak memory 209336 kb
Host smart-d46d1c85-c720-469c-9329-f2caa7c362a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890628427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3890628427
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3042678459
Short name T755
Test name
Test status
Simulation time 426818873 ps
CPU time 4.03 seconds
Started Jun 24 06:16:02 PM PDT 24
Finished Jun 24 06:16:08 PM PDT 24
Peak memory 208508 kb
Host smart-022b786f-2975-40a0-99a9-24a114930d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042678459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3042678459
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.652969225
Short name T875
Test name
Test status
Simulation time 14056711124 ps
CPU time 124 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:18:18 PM PDT 24
Peak memory 216844 kb
Host smart-a84f0702-5905-44d4-8f98-23be248c582f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652969225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.652969225
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.257820321
Short name T176
Test name
Test status
Simulation time 1056703881 ps
CPU time 22.05 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:38 PM PDT 24
Peak memory 223620 kb
Host smart-2d6c2aa7-fef1-4034-b435-03d7de95784e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257820321 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.257820321
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1477443412
Short name T892
Test name
Test status
Simulation time 54920949 ps
CPU time 3.69 seconds
Started Jun 24 06:16:00 PM PDT 24
Finished Jun 24 06:16:04 PM PDT 24
Peak memory 208136 kb
Host smart-65a270cb-97d0-4d8f-a722-321dfab36a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477443412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1477443412
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2197149717
Short name T670
Test name
Test status
Simulation time 278566625 ps
CPU time 2.04 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:19 PM PDT 24
Peak memory 210128 kb
Host smart-d1449c89-fca1-43fc-9746-2f1d1d92c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197149717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2197149717
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1802844659
Short name T634
Test name
Test status
Simulation time 28175164 ps
CPU time 0.77 seconds
Started Jun 24 06:16:17 PM PDT 24
Finished Jun 24 06:16:19 PM PDT 24
Peak memory 205908 kb
Host smart-54065a79-752a-4a1b-86c7-a2b6801aba86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802844659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1802844659
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3811688052
Short name T19
Test name
Test status
Simulation time 253107803 ps
CPU time 3.72 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 208964 kb
Host smart-72f3c49d-8fc6-4f5b-acb4-81e5699f6fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811688052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3811688052
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3785833733
Short name T99
Test name
Test status
Simulation time 174465733 ps
CPU time 5.45 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 221144 kb
Host smart-f34bcf27-1831-4e83-9eb2-85a36c9bb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785833733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3785833733
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1830992723
Short name T478
Test name
Test status
Simulation time 163484508 ps
CPU time 6.14 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 222412 kb
Host smart-c88b71b6-2109-419c-abad-d71ad14d568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830992723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1830992723
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.266645022
Short name T739
Test name
Test status
Simulation time 184772856 ps
CPU time 2.78 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:14 PM PDT 24
Peak memory 214256 kb
Host smart-c61fd8e1-256f-4713-b3eb-79f44d6a0e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266645022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.266645022
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2658368724
Short name T209
Test name
Test status
Simulation time 222964555 ps
CPU time 4.21 seconds
Started Jun 24 06:16:14 PM PDT 24
Finished Jun 24 06:16:19 PM PDT 24
Peak memory 214324 kb
Host smart-f86cc41b-c0aa-43f8-8f2f-85b29d9a17fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658368724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2658368724
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2543254600
Short name T463
Test name
Test status
Simulation time 176318843 ps
CPU time 3.19 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 207720 kb
Host smart-6a0c15f1-adae-4a2d-9af5-23d80bcdb83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543254600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2543254600
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4266653288
Short name T553
Test name
Test status
Simulation time 189350747 ps
CPU time 6.79 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 207960 kb
Host smart-d2255967-ce2f-4028-8996-f7c2d650d99d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266653288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4266653288
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2722310462
Short name T841
Test name
Test status
Simulation time 463809855 ps
CPU time 3.89 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:16 PM PDT 24
Peak memory 208076 kb
Host smart-d63c8380-1c8a-4c62-bbcb-dbe87ee7a1b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722310462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2722310462
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2922069706
Short name T457
Test name
Test status
Simulation time 218669898 ps
CPU time 3.56 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 208756 kb
Host smart-bd2fa606-2ed4-46bb-ab54-98ce9f05b23b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922069706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2922069706
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2901476325
Short name T241
Test name
Test status
Simulation time 126611851 ps
CPU time 3.41 seconds
Started Jun 24 06:16:11 PM PDT 24
Finished Jun 24 06:16:15 PM PDT 24
Peak memory 215416 kb
Host smart-9904f46b-e25f-44ac-8fea-32461bf45fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901476325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2901476325
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.136295060
Short name T846
Test name
Test status
Simulation time 288126159 ps
CPU time 2.7 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:14 PM PDT 24
Peak memory 206864 kb
Host smart-aac11bcd-4a1b-486f-84c6-3bf1b8e1304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136295060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.136295060
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.4202222425
Short name T173
Test name
Test status
Simulation time 403600372 ps
CPU time 10.52 seconds
Started Jun 24 06:16:14 PM PDT 24
Finished Jun 24 06:16:26 PM PDT 24
Peak memory 222592 kb
Host smart-85a3b09e-1d5d-4e84-9bc7-c88b0aaa1561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202222425 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.4202222425
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3739460161
Short name T701
Test name
Test status
Simulation time 319606976 ps
CPU time 4.39 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 207624 kb
Host smart-4ae59303-ba3b-457b-b32f-3aa1b184c7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739460161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3739460161
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2654703442
Short name T533
Test name
Test status
Simulation time 73801007 ps
CPU time 2.2 seconds
Started Jun 24 06:16:11 PM PDT 24
Finished Jun 24 06:16:14 PM PDT 24
Peak memory 210348 kb
Host smart-7f0e0ec4-8ba7-4f81-b2f4-94f5f7d892b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654703442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2654703442
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2497837868
Short name T100
Test name
Test status
Simulation time 62317407 ps
CPU time 0.74 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:12 PM PDT 24
Peak memory 205924 kb
Host smart-d56ed50a-3b57-4db0-83b0-c789a016ae48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497837868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2497837868
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.724084355
Short name T21
Test name
Test status
Simulation time 68465605 ps
CPU time 2.86 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 217924 kb
Host smart-53e43e00-3d87-4084-a07e-2ed70f22e498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724084355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.724084355
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4219883781
Short name T743
Test name
Test status
Simulation time 49135616 ps
CPU time 1.54 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:18 PM PDT 24
Peak memory 208980 kb
Host smart-0f56b4d7-a3d3-4c72-8ecc-9ebf20b08f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219883781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4219883781
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3575633898
Short name T91
Test name
Test status
Simulation time 132402612 ps
CPU time 3.26 seconds
Started Jun 24 06:16:09 PM PDT 24
Finished Jun 24 06:16:12 PM PDT 24
Peak memory 209600 kb
Host smart-29df0356-1012-46d0-b14d-344c266aef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575633898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3575633898
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.830270458
Short name T760
Test name
Test status
Simulation time 34256040 ps
CPU time 2.08 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 214236 kb
Host smart-1a2f97b5-69cd-4712-b463-4a3570f290a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830270458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.830270458
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2005645415
Short name T70
Test name
Test status
Simulation time 1234043490 ps
CPU time 3.9 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 208668 kb
Host smart-e9e61a88-1c70-49a5-83fc-c4af702e17b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005645415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2005645415
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2140278052
Short name T667
Test name
Test status
Simulation time 95724415 ps
CPU time 4.57 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 209316 kb
Host smart-06d9a178-a8d3-42d8-8550-5c308fb504c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140278052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2140278052
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3876340074
Short name T310
Test name
Test status
Simulation time 3378256034 ps
CPU time 64.68 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:17:22 PM PDT 24
Peak memory 208932 kb
Host smart-dc1f4b6a-f707-4a1b-b3f6-3f3459056656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876340074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3876340074
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2597009690
Short name T508
Test name
Test status
Simulation time 1137293860 ps
CPU time 26.97 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:41 PM PDT 24
Peak memory 208124 kb
Host smart-d8d85654-cfbe-430f-9042-d0e5d3008231
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597009690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2597009690
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.409350915
Short name T679
Test name
Test status
Simulation time 2788256059 ps
CPU time 39.7 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:54 PM PDT 24
Peak memory 208324 kb
Host smart-fe097d72-8d17-4ed4-986f-6378c815138c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409350915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.409350915
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.674381211
Short name T662
Test name
Test status
Simulation time 35337181 ps
CPU time 2.49 seconds
Started Jun 24 06:16:14 PM PDT 24
Finished Jun 24 06:16:18 PM PDT 24
Peak memory 208568 kb
Host smart-0ca029f5-a805-4f36-b5c2-cd37c25f996d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674381211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.674381211
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.347426909
Short name T240
Test name
Test status
Simulation time 3841879440 ps
CPU time 26.58 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:38 PM PDT 24
Peak memory 210692 kb
Host smart-d30cd1f3-65d5-48b5-ba33-c2ed1657262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347426909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.347426909
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3339302259
Short name T848
Test name
Test status
Simulation time 2395875817 ps
CPU time 23.1 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:38 PM PDT 24
Peak memory 207880 kb
Host smart-147eece2-d4b8-4fac-856b-cd46e23d6779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339302259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3339302259
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3337861937
Short name T194
Test name
Test status
Simulation time 3325667239 ps
CPU time 37.83 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 215320 kb
Host smart-eb26992e-973e-4861-8e8f-a697e5085544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337861937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3337861937
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.225777086
Short name T78
Test name
Test status
Simulation time 1247787813 ps
CPU time 9.03 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 222496 kb
Host smart-0145a661-d6ff-40eb-bdde-b8aaec65209f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225777086 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.225777086
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1149935337
Short name T556
Test name
Test status
Simulation time 33170823 ps
CPU time 2.44 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:16 PM PDT 24
Peak memory 208336 kb
Host smart-527ceaf2-ceea-4a54-9fb6-b3b69ecf75fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149935337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1149935337
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4262841240
Short name T694
Test name
Test status
Simulation time 112324467 ps
CPU time 1.85 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:16 PM PDT 24
Peak memory 210496 kb
Host smart-2c69fe85-2d5f-4bc2-8e28-17e77a06bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262841240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4262841240
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1458463810
Short name T571
Test name
Test status
Simulation time 78372704 ps
CPU time 0.79 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:38 PM PDT 24
Peak memory 205852 kb
Host smart-30aad277-29a1-4eff-8399-85f6d03c0803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458463810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1458463810
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3444568181
Short name T395
Test name
Test status
Simulation time 522911918 ps
CPU time 3.93 seconds
Started Jun 24 06:13:23 PM PDT 24
Finished Jun 24 06:13:28 PM PDT 24
Peak memory 222464 kb
Host smart-978bc8bf-e85e-4e7f-99e5-679608aa3816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444568181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3444568181
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3042732035
Short name T102
Test name
Test status
Simulation time 57296844 ps
CPU time 2.47 seconds
Started Jun 24 06:13:34 PM PDT 24
Finished Jun 24 06:13:38 PM PDT 24
Peak memory 210076 kb
Host smart-e9d6cc44-470d-4a87-b47b-1c472794f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042732035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3042732035
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1590067002
Short name T767
Test name
Test status
Simulation time 86577083 ps
CPU time 3.64 seconds
Started Jun 24 06:13:22 PM PDT 24
Finished Jun 24 06:13:26 PM PDT 24
Peak memory 214316 kb
Host smart-f1f6c232-c61c-4806-92ce-4c4f0b3ec370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590067002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1590067002
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.240740356
Short name T806
Test name
Test status
Simulation time 158144131 ps
CPU time 4.84 seconds
Started Jun 24 06:13:21 PM PDT 24
Finished Jun 24 06:13:26 PM PDT 24
Peak memory 214304 kb
Host smart-616bcdd4-62ee-4d02-a7ff-6c05174ea9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240740356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.240740356
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2340129044
Short name T752
Test name
Test status
Simulation time 373341253 ps
CPU time 8.69 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 222424 kb
Host smart-376f66ec-da06-4030-b7af-9b137b16acb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340129044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2340129044
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1777064782
Short name T587
Test name
Test status
Simulation time 103818573 ps
CPU time 2.03 seconds
Started Jun 24 06:13:20 PM PDT 24
Finished Jun 24 06:13:23 PM PDT 24
Peak memory 206112 kb
Host smart-4532b117-0eba-4a5d-90ae-028378740d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777064782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1777064782
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2287197075
Short name T245
Test name
Test status
Simulation time 751039337 ps
CPU time 4.25 seconds
Started Jun 24 06:13:24 PM PDT 24
Finished Jun 24 06:13:30 PM PDT 24
Peak memory 207776 kb
Host smart-77b060f0-4ff2-4ee0-8ebf-825bd0cd784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287197075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2287197075
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1565327281
Short name T12
Test name
Test status
Simulation time 589974039 ps
CPU time 8.76 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:46 PM PDT 24
Peak memory 237476 kb
Host smart-f7a672d3-913f-4cc8-b463-d7a6b690d373
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565327281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1565327281
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4079711173
Short name T913
Test name
Test status
Simulation time 75331537 ps
CPU time 1.74 seconds
Started Jun 24 06:13:22 PM PDT 24
Finished Jun 24 06:13:25 PM PDT 24
Peak memory 206836 kb
Host smart-a9ed51c4-0da5-4acd-b7a1-c78c44b6c1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079711173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4079711173
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2451959836
Short name T244
Test name
Test status
Simulation time 1760045920 ps
CPU time 30.97 seconds
Started Jun 24 06:13:22 PM PDT 24
Finished Jun 24 06:13:54 PM PDT 24
Peak memory 207876 kb
Host smart-7adf91ff-7397-459d-9419-d72e86e4c831
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451959836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2451959836
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3009632287
Short name T428
Test name
Test status
Simulation time 194210913 ps
CPU time 3.52 seconds
Started Jun 24 06:13:23 PM PDT 24
Finished Jun 24 06:13:27 PM PDT 24
Peak memory 209040 kb
Host smart-e9c3e309-b214-43ad-ae0a-b59da49cb652
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009632287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3009632287
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2579086407
Short name T612
Test name
Test status
Simulation time 41945949 ps
CPU time 2.57 seconds
Started Jun 24 06:13:21 PM PDT 24
Finished Jun 24 06:13:25 PM PDT 24
Peak memory 208860 kb
Host smart-78e7285b-fa07-489f-8071-a2d7c9dd23f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579086407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2579086407
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1612538466
Short name T801
Test name
Test status
Simulation time 77144434 ps
CPU time 2.82 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 209628 kb
Host smart-2046a0f9-781f-4ed4-88e9-b047b2e8ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612538466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1612538466
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1983755537
Short name T754
Test name
Test status
Simulation time 455362971 ps
CPU time 4.74 seconds
Started Jun 24 06:13:25 PM PDT 24
Finished Jun 24 06:13:30 PM PDT 24
Peak memory 208576 kb
Host smart-8a40b9cc-5238-473e-95ad-95ea155bb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983755537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1983755537
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3981308962
Short name T175
Test name
Test status
Simulation time 256390653 ps
CPU time 9.71 seconds
Started Jun 24 06:13:33 PM PDT 24
Finished Jun 24 06:13:43 PM PDT 24
Peak memory 220612 kb
Host smart-061489ee-4d9a-41eb-be64-6de60acde375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981308962 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3981308962
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.896241860
Short name T257
Test name
Test status
Simulation time 93668251 ps
CPU time 4.53 seconds
Started Jun 24 06:13:24 PM PDT 24
Finished Jun 24 06:13:29 PM PDT 24
Peak memory 210336 kb
Host smart-6b277fa4-0877-4c38-a2dc-6d52e7691761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896241860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.896241860
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.287659089
Short name T636
Test name
Test status
Simulation time 129856950 ps
CPU time 2.27 seconds
Started Jun 24 06:13:34 PM PDT 24
Finished Jun 24 06:13:37 PM PDT 24
Peak memory 210272 kb
Host smart-0abd0f85-b86a-46a2-968a-e5612cb88b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287659089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.287659089
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.93141630
Short name T857
Test name
Test status
Simulation time 47287486 ps
CPU time 0.79 seconds
Started Jun 24 06:16:20 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 205948 kb
Host smart-1932d463-dbe2-41e3-988b-955c8bcc2a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93141630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.93141630
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.648769681
Short name T852
Test name
Test status
Simulation time 463872912 ps
CPU time 6.4 seconds
Started Jun 24 06:16:14 PM PDT 24
Finished Jun 24 06:16:22 PM PDT 24
Peak memory 215632 kb
Host smart-00dc9702-c406-4733-95bb-1dbc3c30951e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648769681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.648769681
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2397730471
Short name T227
Test name
Test status
Simulation time 155866221 ps
CPU time 3.04 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:16 PM PDT 24
Peak memory 210116 kb
Host smart-a5671758-4716-4f79-9e70-8cbbc0aa5242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397730471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2397730471
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.967623041
Short name T315
Test name
Test status
Simulation time 79636884 ps
CPU time 2.5 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 219560 kb
Host smart-9b401202-12b7-4691-8502-37c608e5e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967623041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.967623041
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.113818547
Short name T289
Test name
Test status
Simulation time 72870358 ps
CPU time 2.74 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:16:20 PM PDT 24
Peak memory 213240 kb
Host smart-d88988be-bc6b-4f15-ab3e-e98985b5be49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113818547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.113818547
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1906012868
Short name T332
Test name
Test status
Simulation time 345385250 ps
CPU time 4.23 seconds
Started Jun 24 06:16:12 PM PDT 24
Finished Jun 24 06:16:17 PM PDT 24
Peak memory 209476 kb
Host smart-13de687b-7b91-4877-b467-b373c6a03bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906012868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1906012868
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1268951193
Short name T598
Test name
Test status
Simulation time 332732018 ps
CPU time 4 seconds
Started Jun 24 06:16:16 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 218240 kb
Host smart-39435ef9-ee13-4b16-9f6f-a883193b0797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268951193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1268951193
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3528998862
Short name T655
Test name
Test status
Simulation time 44094144 ps
CPU time 2.5 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:14 PM PDT 24
Peak memory 208564 kb
Host smart-0dc5a972-50bc-4340-95b2-334ebab7d007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528998862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3528998862
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3129155983
Short name T461
Test name
Test status
Simulation time 424378550 ps
CPU time 3.44 seconds
Started Jun 24 06:16:11 PM PDT 24
Finished Jun 24 06:16:15 PM PDT 24
Peak memory 209028 kb
Host smart-2b0e3eb7-0648-4716-a307-c911106f5181
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129155983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3129155983
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.612876892
Short name T782
Test name
Test status
Simulation time 117325196 ps
CPU time 2.34 seconds
Started Jun 24 06:16:14 PM PDT 24
Finished Jun 24 06:16:18 PM PDT 24
Peak memory 206828 kb
Host smart-37049ce5-6a61-488d-bf99-e74d3f66aecc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612876892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.612876892
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2577816417
Short name T653
Test name
Test status
Simulation time 497927606 ps
CPU time 6.51 seconds
Started Jun 24 06:16:13 PM PDT 24
Finished Jun 24 06:16:21 PM PDT 24
Peak memory 208660 kb
Host smart-508dd186-97dc-4d9f-9c86-0717e36a832e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577816417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2577816417
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1149436008
Short name T539
Test name
Test status
Simulation time 790941061 ps
CPU time 13 seconds
Started Jun 24 06:16:10 PM PDT 24
Finished Jun 24 06:16:24 PM PDT 24
Peak memory 207960 kb
Host smart-5f05fe0d-bf1d-49bb-81b7-8d54d8fa3748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149436008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1149436008
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2631901433
Short name T180
Test name
Test status
Simulation time 1664337373 ps
CPU time 12.54 seconds
Started Jun 24 06:16:18 PM PDT 24
Finished Jun 24 06:16:31 PM PDT 24
Peak memory 220644 kb
Host smart-0e02fdb3-fab8-4728-a563-713b2186e1e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631901433 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2631901433
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1733518243
Short name T916
Test name
Test status
Simulation time 2481390364 ps
CPU time 61.29 seconds
Started Jun 24 06:16:15 PM PDT 24
Finished Jun 24 06:17:18 PM PDT 24
Peak memory 209540 kb
Host smart-9ec1bb06-5645-49a2-b66d-a3012d599dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733518243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1733518243
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3234987568
Short name T583
Test name
Test status
Simulation time 287738114 ps
CPU time 3.45 seconds
Started Jun 24 06:16:20 PM PDT 24
Finished Jun 24 06:16:24 PM PDT 24
Peak memory 210572 kb
Host smart-68c4a5a2-43ec-43fa-b6ac-8b75ed7e88b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234987568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3234987568
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2217796153
Short name T766
Test name
Test status
Simulation time 38656761 ps
CPU time 0.84 seconds
Started Jun 24 06:16:20 PM PDT 24
Finished Jun 24 06:16:22 PM PDT 24
Peak memory 205908 kb
Host smart-dda91ad9-0375-4e3b-bae9-fa89a50011cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217796153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2217796153
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2388249075
Short name T392
Test name
Test status
Simulation time 1611358161 ps
CPU time 11.17 seconds
Started Jun 24 06:16:28 PM PDT 24
Finished Jun 24 06:16:39 PM PDT 24
Peak memory 214488 kb
Host smart-83de289c-5a5b-4ce4-b3bc-cf616d632f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388249075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2388249075
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4091049518
Short name T641
Test name
Test status
Simulation time 139312215 ps
CPU time 2.04 seconds
Started Jun 24 06:16:26 PM PDT 24
Finished Jun 24 06:16:28 PM PDT 24
Peak memory 207584 kb
Host smart-5bb6240d-ce6f-49d6-b1fb-0a195845bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091049518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4091049518
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2890552945
Short name T52
Test name
Test status
Simulation time 120474269 ps
CPU time 2.38 seconds
Started Jun 24 06:16:21 PM PDT 24
Finished Jun 24 06:16:24 PM PDT 24
Peak memory 214528 kb
Host smart-611c9346-76a6-489e-86a1-34fd04fd077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890552945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2890552945
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.663001797
Short name T768
Test name
Test status
Simulation time 138239985 ps
CPU time 5.88 seconds
Started Jun 24 06:16:20 PM PDT 24
Finished Jun 24 06:16:27 PM PDT 24
Peak memory 214280 kb
Host smart-a3965e31-b4eb-4776-ac59-b001d0254ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663001797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.663001797
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2250296866
Short name T234
Test name
Test status
Simulation time 103864318 ps
CPU time 4.88 seconds
Started Jun 24 06:16:23 PM PDT 24
Finished Jun 24 06:16:28 PM PDT 24
Peak memory 220076 kb
Host smart-8e6354ca-d601-4455-b5a2-e2bc1f8c360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250296866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2250296866
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3744899212
Short name T902
Test name
Test status
Simulation time 64573191 ps
CPU time 3.51 seconds
Started Jun 24 06:16:18 PM PDT 24
Finished Jun 24 06:16:22 PM PDT 24
Peak memory 208660 kb
Host smart-985db521-c5ea-460c-af9d-e58a8f9d2fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744899212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3744899212
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1450829723
Short name T839
Test name
Test status
Simulation time 877808785 ps
CPU time 24.75 seconds
Started Jun 24 06:16:21 PM PDT 24
Finished Jun 24 06:16:47 PM PDT 24
Peak memory 208196 kb
Host smart-1c2633d2-b25f-4722-bdee-af7f20014d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450829723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1450829723
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3338555461
Short name T903
Test name
Test status
Simulation time 2108595347 ps
CPU time 13.88 seconds
Started Jun 24 06:16:23 PM PDT 24
Finished Jun 24 06:16:38 PM PDT 24
Peak memory 208084 kb
Host smart-50d07eeb-f195-415f-be8e-3eef65440595
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338555461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3338555461
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1575777221
Short name T778
Test name
Test status
Simulation time 224805866 ps
CPU time 3.01 seconds
Started Jun 24 06:16:25 PM PDT 24
Finished Jun 24 06:16:29 PM PDT 24
Peak memory 208132 kb
Host smart-181f0ed9-ba8d-4267-a17b-7d7a81436a64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575777221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1575777221
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.14456559
Short name T859
Test name
Test status
Simulation time 81199179 ps
CPU time 3.86 seconds
Started Jun 24 06:16:26 PM PDT 24
Finished Jun 24 06:16:31 PM PDT 24
Peak memory 208840 kb
Host smart-ae2082c4-1e89-4a6e-a0fb-cb2752e89643
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14456559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.14456559
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2174652906
Short name T361
Test name
Test status
Simulation time 322585813 ps
CPU time 2.05 seconds
Started Jun 24 06:16:19 PM PDT 24
Finished Jun 24 06:16:23 PM PDT 24
Peak memory 208248 kb
Host smart-53d296d2-c51d-4026-8f8b-0121a6ebc58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174652906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2174652906
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1422376871
Short name T523
Test name
Test status
Simulation time 492034829 ps
CPU time 5.65 seconds
Started Jun 24 06:16:27 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 208428 kb
Host smart-81cd845c-84b2-4233-87ed-a0fe39ad766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422376871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1422376871
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3607002898
Short name T296
Test name
Test status
Simulation time 6970183317 ps
CPU time 43.18 seconds
Started Jun 24 06:16:20 PM PDT 24
Finished Jun 24 06:17:05 PM PDT 24
Peak memory 215144 kb
Host smart-ce989e25-c1c1-4799-9742-91ab12aea237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607002898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3607002898
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1683827095
Short name T30
Test name
Test status
Simulation time 1115426952 ps
CPU time 14.68 seconds
Started Jun 24 06:16:19 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 214300 kb
Host smart-a4d98d32-b19b-4020-a0e7-a0adf86e6881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683827095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1683827095
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2436321162
Short name T376
Test name
Test status
Simulation time 28698970 ps
CPU time 1.48 seconds
Started Jun 24 06:16:19 PM PDT 24
Finished Jun 24 06:16:22 PM PDT 24
Peak memory 209716 kb
Host smart-b1a0ab3d-b373-4b96-ac97-166a5fbeb461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436321162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2436321162
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3464498946
Short name T414
Test name
Test status
Simulation time 208891735 ps
CPU time 0.83 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:16:34 PM PDT 24
Peak memory 205924 kb
Host smart-f53f6dd8-8cec-4132-9e46-6539b7fc98c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464498946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3464498946
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2392791615
Short name T380
Test name
Test status
Simulation time 70679603 ps
CPU time 3.99 seconds
Started Jun 24 06:16:23 PM PDT 24
Finished Jun 24 06:16:28 PM PDT 24
Peak memory 214756 kb
Host smart-b19aa5de-8fb9-4442-a9a3-97dfd07ba541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392791615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2392791615
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3363719993
Short name T8
Test name
Test status
Simulation time 50341683 ps
CPU time 2.41 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 218884 kb
Host smart-ab52ab47-16bd-4683-a90e-91ac254b75d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363719993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3363719993
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4058418433
Short name T611
Test name
Test status
Simulation time 154388689 ps
CPU time 1.99 seconds
Started Jun 24 06:16:21 PM PDT 24
Finished Jun 24 06:16:24 PM PDT 24
Peak memory 209616 kb
Host smart-c70591b7-2b76-4b64-aec0-9e538572fa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058418433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4058418433
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4115365322
Short name T87
Test name
Test status
Simulation time 34301583 ps
CPU time 2.25 seconds
Started Jun 24 06:16:19 PM PDT 24
Finished Jun 24 06:16:22 PM PDT 24
Peak memory 214532 kb
Host smart-6aceccf0-2919-4bf3-8024-217dd50443eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115365322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4115365322
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1986545796
Short name T318
Test name
Test status
Simulation time 537370372 ps
CPU time 3.37 seconds
Started Jun 24 06:16:24 PM PDT 24
Finished Jun 24 06:16:28 PM PDT 24
Peak memory 222452 kb
Host smart-48647654-83cd-4363-be2c-373db86696f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986545796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1986545796
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3963019061
Short name T5
Test name
Test status
Simulation time 68713508 ps
CPU time 3.74 seconds
Started Jun 24 06:16:22 PM PDT 24
Finished Jun 24 06:16:26 PM PDT 24
Peak memory 214308 kb
Host smart-d898d92a-c885-4212-8750-214be75733ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963019061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3963019061
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2629364000
Short name T364
Test name
Test status
Simulation time 359142533 ps
CPU time 4.3 seconds
Started Jun 24 06:16:27 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 207460 kb
Host smart-f8d9c56f-bf67-45d9-9694-ede91f05c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629364000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2629364000
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1118360700
Short name T258
Test name
Test status
Simulation time 103178267 ps
CPU time 3.69 seconds
Started Jun 24 06:16:18 PM PDT 24
Finished Jun 24 06:16:22 PM PDT 24
Peak memory 208444 kb
Host smart-457725ce-fb91-4a12-83a9-47de4075de8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118360700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1118360700
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3964106749
Short name T893
Test name
Test status
Simulation time 702522852 ps
CPU time 23.2 seconds
Started Jun 24 06:16:25 PM PDT 24
Finished Jun 24 06:16:49 PM PDT 24
Peak memory 208400 kb
Host smart-a81db3f4-4768-48e5-ab57-9e6fa28c5071
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964106749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3964106749
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3173149865
Short name T215
Test name
Test status
Simulation time 40290442 ps
CPU time 2.77 seconds
Started Jun 24 06:16:25 PM PDT 24
Finished Jun 24 06:16:29 PM PDT 24
Peak memory 208772 kb
Host smart-a94e7258-ef25-4af1-afa7-f5d12b1d58c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173149865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3173149865
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4119498437
Short name T795
Test name
Test status
Simulation time 448725090 ps
CPU time 7.35 seconds
Started Jun 24 06:16:24 PM PDT 24
Finished Jun 24 06:16:32 PM PDT 24
Peak memory 208792 kb
Host smart-88d24b32-d8f0-4620-9460-50ecff300175
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119498437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4119498437
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.225362975
Short name T266
Test name
Test status
Simulation time 56548107 ps
CPU time 2.84 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 208376 kb
Host smart-1550b747-b677-4c5c-ba8b-68ffe387c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225362975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.225362975
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.835225358
Short name T623
Test name
Test status
Simulation time 58818795 ps
CPU time 2.47 seconds
Started Jun 24 06:16:26 PM PDT 24
Finished Jun 24 06:16:29 PM PDT 24
Peak memory 208400 kb
Host smart-2bcedfc0-bc35-475f-b29b-fe5154141724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835225358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.835225358
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.625570625
Short name T64
Test name
Test status
Simulation time 516778523 ps
CPU time 11.33 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 219332 kb
Host smart-f80d87a9-267f-4c8d-add8-e683b784bfb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625570625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.625570625
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.4061848968
Short name T128
Test name
Test status
Simulation time 1239910836 ps
CPU time 25.65 seconds
Started Jun 24 06:16:28 PM PDT 24
Finished Jun 24 06:16:55 PM PDT 24
Peak memory 222588 kb
Host smart-a6e8adbf-7def-40cd-901a-7a73c66d340d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061848968 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.4061848968
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2716895735
Short name T489
Test name
Test status
Simulation time 165670679 ps
CPU time 2.92 seconds
Started Jun 24 06:16:26 PM PDT 24
Finished Jun 24 06:16:30 PM PDT 24
Peak memory 207476 kb
Host smart-8661d2f0-792a-454c-8efe-4f3a783b14a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716895735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2716895735
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2430198567
Short name T191
Test name
Test status
Simulation time 1478186076 ps
CPU time 8.53 seconds
Started Jun 24 06:16:27 PM PDT 24
Finished Jun 24 06:16:36 PM PDT 24
Peak memory 210908 kb
Host smart-128c64e1-5b9a-4989-9780-ee82f78d0e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430198567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2430198567
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1708965014
Short name T435
Test name
Test status
Simulation time 42884009 ps
CPU time 0.76 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 205928 kb
Host smart-3dbaa59f-2a9e-4e6b-9c6a-c7743e812d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708965014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1708965014
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.696028694
Short name T829
Test name
Test status
Simulation time 183132964 ps
CPU time 2.77 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 217476 kb
Host smart-cf027d30-2fe9-4627-b457-1e816c6173eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696028694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.696028694
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.453278945
Short name T909
Test name
Test status
Simulation time 107619196 ps
CPU time 2.63 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 214320 kb
Host smart-b6efdac2-3b9a-4c35-811e-6fba955e54f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453278945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.453278945
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4075910005
Short name T84
Test name
Test status
Simulation time 91064276 ps
CPU time 3.38 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:16:36 PM PDT 24
Peak memory 215516 kb
Host smart-51fa0552-6d49-43ce-976e-78be842a03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075910005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4075910005
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3719475283
Short name T516
Test name
Test status
Simulation time 195588377 ps
CPU time 3.61 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 209276 kb
Host smart-8799dd47-338c-4bf2-9f25-b0e2ab00afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719475283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3719475283
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2918666491
Short name T276
Test name
Test status
Simulation time 179476209 ps
CPU time 5.31 seconds
Started Jun 24 06:16:27 PM PDT 24
Finished Jun 24 06:16:34 PM PDT 24
Peak memory 208180 kb
Host smart-34be1a38-603a-479e-b590-12d495053b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918666491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2918666491
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3800295999
Short name T412
Test name
Test status
Simulation time 273943570 ps
CPU time 3.29 seconds
Started Jun 24 06:16:28 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 206908 kb
Host smart-9b322992-2da1-4b43-b934-45f3395498c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800295999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3800295999
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4241585964
Short name T643
Test name
Test status
Simulation time 58484702 ps
CPU time 3.15 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:34 PM PDT 24
Peak memory 208392 kb
Host smart-f83dfda3-194e-4d73-90cb-457884d61ded
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241585964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4241585964
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.634376895
Short name T740
Test name
Test status
Simulation time 4894731318 ps
CPU time 38.22 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:17:12 PM PDT 24
Peak memory 208340 kb
Host smart-4f27dfd7-d07e-40dd-8e0e-7373eac41794
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634376895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.634376895
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3433894572
Short name T729
Test name
Test status
Simulation time 881385551 ps
CPU time 2.79 seconds
Started Jun 24 06:16:36 PM PDT 24
Finished Jun 24 06:16:39 PM PDT 24
Peak memory 209764 kb
Host smart-5d772e23-a52c-46b6-8265-d68747607635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433894572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3433894572
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1007463961
Short name T432
Test name
Test status
Simulation time 62384392 ps
CPU time 2.44 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:32 PM PDT 24
Peak memory 207068 kb
Host smart-ca08c8d3-63af-4b0b-831f-607f02665eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007463961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1007463961
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1813002164
Short name T65
Test name
Test status
Simulation time 2447902043 ps
CPU time 31.87 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:17:04 PM PDT 24
Peak memory 215716 kb
Host smart-ecec666c-98e8-4a99-a059-0488bd18ce33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813002164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1813002164
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.456101117
Short name T704
Test name
Test status
Simulation time 62508080 ps
CPU time 2.35 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:33 PM PDT 24
Peak memory 209176 kb
Host smart-44c40422-1e97-4a08-aae1-7a87c323b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456101117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.456101117
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3927424708
Short name T167
Test name
Test status
Simulation time 46576644 ps
CPU time 2.21 seconds
Started Jun 24 06:16:28 PM PDT 24
Finished Jun 24 06:16:32 PM PDT 24
Peak memory 209976 kb
Host smart-13874e94-6c91-4729-93f7-0a2c83b7e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927424708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3927424708
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.661912123
Short name T808
Test name
Test status
Simulation time 11880140 ps
CPU time 0.76 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:31 PM PDT 24
Peak memory 205932 kb
Host smart-208e5a5d-8eb2-4389-b5af-239fa3157a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661912123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.661912123
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1944805356
Short name T401
Test name
Test status
Simulation time 206191636 ps
CPU time 3.79 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:36 PM PDT 24
Peak memory 214320 kb
Host smart-1c166c1a-becd-4421-9808-21611ccf9c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944805356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1944805356
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1575096903
Short name T61
Test name
Test status
Simulation time 718329652 ps
CPU time 12.17 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:43 PM PDT 24
Peak memory 214300 kb
Host smart-952d675e-5c4a-417e-a4bc-1e37c2917a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575096903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1575096903
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2289473518
Short name T371
Test name
Test status
Simulation time 344140337 ps
CPU time 5.3 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:37 PM PDT 24
Peak memory 214300 kb
Host smart-529aed70-d1bc-4681-b39d-1a223341faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289473518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2289473518
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1620261149
Short name T570
Test name
Test status
Simulation time 410761564 ps
CPU time 3.64 seconds
Started Jun 24 06:16:36 PM PDT 24
Finished Jun 24 06:16:41 PM PDT 24
Peak memory 219236 kb
Host smart-53d5e27f-1b37-4610-9ab5-2787de4f36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620261149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1620261149
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3089892322
Short name T486
Test name
Test status
Simulation time 45383414 ps
CPU time 2.84 seconds
Started Jun 24 06:16:37 PM PDT 24
Finished Jun 24 06:16:40 PM PDT 24
Peak memory 208112 kb
Host smart-68000e84-ea20-4ac0-a262-d7e0c6891943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089892322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3089892322
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3279829750
Short name T488
Test name
Test status
Simulation time 301727867 ps
CPU time 6.37 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:16:39 PM PDT 24
Peak memory 206976 kb
Host smart-77c31c97-9dfc-482a-a8ca-c7e81618732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279829750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3279829750
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3469302634
Short name T765
Test name
Test status
Simulation time 38837497 ps
CPU time 1.84 seconds
Started Jun 24 06:16:37 PM PDT 24
Finished Jun 24 06:16:39 PM PDT 24
Peak memory 206796 kb
Host smart-b4151340-9afa-4637-9466-fde30767a108
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469302634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3469302634
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2195181699
Short name T818
Test name
Test status
Simulation time 359741925 ps
CPU time 9.96 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:42 PM PDT 24
Peak memory 208912 kb
Host smart-65b768ec-b164-42ef-89e4-e546332025be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195181699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2195181699
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1540307519
Short name T575
Test name
Test status
Simulation time 1329893307 ps
CPU time 23.78 seconds
Started Jun 24 06:16:28 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 208484 kb
Host smart-d4fee4c6-52ac-4cf8-a689-4b2517082d84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540307519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1540307519
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.980612406
Short name T689
Test name
Test status
Simulation time 528605261 ps
CPU time 8.62 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:39 PM PDT 24
Peak memory 209904 kb
Host smart-fc23d2e4-038d-497d-be66-1ac840a8c8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980612406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.980612406
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3218430
Short name T522
Test name
Test status
Simulation time 53461664 ps
CPU time 2.7 seconds
Started Jun 24 06:16:32 PM PDT 24
Finished Jun 24 06:16:36 PM PDT 24
Peak memory 207120 kb
Host smart-02edd06b-990d-4b41-935d-b3158296ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3218430
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3886195208
Short name T196
Test name
Test status
Simulation time 1339354376 ps
CPU time 47.51 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:17:17 PM PDT 24
Peak memory 217032 kb
Host smart-02e9ccd9-6d33-441d-9cc1-bd2ea0076989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886195208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3886195208
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3850374455
Short name T603
Test name
Test status
Simulation time 220146052 ps
CPU time 9.35 seconds
Started Jun 24 06:16:36 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 222588 kb
Host smart-cd63276f-37d9-4c41-8f6b-f282092ca13e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850374455 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3850374455
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1117692050
Short name T330
Test name
Test status
Simulation time 317768023 ps
CPU time 8.14 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:38 PM PDT 24
Peak memory 214332 kb
Host smart-6e7cb0fb-7381-4dbb-9192-bc43d6403d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117692050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1117692050
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.205714427
Short name T563
Test name
Test status
Simulation time 367394556 ps
CPU time 3.71 seconds
Started Jun 24 06:16:30 PM PDT 24
Finished Jun 24 06:16:35 PM PDT 24
Peak memory 210388 kb
Host smart-e17ae31b-b9c9-4e2f-a5d5-47713dfd6157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205714427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.205714427
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1496092151
Short name T592
Test name
Test status
Simulation time 52851768 ps
CPU time 0.84 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 205924 kb
Host smart-5d793e57-2c5e-4a01-b65f-78fa0fbbe6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496092151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1496092151
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4037518779
Short name T286
Test name
Test status
Simulation time 283892666 ps
CPU time 3.92 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 214344 kb
Host smart-bff02e2a-97cb-405c-9d5a-9e9cdaf9cbe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037518779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4037518779
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2775587387
Short name T352
Test name
Test status
Simulation time 139415616 ps
CPU time 2.8 seconds
Started Jun 24 06:16:42 PM PDT 24
Finished Jun 24 06:16:47 PM PDT 24
Peak memory 218124 kb
Host smart-460530bc-7600-4e41-8567-ca869e2c4041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775587387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2775587387
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1361463912
Short name T339
Test name
Test status
Simulation time 77864990 ps
CPU time 4.12 seconds
Started Jun 24 06:16:38 PM PDT 24
Finished Jun 24 06:16:43 PM PDT 24
Peak memory 214300 kb
Host smart-476ac3b9-34f1-4172-a7e7-b3afe5231580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361463912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1361463912
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.131839328
Short name T621
Test name
Test status
Simulation time 93781219 ps
CPU time 3.25 seconds
Started Jun 24 06:16:38 PM PDT 24
Finished Jun 24 06:16:42 PM PDT 24
Peak memory 214236 kb
Host smart-c2a7f06f-d4bd-43ac-b5f0-59181cbdb64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131839328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.131839328
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.110117188
Short name T520
Test name
Test status
Simulation time 59429584 ps
CPU time 3.54 seconds
Started Jun 24 06:16:38 PM PDT 24
Finished Jun 24 06:16:42 PM PDT 24
Peak memory 220408 kb
Host smart-0ead1874-2cab-4ee8-8101-f67f3d71f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110117188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.110117188
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2636973828
Short name T604
Test name
Test status
Simulation time 138358972 ps
CPU time 4.61 seconds
Started Jun 24 06:16:28 PM PDT 24
Finished Jun 24 06:16:34 PM PDT 24
Peak memory 207352 kb
Host smart-7ff3be4a-d86a-4499-b4ed-a22c4827ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636973828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2636973828
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1208209109
Short name T335
Test name
Test status
Simulation time 1333040524 ps
CPU time 10.36 seconds
Started Jun 24 06:16:36 PM PDT 24
Finished Jun 24 06:16:47 PM PDT 24
Peak memory 208672 kb
Host smart-6a483a48-4703-4599-bfb8-57fdcbde3df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208209109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1208209109
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4127762491
Short name T764
Test name
Test status
Simulation time 291575086 ps
CPU time 5.27 seconds
Started Jun 24 06:16:31 PM PDT 24
Finished Jun 24 06:16:38 PM PDT 24
Peak memory 207824 kb
Host smart-7fb3f8f1-a643-4943-8add-a3a3f55e7ab0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127762491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4127762491
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2739324329
Short name T858
Test name
Test status
Simulation time 72274834 ps
CPU time 3.22 seconds
Started Jun 24 06:16:37 PM PDT 24
Finished Jun 24 06:16:41 PM PDT 24
Peak memory 206912 kb
Host smart-3c0ee9eb-0b06-469f-b4a1-1cd873e0360d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739324329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2739324329
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2207127197
Short name T712
Test name
Test status
Simulation time 403525972 ps
CPU time 3.06 seconds
Started Jun 24 06:16:36 PM PDT 24
Finished Jun 24 06:16:40 PM PDT 24
Peak memory 206804 kb
Host smart-61f1338f-ade4-454f-8652-b0a72ce8abae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207127197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2207127197
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2918383906
Short name T465
Test name
Test status
Simulation time 1578890108 ps
CPU time 2.72 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 218512 kb
Host smart-c5bb65f0-0f09-46dd-aaa5-6fa51abacfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918383906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2918383906
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1206109337
Short name T104
Test name
Test status
Simulation time 397218172 ps
CPU time 2.28 seconds
Started Jun 24 06:16:29 PM PDT 24
Finished Jun 24 06:16:32 PM PDT 24
Peak memory 206832 kb
Host smart-667cece7-595b-4561-99d0-063be410635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206109337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1206109337
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4125151584
Short name T246
Test name
Test status
Simulation time 112170008 ps
CPU time 3.75 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:47 PM PDT 24
Peak memory 214324 kb
Host smart-1d2aefe3-c455-4d56-8577-8e8ce0bded3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125151584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4125151584
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.522183619
Short name T55
Test name
Test status
Simulation time 94558565 ps
CPU time 1.79 seconds
Started Jun 24 06:16:43 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 210216 kb
Host smart-c60699e0-d2e5-4552-b639-1e91b9952473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522183619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.522183619
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4172538634
Short name T186
Test name
Test status
Simulation time 10928380 ps
CPU time 0.86 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:41 PM PDT 24
Peak memory 205928 kb
Host smart-dcc08b72-07c8-4a36-87a6-cc74c0415d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172538634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4172538634
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4262199746
Short name T402
Test name
Test status
Simulation time 32067100 ps
CPU time 2.58 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 214328 kb
Host smart-5e40ab0d-fed4-47ea-a195-1c5620322d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262199746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4262199746
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.890581868
Short name T232
Test name
Test status
Simulation time 160211261 ps
CPU time 6.32 seconds
Started Jun 24 06:16:42 PM PDT 24
Finished Jun 24 06:16:50 PM PDT 24
Peak memory 209376 kb
Host smart-e97aab7f-c466-4b63-a168-20c35adeed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890581868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.890581868
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2194866317
Short name T447
Test name
Test status
Simulation time 122872151 ps
CPU time 2.08 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:42 PM PDT 24
Peak memory 218444 kb
Host smart-8563f051-7b32-4fc7-a440-3a959da998e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194866317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2194866317
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2814214280
Short name T90
Test name
Test status
Simulation time 330781175 ps
CPU time 7.22 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:47 PM PDT 24
Peak memory 214300 kb
Host smart-ab7e7cb8-a9ec-44d1-9b1f-2edcc9170107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814214280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2814214280
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3024417558
Short name T305
Test name
Test status
Simulation time 1574748383 ps
CPU time 7.73 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 221524 kb
Host smart-11680baa-2f34-42a4-833c-36ede7423dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024417558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3024417558
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_random.3410386916
Short name T214
Test name
Test status
Simulation time 835436933 ps
CPU time 18.67 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:17:00 PM PDT 24
Peak memory 208024 kb
Host smart-e9b09f0e-dc8c-4851-8052-6ca028e4e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410386916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3410386916
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.140943667
Short name T703
Test name
Test status
Simulation time 248721410 ps
CPU time 3.82 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 208424 kb
Host smart-9d2d19a0-b375-44f8-8775-541f72c4f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140943667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.140943667
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2456076264
Short name T279
Test name
Test status
Simulation time 84022371 ps
CPU time 2.68 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 207008 kb
Host smart-20018edb-2fe1-463e-bbc1-3ea10a7f2f65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456076264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2456076264
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1686139710
Short name T420
Test name
Test status
Simulation time 1709836596 ps
CPU time 40.61 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:17:21 PM PDT 24
Peak memory 208660 kb
Host smart-fabfd7f7-561a-48bb-b6f9-c8a7668e8cec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686139710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1686139710
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.456545032
Short name T490
Test name
Test status
Simulation time 109456669 ps
CPU time 3 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 207028 kb
Host smart-b450c274-af15-4dfb-8199-12a83dc21262
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456545032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.456545032
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3290879449
Short name T552
Test name
Test status
Simulation time 225147373 ps
CPU time 3.7 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 209300 kb
Host smart-2d83a840-7649-4513-b293-f4e27f62b89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290879449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3290879449
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.899228466
Short name T382
Test name
Test status
Simulation time 262913636 ps
CPU time 2.42 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:43 PM PDT 24
Peak memory 207992 kb
Host smart-c8ed9407-829b-43d9-a5b7-e881fdff9c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899228466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.899228466
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3465146174
Short name T474
Test name
Test status
Simulation time 186471956 ps
CPU time 6.05 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:48 PM PDT 24
Peak memory 207192 kb
Host smart-26590ed4-4abd-4cda-bf14-3fcc8396a4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465146174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3465146174
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.655206920
Short name T730
Test name
Test status
Simulation time 42350383 ps
CPU time 0.75 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:41 PM PDT 24
Peak memory 205876 kb
Host smart-98899bbf-7bd5-4404-911e-85a06eb9ee26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655206920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.655206920
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1471691658
Short name T883
Test name
Test status
Simulation time 566168573 ps
CPU time 4.64 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:47 PM PDT 24
Peak memory 209544 kb
Host smart-b2f1ef57-09b0-44fa-9a9d-3faa9d1dd64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471691658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1471691658
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1144757762
Short name T677
Test name
Test status
Simulation time 33610621 ps
CPU time 1.99 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 207676 kb
Host smart-147b3204-0cae-4c1e-a0ff-0706994f19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144757762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1144757762
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1353325850
Short name T89
Test name
Test status
Simulation time 4185694475 ps
CPU time 86.68 seconds
Started Jun 24 06:16:42 PM PDT 24
Finished Jun 24 06:18:11 PM PDT 24
Peak memory 222316 kb
Host smart-1770f32f-caee-4bf9-a6d9-0fe00ac0ade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353325850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1353325850
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2898807435
Short name T784
Test name
Test status
Simulation time 326184334 ps
CPU time 2.57 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 214248 kb
Host smart-7b32cc19-5626-4062-9439-8f5637595338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898807435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2898807435
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4154123484
Short name T546
Test name
Test status
Simulation time 119167023 ps
CPU time 3.53 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 209964 kb
Host smart-b412deb7-b592-4462-a2ef-4aa9d0294a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154123484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4154123484
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3653879534
Short name T751
Test name
Test status
Simulation time 40317264 ps
CPU time 2.98 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 214296 kb
Host smart-a266a79c-d77c-424d-a398-772a7192ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653879534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3653879534
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1849926672
Short name T656
Test name
Test status
Simulation time 125564844 ps
CPU time 4.1 seconds
Started Jun 24 06:16:38 PM PDT 24
Finished Jun 24 06:16:43 PM PDT 24
Peak memory 206996 kb
Host smart-e22278c9-f057-483a-9e30-4c2404da2817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849926672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1849926672
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3814268482
Short name T912
Test name
Test status
Simulation time 1715107354 ps
CPU time 13.73 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:54 PM PDT 24
Peak memory 208384 kb
Host smart-827c3956-b773-4c90-825c-76b27052ea19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814268482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3814268482
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3430721156
Short name T423
Test name
Test status
Simulation time 549009330 ps
CPU time 7.6 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:49 PM PDT 24
Peak memory 208940 kb
Host smart-3d8e6ad3-cdaf-461f-a1a0-ccf340f55c63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430721156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3430721156
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.252686950
Short name T109
Test name
Test status
Simulation time 916949890 ps
CPU time 5.8 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:48 PM PDT 24
Peak memory 208132 kb
Host smart-45ccdde1-54c1-4064-9b3e-c82568927191
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252686950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.252686950
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2626636905
Short name T572
Test name
Test status
Simulation time 121221043 ps
CPU time 2.44 seconds
Started Jun 24 06:16:43 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 208104 kb
Host smart-204075c5-9efd-4aef-ae17-11b700d9e268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626636905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2626636905
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3385428036
Short name T458
Test name
Test status
Simulation time 100427516 ps
CPU time 3.24 seconds
Started Jun 24 06:16:39 PM PDT 24
Finished Jun 24 06:16:44 PM PDT 24
Peak memory 206800 kb
Host smart-810baf2a-bc8c-4d32-b30f-7fd0c50bfb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385428036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3385428036
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2900820384
Short name T110
Test name
Test status
Simulation time 5848017704 ps
CPU time 58.52 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:17:41 PM PDT 24
Peak memory 215252 kb
Host smart-c8d123de-3eb7-4eb6-8c78-fb83a6cee049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900820384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2900820384
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.65280935
Short name T596
Test name
Test status
Simulation time 565603224 ps
CPU time 10.68 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:54 PM PDT 24
Peak memory 219500 kb
Host smart-9670998d-d613-4137-bd94-4dff8daeeeaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65280935 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.65280935
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.415712265
Short name T836
Test name
Test status
Simulation time 109514403 ps
CPU time 2.33 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:16:45 PM PDT 24
Peak memory 209832 kb
Host smart-cae4a61e-1c54-4258-af6a-7f69a3030369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415712265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.415712265
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2824615830
Short name T36
Test name
Test status
Simulation time 30599519 ps
CPU time 1.7 seconds
Started Jun 24 06:16:43 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 209576 kb
Host smart-977fea35-c2c6-4252-8f22-15012cd4a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824615830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2824615830
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3384837459
Short name T878
Test name
Test status
Simulation time 12300031 ps
CPU time 0.88 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 205920 kb
Host smart-c9c77939-102e-4b4f-b244-4825a0dc6522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384837459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3384837459
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2098746766
Short name T405
Test name
Test status
Simulation time 41993785 ps
CPU time 3.12 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 214320 kb
Host smart-41a902a9-9c77-49f9-870a-959339e941b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098746766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2098746766
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2933271956
Short name T652
Test name
Test status
Simulation time 1176193850 ps
CPU time 7.22 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:59 PM PDT 24
Peak memory 208584 kb
Host smart-fbfcf930-8bca-407a-b760-be633f0bc24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933271956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2933271956
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.357478567
Short name T630
Test name
Test status
Simulation time 676290213 ps
CPU time 4.03 seconds
Started Jun 24 06:16:47 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 221488 kb
Host smart-95fc7b2e-a925-47c3-9e48-688ee9437f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357478567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.357478567
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.92237625
Short name T797
Test name
Test status
Simulation time 247440967 ps
CPU time 3.51 seconds
Started Jun 24 06:16:47 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 214880 kb
Host smart-8cc4ffed-97e5-46ac-a8e4-7754098233cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92237625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.92237625
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3305877210
Short name T838
Test name
Test status
Simulation time 96156644 ps
CPU time 4.29 seconds
Started Jun 24 06:16:51 PM PDT 24
Finished Jun 24 06:16:57 PM PDT 24
Peak memory 214316 kb
Host smart-d4d1ea49-ba90-40ac-bcfc-42b5f334b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305877210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3305877210
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3664438418
Short name T283
Test name
Test status
Simulation time 241129409 ps
CPU time 3.62 seconds
Started Jun 24 06:16:42 PM PDT 24
Finished Jun 24 06:16:48 PM PDT 24
Peak memory 209744 kb
Host smart-7d9ccacf-2b75-474d-9d75-b42a1b9cddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664438418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3664438418
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.258165694
Short name T268
Test name
Test status
Simulation time 175814757 ps
CPU time 4.31 seconds
Started Jun 24 06:16:43 PM PDT 24
Finished Jun 24 06:16:49 PM PDT 24
Peak memory 208684 kb
Host smart-02a4d15a-5846-45bc-9cfc-fbd276ab9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258165694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.258165694
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2735482119
Short name T577
Test name
Test status
Simulation time 78442856 ps
CPU time 3.57 seconds
Started Jun 24 06:16:45 PM PDT 24
Finished Jun 24 06:16:50 PM PDT 24
Peak memory 208824 kb
Host smart-96100571-f9b8-41a5-abd9-6029ed9e92fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735482119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2735482119
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4246316896
Short name T357
Test name
Test status
Simulation time 5127202739 ps
CPU time 25.12 seconds
Started Jun 24 06:16:40 PM PDT 24
Finished Jun 24 06:17:07 PM PDT 24
Peak memory 208588 kb
Host smart-cd64306c-1f82-4b4e-acb8-0d0e8e65a73c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246316896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4246316896
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.872831054
Short name T617
Test name
Test status
Simulation time 214585280 ps
CPU time 6.08 seconds
Started Jun 24 06:16:42 PM PDT 24
Finished Jun 24 06:16:50 PM PDT 24
Peak memory 208656 kb
Host smart-b8573199-ee28-4aac-8517-1653a4d2c211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872831054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.872831054
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4280206322
Short name T791
Test name
Test status
Simulation time 48718754 ps
CPU time 2.03 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 214320 kb
Host smart-e231d368-c9de-487c-89a8-4780fc576bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280206322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4280206322
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3859299539
Short name T709
Test name
Test status
Simulation time 231813746 ps
CPU time 2.8 seconds
Started Jun 24 06:16:41 PM PDT 24
Finished Jun 24 06:16:46 PM PDT 24
Peak memory 208428 kb
Host smart-f044330f-9032-4ebb-b854-f2cc440ea9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859299539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3859299539
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2299555090
Short name T793
Test name
Test status
Simulation time 912122317 ps
CPU time 11.73 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:17:04 PM PDT 24
Peak memory 214300 kb
Host smart-90be67bf-b844-4361-84ad-4088e6b54227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299555090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2299555090
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1764140885
Short name T202
Test name
Test status
Simulation time 263055065 ps
CPU time 1.83 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:52 PM PDT 24
Peak memory 210220 kb
Host smart-98399d41-16cd-499a-ba7e-c5b89fbf23aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764140885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1764140885
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2604612139
Short name T453
Test name
Test status
Simulation time 101008300 ps
CPU time 0.8 seconds
Started Jun 24 06:16:52 PM PDT 24
Finished Jun 24 06:16:54 PM PDT 24
Peak memory 205936 kb
Host smart-3c576cdc-0d35-4ce6-bd57-b6501b62b88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604612139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2604612139
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1284144517
Short name T600
Test name
Test status
Simulation time 83504239 ps
CPU time 2.39 seconds
Started Jun 24 06:16:48 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 208296 kb
Host smart-358d4949-4285-4a35-9783-615fe42fdcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284144517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1284144517
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3552251541
Short name T85
Test name
Test status
Simulation time 142070581 ps
CPU time 2.43 seconds
Started Jun 24 06:16:47 PM PDT 24
Finished Jun 24 06:16:50 PM PDT 24
Peak memory 214596 kb
Host smart-cfa58a67-5e9a-4ecf-a0ab-6fee21ac99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552251541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3552251541
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2546737301
Short name T254
Test name
Test status
Simulation time 147289144 ps
CPU time 6 seconds
Started Jun 24 06:16:51 PM PDT 24
Finished Jun 24 06:16:59 PM PDT 24
Peak memory 214232 kb
Host smart-64b39d45-c0af-46c6-a463-48b9cb247181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546737301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2546737301
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2600233897
Short name T619
Test name
Test status
Simulation time 60771302 ps
CPU time 2.46 seconds
Started Jun 24 06:16:48 PM PDT 24
Finished Jun 24 06:16:51 PM PDT 24
Peak memory 208656 kb
Host smart-bcdbb6a6-a914-48ca-8411-d58e58be2751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600233897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2600233897
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.917431630
Short name T314
Test name
Test status
Simulation time 14649587634 ps
CPU time 28.5 seconds
Started Jun 24 06:16:48 PM PDT 24
Finished Jun 24 06:17:17 PM PDT 24
Peak memory 214444 kb
Host smart-41a03840-1a7d-4b98-a402-944ab385b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917431630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.917431630
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3469686873
Short name T826
Test name
Test status
Simulation time 83374651 ps
CPU time 2 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:54 PM PDT 24
Peak memory 208456 kb
Host smart-431a2eed-6db0-46c3-90c5-803e1168a4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469686873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3469686873
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1224063484
Short name T249
Test name
Test status
Simulation time 253431765 ps
CPU time 3.97 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:56 PM PDT 24
Peak memory 208824 kb
Host smart-0f1c3291-db34-434e-9d7c-ba6448f18dbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224063484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1224063484
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1777670814
Short name T779
Test name
Test status
Simulation time 84264536 ps
CPU time 1.87 seconds
Started Jun 24 06:16:49 PM PDT 24
Finished Jun 24 06:16:53 PM PDT 24
Peak memory 206928 kb
Host smart-968348b9-e0b3-4db3-a8dd-e41557488bf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777670814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1777670814
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3745350777
Short name T424
Test name
Test status
Simulation time 560282563 ps
CPU time 3.25 seconds
Started Jun 24 06:16:50 PM PDT 24
Finished Jun 24 06:16:55 PM PDT 24
Peak memory 206984 kb
Host smart-a07dd841-f80f-4774-9338-a0f7c9d6a308
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745350777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3745350777
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.805665063
Short name T300
Test name
Test status
Simulation time 165675598 ps
CPU time 2.45 seconds
Started Jun 24 06:16:51 PM PDT 24
Finished Jun 24 06:16:55 PM PDT 24
Peak memory 209336 kb
Host smart-3ab7de36-88c3-4546-b7b2-d933def882ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805665063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.805665063
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.668881971
Short name T538
Test name
Test status
Simulation time 40933422 ps
CPU time 2.28 seconds
Started Jun 24 06:16:52 PM PDT 24
Finished Jun 24 06:16:56 PM PDT 24
Peak memory 208516 kb
Host smart-d94ce76d-f1ae-41ab-b7bb-d05e27a9cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668881971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.668881971
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1398637676
Short name T798
Test name
Test status
Simulation time 263899598 ps
CPU time 8.1 seconds
Started Jun 24 06:16:53 PM PDT 24
Finished Jun 24 06:17:02 PM PDT 24
Peak memory 215812 kb
Host smart-ca7762a5-e3ba-4c71-9de9-aa8ba7fb7268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398637676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1398637676
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2119912167
Short name T328
Test name
Test status
Simulation time 578834516 ps
CPU time 7.11 seconds
Started Jun 24 06:16:53 PM PDT 24
Finished Jun 24 06:17:01 PM PDT 24
Peak memory 208128 kb
Host smart-034c636b-0b9c-486d-b2d5-335d246d18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119912167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2119912167
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4154120113
Short name T80
Test name
Test status
Simulation time 20810388 ps
CPU time 0.84 seconds
Started Jun 24 06:13:34 PM PDT 24
Finished Jun 24 06:13:36 PM PDT 24
Peak memory 205892 kb
Host smart-de4f19c7-1d1b-427d-930d-8e606205ffba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154120113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4154120113
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4034681609
Short name T285
Test name
Test status
Simulation time 2679384487 ps
CPU time 37.44 seconds
Started Jun 24 06:13:28 PM PDT 24
Finished Jun 24 06:14:06 PM PDT 24
Peak memory 215688 kb
Host smart-5690d629-f8b6-41b7-93e0-9fd37f84f827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4034681609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4034681609
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3317660718
Short name T20
Test name
Test status
Simulation time 90991633 ps
CPU time 3.22 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 210544 kb
Host smart-c6a61f42-61e4-4815-b336-748cb5b81a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317660718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3317660718
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1494196424
Short name T780
Test name
Test status
Simulation time 72582578 ps
CPU time 2 seconds
Started Jun 24 06:13:34 PM PDT 24
Finished Jun 24 06:13:37 PM PDT 24
Peak memory 207340 kb
Host smart-85c733c3-6ca4-4ad0-a1c7-6d515510c764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494196424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1494196424
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3201101943
Short name T759
Test name
Test status
Simulation time 405237996 ps
CPU time 4.95 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:13:41 PM PDT 24
Peak memory 209312 kb
Host smart-659c8333-eca9-4e31-babf-4deea9cdd847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201101943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3201101943
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1460152418
Short name T747
Test name
Test status
Simulation time 72894578 ps
CPU time 3.28 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:13:39 PM PDT 24
Peak memory 214252 kb
Host smart-50aa7c6b-abe1-4c96-bc61-01ea4dc0696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460152418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1460152418
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4048767112
Short name T459
Test name
Test status
Simulation time 186037156 ps
CPU time 2.56 seconds
Started Jun 24 06:13:37 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 214636 kb
Host smart-f3cf95e3-c45e-484f-9e2a-cfb605d8c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048767112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4048767112
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3234666039
Short name T786
Test name
Test status
Simulation time 248836656 ps
CPU time 5.35 seconds
Started Jun 24 06:13:37 PM PDT 24
Finished Jun 24 06:13:43 PM PDT 24
Peak memory 209736 kb
Host smart-45c77179-c7c3-40eb-80ec-0308f2362c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234666039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3234666039
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3607688476
Short name T682
Test name
Test status
Simulation time 878207671 ps
CPU time 23.28 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:14:00 PM PDT 24
Peak memory 208436 kb
Host smart-17a4bd18-d441-4ea7-94d8-3cc67e1fe7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607688476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3607688476
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1051680773
Short name T469
Test name
Test status
Simulation time 404564043 ps
CPU time 3.24 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 208668 kb
Host smart-79459b12-15e7-4f3c-ad75-3c3fe95f25ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051680773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1051680773
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.764222256
Short name T480
Test name
Test status
Simulation time 1667110705 ps
CPU time 51.9 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:14:28 PM PDT 24
Peak memory 208380 kb
Host smart-7b61e1bd-9516-498d-982d-84953722b3cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764222256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.764222256
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1433058123
Short name T551
Test name
Test status
Simulation time 150895458 ps
CPU time 2.71 seconds
Started Jun 24 06:13:34 PM PDT 24
Finished Jun 24 06:13:37 PM PDT 24
Peak memory 208960 kb
Host smart-fd1fff6b-1c7f-4463-9cde-c3c7066e312b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433058123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1433058123
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1696138688
Short name T581
Test name
Test status
Simulation time 35283181 ps
CPU time 2.11 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 215444 kb
Host smart-a8745b77-974e-463e-a737-b933be357fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696138688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1696138688
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1686214710
Short name T693
Test name
Test status
Simulation time 477561307 ps
CPU time 3.37 seconds
Started Jun 24 06:13:37 PM PDT 24
Finished Jun 24 06:13:41 PM PDT 24
Peak memory 206708 kb
Host smart-0040f85e-1e52-4ed7-91dc-38fbfd9c0210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686214710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1686214710
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1620259290
Short name T723
Test name
Test status
Simulation time 1782865613 ps
CPU time 18.25 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:13:54 PM PDT 24
Peak memory 217688 kb
Host smart-8f1cff3b-afb3-450a-9a9f-1008670e38de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620259290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1620259290
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2434875839
Short name T707
Test name
Test status
Simulation time 646053611 ps
CPU time 5.69 seconds
Started Jun 24 06:13:35 PM PDT 24
Finished Jun 24 06:13:42 PM PDT 24
Peak memory 214284 kb
Host smart-1c0607b5-5439-4f05-b543-265868a5664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434875839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2434875839
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2152790800
Short name T63
Test name
Test status
Simulation time 95242777 ps
CPU time 3.51 seconds
Started Jun 24 06:13:36 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 210408 kb
Host smart-25d9e46f-9530-4ba0-a34c-2736cdea796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152790800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2152790800
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.418148974
Short name T900
Test name
Test status
Simulation time 63298856 ps
CPU time 0.98 seconds
Started Jun 24 06:13:37 PM PDT 24
Finished Jun 24 06:13:39 PM PDT 24
Peak memory 205912 kb
Host smart-49c367c4-bb69-4742-bc6e-d4cfc6ed1965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418148974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.418148974
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1885242225
Short name T681
Test name
Test status
Simulation time 55231040 ps
CPU time 1.86 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:43 PM PDT 24
Peak memory 207396 kb
Host smart-5c2ae5a4-7d6f-41a8-9635-c1f4e8a967ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885242225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1885242225
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2330590357
Short name T895
Test name
Test status
Simulation time 876404266 ps
CPU time 9.08 seconds
Started Jun 24 06:13:41 PM PDT 24
Finished Jun 24 06:13:51 PM PDT 24
Peak memory 208924 kb
Host smart-a3b7d1d3-1c2c-4077-b3fe-52968a4af845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330590357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2330590357
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3092751487
Short name T728
Test name
Test status
Simulation time 140695090 ps
CPU time 2.82 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 214248 kb
Host smart-bb4adcc9-5a66-4e40-8859-da09aa25884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092751487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3092751487
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4214301940
Short name T716
Test name
Test status
Simulation time 149455410 ps
CPU time 4.01 seconds
Started Jun 24 06:13:41 PM PDT 24
Finished Jun 24 06:13:46 PM PDT 24
Peak memory 209804 kb
Host smart-d4feaaa7-b39b-43f0-b456-6352e58047a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214301940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4214301940
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4232639855
Short name T333
Test name
Test status
Simulation time 2647174588 ps
CPU time 46.63 seconds
Started Jun 24 06:13:38 PM PDT 24
Finished Jun 24 06:14:26 PM PDT 24
Peak memory 208592 kb
Host smart-2707a543-4d9d-4b01-9e44-50b05beffe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232639855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4232639855
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.402800704
Short name T308
Test name
Test status
Simulation time 686290506 ps
CPU time 3.11 seconds
Started Jun 24 06:13:38 PM PDT 24
Finished Jun 24 06:13:42 PM PDT 24
Peak memory 208744 kb
Host smart-7984bffb-fad5-45ba-ab30-f7665febbbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402800704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.402800704
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1403520884
Short name T14
Test name
Test status
Simulation time 606796955 ps
CPU time 12.32 seconds
Started Jun 24 06:13:38 PM PDT 24
Finished Jun 24 06:13:51 PM PDT 24
Peak memory 207980 kb
Host smart-3303ff2e-f92f-4a75-b7d8-7f4cf465d065
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403520884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1403520884
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3249000065
Short name T628
Test name
Test status
Simulation time 41704893 ps
CPU time 2.79 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 208668 kb
Host smart-3c4edbf8-8680-49c7-b11a-7ef99f43c119
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249000065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3249000065
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3814514022
Short name T337
Test name
Test status
Simulation time 543343988 ps
CPU time 4.06 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:45 PM PDT 24
Peak memory 207064 kb
Host smart-a9981306-54fa-4600-bce8-0535509727b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814514022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3814514022
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.492879861
Short name T363
Test name
Test status
Simulation time 284483196 ps
CPU time 3.52 seconds
Started Jun 24 06:13:38 PM PDT 24
Finished Jun 24 06:13:42 PM PDT 24
Peak memory 218200 kb
Host smart-7181574a-16a2-4876-b299-6dbffaf3b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492879861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.492879861
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.48059211
Short name T500
Test name
Test status
Simulation time 86614381 ps
CPU time 1.65 seconds
Started Jun 24 06:13:37 PM PDT 24
Finished Jun 24 06:13:40 PM PDT 24
Peak memory 206696 kb
Host smart-15ecf68b-7ee8-48e4-a5a0-190a5ee01fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48059211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.48059211
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2359768398
Short name T225
Test name
Test status
Simulation time 4935009379 ps
CPU time 48.48 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:14:30 PM PDT 24
Peak memory 215488 kb
Host smart-b9c846a3-15ee-4783-b72f-3f2857bf10f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359768398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2359768398
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3097788848
Short name T917
Test name
Test status
Simulation time 550761952 ps
CPU time 8.22 seconds
Started Jun 24 06:13:38 PM PDT 24
Finished Jun 24 06:13:47 PM PDT 24
Peak memory 222568 kb
Host smart-7a4dc0d4-420c-4c60-90ba-843f7779254c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097788848 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3097788848
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2459153931
Short name T761
Test name
Test status
Simulation time 959195584 ps
CPU time 32.29 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:14:14 PM PDT 24
Peak memory 209356 kb
Host smart-6487db12-65d6-4514-9c44-e5eead431116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459153931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2459153931
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2064019756
Short name T441
Test name
Test status
Simulation time 229098368 ps
CPU time 2.64 seconds
Started Jun 24 06:13:41 PM PDT 24
Finished Jun 24 06:13:45 PM PDT 24
Peak memory 210320 kb
Host smart-4ef7ff8d-f1d0-4af3-88f8-25f574682ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064019756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2064019756
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.4057689074
Short name T748
Test name
Test status
Simulation time 20119757 ps
CPU time 0.82 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:13:54 PM PDT 24
Peak memory 205924 kb
Host smart-df9a2067-9aca-40b0-86c1-77335b1a8196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057689074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4057689074
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.865869106
Short name T119
Test name
Test status
Simulation time 130647212 ps
CPU time 3.78 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:59 PM PDT 24
Peak memory 214312 kb
Host smart-feebf2e8-d238-4394-a96c-5f0bb430d6af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865869106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.865869106
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3933695405
Short name T512
Test name
Test status
Simulation time 402032389 ps
CPU time 4.59 seconds
Started Jun 24 06:13:54 PM PDT 24
Finished Jun 24 06:14:00 PM PDT 24
Peak memory 217176 kb
Host smart-784f9f89-3fe8-4a4e-ba24-541e6efbea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933695405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3933695405
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3277240931
Short name T311
Test name
Test status
Simulation time 62229261 ps
CPU time 2.49 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:57 PM PDT 24
Peak memory 214336 kb
Host smart-a4389c89-77ac-4bb3-9d08-499205e40997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277240931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3277240931
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1301783904
Short name T96
Test name
Test status
Simulation time 63384075 ps
CPU time 2.48 seconds
Started Jun 24 06:13:51 PM PDT 24
Finished Jun 24 06:13:54 PM PDT 24
Peak memory 209484 kb
Host smart-61002864-bd2d-49c3-9d2f-bcb20250fdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301783904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1301783904
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2160987658
Short name T665
Test name
Test status
Simulation time 172466156 ps
CPU time 6.54 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:13:59 PM PDT 24
Peak memory 214300 kb
Host smart-9acb11d9-379d-460c-8d2d-ab609cba10ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160987658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2160987658
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4211118836
Short name T595
Test name
Test status
Simulation time 226638181 ps
CPU time 4.2 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:59 PM PDT 24
Peak memory 218108 kb
Host smart-e1fd21ef-364c-44f9-b6d9-b8e567e58573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211118836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4211118836
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1367417659
Short name T627
Test name
Test status
Simulation time 65322717 ps
CPU time 2.98 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:13:56 PM PDT 24
Peak memory 209464 kb
Host smart-b6b83c8a-3a7a-4778-97de-a4f7ff7e108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367417659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1367417659
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2481200329
Short name T886
Test name
Test status
Simulation time 42623853 ps
CPU time 2.28 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 208016 kb
Host smart-62143daf-11a1-41af-9f45-5a44bef02ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481200329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2481200329
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.982702914
Short name T853
Test name
Test status
Simulation time 42381427 ps
CPU time 2.57 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 207052 kb
Host smart-5b3db5dd-554c-4c47-aacb-c8568ac1c28b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982702914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.982702914
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.14530672
Short name T871
Test name
Test status
Simulation time 273587669 ps
CPU time 2.9 seconds
Started Jun 24 06:13:40 PM PDT 24
Finished Jun 24 06:13:44 PM PDT 24
Peak memory 206808 kb
Host smart-a985da1e-5173-4e1b-a1b8-525727c5d7ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.14530672
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.401040666
Short name T668
Test name
Test status
Simulation time 163995943 ps
CPU time 2.39 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:56 PM PDT 24
Peak memory 206976 kb
Host smart-6e1bf2d2-e39d-4b53-bbcd-01abdedf920c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401040666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.401040666
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.748198086
Short name T344
Test name
Test status
Simulation time 114682760 ps
CPU time 4.16 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:59 PM PDT 24
Peak memory 214352 kb
Host smart-1021f71e-21af-4f29-ac3d-a7c780cb2ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748198086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.748198086
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2057388939
Short name T407
Test name
Test status
Simulation time 1458602306 ps
CPU time 4.08 seconds
Started Jun 24 06:13:41 PM PDT 24
Finished Jun 24 06:13:46 PM PDT 24
Peak memory 208516 kb
Host smart-c0e99478-bebd-425c-a419-c71bda13c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057388939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2057388939
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1819187130
Short name T247
Test name
Test status
Simulation time 6143302140 ps
CPU time 62.05 seconds
Started Jun 24 06:13:51 PM PDT 24
Finished Jun 24 06:14:54 PM PDT 24
Peak memory 216168 kb
Host smart-6d9de929-fc32-440c-ac9e-56c9126850a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819187130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1819187130
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2629712027
Short name T126
Test name
Test status
Simulation time 709701041 ps
CPU time 9.48 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:14:02 PM PDT 24
Peak memory 219504 kb
Host smart-51401280-5c20-4bc7-935e-5b0c08140f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629712027 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2629712027
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3798495351
Short name T211
Test name
Test status
Simulation time 175689636 ps
CPU time 6.76 seconds
Started Jun 24 06:13:54 PM PDT 24
Finished Jun 24 06:14:02 PM PDT 24
Peak memory 208264 kb
Host smart-06587a5e-1ab8-4e94-a329-a00b16f8d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798495351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3798495351
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2513856859
Short name T774
Test name
Test status
Simulation time 951181776 ps
CPU time 3.2 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:57 PM PDT 24
Peak memory 210200 kb
Host smart-1c1bddad-99c7-4642-91c4-04024c44dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513856859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2513856859
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2888945631
Short name T418
Test name
Test status
Simulation time 11167669 ps
CPU time 0.77 seconds
Started Jun 24 06:14:07 PM PDT 24
Finished Jun 24 06:14:09 PM PDT 24
Peak memory 205920 kb
Host smart-833cba2e-297a-41c9-a86e-0e7c6100066f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888945631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2888945631
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1467219803
Short name T393
Test name
Test status
Simulation time 271212962 ps
CPU time 3.98 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:58 PM PDT 24
Peak memory 214312 kb
Host smart-e08fdab6-2732-4297-a2ea-3ac06da19683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467219803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1467219803
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3781980820
Short name T699
Test name
Test status
Simulation time 79860501 ps
CPU time 2.72 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:13:55 PM PDT 24
Peak memory 209624 kb
Host smart-7c64e129-3d8c-4367-acee-a4c8e5dba051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781980820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3781980820
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.238294995
Short name T73
Test name
Test status
Simulation time 241178679 ps
CPU time 4.31 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:59 PM PDT 24
Peak memory 208112 kb
Host smart-1520941b-8817-4c1b-8c08-5f9279de2663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238294995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.238294995
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1072138117
Short name T710
Test name
Test status
Simulation time 63811199 ps
CPU time 2.69 seconds
Started Jun 24 06:13:54 PM PDT 24
Finished Jun 24 06:13:58 PM PDT 24
Peak memory 214404 kb
Host smart-9da7a055-3635-4f9d-a51c-17802802dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072138117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1072138117
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3301805675
Short name T863
Test name
Test status
Simulation time 244423577 ps
CPU time 2.65 seconds
Started Jun 24 06:13:51 PM PDT 24
Finished Jun 24 06:13:54 PM PDT 24
Peak memory 209492 kb
Host smart-daa7c8a2-158c-4abe-9b65-4d435336cdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301805675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3301805675
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3560606128
Short name T206
Test name
Test status
Simulation time 244962531 ps
CPU time 3.42 seconds
Started Jun 24 06:13:51 PM PDT 24
Finished Jun 24 06:13:55 PM PDT 24
Peak memory 214416 kb
Host smart-32cd0d9e-eacb-45b6-96de-01abad476a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560606128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3560606128
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4027878940
Short name T649
Test name
Test status
Simulation time 78429301 ps
CPU time 1.79 seconds
Started Jun 24 06:13:54 PM PDT 24
Finished Jun 24 06:13:57 PM PDT 24
Peak memory 206884 kb
Host smart-f13f6954-654e-4e66-bcbf-9c13795e4d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027878940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4027878940
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3983104738
Short name T248
Test name
Test status
Simulation time 131382120 ps
CPU time 3.34 seconds
Started Jun 24 06:13:55 PM PDT 24
Finished Jun 24 06:13:59 PM PDT 24
Peak memory 208664 kb
Host smart-b2fbc6a8-0e64-4469-9812-1c0c872d59b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983104738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3983104738
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2802568182
Short name T544
Test name
Test status
Simulation time 260765943 ps
CPU time 4.2 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:13:57 PM PDT 24
Peak memory 206960 kb
Host smart-a9881204-e4e3-4f2e-a7ca-f48c16c1682f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802568182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2802568182
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.290395312
Short name T503
Test name
Test status
Simulation time 146711733 ps
CPU time 3.29 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:57 PM PDT 24
Peak memory 208800 kb
Host smart-2d7f8f93-dc42-4686-9c38-d931b699a749
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290395312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.290395312
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2132135544
Short name T746
Test name
Test status
Simulation time 168324605 ps
CPU time 3.89 seconds
Started Jun 24 06:13:51 PM PDT 24
Finished Jun 24 06:13:55 PM PDT 24
Peak memory 209892 kb
Host smart-c0e81137-5d02-449c-97a2-bf8eeac3544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132135544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2132135544
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3776294252
Short name T638
Test name
Test status
Simulation time 61373764 ps
CPU time 2.82 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:58 PM PDT 24
Peak memory 207980 kb
Host smart-a658d0b6-51b9-4e8a-b3b6-89cf21cc1671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776294252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3776294252
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2064695762
Short name T889
Test name
Test status
Simulation time 1357057921 ps
CPU time 43.04 seconds
Started Jun 24 06:13:52 PM PDT 24
Finished Jun 24 06:14:36 PM PDT 24
Peak memory 222468 kb
Host smart-3ec85075-4bc4-4b28-9ffd-332fe9a5c951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064695762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2064695762
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.93955379
Short name T446
Test name
Test status
Simulation time 155347879 ps
CPU time 4.45 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:58 PM PDT 24
Peak memory 209184 kb
Host smart-095c3a84-f4e1-4f31-b4b2-3a30851aa676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93955379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.93955379
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.73077220
Short name T526
Test name
Test status
Simulation time 100218758 ps
CPU time 2.87 seconds
Started Jun 24 06:13:53 PM PDT 24
Finished Jun 24 06:13:57 PM PDT 24
Peak memory 209876 kb
Host smart-b2b83a98-7cf7-47d7-8ad2-6a0d1a6c7ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73077220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.73077220
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1633251033
Short name T427
Test name
Test status
Simulation time 84065469 ps
CPU time 0.78 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:09 PM PDT 24
Peak memory 205928 kb
Host smart-0be37682-0d2a-404c-a6ed-a0f78a973626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633251033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1633251033
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.553463817
Short name T136
Test name
Test status
Simulation time 201699681 ps
CPU time 4.04 seconds
Started Jun 24 06:14:06 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 214300 kb
Host smart-ff364656-b251-49db-9a54-8c2e6775fa3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553463817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.553463817
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2994723357
Short name T726
Test name
Test status
Simulation time 63165234 ps
CPU time 3.82 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 222804 kb
Host smart-b610af96-0623-460a-ad04-f8f0d39e69bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994723357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2994723357
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.595758055
Short name T83
Test name
Test status
Simulation time 75134900 ps
CPU time 3.48 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:14 PM PDT 24
Peak memory 208036 kb
Host smart-e1d8f981-3755-4be7-bf56-93ad8d458d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595758055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.595758055
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2075798652
Short name T319
Test name
Test status
Simulation time 87603722 ps
CPU time 2.63 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 220932 kb
Host smart-17985ce4-aa6a-4ab6-a5e2-d093bf41186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075798652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2075798652
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2050286921
Short name T555
Test name
Test status
Simulation time 268576913 ps
CPU time 3.57 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:12 PM PDT 24
Peak memory 222368 kb
Host smart-6fa59b0f-0562-491a-92f3-8b06642fc9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050286921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2050286921
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3378321119
Short name T230
Test name
Test status
Simulation time 42494599 ps
CPU time 2.96 seconds
Started Jun 24 06:14:12 PM PDT 24
Finished Jun 24 06:14:16 PM PDT 24
Peak memory 208336 kb
Host smart-838cab9c-a9cf-4756-81da-aa8cb11943d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378321119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3378321119
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.628116111
Short name T844
Test name
Test status
Simulation time 3280195239 ps
CPU time 11.55 seconds
Started Jun 24 06:14:09 PM PDT 24
Finished Jun 24 06:14:21 PM PDT 24
Peak memory 209996 kb
Host smart-60939f81-457b-4720-ab23-611a5e37f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628116111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.628116111
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1874673295
Short name T680
Test name
Test status
Simulation time 639727309 ps
CPU time 4.91 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:14 PM PDT 24
Peak memory 208588 kb
Host smart-d69c944b-08da-4889-8220-ece977211ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874673295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1874673295
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1429963530
Short name T466
Test name
Test status
Simulation time 256831647 ps
CPU time 3.94 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:14 PM PDT 24
Peak memory 207620 kb
Host smart-5bc3719d-c830-4ca4-8277-08d8d2064873
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429963530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1429963530
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2989498672
Short name T911
Test name
Test status
Simulation time 22317322726 ps
CPU time 52.03 seconds
Started Jun 24 06:14:09 PM PDT 24
Finished Jun 24 06:15:02 PM PDT 24
Peak memory 208840 kb
Host smart-5835ce42-41c7-4857-81d9-a0663a739112
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989498672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2989498672
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.315152170
Short name T207
Test name
Test status
Simulation time 654664747 ps
CPU time 6.44 seconds
Started Jun 24 06:14:07 PM PDT 24
Finished Jun 24 06:14:14 PM PDT 24
Peak memory 208512 kb
Host smart-bc4a37bf-000a-491a-9cef-9ec170dba4f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315152170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.315152170
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.700986554
Short name T261
Test name
Test status
Simulation time 40564851 ps
CPU time 2.11 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 215496 kb
Host smart-aa7d818b-c3c3-4ec6-b9a3-ad5e394d53a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700986554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.700986554
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2225593984
Short name T622
Test name
Test status
Simulation time 146548606 ps
CPU time 3.46 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:13 PM PDT 24
Peak memory 207144 kb
Host smart-d0d41618-14db-4c81-81f9-3718be7f0c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225593984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2225593984
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2098129407
Short name T7
Test name
Test status
Simulation time 2241287307 ps
CPU time 54.81 seconds
Started Jun 24 06:14:10 PM PDT 24
Finished Jun 24 06:15:05 PM PDT 24
Peak memory 216288 kb
Host smart-0a8b4dd6-76e6-4ad7-8bec-19aa6641442b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098129407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2098129407
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1517313638
Short name T177
Test name
Test status
Simulation time 382976811 ps
CPU time 16.24 seconds
Started Jun 24 06:14:06 PM PDT 24
Finished Jun 24 06:14:23 PM PDT 24
Peak memory 222608 kb
Host smart-9c7efdde-6e19-4bec-afa2-742d4a4fa90a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517313638 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1517313638
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1158623002
Short name T343
Test name
Test status
Simulation time 84444997 ps
CPU time 4.1 seconds
Started Jun 24 06:14:14 PM PDT 24
Finished Jun 24 06:14:20 PM PDT 24
Peak memory 207668 kb
Host smart-9ef2c5c3-6189-4912-96ca-9fbd2b7e0961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158623002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1158623002
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2057585498
Short name T718
Test name
Test status
Simulation time 38773281 ps
CPU time 1.61 seconds
Started Jun 24 06:14:08 PM PDT 24
Finished Jun 24 06:14:11 PM PDT 24
Peak memory 210144 kb
Host smart-d9871601-635a-41ea-9ec2-ef1854767bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057585498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2057585498
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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