Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	44	1			T46	3		T47	3		T48	1
auto[OpGenId]	19	1			T1	1		T6	1		T80	1
auto[OpGenSwOut]	31	1			T46	1		T55	1		T54	1
auto[OpGenHwOut]	20	1			T6	4		T7	1		T77	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1762	1			T1	1		T15	1		T18	1
auto[StInit]	97	1			T3	1		T17	1		T6	5
auto[StCreatorRootKey]	55	1			T18	1		T38	1		T6	1
auto[StOwnerIntKey]	48	1			T1	1		T8	1		T119	1
auto[StOwnerKey]	42	1			T36	1		T47	1		T62	1
auto[StDisabled]	491	1			T1	9		T5	4		T15	4
auto[StInvalid]	50	1			T14	1		T37	1		T26	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3516

1

T1

11

T2

1

T3

2

auto[1]

114

1

T1

1

T6

5

T46

4

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1757	1			T1	1		T15	1		T18	1
auto[StReset]	auto[1]	5	1			T46	1		T141	1		T51	1
auto[StInit]	auto[0]	42	1			T3	1		T17	1		T120	1
auto[StInit]	auto[1]	55	1			T6	5		T46	3		T55	1
auto[StCreatorRootKey]	auto[0]	36	1			T18	1		T38	1		T6	1
auto[StCreatorRootKey]	auto[1]	19	1			T47	2		T48	1		T121	1
auto[StOwnerIntKey]	auto[0]	33	1			T119	1		T61	1		T56	1
auto[StOwnerIntKey]	auto[1]	15	1			T1	1		T8	1		T59	1
auto[StOwnerKey]	auto[0]	29	1			T36	1		T120	1		T43	1
auto[StOwnerKey]	auto[1]	13	1			T47	1		T62	1		T63	1
auto[StDisabled]	auto[0]	484	1			T1	9		T5	4		T15	4
auto[StDisabled]	auto[1]	7	1			T7	1		T203	1		T204	1
auto[StInvalid]	auto[0]	50	1			T14	1		T37	1		T26	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	5	1			T46	1		T141	1		T51	1
auto[StInit]	auto[OpAdvance]	17	1			T46	2		T28	1		T205	3
auto[StInit]	auto[OpGenId]	15	1			T6	1		T80	1		T66	1
auto[StInit]	auto[OpGenSwOut]	14	1			T46	1		T55	1		T54	1
auto[StInit]	auto[OpGenHwOut]	9	1			T6	4		T77	1		T206	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T47	2		T48	1		T207	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T208	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T64	1		T209	1		T210	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T121	1		T211	1		T212	1
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T72	1		T142	1		T213	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T1	1		T214	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T59	1		T215	1		T216	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T8	1		T217	1		T218	1
auto[StOwnerKey]	auto[OpAdvance]	5	1			T47	1		T63	1		T219	1
auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T62	1		T220	1		T221	1
auto[StOwnerKey]	auto[OpGenHwOut]	4	1			T64	1		T222	1		T223	1
auto[StDisabled]	auto[OpAdvance]	3	1			T203	1		T204	1		T224	1
auto[StDisabled]	auto[OpGenId]	1	1			T225	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T226	1		T224	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T7	1		-	-		-	-