Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11154

1

T1

73

T2

5

T4

5

auto[Attestation]

7813

1

T1

44

T2

5

T4

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2748	1			T1	20		T2	1		T5	10
auto[Aes]	3404	1			T1	20		T2	2		T5	9
auto[Kmac]	3337	1			T1	23		T5	9		T15	10
auto[Otbn]	3403	1			T1	19		T2	2		T4	11

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7985	1			T1	75		T2	3		T3	1
auto[OpGenId]	6075	1			T1	35		T2	5		T5	14
auto[OpGenSwOut]	5888	1			T1	42		T2	3		T5	23
auto[OpGenHwOut]	7004	1			T1	40		T2	2		T4	11
auto[OpDisable]	130	1			T2	1		T5	2		T49	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10878

1

T1

79

T2

10

T3

1

auto[OpDoneFail]

16204

1

T1

113

T2

4

T4

11

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6303	1			T1	41		T2	1		T3	1
auto[StInit]	3893	1			T1	26		T2	4		T4	2
auto[StCreatorRootKey]	3217	1			T1	19		T2	5		T4	2
auto[StOwnerIntKey]	2831	1			T1	22		T2	3		T4	2
auto[StOwnerKey]	2547	1			T1	20		T4	2		T5	10
auto[StDisabled]	8291	1			T1	64		T2	1		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	315	1			T1	3		T35	1		T83	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T5	1		T18	1		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T5	1		T200	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T5	1		T83	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T1	1		T5	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	235	1			T1	4		T5	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	326	1			T1	4		T16	3		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	87	1			T5	1		T15	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	80	1			T5	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T5	1		T18	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	72	1			T1	1		T36	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	202	1			T1	1		T18	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	305	1			T1	1		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	108	1			T1	2		T5	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	69	1			T1	1		T5	1		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	70	1			T1	1		T34	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	61	1			T5	1		T46	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	217	1			T1	3		T5	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	313	1			T1	2		T35	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	100	1			T1	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T1	2		T18	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T200	1		T46	1		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	61	1			T1	1		T5	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	249	1			T1	3		T15	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T6	2		T120	1		T121	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	111	1			T15	1		T34	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T60	1		T46	2		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T1	1		T46	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	76	1			T5	1		T83	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	212	1			T5	1		T15	3		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T18	1		T49	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	90	1			T1	1		T15	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T2	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	59	1			T2	1		T192	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	54	1			T1	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	224	1			T1	2		T5	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T18	1		T49	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	120	1			T1	1		T15	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	86	1			T5	1		T36	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T1	1		T49	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	73	1			T1	1		T6	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	251	1			T1	1		T5	1		T15	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T49	2		T6	2		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T2	1		T15	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T6	3		T7	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T18	1		T6	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	58	1			T189	1		T8	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	235	1			T1	2		T5	2		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	294	1			T1	2		T18	5		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	119	1			T1	2		T34	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T5	2		T49	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T1	1		T83	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T15	1		T16	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	175	1			T5	1		T15	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	496	1			T1	2		T16	2		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	128	1			T5	1		T15	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	109	1			T1	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T1	1		T18	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	91	1			T84	1		T46	1		T192	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	264	1			T1	1		T5	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	429	1			T1	1		T18	3		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T16	1		T35	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T35	1		T125	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T1	2		T34	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	95	1			T5	1		T15	2		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	275	1			T1	1		T16	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	443	1			T1	2		T4	3		T16	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T1	2		T6	2		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T2	1		T18	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T4	1		T15	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	96	1			T34	1		T192	1		T8	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	279	1			T1	1		T4	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T49	1		T119	2		T120	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	105	1			T1	2		T2	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	70	1			T6	1		T8	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T1	1		T189	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T1	1		T49	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	156	1			T1	2		T15	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T1	1		T15	1		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T15	1		T83	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	117	1			T1	1		T38	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T5	1		T15	3		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	97	1			T34	2		T7	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	292	1			T1	3		T5	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	49	1			T1	1		T49	1		T6	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T1	3		T5	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T1	1		T16	1		T191	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	111	1			T36	1		T6	2		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	88	1			T34	1		T83	1		T8	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	291	1			T1	2		T16	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	48	1			T6	2		T120	1		T121	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	128	1			T4	1		T15	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T4	1		T5	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T16	1		T18	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T1	1		T4	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	290	1			T1	2		T4	3		T5	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T1	1		T5	3		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	670	1			T1	7		T5	2		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	216	1			T1	1		T5	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	636	1			T1	5		T5	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	190	1			T1	1		T5	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	640	1			T1	7		T5	3		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	188	1			T1	3		T5	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	677	1			T1	6		T5	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T1	1		T5	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	414	1			T5	1		T15	4		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	200	1			T1	1		T2	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	400	1			T1	3		T5	2		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T1	2		T5	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	441	1			T1	2		T5	1		T15	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	201	1			T18	1		T6	4		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	429	1			T1	2		T2	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	197	1			T1	1		T5	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	599	1			T1	4		T5	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	281	1			T1	2		T15	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	905	1			T1	3		T5	2		T15	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T1	1		T5	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	840	1			T1	3		T16	2		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	286	1			T2	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	862	1			T1	5		T4	4		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	167	1			T1	2		T49	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	331	1			T1	4		T2	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	279	1			T1	1		T5	1		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	487	1			T1	4		T5	1		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T1	1		T16	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	470	1			T1	6		T5	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T1	1		T4	2		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	481	1			T1	2		T4	4		T5	1