Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33466

1

T1

225

T2

16

T3

1

auto[1]

273

1

T16

6

T125

5

T82

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33475	1			T1	225		T2	16		T3	1
auto[134217728:268435455]	1	1			T357	1		-	-		-	-
auto[268435456:402653183]	3	1			T268	1		T394	1		T410	1
auto[402653184:536870911]	10	1			T128	1		T182	1		T361	1
auto[536870912:671088639]	7	1			T394	1		T411	1		T406	1
auto[671088640:805306367]	6	1			T16	1		T411	1		T286	1
auto[805306368:939524095]	8	1			T127	1		T361	1		T327	1
auto[939524096:1073741823]	10	1			T125	1		T268	1		T394	1
auto[1073741824:1207959551]	10	1			T16	1		T128	1		T309	1
auto[1207959552:1342177279]	12	1			T125	1		T127	1		T128	1
auto[1342177280:1476395007]	10	1			T314	1		T129	1		T394	1
auto[1476395008:1610612735]	11	1			T127	1		T128	1		T309	1
auto[1610612736:1744830463]	10	1			T82	1		T237	2		T394	1
auto[1744830464:1879048191]	11	1			T82	1		T128	1		T237	1
auto[1879048192:2013265919]	11	1			T125	2		T127	1		T309	1
auto[2013265920:2147483647]	10	1			T309	3		T182	1		T327	1
auto[2147483648:2281701375]	6	1			T309	1		T327	1		T412	2
auto[2281701376:2415919103]	10	1			T314	1		T285	1		T394	1
auto[2415919104:2550136831]	13	1			T285	2		T394	1		T327	3
auto[2550136832:2684354559]	15	1			T127	1		T129	1		T394	2
auto[2684354560:2818572287]	12	1			T16	2		T125	1		T82	1
auto[2818572288:2952790015]	12	1			T16	2		T352	1		T129	1
auto[2952790016:3087007743]	5	1			T82	1		T394	1		T411	1
auto[3087007744:3221225471]	7	1			T182	1		T268	1		T228	1
auto[3221225472:3355443199]	6	1			T82	1		T314	1		T268	1
auto[3355443200:3489660927]	7	1			T127	1		T394	1		T413	1
auto[3489660928:3623878655]	3	1			T82	1		T300	2		-	-
auto[3623878656:3758096383]	7	1			T127	1		T411	1		T414	1
auto[3758096384:3892314111]	10	1			T128	1		T285	1		T268	1
auto[3892314112:4026531839]	5	1			T127	1		T314	1		T406	1
auto[4026531840:4160749567]	4	1			T361	1		T415	1		T410	1
auto[4160749568:4294967295]	12	1			T285	1		T268	1		T411	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33466	1			T1	225		T2	16		T3	1
auto[0:134217727]	auto[1]	9	1			T82	2		T314	1		T406	1
auto[134217728:268435455]	auto[1]	1	1			T357	1		-	-		-	-
auto[268435456:402653183]	auto[1]	3	1			T268	1		T394	1		T410	1
auto[402653184:536870911]	auto[1]	10	1			T128	1		T182	1		T361	1
auto[536870912:671088639]	auto[1]	7	1			T394	1		T411	1		T406	1
auto[671088640:805306367]	auto[1]	6	1			T16	1		T411	1		T286	1
auto[805306368:939524095]	auto[1]	8	1			T127	1		T361	1		T327	1
auto[939524096:1073741823]	auto[1]	10	1			T125	1		T268	1		T394	1
auto[1073741824:1207959551]	auto[1]	10	1			T16	1		T128	1		T309	1
auto[1207959552:1342177279]	auto[1]	12	1			T125	1		T127	1		T128	1
auto[1342177280:1476395007]	auto[1]	10	1			T314	1		T129	1		T394	1
auto[1476395008:1610612735]	auto[1]	11	1			T127	1		T128	1		T309	1
auto[1610612736:1744830463]	auto[1]	10	1			T82	1		T237	2		T394	1
auto[1744830464:1879048191]	auto[1]	11	1			T82	1		T128	1		T237	1
auto[1879048192:2013265919]	auto[1]	11	1			T125	2		T127	1		T309	1
auto[2013265920:2147483647]	auto[1]	10	1			T309	3		T182	1		T327	1
auto[2147483648:2281701375]	auto[1]	6	1			T309	1		T327	1		T412	2
auto[2281701376:2415919103]	auto[1]	10	1			T314	1		T285	1		T394	1
auto[2415919104:2550136831]	auto[1]	13	1			T285	2		T394	1		T327	3
auto[2550136832:2684354559]	auto[1]	15	1			T127	1		T129	1		T394	2
auto[2684354560:2818572287]	auto[1]	12	1			T16	2		T125	1		T82	1
auto[2818572288:2952790015]	auto[1]	12	1			T16	2		T352	1		T129	1
auto[2952790016:3087007743]	auto[1]	5	1			T82	1		T394	1		T411	1
auto[3087007744:3221225471]	auto[1]	7	1			T182	1		T268	1		T228	1
auto[3221225472:3355443199]	auto[1]	6	1			T82	1		T314	1		T268	1
auto[3355443200:3489660927]	auto[1]	7	1			T127	1		T394	1		T413	1
auto[3489660928:3623878655]	auto[1]	3	1			T82	1		T300	2		-	-
auto[3623878656:3758096383]	auto[1]	7	1			T127	1		T411	1		T414	1
auto[3758096384:3892314111]	auto[1]	10	1			T128	1		T285	1		T268	1
auto[3892314112:4026531839]	auto[1]	5	1			T127	1		T314	1		T406	1
auto[4026531840:4160749567]	auto[1]	4	1			T361	1		T415	1		T410	1
auto[4160749568:4294967295]	auto[1]	12	1			T285	1		T268	1		T411	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T1

5

T2

1

T5

1

auto[1]

1756

1

T1

2

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T18	1		T6	3		T189	1
auto[134217728:268435455]	88	1			T1	1		T2	1		T15	1
auto[268435456:402653183]	113	1			T18	1		T46	3		T55	1
auto[402653184:536870911]	94	1			T14	1		T83	1		T6	1
auto[536870912:671088639]	107	1			T6	2		T7	1		T77	1
auto[671088640:805306367]	107	1			T7	2		T8	1		T82	1
auto[805306368:939524095]	107	1			T83	1		T49	1		T6	1
auto[939524096:1073741823]	121	1			T14	1		T16	1		T6	1
auto[1073741824:1207959551]	102	1			T15	2		T46	1		T192	1
auto[1207959552:1342177279]	110	1			T6	2		T46	3		T47	4
auto[1342177280:1476395007]	104	1			T15	1		T18	2		T34	1
auto[1476395008:1610612735]	103	1			T14	1		T18	1		T37	1
auto[1610612736:1744830463]	101	1			T16	1		T83	1		T6	1
auto[1744830464:1879048191]	106	1			T6	2		T121	1		T375	1
auto[1879048192:2013265919]	107	1			T1	1		T37	1		T46	1
auto[2013265920:2147483647]	116	1			T18	1		T6	1		T46	2
auto[2147483648:2281701375]	93	1			T15	2		T37	1		T6	1
auto[2281701376:2415919103]	98	1			T15	1		T18	1		T37	1
auto[2415919104:2550136831]	110	1			T15	1		T34	1		T6	1
auto[2550136832:2684354559]	109	1			T5	1		T47	1		T119	1
auto[2684354560:2818572287]	103	1			T15	1		T6	1		T7	3
auto[2818572288:2952790015]	122	1			T6	1		T55	1		T201	1
auto[2952790016:3087007743]	101	1			T3	1		T15	1		T18	1
auto[3087007744:3221225471]	99	1			T6	2		T54	1		T47	1
auto[3221225472:3355443199]	120	1			T6	1		T46	3		T125	1
auto[3355443200:3489660927]	100	1			T14	1		T15	1		T18	1
auto[3489660928:3623878655]	96	1			T1	1		T5	1		T15	1
auto[3623878656:3758096383]	122	1			T1	2		T16	1		T6	1
auto[3758096384:3892314111]	117	1			T14	1		T18	3		T83	1
auto[3892314112:4026531839]	90	1			T1	2		T15	1		T6	1
auto[4026531840:4160749567]	96	1			T60	1		T192	1		T80	1
auto[4160749568:4294967295]	100	1			T15	2		T6	1		T46	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T18	1		T46	3		T55	1
auto[0:134217727]	auto[1]	55	1			T6	3		T189	1		T7	1
auto[134217728:268435455]	auto[0]	39	1			T2	1		T16	1		T6	1
auto[134217728:268435455]	auto[1]	49	1			T1	1		T15	1		T49	1
auto[268435456:402653183]	auto[0]	51	1			T18	1		T46	2		T55	1
auto[268435456:402653183]	auto[1]	62	1			T46	1		T7	2		T47	1
auto[402653184:536870911]	auto[0]	54	1			T83	1		T6	1		T46	2
auto[402653184:536870911]	auto[1]	40	1			T14	1		T46	1		T55	1
auto[536870912:671088639]	auto[0]	52	1			T77	1		T47	2		T230	1
auto[536870912:671088639]	auto[1]	55	1			T6	2		T7	1		T201	1
auto[671088640:805306367]	auto[0]	54	1			T8	1		T82	1		T47	1
auto[671088640:805306367]	auto[1]	53	1			T7	2		T67	2		T122	1
auto[805306368:939524095]	auto[0]	43	1			T9	1		T8	1		T80	1
auto[805306368:939524095]	auto[1]	64	1			T83	1		T49	1		T6	1
auto[939524096:1073741823]	auto[0]	56	1			T16	1		T6	1		T46	1
auto[939524096:1073741823]	auto[1]	65	1			T14	1		T7	1		T8	2
auto[1073741824:1207959551]	auto[0]	56	1			T15	1		T46	1		T8	1
auto[1073741824:1207959551]	auto[1]	46	1			T15	1		T192	1		T80	1
auto[1207959552:1342177279]	auto[0]	55	1			T6	1		T46	2		T47	2
auto[1207959552:1342177279]	auto[1]	55	1			T6	1		T46	1		T47	2
auto[1342177280:1476395007]	auto[0]	49	1			T15	1		T18	1		T55	1
auto[1342177280:1476395007]	auto[1]	55	1			T18	1		T34	1		T6	1
auto[1476395008:1610612735]	auto[0]	57	1			T6	1		T46	2		T7	1
auto[1476395008:1610612735]	auto[1]	46	1			T14	1		T18	1		T37	1
auto[1610612736:1744830463]	auto[0]	45	1			T16	1		T8	1		T47	1
auto[1610612736:1744830463]	auto[1]	56	1			T83	1		T6	1		T125	1
auto[1744830464:1879048191]	auto[0]	48	1			T6	1		T375	1		T67	1
auto[1744830464:1879048191]	auto[1]	58	1			T6	1		T121	1		T67	2
auto[1879048192:2013265919]	auto[0]	52	1			T1	1		T37	1		T46	1
auto[1879048192:2013265919]	auto[1]	55	1			T7	2		T8	2		T128	1
auto[2013265920:2147483647]	auto[0]	66	1			T18	1		T6	1		T46	2
auto[2013265920:2147483647]	auto[1]	50	1			T47	1		T119	2		T10	1
auto[2147483648:2281701375]	auto[0]	47	1			T37	1		T6	1		T8	1
auto[2147483648:2281701375]	auto[1]	46	1			T15	2		T80	1		T61	1
auto[2281701376:2415919103]	auto[0]	54	1			T37	1		T46	1		T55	1
auto[2281701376:2415919103]	auto[1]	44	1			T15	1		T18	1		T6	1
auto[2415919104:2550136831]	auto[0]	49	1			T179	1		T128	1		T207	1
auto[2415919104:2550136831]	auto[1]	61	1			T15	1		T34	1		T6	1
auto[2550136832:2684354559]	auto[0]	43	1			T5	1		T10	1		T25	1
auto[2550136832:2684354559]	auto[1]	66	1			T47	1		T119	1		T180	1
auto[2684354560:2818572287]	auto[0]	47	1			T15	1		T6	1		T7	1
auto[2684354560:2818572287]	auto[1]	56	1			T7	2		T8	1		T80	1
auto[2818572288:2952790015]	auto[0]	56	1			T6	1		T55	1		T201	1
auto[2818572288:2952790015]	auto[1]	66	1			T119	1		T120	1		T128	1
auto[2952790016:3087007743]	auto[0]	42	1			T34	1		T126	1		T207	1
auto[2952790016:3087007743]	auto[1]	59	1			T3	1		T15	1		T18	1
auto[3087007744:3221225471]	auto[0]	40	1			T6	1		T47	1		T119	1
auto[3087007744:3221225471]	auto[1]	59	1			T6	1		T54	1		T61	1
auto[3221225472:3355443199]	auto[0]	60	1			T6	1		T46	2		T125	1
auto[3221225472:3355443199]	auto[1]	60	1			T46	1		T8	1		T62	1
auto[3355443200:3489660927]	auto[0]	55	1			T60	1		T47	2		T237	1
auto[3355443200:3489660927]	auto[1]	45	1			T14	1		T15	1		T18	1
auto[3489660928:3623878655]	auto[0]	44	1			T46	1		T25	1		T180	1
auto[3489660928:3623878655]	auto[1]	52	1			T1	1		T5	1		T15	1
auto[3623878656:3758096383]	auto[0]	55	1			T1	2		T16	1		T6	1
auto[3623878656:3758096383]	auto[1]	67	1			T125	1		T7	1		T47	2
auto[3758096384:3892314111]	auto[0]	50	1			T14	1		T18	1		T189	1
auto[3758096384:3892314111]	auto[1]	67	1			T18	2		T83	1		T7	1
auto[3892314112:4026531839]	auto[0]	49	1			T1	2		T15	1		T6	1
auto[3892314112:4026531839]	auto[1]	41	1			T47	1		T119	1		T67	1
auto[4026531840:4160749567]	auto[0]	46	1			T60	1		T192	1		T120	1
auto[4026531840:4160749567]	auto[1]	50	1			T80	1		T82	1		T180	1
auto[4160749568:4294967295]	auto[0]	47	1			T15	2		T46	1		T82	1
auto[4160749568:4294967295]	auto[1]	53	1			T6	1		T46	2		T8	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1610

1

T1

4

T2

1

T5

2

auto[1]

1763

1

T1

3

T3

1

T14

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T1	1		T15	1		T83	2
auto[134217728:268435455]	112	1			T1	1		T15	1		T16	1
auto[268435456:402653183]	101	1			T6	1		T60	1		T46	3
auto[402653184:536870911]	109	1			T16	1		T37	1		T6	2
auto[536870912:671088639]	128	1			T1	1		T15	2		T18	1
auto[671088640:805306367]	115	1			T3	1		T16	1		T37	1
auto[805306368:939524095]	108	1			T14	1		T18	1		T6	1
auto[939524096:1073741823]	120	1			T18	1		T6	1		T46	1
auto[1073741824:1207959551]	107	1			T15	1		T6	1		T60	1
auto[1207959552:1342177279]	99	1			T6	1		T46	2		T55	1
auto[1342177280:1476395007]	111	1			T5	1		T15	1		T189	1
auto[1476395008:1610612735]	124	1			T46	1		T201	1		T47	1
auto[1610612736:1744830463]	101	1			T16	1		T34	1		T6	4
auto[1744830464:1879048191]	88	1			T18	1		T83	1		T49	1
auto[1879048192:2013265919]	104	1			T2	1		T6	3		T46	2
auto[2013265920:2147483647]	97	1			T5	1		T15	1		T6	1
auto[2147483648:2281701375]	103	1			T1	1		T15	1		T6	1
auto[2281701376:2415919103]	118	1			T18	2		T6	1		T46	2
auto[2415919104:2550136831]	103	1			T14	2		T34	1		T6	2
auto[2550136832:2684354559]	105	1			T18	1		T6	2		T46	1
auto[2684354560:2818572287]	98	1			T15	1		T18	2		T6	2
auto[2818572288:2952790015]	105	1			T46	1		T7	1		T8	1
auto[2952790016:3087007743]	101	1			T34	1		T46	2		T8	1
auto[3087007744:3221225471]	95	1			T15	3		T18	1		T6	2
auto[3221225472:3355443199]	88	1			T1	1		T18	1		T46	1
auto[3355443200:3489660927]	95	1			T15	1		T6	1		T7	1
auto[3489660928:3623878655]	108	1			T1	1		T15	1		T6	2
auto[3623878656:3758096383]	121	1			T14	1		T6	1		T46	2
auto[3758096384:3892314111]	104	1			T18	1		T37	2		T55	1
auto[3892314112:4026531839]	93	1			T1	1		T6	1		T46	1
auto[4026531840:4160749567]	94	1			T14	1		T15	1		T47	1
auto[4160749568:4294967295]	114	1			T83	1		T49	1		T201	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T1	1		T83	1		T46	1
auto[0:134217727]	auto[1]	57	1			T15	1		T83	1		T6	1
auto[134217728:268435455]	auto[0]	52	1			T189	1		T8	1		T291	1
auto[134217728:268435455]	auto[1]	60	1			T1	1		T15	1		T16	1
auto[268435456:402653183]	auto[0]	55	1			T60	1		T46	3		T125	1
auto[268435456:402653183]	auto[1]	46	1			T6	1		T47	1		T120	1
auto[402653184:536870911]	auto[0]	44	1			T16	1		T6	1		T8	1
auto[402653184:536870911]	auto[1]	65	1			T37	1		T6	1		T80	1
auto[536870912:671088639]	auto[0]	54	1			T1	1		T15	1		T46	2
auto[536870912:671088639]	auto[1]	74	1			T15	1		T18	1		T6	1
auto[671088640:805306367]	auto[0]	54	1			T16	1		T37	1		T47	1
auto[671088640:805306367]	auto[1]	61	1			T3	1		T8	1		T120	1
auto[805306368:939524095]	auto[0]	44	1			T46	1		T55	1		T47	1
auto[805306368:939524095]	auto[1]	64	1			T14	1		T18	1		T6	1
auto[939524096:1073741823]	auto[0]	56	1			T18	1		T46	1		T47	1
auto[939524096:1073741823]	auto[1]	64	1			T6	1		T47	1		T119	2
auto[1073741824:1207959551]	auto[0]	50	1			T15	1		T60	1		T7	1
auto[1073741824:1207959551]	auto[1]	57	1			T6	1		T46	1		T7	1
auto[1207959552:1342177279]	auto[0]	53	1			T6	1		T46	1		T55	1
auto[1207959552:1342177279]	auto[1]	46	1			T46	1		T47	1		T119	1
auto[1342177280:1476395007]	auto[0]	57	1			T5	1		T46	1		T201	1
auto[1342177280:1476395007]	auto[1]	54	1			T15	1		T189	1		T125	2
auto[1476395008:1610612735]	auto[0]	62	1			T46	1		T201	1		T47	1
auto[1476395008:1610612735]	auto[1]	62	1			T119	1		T309	2		T248	1
auto[1610612736:1744830463]	auto[0]	53	1			T6	3		T80	1		T47	2
auto[1610612736:1744830463]	auto[1]	48	1			T16	1		T34	1		T6	1
auto[1744830464:1879048191]	auto[0]	47	1			T8	1		T180	1		T122	2
auto[1744830464:1879048191]	auto[1]	41	1			T18	1		T83	1		T49	1
auto[1879048192:2013265919]	auto[0]	46	1			T2	1		T6	1		T46	1
auto[1879048192:2013265919]	auto[1]	58	1			T6	2		T46	1		T8	1
auto[2013265920:2147483647]	auto[0]	38	1			T5	1		T6	1		T46	1
auto[2013265920:2147483647]	auto[1]	59	1			T15	1		T7	1		T47	1
auto[2147483648:2281701375]	auto[0]	45	1			T1	1		T15	1		T46	1
auto[2147483648:2281701375]	auto[1]	58	1			T6	1		T46	1		T8	1
auto[2281701376:2415919103]	auto[0]	57	1			T18	2		T6	1		T46	1
auto[2281701376:2415919103]	auto[1]	61	1			T46	1		T50	1		T127	1
auto[2415919104:2550136831]	auto[0]	50	1			T34	1		T46	2		T352	1
auto[2415919104:2550136831]	auto[1]	53	1			T14	2		T6	2		T61	1
auto[2550136832:2684354559]	auto[0]	54	1			T6	1		T7	1		T8	1
auto[2550136832:2684354559]	auto[1]	51	1			T18	1		T6	1		T46	1
auto[2684354560:2818572287]	auto[0]	47	1			T15	1		T18	1		T6	1
auto[2684354560:2818572287]	auto[1]	51	1			T18	1		T6	1		T47	1
auto[2818572288:2952790015]	auto[0]	46	1			T8	1		T82	1		T47	1
auto[2818572288:2952790015]	auto[1]	59	1			T46	1		T7	1		T47	1
auto[2952790016:3087007743]	auto[0]	35	1			T46	1		T82	1		T248	1
auto[2952790016:3087007743]	auto[1]	66	1			T34	1		T46	1		T8	1
auto[3087007744:3221225471]	auto[0]	51	1			T15	1		T6	1		T55	1
auto[3087007744:3221225471]	auto[1]	44	1			T15	2		T18	1		T6	1
auto[3221225472:3355443199]	auto[0]	57	1			T1	1		T18	1		T77	1
auto[3221225472:3355443199]	auto[1]	31	1			T46	1		T7	1		T119	1
auto[3355443200:3489660927]	auto[0]	35	1			T8	1		T80	1		T82	1
auto[3355443200:3489660927]	auto[1]	60	1			T15	1		T6	1		T7	1
auto[3489660928:3623878655]	auto[0]	55	1			T60	1		T46	2		T55	2
auto[3489660928:3623878655]	auto[1]	53	1			T1	1		T15	1		T6	2
auto[3623878656:3758096383]	auto[0]	55	1			T46	1		T9	1		T8	1
auto[3623878656:3758096383]	auto[1]	66	1			T14	1		T6	1		T46	1
auto[3758096384:3892314111]	auto[0]	59	1			T18	1		T37	2		T55	1
auto[3758096384:3892314111]	auto[1]	45	1			T192	1		T54	1		T120	1
auto[3892314112:4026531839]	auto[0]	41	1			T46	1		T125	1		T7	1
auto[3892314112:4026531839]	auto[1]	52	1			T1	1		T6	1		T47	1
auto[4026531840:4160749567]	auto[0]	54	1			T14	1		T15	1		T47	1
auto[4026531840:4160749567]	auto[1]	40	1			T120	1		T121	1		T311	1
auto[4160749568:4294967295]	auto[0]	57	1			T49	1		T201	1		T48	1
auto[4160749568:4294967295]	auto[1]	57	1			T83	1		T47	1		T119	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1610

1

T1

5

T2

1

T5

1

auto[1]

1763

1

T1

2

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T1	1		T15	1		T46	1
auto[134217728:268435455]	94	1			T1	1		T16	1		T37	1
auto[268435456:402653183]	77	1			T1	1		T15	1		T6	1
auto[402653184:536870911]	105	1			T15	1		T34	1		T37	1
auto[536870912:671088639]	98	1			T15	1		T49	1		T46	1
auto[671088640:805306367]	110	1			T46	1		T55	1		T47	2
auto[805306368:939524095]	118	1			T16	1		T18	1		T6	1
auto[939524096:1073741823]	118	1			T1	1		T5	1		T15	1
auto[1073741824:1207959551]	103	1			T18	1		T46	1		T8	1
auto[1207959552:1342177279]	115	1			T15	2		T6	2		T46	1
auto[1342177280:1476395007]	124	1			T83	1		T37	1		T7	1
auto[1476395008:1610612735]	98	1			T6	1		T119	2		T10	1
auto[1610612736:1744830463]	93	1			T1	1		T15	1		T6	1
auto[1744830464:1879048191]	103	1			T15	1		T34	1		T6	2
auto[1879048192:2013265919]	94	1			T6	2		T47	1		T119	2
auto[2013265920:2147483647]	100	1			T15	1		T7	1		T47	3
auto[2147483648:2281701375]	105	1			T16	1		T83	1		T6	1
auto[2281701376:2415919103]	112	1			T5	1		T16	1		T18	1
auto[2415919104:2550136831]	105	1			T14	1		T18	1		T6	1
auto[2550136832:2684354559]	126	1			T2	1		T18	1		T6	1
auto[2684354560:2818572287]	97	1			T18	1		T46	5		T55	1
auto[2818572288:2952790015]	110	1			T15	1		T34	1		T46	2
auto[2952790016:3087007743]	112	1			T14	1		T15	1		T6	2
auto[3087007744:3221225471]	99	1			T15	1		T6	1		T46	2
auto[3221225472:3355443199]	106	1			T6	1		T46	1		T7	1
auto[3355443200:3489660927]	103	1			T6	2		T46	1		T192	1
auto[3489660928:3623878655]	108	1			T14	1		T18	1		T60	1
auto[3623878656:3758096383]	122	1			T18	1		T6	4		T46	2
auto[3758096384:3892314111]	101	1			T1	1		T18	2		T189	1
auto[3892314112:4026531839]	104	1			T14	1		T37	1		T49	1
auto[4026531840:4160749567]	93	1			T1	1		T15	1		T18	1
auto[4160749568:4294967295]	111	1			T3	1		T14	1		T15	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T1	1		T55	1		T8	1
auto[0:134217727]	auto[1]	53	1			T15	1		T46	1		T47	1
auto[134217728:268435455]	auto[0]	47	1			T1	1		T16	1		T6	1
auto[134217728:268435455]	auto[1]	47	1			T37	1		T80	1		T61	1
auto[268435456:402653183]	auto[0]	34	1			T15	1		T46	1		T309	1
auto[268435456:402653183]	auto[1]	43	1			T1	1		T6	1		T121	1
auto[402653184:536870911]	auto[0]	46	1			T37	1		T8	1		T47	2
auto[402653184:536870911]	auto[1]	59	1			T15	1		T34	1		T6	1
auto[536870912:671088639]	auto[0]	44	1			T15	1		T46	1		T237	2
auto[536870912:671088639]	auto[1]	54	1			T49	1		T125	1		T7	1
auto[671088640:805306367]	auto[0]	52	1			T46	1		T47	2		T121	1
auto[671088640:805306367]	auto[1]	58	1			T55	1		T119	1		T375	1
auto[805306368:939524095]	auto[0]	66	1			T16	1		T18	1		T82	1
auto[805306368:939524095]	auto[1]	52	1			T6	1		T7	1		T47	1
auto[939524096:1073741823]	auto[0]	59	1			T1	1		T6	1		T55	1
auto[939524096:1073741823]	auto[1]	59	1			T5	1		T15	1		T83	1
auto[1073741824:1207959551]	auto[0]	45	1			T46	1		T25	1		T67	2
auto[1073741824:1207959551]	auto[1]	58	1			T18	1		T8	1		T47	1
auto[1207959552:1342177279]	auto[0]	54	1			T15	2		T6	1		T46	1
auto[1207959552:1342177279]	auto[1]	61	1			T6	1		T7	1		T10	1
auto[1342177280:1476395007]	auto[0]	56	1			T37	1		T9	1		T8	1
auto[1342177280:1476395007]	auto[1]	68	1			T83	1		T7	1		T47	1
auto[1476395008:1610612735]	auto[0]	40	1			T6	1		T10	1		T120	1
auto[1476395008:1610612735]	auto[1]	58	1			T119	2		T120	1		T121	1
auto[1610612736:1744830463]	auto[0]	45	1			T1	1		T46	2		T120	1
auto[1610612736:1744830463]	auto[1]	48	1			T15	1		T6	1		T47	2
auto[1744830464:1879048191]	auto[0]	53	1			T15	1		T8	1		T47	1
auto[1744830464:1879048191]	auto[1]	50	1			T34	1		T6	2		T46	2
auto[1879048192:2013265919]	auto[0]	43	1			T6	1		T61	1		T25	1
auto[1879048192:2013265919]	auto[1]	51	1			T6	1		T47	1		T119	2
auto[2013265920:2147483647]	auto[0]	48	1			T47	2		T48	1		T67	2
auto[2013265920:2147483647]	auto[1]	52	1			T15	1		T7	1		T47	1
auto[2147483648:2281701375]	auto[0]	51	1			T16	1		T46	1		T201	1
auto[2147483648:2281701375]	auto[1]	54	1			T83	1		T6	1		T8	1
auto[2281701376:2415919103]	auto[0]	53	1			T5	1		T16	1		T6	2
auto[2281701376:2415919103]	auto[1]	59	1			T18	1		T6	1		T8	1
auto[2415919104:2550136831]	auto[0]	49	1			T6	1		T8	2		T25	1
auto[2415919104:2550136831]	auto[1]	56	1			T14	1		T18	1		T192	1
auto[2550136832:2684354559]	auto[0]	64	1			T2	1		T18	1		T189	1
auto[2550136832:2684354559]	auto[1]	62	1			T6	1		T46	1		T7	1
auto[2684354560:2818572287]	auto[0]	53	1			T46	3		T55	1		T80	1
auto[2684354560:2818572287]	auto[1]	44	1			T18	1		T46	2		T48	1
auto[2818572288:2952790015]	auto[0]	53	1			T34	1		T46	2		T47	1
auto[2818572288:2952790015]	auto[1]	57	1			T15	1		T8	1		T47	1
auto[2952790016:3087007743]	auto[0]	50	1			T14	1		T15	1		T6	1
auto[2952790016:3087007743]	auto[1]	62	1			T6	1		T46	1		T8	1
auto[3087007744:3221225471]	auto[0]	55	1			T46	1		T80	1		T82	1
auto[3087007744:3221225471]	auto[1]	44	1			T15	1		T6	1		T46	1
auto[3221225472:3355443199]	auto[0]	51	1			T46	1		T8	1		T47	2
auto[3221225472:3355443199]	auto[1]	55	1			T6	1		T7	1		T8	1
auto[3355443200:3489660927]	auto[0]	44	1			T28	1		T67	2		T88	1
auto[3355443200:3489660927]	auto[1]	59	1			T6	2		T46	1		T192	1
auto[3489660928:3623878655]	auto[0]	54	1			T18	1		T46	1		T398	2
auto[3489660928:3623878655]	auto[1]	54	1			T14	1		T60	1		T61	1
auto[3623878656:3758096383]	auto[0]	59	1			T46	1		T179	1		T25	1
auto[3623878656:3758096383]	auto[1]	63	1			T18	1		T6	4		T46	1
auto[3758096384:3892314111]	auto[0]	38	1			T18	1		T55	1		T7	1
auto[3758096384:3892314111]	auto[1]	63	1			T1	1		T18	1		T189	1
auto[3892314112:4026531839]	auto[0]	52	1			T37	1		T60	1		T55	1
auto[3892314112:4026531839]	auto[1]	52	1			T14	1		T49	1		T6	1
auto[4026531840:4160749567]	auto[0]	42	1			T1	1		T15	1		T18	1
auto[4026531840:4160749567]	auto[1]	51	1			T6	1		T231	1		T122	1
auto[4160749568:4294967295]	auto[0]	54	1			T18	1		T46	1		T77	1
auto[4160749568:4294967295]	auto[1]	57	1			T3	1		T14	1		T15	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1590

1

T1

5

T2

1

T5

1

auto[1]

1783

1

T1

2

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T1	1		T15	1		T37	1
auto[134217728:268435455]	90	1			T6	1		T8	1		T119	1
auto[268435456:402653183]	93	1			T14	2		T15	1		T83	1
auto[402653184:536870911]	113	1			T15	1		T6	2		T46	2
auto[536870912:671088639]	92	1			T6	1		T192	1		T7	1
auto[671088640:805306367]	110	1			T6	3		T46	1		T47	1
auto[805306368:939524095]	119	1			T18	3		T6	3		T46	2
auto[939524096:1073741823]	124	1			T5	1		T18	1		T34	1
auto[1073741824:1207959551]	100	1			T18	1		T46	1		T47	2
auto[1207959552:1342177279]	99	1			T6	2		T60	1		T7	1
auto[1342177280:1476395007]	116	1			T2	1		T5	1		T15	2
auto[1476395008:1610612735]	98	1			T82	1		T47	2		T120	1
auto[1610612736:1744830463]	95	1			T1	1		T15	1		T37	1
auto[1744830464:1879048191]	90	1			T1	1		T14	1		T6	1
auto[1879048192:2013265919]	127	1			T1	1		T15	1		T55	2
auto[2013265920:2147483647]	115	1			T1	1		T15	1		T49	1
auto[2147483648:2281701375]	122	1			T6	1		T60	1		T55	1
auto[2281701376:2415919103]	97	1			T46	1		T8	2		T47	2
auto[2415919104:2550136831]	104	1			T15	1		T18	1		T83	1
auto[2550136832:2684354559]	102	1			T1	1		T15	1		T46	1
auto[2684354560:2818572287]	119	1			T3	1		T6	1		T46	1
auto[2818572288:2952790015]	93	1			T14	1		T46	2		T125	1
auto[2952790016:3087007743]	94	1			T37	1		T6	1		T46	1
auto[3087007744:3221225471]	116	1			T83	1		T6	2		T46	3
auto[3221225472:3355443199]	90	1			T49	1		T6	1		T54	1
auto[3355443200:3489660927]	117	1			T15	1		T18	1		T34	1
auto[3489660928:3623878655]	95	1			T18	1		T6	2		T7	1
auto[3623878656:3758096383]	92	1			T14	1		T6	2		T46	2
auto[3758096384:3892314111]	112	1			T15	1		T16	2		T18	1
auto[3892314112:4026531839]	97	1			T16	1		T6	2		T8	1
auto[4026531840:4160749567]	105	1			T15	2		T16	1		T18	1
auto[4160749568:4294967295]	129	1			T1	1		T15	1		T34	1