Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2957

1

T1

4

T2

1

T3

1

auto[1]

286

1

T16

6

T125

2

T82

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T2	1		T6	1		T189	2
auto[134217728:268435455]	118	1			T16	1		T125	1		T82	1
auto[268435456:402653183]	110	1			T15	2		T16	1		T6	1
auto[402653184:536870911]	116	1			T18	1		T49	1		T8	1
auto[536870912:671088639]	87	1			T18	1		T46	1		T7	1
auto[671088640:805306367]	106	1			T18	1		T60	1		T8	1
auto[805306368:939524095]	118	1			T6	2		T82	1		T119	1
auto[939524096:1073741823]	93	1			T3	1		T18	1		T60	1
auto[1073741824:1207959551]	120	1			T14	1		T18	1		T8	2
auto[1207959552:1342177279]	100	1			T15	1		T16	1		T6	1
auto[1342177280:1476395007]	87	1			T18	1		T6	1		T46	1
auto[1476395008:1610612735]	81	1			T1	1		T46	1		T47	2
auto[1610612736:1744830463]	83	1			T18	1		T7	2		T179	1
auto[1744830464:1879048191]	97	1			T18	1		T46	1		T7	1
auto[1879048192:2013265919]	116	1			T15	1		T16	3		T18	1
auto[2013265920:2147483647]	105	1			T1	1		T15	1		T34	1
auto[2147483648:2281701375]	86	1			T18	1		T37	1		T6	1
auto[2281701376:2415919103]	108	1			T1	1		T15	2		T83	1
auto[2415919104:2550136831]	95	1			T1	1		T34	1		T6	1
auto[2550136832:2684354559]	103	1			T15	3		T37	2		T7	2
auto[2684354560:2818572287]	102	1			T15	1		T46	1		T7	1
auto[2818572288:2952790015]	104	1			T16	1		T46	1		T125	1
auto[2952790016:3087007743]	119	1			T46	1		T7	3		T47	3
auto[3087007744:3221225471]	99	1			T15	1		T16	1		T83	1
auto[3221225472:3355443199]	92	1			T5	1		T14	1		T6	1
auto[3355443200:3489660927]	99	1			T15	1		T16	1		T125	1
auto[3489660928:3623878655]	85	1			T83	1		T6	1		T46	1
auto[3623878656:3758096383]	97	1			T14	1		T18	1		T34	1
auto[3758096384:3892314111]	106	1			T15	1		T18	1		T125	1
auto[3892314112:4026531839]	83	1			T15	1		T16	1		T83	1
auto[4026531840:4160749567]	107	1			T6	2		T46	1		T7	3
auto[4160749568:4294967295]	101	1			T5	1		T14	2		T82	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	111	1			T2	1		T6	1		T189	2
auto[0:134217727]	auto[1]	9	1			T82	1		T127	2		T315	1
auto[134217728:268435455]	auto[0]	100	1			T125	1		T201	1		T47	2
auto[134217728:268435455]	auto[1]	18	1			T16	1		T82	1		T128	1
auto[268435456:402653183]	auto[0]	99	1			T15	2		T16	1		T6	1
auto[268435456:402653183]	auto[1]	11	1			T127	1		T129	1		T268	1
auto[402653184:536870911]	auto[0]	108	1			T18	1		T49	1		T8	1
auto[402653184:536870911]	auto[1]	8	1			T309	1		T285	1		T411	1
auto[536870912:671088639]	auto[0]	79	1			T18	1		T46	1		T7	1
auto[536870912:671088639]	auto[1]	8	1			T268	1		T411	1		T425	1
auto[671088640:805306367]	auto[0]	100	1			T18	1		T60	1		T8	1
auto[671088640:805306367]	auto[1]	6	1			T309	1		T129	1		T394	1
auto[805306368:939524095]	auto[0]	110	1			T6	2		T119	1		T126	1
auto[805306368:939524095]	auto[1]	8	1			T82	1		T406	1		T382	1
auto[939524096:1073741823]	auto[0]	88	1			T3	1		T18	1		T60	1
auto[939524096:1073741823]	auto[1]	5	1			T309	1		T285	1		T425	1
auto[1073741824:1207959551]	auto[0]	106	1			T14	1		T18	1		T8	2
auto[1073741824:1207959551]	auto[1]	14	1			T309	2		T314	1		T129	1
auto[1207959552:1342177279]	auto[0]	87	1			T15	1		T6	1		T60	1
auto[1207959552:1342177279]	auto[1]	13	1			T16	1		T237	1		T309	1
auto[1342177280:1476395007]	auto[0]	78	1			T18	1		T6	1		T46	1
auto[1342177280:1476395007]	auto[1]	9	1			T314	1		T394	1		T327	2
auto[1476395008:1610612735]	auto[0]	71	1			T1	1		T46	1		T47	2
auto[1476395008:1610612735]	auto[1]	10	1			T128	1		T361	1		T411	2
auto[1610612736:1744830463]	auto[0]	79	1			T18	1		T7	2		T179	1
auto[1610612736:1744830463]	auto[1]	4	1			T336	2		T357	1		T413	1
auto[1744830464:1879048191]	auto[0]	85	1			T18	1		T46	1		T7	1
auto[1744830464:1879048191]	auto[1]	12	1			T126	1		T309	1		T182	1
auto[1879048192:2013265919]	auto[0]	104	1			T15	1		T16	1		T18	1
auto[1879048192:2013265919]	auto[1]	12	1			T16	2		T82	1		T309	1
auto[2013265920:2147483647]	auto[0]	91	1			T1	1		T15	1		T34	1
auto[2013265920:2147483647]	auto[1]	14	1			T82	1		T126	1		T128	1
auto[2147483648:2281701375]	auto[0]	78	1			T18	1		T37	1		T6	1
auto[2147483648:2281701375]	auto[1]	8	1			T82	1		T127	1		T128	1
auto[2281701376:2415919103]	auto[0]	99	1			T1	1		T15	2		T83	1
auto[2281701376:2415919103]	auto[1]	9	1			T128	1		T361	1		T411	1
auto[2415919104:2550136831]	auto[0]	88	1			T1	1		T34	1		T6	1
auto[2415919104:2550136831]	auto[1]	7	1			T126	1		T127	1		T128	1
auto[2550136832:2684354559]	auto[0]	99	1			T15	3		T37	2		T7	2
auto[2550136832:2684354559]	auto[1]	4	1			T414	1		T286	1		T426	1
auto[2684354560:2818572287]	auto[0]	95	1			T15	1		T46	1		T7	1
auto[2684354560:2818572287]	auto[1]	7	1			T268	1		T361	1		T406	1
auto[2818572288:2952790015]	auto[0]	92	1			T16	1		T46	1		T7	1
auto[2818572288:2952790015]	auto[1]	12	1			T125	1		T128	1		T285	1
auto[2952790016:3087007743]	auto[0]	113	1			T46	1		T7	3		T47	3
auto[2952790016:3087007743]	auto[1]	6	1			T327	2		T357	2		T419	1
auto[3087007744:3221225471]	auto[0]	88	1			T15	1		T83	1		T6	1
auto[3087007744:3221225471]	auto[1]	11	1			T16	1		T127	1		T314	1
auto[3221225472:3355443199]	auto[0]	83	1			T5	1		T14	1		T6	1
auto[3221225472:3355443199]	auto[1]	9	1			T129	1		T327	1		T228	1
auto[3355443200:3489660927]	auto[0]	92	1			T15	1		T16	1		T47	2
auto[3355443200:3489660927]	auto[1]	7	1			T125	1		T394	1		T361	1
auto[3489660928:3623878655]	auto[0]	78	1			T83	1		T6	1		T46	1
auto[3489660928:3623878655]	auto[1]	7	1			T411	1		T276	1		T414	1
auto[3623878656:3758096383]	auto[0]	91	1			T14	1		T18	1		T34	1
auto[3623878656:3758096383]	auto[1]	6	1			T127	1		T237	1		T412	1
auto[3758096384:3892314111]	auto[0]	97	1			T15	1		T18	1		T125	1
auto[3758096384:3892314111]	auto[1]	9	1			T268	1		T394	1		T361	1
auto[3892314112:4026531839]	auto[0]	77	1			T15	1		T83	1		T47	2
auto[3892314112:4026531839]	auto[1]	6	1			T16	1		T309	1		T327	1
auto[4026531840:4160749567]	auto[0]	95	1			T6	2		T46	1		T7	3
auto[4026531840:4160749567]	auto[1]	12	1			T127	1		T128	1		T309	1
auto[4160749568:4294967295]	auto[0]	96	1			T5	1		T14	2		T82	1
auto[4160749568:4294967295]	auto[1]	5	1			T129	1		T411	1		T412	2